2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
38 #include "hw/fw-path-provider.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "mmu-hash64.h"
50 #include "mmu-book3s-v3.h"
51 #include "cpu-models.h"
52 #include "hw/core/cpu.h"
54 #include "hw/boards.h"
55 #include "hw/ppc/ppc.h"
56 #include "hw/loader.h"
58 #include "hw/ppc/fdt.h"
59 #include "hw/ppc/spapr.h"
60 #include "hw/ppc/spapr_vio.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/pci-host/spapr.h"
63 #include "hw/pci/msi.h"
65 #include "hw/pci/pci.h"
66 #include "hw/scsi/scsi.h"
67 #include "hw/virtio/virtio-scsi.h"
68 #include "hw/virtio/vhost-scsi-common.h"
70 #include "exec/address-spaces.h"
71 #include "exec/ram_addr.h"
73 #include "qemu/config-file.h"
74 #include "qemu/error-report.h"
77 #include "hw/intc/intc.h"
79 #include "qemu/cutils.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
84 #include "monitor/monitor.h"
88 /* SLOF memory layout:
90 * SLOF raw image loaded at 0, copies its romfs right below the flat
91 * device-tree, then position SLOF itself 31M below that
93 * So we set FW_OVERHEAD to 40MB which should account for all of that
96 * We load our kernel at 4M, leaving space for SLOF initial image
98 #define FDT_MAX_SIZE 0x100000
99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
100 #define FW_MAX_SIZE 0x400000
101 #define FW_FILE_NAME "slof.bin"
102 #define FW_OVERHEAD 0x2800000
103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
105 #define MIN_RMA_SLOF 128UL
107 #define PHANDLE_INTC 0x00001111
109 /* These two functions implement the VCPU id numbering: one to compute them
110 * all and one to identify thread 0 of a VCORE. Any change to the first one
111 * is likely to have an impact on the second one, so let's keep them close.
113 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
115 MachineState
*ms
= MACHINE(spapr
);
116 unsigned int smp_threads
= ms
->smp
.threads
;
120 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
122 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
126 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
131 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
132 * and newer QEMUs don't even have them. In both cases, we don't want
133 * to send anything on the wire.
138 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
139 .name
= "icp/server",
141 .minimum_version_id
= 1,
142 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
143 .fields
= (VMStateField
[]) {
144 VMSTATE_UNUSED(4), /* uint32_t xirr */
145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
146 VMSTATE_UNUSED(1), /* uint8_t mfrr */
147 VMSTATE_END_OF_LIST()
151 static void pre_2_10_vmstate_register_dummy_icp(int i
)
153 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
154 (void *)(uintptr_t) i
);
157 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
159 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
160 (void *)(uintptr_t) i
);
163 int spapr_max_server_number(SpaprMachineState
*spapr
)
165 MachineState
*ms
= MACHINE(spapr
);
168 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
171 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
175 uint32_t servers_prop
[smt_threads
];
176 uint32_t gservers_prop
[smt_threads
* 2];
177 int index
= spapr_get_vcpu_id(cpu
);
179 if (cpu
->compat_pvr
) {
180 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
186 /* Build interrupt servers and gservers properties */
187 for (i
= 0; i
< smt_threads
; i
++) {
188 servers_prop
[i
] = cpu_to_be32(index
+ i
);
189 /* Hack, direct the group queues back to cpu 0 */
190 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
191 gservers_prop
[i
*2 + 1] = 0;
193 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
194 servers_prop
, sizeof(servers_prop
));
198 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
199 gservers_prop
, sizeof(gservers_prop
));
204 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
206 int index
= spapr_get_vcpu_id(cpu
);
207 uint32_t associativity
[] = {cpu_to_be32(0x5),
211 cpu_to_be32(cpu
->node_id
),
214 /* Advertise NUMA via ibm,associativity */
215 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
216 sizeof(associativity
));
219 /* Populate the "ibm,pa-features" property */
220 static void spapr_populate_pa_features(SpaprMachineState
*spapr
,
222 void *fdt
, int offset
)
224 uint8_t pa_features_206
[] = { 6, 0,
225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
226 uint8_t pa_features_207
[] = { 24, 0,
227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
231 uint8_t pa_features_300
[] = { 66, 0,
232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
247 /* 42: PM, 44: PC RA, 46: SC vec'd */
248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
249 /* 48: SIMD, 50: QP BFP, 52: String */
250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
251 /* 54: DecFP, 56: DecI, 58: SHA */
252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
253 /* 60: NM atomic, 62: RNG */
254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
256 uint8_t *pa_features
= NULL
;
259 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
260 pa_features
= pa_features_206
;
261 pa_size
= sizeof(pa_features_206
);
263 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
264 pa_features
= pa_features_207
;
265 pa_size
= sizeof(pa_features_207
);
267 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
268 pa_features
= pa_features_300
;
269 pa_size
= sizeof(pa_features_300
);
275 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
277 * Note: we keep CI large pages off by default because a 64K capable
278 * guest provisioned with large pages might otherwise try to map a qemu
279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
280 * even if that qemu runs on a 4k host.
281 * We dd this bit back here if we are confident this is not an issue
283 pa_features
[3] |= 0x20;
285 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
286 pa_features
[24] |= 0x80; /* Transactional memory support */
288 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
289 /* Workaround for broken kernels that attempt (guest) radix
290 * mode when they can't handle it, if they see the radix bit set
291 * in pa-features. So hide it from them. */
292 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
295 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
298 static hwaddr
spapr_node0_size(MachineState
*machine
)
300 if (machine
->numa_state
->num_nodes
) {
302 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
303 if (machine
->numa_state
->nodes
[i
].node_mem
) {
304 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
309 return machine
->ram_size
;
312 static void add_str(GString
*s
, const gchar
*s1
)
314 g_string_append_len(s
, s1
, strlen(s1
) + 1);
317 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
320 uint32_t associativity
[] = {
321 cpu_to_be32(0x4), /* length */
322 cpu_to_be32(0x0), cpu_to_be32(0x0),
323 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
326 uint64_t mem_reg_property
[2];
329 mem_reg_property
[0] = cpu_to_be64(start
);
330 mem_reg_property
[1] = cpu_to_be64(size
);
332 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
333 off
= fdt_add_subnode(fdt
, 0, mem_name
);
335 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
336 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
337 sizeof(mem_reg_property
))));
338 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
339 sizeof(associativity
))));
343 static int spapr_populate_memory(SpaprMachineState
*spapr
, void *fdt
)
345 MachineState
*machine
= MACHINE(spapr
);
346 hwaddr mem_start
, node_size
;
347 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
348 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
351 /* No NUMA nodes, assume there is just one node with whole RAM */
354 ramnode
.node_mem
= machine
->ram_size
;
358 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
359 if (!nodes
[i
].node_mem
) {
362 if (mem_start
>= machine
->ram_size
) {
365 node_size
= nodes
[i
].node_mem
;
366 if (node_size
> machine
->ram_size
- mem_start
) {
367 node_size
= machine
->ram_size
- mem_start
;
371 /* spapr_machine_init() checks for rma_size <= node0_size
373 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
374 mem_start
+= spapr
->rma_size
;
375 node_size
-= spapr
->rma_size
;
377 for ( ; node_size
; ) {
378 hwaddr sizetmp
= pow2floor(node_size
);
380 /* mem_start != 0 here */
381 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
382 sizetmp
= 1ULL << ctzl(mem_start
);
385 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
386 node_size
-= sizetmp
;
387 mem_start
+= sizetmp
;
394 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
395 SpaprMachineState
*spapr
)
397 MachineState
*ms
= MACHINE(spapr
);
398 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
399 CPUPPCState
*env
= &cpu
->env
;
400 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
401 int index
= spapr_get_vcpu_id(cpu
);
402 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
403 0xffffffff, 0xffffffff};
404 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
405 : SPAPR_TIMEBASE_FREQ
;
406 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
407 uint32_t page_sizes_prop
[64];
408 size_t page_sizes_prop_size
;
409 unsigned int smp_threads
= ms
->smp
.threads
;
410 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
411 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
412 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
415 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
418 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
420 drc_index
= spapr_drc_index(drc
);
421 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
424 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
425 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
427 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
428 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
429 env
->dcache_line_size
)));
430 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
431 env
->dcache_line_size
)));
432 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
433 env
->icache_line_size
)));
434 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
435 env
->icache_line_size
)));
437 if (pcc
->l1_dcache_size
) {
438 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
439 pcc
->l1_dcache_size
)));
441 warn_report("Unknown L1 dcache size for cpu");
443 if (pcc
->l1_icache_size
) {
444 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
445 pcc
->l1_icache_size
)));
447 warn_report("Unknown L1 icache size for cpu");
450 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
451 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
452 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
453 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
454 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
455 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
457 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
458 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
460 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
461 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
464 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
465 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
466 segs
, sizeof(segs
))));
469 /* Advertise VSX (vector extensions) if available
470 * 1 == VMX / Altivec available
473 * Only CPUs for which we create core types in spapr_cpu_core.c
474 * are possible, and all of those have VMX */
475 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
476 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
478 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
481 /* Advertise DFP (Decimal Floating Point) if available
482 * 0 / no property == no DFP
483 * 1 == DFP available */
484 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
485 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
488 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
489 sizeof(page_sizes_prop
));
490 if (page_sizes_prop_size
) {
491 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
492 page_sizes_prop
, page_sizes_prop_size
)));
495 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
);
497 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
498 cs
->cpu_index
/ vcpus_per_socket
)));
500 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
501 pft_size_prop
, sizeof(pft_size_prop
))));
503 if (ms
->numa_state
->num_nodes
> 1) {
504 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
507 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
509 if (pcc
->radix_page_info
) {
510 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
511 radix_AP_encodings
[i
] =
512 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
514 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
516 pcc
->radix_page_info
->count
*
517 sizeof(radix_AP_encodings
[0]))));
521 * We set this property to let the guest know that it can use the large
522 * decrementer and its width in bits.
524 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
525 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
526 pcc
->lrg_decr_bits
)));
529 static void spapr_populate_cpus_dt_node(void *fdt
, SpaprMachineState
*spapr
)
538 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
540 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
541 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
544 * We walk the CPUs in reverse order to ensure that CPU DT nodes
545 * created by fdt_add_subnode() end up in the right order in FDT
546 * for the guest kernel the enumerate the CPUs correctly.
548 * The CPU list cannot be traversed in reverse order, so we need
554 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
558 for (i
= n_cpus
- 1; i
>= 0; i
--) {
559 CPUState
*cs
= rev
[i
];
560 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
561 int index
= spapr_get_vcpu_id(cpu
);
562 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
565 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
569 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
570 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
573 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
579 static int spapr_rng_populate_dt(void *fdt
)
584 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
588 ret
= fdt_setprop_string(fdt
, node
, "device_type",
589 "ibm,platform-facilities");
590 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
591 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
593 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
597 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
602 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
604 MemoryDeviceInfoList
*info
;
606 for (info
= list
; info
; info
= info
->next
) {
607 MemoryDeviceInfo
*value
= info
->value
;
609 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
610 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
612 if (addr
>= pcdimm_info
->addr
&&
613 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
614 return pcdimm_info
->node
;
622 struct sPAPRDrconfCellV2
{
630 typedef struct DrconfCellQueue
{
631 struct sPAPRDrconfCellV2 cell
;
632 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
635 static DrconfCellQueue
*
636 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
637 uint32_t drc_index
, uint32_t aa_index
,
640 DrconfCellQueue
*elem
;
642 elem
= g_malloc0(sizeof(*elem
));
643 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
644 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
645 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
646 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
647 elem
->cell
.flags
= cpu_to_be32(flags
);
652 /* ibm,dynamic-memory-v2 */
653 static int spapr_populate_drmem_v2(SpaprMachineState
*spapr
, void *fdt
,
654 int offset
, MemoryDeviceInfoList
*dimms
)
656 MachineState
*machine
= MACHINE(spapr
);
657 uint8_t *int_buf
, *cur_index
;
659 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
660 uint64_t addr
, cur_addr
, size
;
661 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
662 uint64_t mem_end
= machine
->device_memory
->base
+
663 memory_region_size(&machine
->device_memory
->mr
);
664 uint32_t node
, buf_len
, nr_entries
= 0;
666 DrconfCellQueue
*elem
, *next
;
667 MemoryDeviceInfoList
*info
;
668 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
669 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
671 /* Entry to cover RAM and the gap area */
672 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
673 SPAPR_LMB_FLAGS_RESERVED
|
674 SPAPR_LMB_FLAGS_DRC_INVALID
);
675 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
678 cur_addr
= machine
->device_memory
->base
;
679 for (info
= dimms
; info
; info
= info
->next
) {
680 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
686 /* Entry for hot-pluggable area */
687 if (cur_addr
< addr
) {
688 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
690 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
691 cur_addr
, spapr_drc_index(drc
), -1, 0);
692 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
697 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
699 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
700 spapr_drc_index(drc
), node
,
701 SPAPR_LMB_FLAGS_ASSIGNED
);
702 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
704 cur_addr
= addr
+ size
;
707 /* Entry for remaining hotpluggable area */
708 if (cur_addr
< mem_end
) {
709 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
711 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
712 cur_addr
, spapr_drc_index(drc
), -1, 0);
713 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
717 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
718 int_buf
= cur_index
= g_malloc0(buf_len
);
719 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
720 cur_index
+= sizeof(nr_entries
);
722 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
723 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
724 cur_index
+= sizeof(elem
->cell
);
725 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
729 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
737 /* ibm,dynamic-memory */
738 static int spapr_populate_drmem_v1(SpaprMachineState
*spapr
, void *fdt
,
739 int offset
, MemoryDeviceInfoList
*dimms
)
741 MachineState
*machine
= MACHINE(spapr
);
743 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
744 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
745 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
746 memory_region_size(&machine
->device_memory
->mr
)) /
748 uint32_t *int_buf
, *cur_index
, buf_len
;
751 * Allocate enough buffer size to fit in ibm,dynamic-memory
753 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
754 cur_index
= int_buf
= g_malloc0(buf_len
);
755 int_buf
[0] = cpu_to_be32(nr_lmbs
);
757 for (i
= 0; i
< nr_lmbs
; i
++) {
758 uint64_t addr
= i
* lmb_size
;
759 uint32_t *dynamic_memory
= cur_index
;
761 if (i
>= device_lmb_start
) {
764 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
767 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
768 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
769 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
770 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
771 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
772 if (memory_region_present(get_system_memory(), addr
)) {
773 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
775 dynamic_memory
[5] = cpu_to_be32(0);
779 * LMB information for RMA, boot time RAM and gap b/n RAM and
780 * device memory region -- all these are marked as reserved
781 * and as having no valid DRC.
783 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
784 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
785 dynamic_memory
[2] = cpu_to_be32(0);
786 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
787 dynamic_memory
[4] = cpu_to_be32(-1);
788 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
789 SPAPR_LMB_FLAGS_DRC_INVALID
);
792 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
794 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
803 * Adds ibm,dynamic-reconfiguration-memory node.
804 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
805 * of this device tree node.
807 static int spapr_populate_drconf_memory(SpaprMachineState
*spapr
, void *fdt
)
809 MachineState
*machine
= MACHINE(spapr
);
810 int nb_numa_nodes
= machine
->numa_state
->num_nodes
;
812 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
813 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
814 uint32_t *int_buf
, *cur_index
, buf_len
;
815 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
816 MemoryDeviceInfoList
*dimms
= NULL
;
819 * Don't create the node if there is no device memory
821 if (machine
->ram_size
== machine
->maxram_size
) {
825 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
827 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
828 sizeof(prop_lmb_size
));
833 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
838 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
843 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
844 dimms
= qmp_memory_device_list();
845 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
846 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
848 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
850 qapi_free_MemoryDeviceInfoList(dimms
);
856 /* ibm,associativity-lookup-arrays */
857 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
858 cur_index
= int_buf
= g_malloc0(buf_len
);
859 int_buf
[0] = cpu_to_be32(nr_nodes
);
860 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
862 for (i
= 0; i
< nr_nodes
; i
++) {
863 uint32_t associativity
[] = {
869 memcpy(cur_index
, associativity
, sizeof(associativity
));
872 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
873 (cur_index
- int_buf
) * sizeof(uint32_t));
879 static int spapr_dt_cas_updates(SpaprMachineState
*spapr
, void *fdt
,
880 SpaprOptionVector
*ov5_updates
)
882 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
885 /* Generate ibm,dynamic-reconfiguration-memory node if required */
886 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
887 g_assert(smc
->dr_lmb_enabled
);
888 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
894 offset
= fdt_path_offset(fdt
, "/chosen");
896 offset
= fdt_add_subnode(fdt
, 0, "chosen");
901 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
902 "ibm,architecture-vec-5");
908 static bool spapr_hotplugged_dev_before_cas(void)
910 Object
*drc_container
, *obj
;
911 ObjectProperty
*prop
;
912 ObjectPropertyIterator iter
;
914 drc_container
= container_get(object_get_root(), "/dr-connector");
915 object_property_iter_init(&iter
, drc_container
);
916 while ((prop
= object_property_iter_next(&iter
))) {
917 if (!strstart(prop
->type
, "link<", NULL
)) {
920 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
921 if (spapr_drc_needed(obj
)) {
928 static void *spapr_build_fdt(SpaprMachineState
*spapr
);
930 int spapr_h_cas_compose_response(SpaprMachineState
*spapr
,
931 target_ulong addr
, target_ulong size
,
932 SpaprOptionVector
*ov5_updates
)
935 SpaprDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
937 if (spapr_hotplugged_dev_before_cas()) {
941 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
942 error_report("SLOF provided an unexpected CAS buffer size "
943 TARGET_FMT_lu
" (min: %zu, max: %u)",
944 size
, sizeof(hdr
), FW_MAX_SIZE
);
950 fdt
= spapr_build_fdt(spapr
);
951 _FDT((fdt_pack(fdt
)));
953 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
955 trace_spapr_cas_failed(size
);
959 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
960 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
961 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
963 g_free(spapr
->fdt_blob
);
964 spapr
->fdt_size
= fdt_totalsize(fdt
);
965 spapr
->fdt_initial_size
= spapr
->fdt_size
;
966 spapr
->fdt_blob
= fdt
;
971 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
973 MachineState
*ms
= MACHINE(spapr
);
975 GString
*hypertas
= g_string_sized_new(256);
976 GString
*qemu_hypertas
= g_string_sized_new(256);
977 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
978 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
979 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
980 uint32_t lrdr_capacity
[] = {
981 cpu_to_be32(max_device_addr
>> 32),
982 cpu_to_be32(max_device_addr
& 0xffffffff),
983 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
984 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
986 uint32_t maxdomain
= cpu_to_be32(spapr
->gpu_numa_id
> 1 ? 1 : 0);
987 uint32_t maxdomains
[] = {
992 cpu_to_be32(spapr
->gpu_numa_id
),
995 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
998 add_str(hypertas
, "hcall-pft");
999 add_str(hypertas
, "hcall-term");
1000 add_str(hypertas
, "hcall-dabr");
1001 add_str(hypertas
, "hcall-interrupt");
1002 add_str(hypertas
, "hcall-tce");
1003 add_str(hypertas
, "hcall-vio");
1004 add_str(hypertas
, "hcall-splpar");
1005 add_str(hypertas
, "hcall-join");
1006 add_str(hypertas
, "hcall-bulk");
1007 add_str(hypertas
, "hcall-set-mode");
1008 add_str(hypertas
, "hcall-sprg0");
1009 add_str(hypertas
, "hcall-copy");
1010 add_str(hypertas
, "hcall-debug");
1011 add_str(hypertas
, "hcall-vphn");
1012 add_str(qemu_hypertas
, "hcall-memop1");
1014 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1015 add_str(hypertas
, "hcall-multi-tce");
1018 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1019 add_str(hypertas
, "hcall-hpt-resize");
1022 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1023 hypertas
->str
, hypertas
->len
));
1024 g_string_free(hypertas
, TRUE
);
1025 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1026 qemu_hypertas
->str
, qemu_hypertas
->len
));
1027 g_string_free(qemu_hypertas
, TRUE
);
1029 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1030 refpoints
, sizeof(refpoints
)));
1032 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1033 maxdomains
, sizeof(maxdomains
)));
1035 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1036 RTAS_ERROR_LOG_MAX
));
1037 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1038 RTAS_EVENT_SCAN_RATE
));
1040 g_assert(msi_nonbroken
);
1041 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1044 * According to PAPR, rtas ibm,os-term does not guarantee a return
1045 * back to the guest cpu.
1047 * While an additional ibm,extended-os-term property indicates
1048 * that rtas call return will always occur. Set this property.
1050 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1052 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1053 lrdr_capacity
, sizeof(lrdr_capacity
)));
1055 spapr_dt_rtas_tokens(fdt
, rtas
);
1059 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1060 * and the XIVE features that the guest may request and thus the valid
1061 * values for bytes 23..26 of option vector 5:
1063 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
1066 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1069 23, 0x00, /* XICS / XIVE mode */
1070 24, 0x00, /* Hash/Radix, filled in below. */
1071 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1072 26, 0x40, /* Radix options: GTSE == yes. */
1075 if (spapr
->irq
->xics
&& spapr
->irq
->xive
) {
1076 val
[1] = SPAPR_OV5_XIVE_BOTH
;
1077 } else if (spapr
->irq
->xive
) {
1078 val
[1] = SPAPR_OV5_XIVE_EXPLOIT
;
1080 assert(spapr
->irq
->xics
);
1081 val
[1] = SPAPR_OV5_XIVE_LEGACY
;
1084 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1085 first_ppc_cpu
->compat_pvr
)) {
1087 * If we're in a pre POWER9 compat mode then the guest should
1088 * do hash and use the legacy interrupt mode
1090 val
[1] = SPAPR_OV5_XIVE_LEGACY
; /* XICS */
1091 val
[3] = 0x00; /* Hash */
1092 } else if (kvm_enabled()) {
1093 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1094 val
[3] = 0x80; /* OV5_MMU_BOTH */
1095 } else if (kvmppc_has_cap_mmu_radix()) {
1096 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1098 val
[3] = 0x00; /* Hash */
1101 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1104 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1108 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
)
1110 MachineState
*machine
= MACHINE(spapr
);
1111 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1113 const char *boot_device
= machine
->boot_order
;
1114 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1116 char *bootlist
= get_boot_devices_list(&cb
);
1118 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1120 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1121 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1122 machine
->kernel_cmdline
));
1124 if (spapr
->initrd_size
) {
1125 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1126 spapr
->initrd_base
));
1127 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1128 spapr
->initrd_base
+ spapr
->initrd_size
));
1131 if (spapr
->kernel_size
) {
1132 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1133 cpu_to_be64(spapr
->kernel_size
) };
1135 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1136 &kprop
, sizeof(kprop
)));
1137 if (spapr
->kernel_le
) {
1138 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1142 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1144 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1145 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1146 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1148 if (cb
&& bootlist
) {
1151 for (i
= 0; i
< cb
; i
++) {
1152 if (bootlist
[i
] == '\n') {
1156 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1159 if (boot_device
&& strlen(boot_device
)) {
1160 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1163 if (!spapr
->has_graphics
&& stdout_path
) {
1165 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1166 * kernel. New platforms should only use the "stdout-path" property. Set
1167 * the new property and continue using older property to remain
1168 * compatible with the existing firmware.
1170 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1171 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1174 /* We can deal with BAR reallocation just fine, advertise it to the guest */
1175 if (smc
->linux_pci_probe
) {
1176 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1179 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1181 g_free(stdout_path
);
1185 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1187 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1188 * KVM to work under pHyp with some guest co-operation */
1190 uint8_t hypercall
[16];
1192 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1193 /* indicate KVM hypercall interface */
1194 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1195 if (kvmppc_has_cap_fixup_hcalls()) {
1197 * Older KVM versions with older guest kernels were broken
1198 * with the magic page, don't allow the guest to map it.
1200 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1201 sizeof(hypercall
))) {
1202 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1203 hypercall
, sizeof(hypercall
)));
1208 static void *spapr_build_fdt(SpaprMachineState
*spapr
)
1210 MachineState
*machine
= MACHINE(spapr
);
1211 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1212 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1218 fdt
= g_malloc0(FDT_MAX_SIZE
);
1219 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1222 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1223 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1224 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1226 /* Guest UUID & Name*/
1227 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1228 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1229 if (qemu_uuid_set
) {
1230 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1234 if (qemu_get_vm_name()) {
1235 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1236 qemu_get_vm_name()));
1239 /* Host Model & Serial Number */
1240 if (spapr
->host_model
) {
1241 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1242 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1243 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1247 if (spapr
->host_serial
) {
1248 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1249 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1250 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1254 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1255 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1257 /* /interrupt controller */
1258 spapr
->irq
->dt_populate(spapr
, spapr_max_server_number(spapr
), fdt
,
1261 ret
= spapr_populate_memory(spapr
, fdt
);
1263 error_report("couldn't setup memory nodes in fdt");
1268 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1270 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1271 ret
= spapr_rng_populate_dt(fdt
);
1273 error_report("could not set up rng device in the fdt");
1278 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1279 ret
= spapr_dt_phb(phb
, PHANDLE_INTC
, fdt
, spapr
->irq
->nr_msis
, NULL
);
1281 error_report("couldn't setup PCI devices in fdt");
1287 spapr_populate_cpus_dt_node(fdt
, spapr
);
1289 if (smc
->dr_lmb_enabled
) {
1290 _FDT(spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1293 if (mc
->has_hotpluggable_cpus
) {
1294 int offset
= fdt_path_offset(fdt
, "/cpus");
1295 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1297 error_report("Couldn't set up CPU DR device tree properties");
1302 /* /event-sources */
1303 spapr_dt_events(spapr
, fdt
);
1306 spapr_dt_rtas(spapr
, fdt
);
1309 spapr_dt_chosen(spapr
, fdt
);
1312 if (kvm_enabled()) {
1313 spapr_dt_hypervisor(spapr
, fdt
);
1316 /* Build memory reserve map */
1317 if (spapr
->kernel_size
) {
1318 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1320 if (spapr
->initrd_size
) {
1321 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1324 /* ibm,client-architecture-support updates */
1325 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1327 error_report("couldn't setup CAS properties fdt");
1331 if (smc
->dr_phb_enabled
) {
1332 ret
= spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_PHB
);
1334 error_report("Couldn't set up PHB DR device tree properties");
1342 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1344 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1347 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1350 CPUPPCState
*env
= &cpu
->env
;
1352 /* The TCG path should also be holding the BQL at this point */
1353 g_assert(qemu_mutex_iothread_locked());
1356 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1357 env
->gpr
[3] = H_PRIVILEGE
;
1359 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1363 struct LPCRSyncState
{
1368 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1370 struct LPCRSyncState
*s
= arg
.host_ptr
;
1371 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1372 CPUPPCState
*env
= &cpu
->env
;
1375 cpu_synchronize_state(cs
);
1376 lpcr
= env
->spr
[SPR_LPCR
];
1379 ppc_store_lpcr(cpu
, lpcr
);
1382 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1385 struct LPCRSyncState s
= {
1390 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1394 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1396 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1398 /* Copy PATE1:GR into PATE0:HR */
1399 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1400 entry
->dw1
= spapr
->patb_entry
;
1403 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1404 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1405 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1406 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1407 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1410 * Get the fd to access the kernel htab, re-opening it if necessary
1412 static int get_htab_fd(SpaprMachineState
*spapr
)
1414 Error
*local_err
= NULL
;
1416 if (spapr
->htab_fd
>= 0) {
1417 return spapr
->htab_fd
;
1420 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1421 if (spapr
->htab_fd
< 0) {
1422 error_report_err(local_err
);
1425 return spapr
->htab_fd
;
1428 void close_htab_fd(SpaprMachineState
*spapr
)
1430 if (spapr
->htab_fd
>= 0) {
1431 close(spapr
->htab_fd
);
1433 spapr
->htab_fd
= -1;
1436 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1438 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1440 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1443 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1445 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1447 assert(kvm_enabled());
1453 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1456 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1459 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1460 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1464 * HTAB is controlled by KVM. Fetch into temporary buffer
1466 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1467 kvmppc_read_hptes(hptes
, ptex
, n
);
1472 * HTAB is controlled by QEMU. Just point to the internally
1475 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1478 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1479 const ppc_hash_pte64_t
*hptes
,
1482 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1485 g_free((void *)hptes
);
1488 /* Nothing to do for qemu managed HPT */
1491 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1492 uint64_t pte0
, uint64_t pte1
)
1494 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1495 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1498 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1500 if (pte0
& HPTE64_V_VALID
) {
1501 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1503 * When setting valid, we write PTE1 first. This ensures
1504 * proper synchronization with the reading code in
1505 * ppc_hash64_pteg_search()
1508 stq_p(spapr
->htab
+ offset
, pte0
);
1510 stq_p(spapr
->htab
+ offset
, pte0
);
1512 * When clearing it we set PTE0 first. This ensures proper
1513 * synchronization with the reading code in
1514 * ppc_hash64_pteg_search()
1517 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1522 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1525 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1526 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1529 /* There should always be a hash table when this is called */
1530 error_report("spapr_hpte_set_c called with no hash table !");
1534 /* The HW performs a non-atomic byte update */
1535 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1538 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1541 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1542 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1545 /* There should always be a hash table when this is called */
1546 error_report("spapr_hpte_set_r called with no hash table !");
1550 /* The HW performs a non-atomic byte update */
1551 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1554 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1558 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1559 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1560 * that's much more than is needed for Linux guests */
1561 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1562 shift
= MAX(shift
, 18); /* Minimum architected size */
1563 shift
= MIN(shift
, 46); /* Maximum architected size */
1567 void spapr_free_hpt(SpaprMachineState
*spapr
)
1569 g_free(spapr
->htab
);
1571 spapr
->htab_shift
= 0;
1572 close_htab_fd(spapr
);
1575 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
1580 /* Clean up any HPT info from a previous boot */
1581 spapr_free_hpt(spapr
);
1583 rc
= kvmppc_reset_htab(shift
);
1585 /* kernel-side HPT needed, but couldn't allocate one */
1586 error_setg_errno(errp
, errno
,
1587 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1589 /* This is almost certainly fatal, but if the caller really
1590 * wants to carry on with shift == 0, it's welcome to try */
1591 } else if (rc
> 0) {
1592 /* kernel-side HPT allocated */
1595 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1599 spapr
->htab_shift
= shift
;
1602 /* kernel-side HPT not needed, allocate in userspace instead */
1603 size_t size
= 1ULL << shift
;
1606 spapr
->htab
= qemu_memalign(size
, size
);
1608 error_setg_errno(errp
, errno
,
1609 "Could not allocate HPT of order %d", shift
);
1613 memset(spapr
->htab
, 0, size
);
1614 spapr
->htab_shift
= shift
;
1616 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1617 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1620 /* We're setting up a hash table, so that means we're not radix */
1621 spapr
->patb_entry
= 0;
1622 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1625 void spapr_setup_hpt_and_vrma(SpaprMachineState
*spapr
)
1629 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1630 || (spapr
->cas_reboot
1631 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1632 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1634 uint64_t current_ram_size
;
1636 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1637 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1639 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1641 if (spapr
->vrma_adjust
) {
1642 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1647 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1650 (SpaprDrc
*) object_dynamic_cast(child
,
1651 TYPE_SPAPR_DR_CONNECTOR
);
1654 spapr_drc_reset(drc
);
1660 static void spapr_machine_reset(MachineState
*machine
)
1662 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1663 PowerPCCPU
*first_ppc_cpu
;
1668 spapr_caps_apply(spapr
);
1670 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1671 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1672 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1673 spapr
->max_compat_pvr
)) {
1675 * If using KVM with radix mode available, VCPUs can be started
1676 * without a HPT because KVM will start them in radix mode.
1677 * Set the GR bit in PATE so that we know there is no HPT.
1679 spapr
->patb_entry
= PATE1_GR
;
1680 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1682 spapr_setup_hpt_and_vrma(spapr
);
1685 qemu_devices_reset();
1688 * If this reset wasn't generated by CAS, we should reset our
1689 * negotiated options and start from scratch
1691 if (!spapr
->cas_reboot
) {
1692 spapr_ovec_cleanup(spapr
->ov5_cas
);
1693 spapr
->ov5_cas
= spapr_ovec_new();
1695 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1699 * This is fixing some of the default configuration of the XIVE
1700 * devices. To be called after the reset of the machine devices.
1702 spapr_irq_reset(spapr
, &error_fatal
);
1705 * There is no CAS under qtest. Simulate one to please the code that
1706 * depends on spapr->ov5_cas. This is especially needed to test device
1707 * unplug, so we do that before resetting the DRCs.
1709 if (qtest_enabled()) {
1710 spapr_ovec_cleanup(spapr
->ov5_cas
);
1711 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1714 /* DRC reset may cause a device to be unplugged. This will cause troubles
1715 * if this device is used by another device (eg, a running vhost backend
1716 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1717 * situations, we reset DRCs after all devices have been reset.
1719 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1721 spapr_clear_pending_events(spapr
);
1724 * We place the device tree and RTAS just below either the top of the RMA,
1725 * or just below 2GB, whichever is lower, so that it can be
1726 * processed with 32-bit real mode code if necessary
1728 fdt_addr
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FDT_MAX_SIZE
;
1730 fdt
= spapr_build_fdt(spapr
);
1734 /* Should only fail if we've built a corrupted tree */
1737 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1738 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1739 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1744 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1745 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1746 g_free(spapr
->fdt_blob
);
1747 spapr
->fdt_size
= fdt_totalsize(fdt
);
1748 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1749 spapr
->fdt_blob
= fdt
;
1751 /* Set up the entry state */
1752 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1753 first_ppc_cpu
->env
.gpr
[5] = 0;
1755 spapr
->cas_reboot
= false;
1758 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1760 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1761 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1764 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1768 qdev_init_nofail(dev
);
1770 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1773 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1775 object_initialize_child(OBJECT(spapr
), "rtc",
1776 &spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1777 &error_fatal
, NULL
);
1778 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1780 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1781 "date", &error_fatal
);
1784 /* Returns whether we want to use VGA or not */
1785 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1787 switch (vga_interface_type
) {
1795 return pci_vga_init(pci_bus
) != NULL
;
1798 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1803 static int spapr_pre_load(void *opaque
)
1807 rc
= spapr_caps_pre_load(opaque
);
1815 static int spapr_post_load(void *opaque
, int version_id
)
1817 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1820 err
= spapr_caps_post_migration(spapr
);
1826 * In earlier versions, there was no separate qdev for the PAPR
1827 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1828 * So when migrating from those versions, poke the incoming offset
1829 * value into the RTC device
1831 if (version_id
< 3) {
1832 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1838 if (kvm_enabled() && spapr
->patb_entry
) {
1839 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1840 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1841 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1844 * Update LPCR:HR and UPRT as they may not be set properly in
1847 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1848 LPCR_HR
| LPCR_UPRT
);
1850 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1852 error_report("Process table config unsupported by the host");
1857 err
= spapr_irq_post_load(spapr
, version_id
);
1865 static int spapr_pre_save(void *opaque
)
1869 rc
= spapr_caps_pre_save(opaque
);
1877 static bool version_before_3(void *opaque
, int version_id
)
1879 return version_id
< 3;
1882 static bool spapr_pending_events_needed(void *opaque
)
1884 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1885 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1888 static const VMStateDescription vmstate_spapr_event_entry
= {
1889 .name
= "spapr_event_log_entry",
1891 .minimum_version_id
= 1,
1892 .fields
= (VMStateField
[]) {
1893 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1894 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1895 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1896 NULL
, extended_length
),
1897 VMSTATE_END_OF_LIST()
1901 static const VMStateDescription vmstate_spapr_pending_events
= {
1902 .name
= "spapr_pending_events",
1904 .minimum_version_id
= 1,
1905 .needed
= spapr_pending_events_needed
,
1906 .fields
= (VMStateField
[]) {
1907 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1908 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1909 VMSTATE_END_OF_LIST()
1913 static bool spapr_ov5_cas_needed(void *opaque
)
1915 SpaprMachineState
*spapr
= opaque
;
1916 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1917 SpaprOptionVector
*ov5_legacy
= spapr_ovec_new();
1918 SpaprOptionVector
*ov5_removed
= spapr_ovec_new();
1921 /* Prior to the introduction of SpaprOptionVector, we had two option
1922 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1923 * Both of these options encode machine topology into the device-tree
1924 * in such a way that the now-booted OS should still be able to interact
1925 * appropriately with QEMU regardless of what options were actually
1926 * negotiatied on the source side.
1928 * As such, we can avoid migrating the CAS-negotiated options if these
1929 * are the only options available on the current machine/platform.
1930 * Since these are the only options available for pseries-2.7 and
1931 * earlier, this allows us to maintain old->new/new->old migration
1934 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1935 * via default pseries-2.8 machines and explicit command-line parameters.
1936 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1937 * of the actual CAS-negotiated values to continue working properly. For
1938 * example, availability of memory unplug depends on knowing whether
1939 * OV5_HP_EVT was negotiated via CAS.
1941 * Thus, for any cases where the set of available CAS-negotiatable
1942 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1943 * include the CAS-negotiated options in the migration stream, unless
1944 * if they affect boot time behaviour only.
1946 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1947 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1948 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1950 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1951 * the mask itself since in the future it's possible "legacy" bits may be
1952 * removed via machine options, which could generate a false positive
1953 * that breaks migration.
1955 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
1956 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
1958 spapr_ovec_cleanup(ov5_mask
);
1959 spapr_ovec_cleanup(ov5_legacy
);
1960 spapr_ovec_cleanup(ov5_removed
);
1965 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1966 .name
= "spapr_option_vector_ov5_cas",
1968 .minimum_version_id
= 1,
1969 .needed
= spapr_ov5_cas_needed
,
1970 .fields
= (VMStateField
[]) {
1971 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1972 vmstate_spapr_ovec
, SpaprOptionVector
),
1973 VMSTATE_END_OF_LIST()
1977 static bool spapr_patb_entry_needed(void *opaque
)
1979 SpaprMachineState
*spapr
= opaque
;
1981 return !!spapr
->patb_entry
;
1984 static const VMStateDescription vmstate_spapr_patb_entry
= {
1985 .name
= "spapr_patb_entry",
1987 .minimum_version_id
= 1,
1988 .needed
= spapr_patb_entry_needed
,
1989 .fields
= (VMStateField
[]) {
1990 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1991 VMSTATE_END_OF_LIST()
1995 static bool spapr_irq_map_needed(void *opaque
)
1997 SpaprMachineState
*spapr
= opaque
;
1999 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
2002 static const VMStateDescription vmstate_spapr_irq_map
= {
2003 .name
= "spapr_irq_map",
2005 .minimum_version_id
= 1,
2006 .needed
= spapr_irq_map_needed
,
2007 .fields
= (VMStateField
[]) {
2008 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
2009 VMSTATE_END_OF_LIST()
2013 static bool spapr_dtb_needed(void *opaque
)
2015 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
2017 return smc
->update_dt_enabled
;
2020 static int spapr_dtb_pre_load(void *opaque
)
2022 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2024 g_free(spapr
->fdt_blob
);
2025 spapr
->fdt_blob
= NULL
;
2026 spapr
->fdt_size
= 0;
2031 static const VMStateDescription vmstate_spapr_dtb
= {
2032 .name
= "spapr_dtb",
2034 .minimum_version_id
= 1,
2035 .needed
= spapr_dtb_needed
,
2036 .pre_load
= spapr_dtb_pre_load
,
2037 .fields
= (VMStateField
[]) {
2038 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
2039 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
2040 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
2042 VMSTATE_END_OF_LIST()
2046 static const VMStateDescription vmstate_spapr
= {
2049 .minimum_version_id
= 1,
2050 .pre_load
= spapr_pre_load
,
2051 .post_load
= spapr_post_load
,
2052 .pre_save
= spapr_pre_save
,
2053 .fields
= (VMStateField
[]) {
2054 /* used to be @next_irq */
2055 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2058 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2060 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2061 VMSTATE_END_OF_LIST()
2063 .subsections
= (const VMStateDescription
*[]) {
2064 &vmstate_spapr_ov5_cas
,
2065 &vmstate_spapr_patb_entry
,
2066 &vmstate_spapr_pending_events
,
2067 &vmstate_spapr_cap_htm
,
2068 &vmstate_spapr_cap_vsx
,
2069 &vmstate_spapr_cap_dfp
,
2070 &vmstate_spapr_cap_cfpc
,
2071 &vmstate_spapr_cap_sbbc
,
2072 &vmstate_spapr_cap_ibs
,
2073 &vmstate_spapr_cap_hpt_maxpagesize
,
2074 &vmstate_spapr_irq_map
,
2075 &vmstate_spapr_cap_nested_kvm_hv
,
2077 &vmstate_spapr_cap_large_decr
,
2078 &vmstate_spapr_cap_ccf_assist
,
2083 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2085 SpaprMachineState
*spapr
= opaque
;
2087 /* "Iteration" header */
2088 if (!spapr
->htab_shift
) {
2089 qemu_put_be32(f
, -1);
2091 qemu_put_be32(f
, spapr
->htab_shift
);
2095 spapr
->htab_save_index
= 0;
2096 spapr
->htab_first_pass
= true;
2098 if (spapr
->htab_shift
) {
2099 assert(kvm_enabled());
2107 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2108 int chunkstart
, int n_valid
, int n_invalid
)
2110 qemu_put_be32(f
, chunkstart
);
2111 qemu_put_be16(f
, n_valid
);
2112 qemu_put_be16(f
, n_invalid
);
2113 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2114 HASH_PTE_SIZE_64
* n_valid
);
2117 static void htab_save_end_marker(QEMUFile
*f
)
2119 qemu_put_be32(f
, 0);
2120 qemu_put_be16(f
, 0);
2121 qemu_put_be16(f
, 0);
2124 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2127 bool has_timeout
= max_ns
!= -1;
2128 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2129 int index
= spapr
->htab_save_index
;
2130 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2132 assert(spapr
->htab_first_pass
);
2137 /* Consume invalid HPTEs */
2138 while ((index
< htabslots
)
2139 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2140 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2144 /* Consume valid HPTEs */
2146 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2147 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2148 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2152 if (index
> chunkstart
) {
2153 int n_valid
= index
- chunkstart
;
2155 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2158 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2162 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2164 if (index
>= htabslots
) {
2165 assert(index
== htabslots
);
2167 spapr
->htab_first_pass
= false;
2169 spapr
->htab_save_index
= index
;
2172 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2175 bool final
= max_ns
< 0;
2176 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2177 int examined
= 0, sent
= 0;
2178 int index
= spapr
->htab_save_index
;
2179 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2181 assert(!spapr
->htab_first_pass
);
2184 int chunkstart
, invalidstart
;
2186 /* Consume non-dirty HPTEs */
2187 while ((index
< htabslots
)
2188 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2194 /* Consume valid dirty HPTEs */
2195 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2196 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2197 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2198 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2203 invalidstart
= index
;
2204 /* Consume invalid dirty HPTEs */
2205 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2206 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2207 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2208 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2213 if (index
> chunkstart
) {
2214 int n_valid
= invalidstart
- chunkstart
;
2215 int n_invalid
= index
- invalidstart
;
2217 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2218 sent
+= index
- chunkstart
;
2220 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2225 if (examined
>= htabslots
) {
2229 if (index
>= htabslots
) {
2230 assert(index
== htabslots
);
2233 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2235 if (index
>= htabslots
) {
2236 assert(index
== htabslots
);
2240 spapr
->htab_save_index
= index
;
2242 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2245 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2246 #define MAX_KVM_BUF_SIZE 2048
2248 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2250 SpaprMachineState
*spapr
= opaque
;
2254 /* Iteration header */
2255 if (!spapr
->htab_shift
) {
2256 qemu_put_be32(f
, -1);
2259 qemu_put_be32(f
, 0);
2263 assert(kvm_enabled());
2265 fd
= get_htab_fd(spapr
);
2270 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2274 } else if (spapr
->htab_first_pass
) {
2275 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2277 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2280 htab_save_end_marker(f
);
2285 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2287 SpaprMachineState
*spapr
= opaque
;
2290 /* Iteration header */
2291 if (!spapr
->htab_shift
) {
2292 qemu_put_be32(f
, -1);
2295 qemu_put_be32(f
, 0);
2301 assert(kvm_enabled());
2303 fd
= get_htab_fd(spapr
);
2308 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2313 if (spapr
->htab_first_pass
) {
2314 htab_save_first_pass(f
, spapr
, -1);
2316 htab_save_later_pass(f
, spapr
, -1);
2320 htab_save_end_marker(f
);
2325 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2327 SpaprMachineState
*spapr
= opaque
;
2328 uint32_t section_hdr
;
2330 Error
*local_err
= NULL
;
2332 if (version_id
< 1 || version_id
> 1) {
2333 error_report("htab_load() bad version");
2337 section_hdr
= qemu_get_be32(f
);
2339 if (section_hdr
== -1) {
2340 spapr_free_hpt(spapr
);
2345 /* First section gives the htab size */
2346 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2348 error_report_err(local_err
);
2355 assert(kvm_enabled());
2357 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2359 error_report_err(local_err
);
2366 uint16_t n_valid
, n_invalid
;
2368 index
= qemu_get_be32(f
);
2369 n_valid
= qemu_get_be16(f
);
2370 n_invalid
= qemu_get_be16(f
);
2372 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2377 if ((index
+ n_valid
+ n_invalid
) >
2378 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2379 /* Bad index in stream */
2381 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2382 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2388 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2389 HASH_PTE_SIZE_64
* n_valid
);
2392 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2393 HASH_PTE_SIZE_64
* n_invalid
);
2400 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2415 static void htab_save_cleanup(void *opaque
)
2417 SpaprMachineState
*spapr
= opaque
;
2419 close_htab_fd(spapr
);
2422 static SaveVMHandlers savevm_htab_handlers
= {
2423 .save_setup
= htab_save_setup
,
2424 .save_live_iterate
= htab_save_iterate
,
2425 .save_live_complete_precopy
= htab_save_complete
,
2426 .save_cleanup
= htab_save_cleanup
,
2427 .load_state
= htab_load
,
2430 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2433 MachineState
*machine
= MACHINE(opaque
);
2434 machine
->boot_order
= g_strdup(boot_device
);
2437 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2439 MachineState
*machine
= MACHINE(spapr
);
2440 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2441 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2444 for (i
= 0; i
< nr_lmbs
; i
++) {
2447 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2448 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2454 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2455 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2456 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2458 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2462 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2463 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2464 " is not aligned to %" PRIu64
" MiB",
2466 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2470 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2471 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2472 " is not aligned to %" PRIu64
" MiB",
2474 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2478 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2479 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2481 "Node %d memory size 0x%" PRIx64
2482 " is not aligned to %" PRIu64
" MiB",
2483 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2484 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2490 /* find cpu slot in machine->possible_cpus by core_id */
2491 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2493 int index
= id
/ ms
->smp
.threads
;
2495 if (index
>= ms
->possible_cpus
->len
) {
2501 return &ms
->possible_cpus
->cpus
[index
];
2504 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2506 MachineState
*ms
= MACHINE(spapr
);
2507 Error
*local_err
= NULL
;
2508 bool vsmt_user
= !!spapr
->vsmt
;
2509 int kvm_smt
= kvmppc_smt_threads();
2511 unsigned int smp_threads
= ms
->smp
.threads
;
2513 if (!kvm_enabled() && (smp_threads
> 1)) {
2514 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2515 "on a pseries machine");
2518 if (!is_power_of_2(smp_threads
)) {
2519 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2520 "machine because it must be a power of 2", smp_threads
);
2524 /* Detemine the VSMT mode to use: */
2526 if (spapr
->vsmt
< smp_threads
) {
2527 error_setg(&local_err
, "Cannot support VSMT mode %d"
2528 " because it must be >= threads/core (%d)",
2529 spapr
->vsmt
, smp_threads
);
2532 /* In this case, spapr->vsmt has been set by the command line */
2535 * Default VSMT value is tricky, because we need it to be as
2536 * consistent as possible (for migration), but this requires
2537 * changing it for at least some existing cases. We pick 8 as
2538 * the value that we'd get with KVM on POWER8, the
2539 * overwhelmingly common case in production systems.
2541 spapr
->vsmt
= MAX(8, smp_threads
);
2544 /* KVM: If necessary, set the SMT mode: */
2545 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2546 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2548 /* Looks like KVM isn't able to change VSMT mode */
2549 error_setg(&local_err
,
2550 "Failed to set KVM's VSMT mode to %d (errno %d)",
2552 /* We can live with that if the default one is big enough
2553 * for the number of threads, and a submultiple of the one
2554 * we want. In this case we'll waste some vcpu ids, but
2555 * behaviour will be correct */
2556 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2557 warn_report_err(local_err
);
2562 error_append_hint(&local_err
,
2563 "On PPC, a VM with %d threads/core"
2564 " on a host with %d threads/core"
2565 " requires the use of VSMT mode %d.\n",
2566 smp_threads
, kvm_smt
, spapr
->vsmt
);
2568 kvmppc_hint_smt_possible(&local_err
);
2573 /* else TCG: nothing to do currently */
2575 error_propagate(errp
, local_err
);
2578 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2580 MachineState
*machine
= MACHINE(spapr
);
2581 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2582 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2583 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2584 const CPUArchIdList
*possible_cpus
;
2585 unsigned int smp_cpus
= machine
->smp
.cpus
;
2586 unsigned int smp_threads
= machine
->smp
.threads
;
2587 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2588 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2591 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2592 if (mc
->has_hotpluggable_cpus
) {
2593 if (smp_cpus
% smp_threads
) {
2594 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2595 smp_cpus
, smp_threads
);
2598 if (max_cpus
% smp_threads
) {
2599 error_report("max_cpus (%u) must be multiple of threads (%u)",
2600 max_cpus
, smp_threads
);
2604 if (max_cpus
!= smp_cpus
) {
2605 error_report("This machine version does not support CPU hotplug");
2608 boot_cores_nr
= possible_cpus
->len
;
2611 if (smc
->pre_2_10_has_unused_icps
) {
2614 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2615 /* Dummy entries get deregistered when real ICPState objects
2616 * are registered during CPU core hotplug.
2618 pre_2_10_vmstate_register_dummy_icp(i
);
2622 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2623 int core_id
= i
* smp_threads
;
2625 if (mc
->has_hotpluggable_cpus
) {
2626 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2627 spapr_vcpu_id(spapr
, core_id
));
2630 if (i
< boot_cores_nr
) {
2631 Object
*core
= object_new(type
);
2632 int nr_threads
= smp_threads
;
2634 /* Handle the partially filled core for older machine types */
2635 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2636 nr_threads
= smp_cpus
- i
* smp_threads
;
2639 object_property_set_int(core
, nr_threads
, "nr-threads",
2641 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2643 object_property_set_bool(core
, true, "realized", &error_fatal
);
2650 static PCIHostState
*spapr_create_default_phb(void)
2654 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2655 qdev_prop_set_uint32(dev
, "index", 0);
2656 qdev_init_nofail(dev
);
2658 return PCI_HOST_BRIDGE(dev
);
2661 /* pSeries LPAR / sPAPR hardware init */
2662 static void spapr_machine_init(MachineState
*machine
)
2664 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2665 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2666 const char *kernel_filename
= machine
->kernel_filename
;
2667 const char *initrd_filename
= machine
->initrd_filename
;
2670 MemoryRegion
*sysmem
= get_system_memory();
2671 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2672 hwaddr node0_size
= spapr_node0_size(machine
);
2673 long load_limit
, fw_size
;
2675 Error
*resize_hpt_err
= NULL
;
2677 msi_nonbroken
= true;
2679 QLIST_INIT(&spapr
->phbs
);
2680 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2682 /* Determine capabilities to run with */
2683 spapr_caps_init(spapr
);
2685 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2686 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2688 * If the user explicitly requested a mode we should either
2689 * supply it, or fail completely (which we do below). But if
2690 * it's not set explicitly, we reset our mode to something
2693 if (resize_hpt_err
) {
2694 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2695 error_free(resize_hpt_err
);
2696 resize_hpt_err
= NULL
;
2698 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2702 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2704 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2706 * User requested HPT resize, but this host can't supply it. Bail out
2708 error_report_err(resize_hpt_err
);
2712 spapr
->rma_size
= node0_size
;
2714 /* With KVM, we don't actually know whether KVM supports an
2715 * unbounded RMA (PR KVM) or is limited by the hash table size
2716 * (HV KVM using VRMA), so we always assume the latter
2718 * In that case, we also limit the initial allocations for RTAS
2719 * etc... to 256M since we have no way to know what the VRMA size
2720 * is going to be as it depends on the size of the hash table
2721 * which isn't determined yet.
2723 if (kvm_enabled()) {
2724 spapr
->vrma_adjust
= 1;
2725 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2728 /* Actually we don't support unbounded RMA anymore since we added
2729 * proper emulation of HV mode. The max we can get is 16G which
2730 * also happens to be what we configure for PAPR mode so make sure
2731 * we don't do anything bigger than that
2733 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2735 if (spapr
->rma_size
> node0_size
) {
2736 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2741 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2742 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2745 * VSMT must be set in order to be able to compute VCPU ids, ie to
2746 * call spapr_max_server_number() or spapr_vcpu_id().
2748 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2750 /* Set up Interrupt Controller before we create the VCPUs */
2751 spapr_irq_init(spapr
, &error_fatal
);
2753 /* Set up containers for ibm,client-architecture-support negotiated options
2755 spapr
->ov5
= spapr_ovec_new();
2756 spapr
->ov5_cas
= spapr_ovec_new();
2758 if (smc
->dr_lmb_enabled
) {
2759 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2760 spapr_validate_node_memory(machine
, &error_fatal
);
2763 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2765 /* advertise support for dedicated HP event source to guests */
2766 if (spapr
->use_hotplug_event_source
) {
2767 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2770 /* advertise support for HPT resizing */
2771 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2772 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2775 /* advertise support for ibm,dyamic-memory-v2 */
2776 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2778 /* advertise XIVE on POWER9 machines */
2779 if (spapr
->irq
->xive
) {
2780 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2784 spapr_init_cpus(spapr
);
2787 * check we don't have a memory-less/cpu-less NUMA node
2788 * Firmware relies on the existing memory/cpu topology to provide the
2789 * NUMA topology to the kernel.
2790 * And the linux kernel needs to know the NUMA topology at start
2791 * to be able to hotplug CPUs later.
2793 if (machine
->numa_state
->num_nodes
) {
2794 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
2795 /* check for memory-less node */
2796 if (machine
->numa_state
->nodes
[i
].node_mem
== 0) {
2799 /* check for cpu-less node */
2801 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2802 if (cpu
->node_id
== i
) {
2807 /* memory-less and cpu-less node */
2810 "Memory-less/cpu-less nodes are not supported (node %d)",
2820 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2821 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2822 * called from vPHB reset handler so we initialize the counter here.
2823 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2824 * must be equally distant from any other node.
2825 * The final value of spapr->gpu_numa_id is going to be written to
2826 * max-associativity-domains in spapr_build_fdt().
2828 spapr
->gpu_numa_id
= MAX(1, machine
->numa_state
->num_nodes
);
2830 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2831 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2832 spapr
->max_compat_pvr
)) {
2833 /* KVM and TCG always allow GTSE with radix... */
2834 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2836 /* ... but not with hash (currently). */
2838 if (kvm_enabled()) {
2839 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2840 kvmppc_enable_logical_ci_hcalls();
2841 kvmppc_enable_set_mode_hcall();
2843 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2844 kvmppc_enable_clear_ref_mod_hcalls();
2846 /* Enable H_PAGE_INIT */
2847 kvmppc_enable_h_page_init();
2851 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2853 memory_region_add_subregion(sysmem
, 0, ram
);
2855 /* always allocate the device memory information */
2856 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2858 /* initialize hotplug memory address space */
2859 if (machine
->ram_size
< machine
->maxram_size
) {
2860 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2862 * Limit the number of hotpluggable memory slots to half the number
2863 * slots that KVM supports, leaving the other half for PCI and other
2864 * devices. However ensure that number of slots doesn't drop below 32.
2866 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2867 SPAPR_MAX_RAM_SLOTS
;
2869 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2870 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2872 if (machine
->ram_slots
> max_memslots
) {
2873 error_report("Specified number of memory slots %"
2874 PRIu64
" exceeds max supported %d",
2875 machine
->ram_slots
, max_memslots
);
2879 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2880 SPAPR_DEVICE_MEM_ALIGN
);
2881 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2882 "device-memory", device_mem_size
);
2883 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2884 &machine
->device_memory
->mr
);
2887 if (smc
->dr_lmb_enabled
) {
2888 spapr_create_lmb_dr_connectors(spapr
);
2891 /* Set up RTAS event infrastructure */
2892 spapr_events_init(spapr
);
2894 /* Set up the RTC RTAS interfaces */
2895 spapr_rtc_create(spapr
);
2897 /* Set up VIO bus */
2898 spapr
->vio_bus
= spapr_vio_bus_init();
2900 for (i
= 0; i
< serial_max_hds(); i
++) {
2902 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2906 /* We always have at least the nvram device on VIO */
2907 spapr_create_nvram(spapr
);
2910 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2911 * connectors (described in root DT node's "ibm,drc-types" property)
2912 * are pre-initialized here. additional child connectors (such as
2913 * connectors for a PHBs PCI slots) are added as needed during their
2914 * parent's realization.
2916 if (smc
->dr_phb_enabled
) {
2917 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2918 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2923 spapr_pci_rtas_init();
2925 phb
= spapr_create_default_phb();
2927 for (i
= 0; i
< nb_nics
; i
++) {
2928 NICInfo
*nd
= &nd_table
[i
];
2931 nd
->model
= g_strdup("spapr-vlan");
2934 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2935 g_str_equal(nd
->model
, "ibmveth")) {
2936 spapr_vlan_create(spapr
->vio_bus
, nd
);
2938 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2942 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2943 spapr_vscsi_create(spapr
->vio_bus
);
2947 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2948 spapr
->has_graphics
= true;
2949 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2953 if (smc
->use_ohci_by_default
) {
2954 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2956 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2959 if (spapr
->has_graphics
) {
2960 USBBus
*usb_bus
= usb_bus_find(-1);
2962 usb_create_simple(usb_bus
, "usb-kbd");
2963 usb_create_simple(usb_bus
, "usb-mouse");
2967 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
2969 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2974 if (kernel_filename
) {
2975 uint64_t lowaddr
= 0;
2977 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2978 translate_kernel_address
, NULL
,
2979 NULL
, &lowaddr
, NULL
, 1,
2980 PPC_ELF_MACHINE
, 0, 0);
2981 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2982 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2983 translate_kernel_address
, NULL
, NULL
,
2984 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
2986 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2988 if (spapr
->kernel_size
< 0) {
2989 error_report("error loading %s: %s", kernel_filename
,
2990 load_elf_strerror(spapr
->kernel_size
));
2995 if (initrd_filename
) {
2996 /* Try to locate the initrd in the gap between the kernel
2997 * and the firmware. Add a bit of space just in case
2999 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
3000 + 0x1ffff) & ~0xffff;
3001 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
3004 - spapr
->initrd_base
);
3005 if (spapr
->initrd_size
< 0) {
3006 error_report("could not load initial ram disk '%s'",
3013 if (bios_name
== NULL
) {
3014 bios_name
= FW_FILE_NAME
;
3016 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
3018 error_report("Could not find LPAR firmware '%s'", bios_name
);
3021 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
3023 error_report("Could not load LPAR firmware '%s'", filename
);
3028 /* FIXME: Should register things through the MachineState's qdev
3029 * interface, this is a legacy from the sPAPREnvironment structure
3030 * which predated MachineState but had a similar function */
3031 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3032 register_savevm_live("spapr/htab", -1, 1,
3033 &savevm_htab_handlers
, spapr
);
3035 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
),
3038 qemu_register_boot_set(spapr_boot_set
, spapr
);
3041 * Nothing needs to be done to resume a suspended guest because
3042 * suspending does not change the machine state, so no need for
3043 * a ->wakeup method.
3045 qemu_register_wakeup_support();
3047 if (kvm_enabled()) {
3048 /* to stop and start vmclock */
3049 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3052 kvmppc_spapr_enable_inkernel_multitce();
3056 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3062 if (!strcmp(vm_type
, "HV")) {
3066 if (!strcmp(vm_type
, "PR")) {
3070 error_report("Unknown kvm-type specified '%s'", vm_type
);
3075 * Implementation of an interface to adjust firmware path
3076 * for the bootindex property handling.
3078 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3081 #define CAST(type, obj, name) \
3082 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3083 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3084 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3085 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3088 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3089 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3090 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3094 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3095 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3096 * 0x8000 | (target << 8) | (bus << 5) | lun
3097 * (see the "Logical unit addressing format" table in SAM5)
3099 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3100 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3101 (uint64_t)id
<< 48);
3102 } else if (virtio
) {
3104 * We use SRP luns of the form 01000000 | (target << 8) | lun
3105 * in the top 32 bits of the 64-bit LUN
3106 * Note: the quote above is from SLOF and it is wrong,
3107 * the actual binding is:
3108 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3110 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3111 if (d
->lun
>= 256) {
3112 /* Use the LUN "flat space addressing method" */
3115 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3116 (uint64_t)id
<< 32);
3119 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3120 * in the top 32 bits of the 64-bit LUN
3122 unsigned usb_port
= atoi(usb
->port
->path
);
3123 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3124 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3125 (uint64_t)id
<< 32);
3130 * SLOF probes the USB devices, and if it recognizes that the device is a
3131 * storage device, it changes its name to "storage" instead of "usb-host",
3132 * and additionally adds a child node for the SCSI LUN, so the correct
3133 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3135 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3136 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3137 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3138 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3143 /* Replace "pci" with "pci@800000020000000" */
3144 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3148 /* Same logic as virtio above */
3149 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3150 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3153 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3154 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3155 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3156 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3162 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3164 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3166 return g_strdup(spapr
->kvm_type
);
3169 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3171 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3173 g_free(spapr
->kvm_type
);
3174 spapr
->kvm_type
= g_strdup(value
);
3177 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3179 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3181 return spapr
->use_hotplug_event_source
;
3184 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3187 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3189 spapr
->use_hotplug_event_source
= value
;
3192 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3197 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3199 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3201 switch (spapr
->resize_hpt
) {
3202 case SPAPR_RESIZE_HPT_DEFAULT
:
3203 return g_strdup("default");
3204 case SPAPR_RESIZE_HPT_DISABLED
:
3205 return g_strdup("disabled");
3206 case SPAPR_RESIZE_HPT_ENABLED
:
3207 return g_strdup("enabled");
3208 case SPAPR_RESIZE_HPT_REQUIRED
:
3209 return g_strdup("required");
3211 g_assert_not_reached();
3214 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3216 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3218 if (strcmp(value
, "default") == 0) {
3219 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3220 } else if (strcmp(value
, "disabled") == 0) {
3221 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3222 } else if (strcmp(value
, "enabled") == 0) {
3223 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3224 } else if (strcmp(value
, "required") == 0) {
3225 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3227 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3231 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3232 void *opaque
, Error
**errp
)
3234 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3237 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3238 void *opaque
, Error
**errp
)
3240 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3243 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3245 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3247 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3248 return g_strdup("legacy");
3249 } else if (spapr
->irq
== &spapr_irq_xics
) {
3250 return g_strdup("xics");
3251 } else if (spapr
->irq
== &spapr_irq_xive
) {
3252 return g_strdup("xive");
3253 } else if (spapr
->irq
== &spapr_irq_dual
) {
3254 return g_strdup("dual");
3256 g_assert_not_reached();
3259 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3261 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3263 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3264 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3268 /* The legacy IRQ backend can not be set */
3269 if (strcmp(value
, "xics") == 0) {
3270 spapr
->irq
= &spapr_irq_xics
;
3271 } else if (strcmp(value
, "xive") == 0) {
3272 spapr
->irq
= &spapr_irq_xive
;
3273 } else if (strcmp(value
, "dual") == 0) {
3274 spapr
->irq
= &spapr_irq_dual
;
3276 error_setg(errp
, "Bad value for \"ic-mode\" property");
3280 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3282 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3284 return g_strdup(spapr
->host_model
);
3287 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3289 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3291 g_free(spapr
->host_model
);
3292 spapr
->host_model
= g_strdup(value
);
3295 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3297 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3299 return g_strdup(spapr
->host_serial
);
3302 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3304 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3306 g_free(spapr
->host_serial
);
3307 spapr
->host_serial
= g_strdup(value
);
3310 static void spapr_instance_init(Object
*obj
)
3312 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3313 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3315 spapr
->htab_fd
= -1;
3316 spapr
->use_hotplug_event_source
= true;
3317 object_property_add_str(obj
, "kvm-type",
3318 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3319 object_property_set_description(obj
, "kvm-type",
3320 "Specifies the KVM virtualization mode (HV, PR)",
3322 object_property_add_bool(obj
, "modern-hotplug-events",
3323 spapr_get_modern_hotplug_events
,
3324 spapr_set_modern_hotplug_events
,
3326 object_property_set_description(obj
, "modern-hotplug-events",
3327 "Use dedicated hotplug event mechanism in"
3328 " place of standard EPOW events when possible"
3329 " (required for memory hot-unplug support)",
3331 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3332 "Maximum permitted CPU compatibility mode",
3335 object_property_add_str(obj
, "resize-hpt",
3336 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3337 object_property_set_description(obj
, "resize-hpt",
3338 "Resizing of the Hash Page Table (enabled, disabled, required)",
3340 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3341 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3342 object_property_set_description(obj
, "vsmt",
3343 "Virtual SMT: KVM behaves as if this were"
3344 " the host's SMT mode", &error_abort
);
3345 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3346 spapr_get_msix_emulation
, NULL
, NULL
);
3348 /* The machine class defines the default interrupt controller mode */
3349 spapr
->irq
= smc
->irq
;
3350 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3351 spapr_set_ic_mode
, NULL
);
3352 object_property_set_description(obj
, "ic-mode",
3353 "Specifies the interrupt controller mode (xics, xive, dual)",
3356 object_property_add_str(obj
, "host-model",
3357 spapr_get_host_model
, spapr_set_host_model
,
3359 object_property_set_description(obj
, "host-model",
3360 "Host model to advertise in guest device tree", &error_abort
);
3361 object_property_add_str(obj
, "host-serial",
3362 spapr_get_host_serial
, spapr_set_host_serial
,
3364 object_property_set_description(obj
, "host-serial",
3365 "Host serial number to advertise in guest device tree", &error_abort
);
3368 static void spapr_machine_finalizefn(Object
*obj
)
3370 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3372 g_free(spapr
->kvm_type
);
3375 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3377 cpu_synchronize_state(cs
);
3378 ppc_cpu_do_system_reset(cs
);
3381 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3386 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3390 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3391 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3396 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3397 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3399 *fdt_start_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3400 SPAPR_MEMORY_BLOCK_SIZE
);
3404 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3405 bool dedicated_hp_event_source
, Error
**errp
)
3408 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3410 uint64_t addr
= addr_start
;
3411 bool hotplugged
= spapr_drc_hotplugged(dev
);
3412 Error
*local_err
= NULL
;
3414 for (i
= 0; i
< nr_lmbs
; i
++) {
3415 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3416 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3419 spapr_drc_attach(drc
, dev
, &local_err
);
3421 while (addr
> addr_start
) {
3422 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3423 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3424 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3425 spapr_drc_detach(drc
);
3427 error_propagate(errp
, local_err
);
3431 spapr_drc_reset(drc
);
3433 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3435 /* send hotplug notification to the
3436 * guest only in case of hotplugged memory
3439 if (dedicated_hp_event_source
) {
3440 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3441 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3442 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3444 spapr_drc_index(drc
));
3446 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3452 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3455 Error
*local_err
= NULL
;
3456 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3457 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3458 uint64_t size
, addr
;
3460 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3462 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3467 addr
= object_property_get_uint(OBJECT(dimm
),
3468 PC_DIMM_ADDR_PROP
, &local_err
);
3473 spapr_add_lmbs(dev
, addr
, size
, spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3482 pc_dimm_unplug(dimm
, MACHINE(ms
));
3484 error_propagate(errp
, local_err
);
3487 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3490 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3491 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3492 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3493 Error
*local_err
= NULL
;
3498 if (!smc
->dr_lmb_enabled
) {
3499 error_setg(errp
, "Memory hotplug not supported for this machine");
3503 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3505 error_propagate(errp
, local_err
);
3509 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3510 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3511 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3515 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3517 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3518 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3520 error_propagate(errp
, local_err
);
3524 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3527 struct SpaprDimmState
{
3530 QTAILQ_ENTRY(SpaprDimmState
) next
;
3533 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3536 SpaprDimmState
*dimm_state
= NULL
;
3538 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3539 if (dimm_state
->dimm
== dimm
) {
3546 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3550 SpaprDimmState
*ds
= NULL
;
3553 * If this request is for a DIMM whose removal had failed earlier
3554 * (due to guest's refusal to remove the LMBs), we would have this
3555 * dimm already in the pending_dimm_unplugs list. In that
3556 * case don't add again.
3558 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3560 ds
= g_malloc0(sizeof(SpaprDimmState
));
3561 ds
->nr_lmbs
= nr_lmbs
;
3563 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3568 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3569 SpaprDimmState
*dimm_state
)
3571 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3575 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3579 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3581 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3582 uint32_t avail_lmbs
= 0;
3583 uint64_t addr_start
, addr
;
3586 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3590 for (i
= 0; i
< nr_lmbs
; i
++) {
3591 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3592 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3597 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3600 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3603 /* Callback to be called during DRC release. */
3604 void spapr_lmb_release(DeviceState
*dev
)
3606 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3607 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3608 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3610 /* This information will get lost if a migration occurs
3611 * during the unplug process. In this case recover it. */
3613 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3615 /* The DRC being examined by the caller at least must be counted */
3616 g_assert(ds
->nr_lmbs
);
3619 if (--ds
->nr_lmbs
) {
3624 * Now that all the LMBs have been removed by the guest, call the
3625 * unplug handler chain. This can never fail.
3627 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3628 object_unparent(OBJECT(dev
));
3631 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3633 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3634 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3636 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3637 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3638 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3641 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3642 DeviceState
*dev
, Error
**errp
)
3644 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3645 Error
*local_err
= NULL
;
3646 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3648 uint64_t size
, addr_start
, addr
;
3652 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3653 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3655 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3662 * An existing pending dimm state for this DIMM means that there is an
3663 * unplug operation in progress, waiting for the spapr_lmb_release
3664 * callback to complete the job (BQL can't cover that far). In this case,
3665 * bail out to avoid detaching DRCs that were already released.
3667 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3668 error_setg(&local_err
,
3669 "Memory unplug already in progress for device %s",
3674 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3677 for (i
= 0; i
< nr_lmbs
; i
++) {
3678 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3679 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3682 spapr_drc_detach(drc
);
3683 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3686 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3687 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3688 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3689 nr_lmbs
, spapr_drc_index(drc
));
3691 error_propagate(errp
, local_err
);
3694 /* Callback to be called during DRC release. */
3695 void spapr_core_release(DeviceState
*dev
)
3697 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3699 /* Call the unplug handler chain. This can never fail. */
3700 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3701 object_unparent(OBJECT(dev
));
3704 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3706 MachineState
*ms
= MACHINE(hotplug_dev
);
3707 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3708 CPUCore
*cc
= CPU_CORE(dev
);
3709 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3711 if (smc
->pre_2_10_has_unused_icps
) {
3712 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3715 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3716 CPUState
*cs
= CPU(sc
->threads
[i
]);
3718 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3723 core_slot
->cpu
= NULL
;
3724 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3728 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3731 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3734 CPUCore
*cc
= CPU_CORE(dev
);
3736 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3737 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3742 error_setg(errp
, "Boot CPU core may not be unplugged");
3746 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3747 spapr_vcpu_id(spapr
, cc
->core_id
));
3750 spapr_drc_detach(drc
);
3752 spapr_hotplug_req_remove_by_index(drc
);
3755 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3756 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3758 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3759 CPUState
*cs
= CPU(core
->threads
[0]);
3760 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3761 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3762 int id
= spapr_get_vcpu_id(cpu
);
3766 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3767 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3770 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3772 *fdt_start_offset
= offset
;
3776 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3779 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3780 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3781 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3782 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3783 CPUCore
*cc
= CPU_CORE(dev
);
3786 Error
*local_err
= NULL
;
3787 CPUArchId
*core_slot
;
3789 bool hotplugged
= spapr_drc_hotplugged(dev
);
3792 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3794 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3798 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3799 spapr_vcpu_id(spapr
, cc
->core_id
));
3801 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3804 spapr_drc_attach(drc
, dev
, &local_err
);
3806 error_propagate(errp
, local_err
);
3812 * Send hotplug notification interrupt to the guest only
3813 * in case of hotplugged CPUs.
3815 spapr_hotplug_req_add_by_index(drc
);
3817 spapr_drc_reset(drc
);
3821 core_slot
->cpu
= OBJECT(dev
);
3823 if (smc
->pre_2_10_has_unused_icps
) {
3824 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3825 cs
= CPU(core
->threads
[i
]);
3826 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3831 * Set compatibility mode to match the boot CPU, which was either set
3832 * by the machine reset code or by CAS.
3835 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3836 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3839 error_propagate(errp
, local_err
);
3846 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3849 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3850 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3851 Error
*local_err
= NULL
;
3852 CPUCore
*cc
= CPU_CORE(dev
);
3853 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3854 const char *type
= object_get_typename(OBJECT(dev
));
3855 CPUArchId
*core_slot
;
3857 unsigned int smp_threads
= machine
->smp
.threads
;
3859 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3860 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3864 if (strcmp(base_core_type
, type
)) {
3865 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3869 if (cc
->core_id
% smp_threads
) {
3870 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3875 * In general we should have homogeneous threads-per-core, but old
3876 * (pre hotplug support) machine types allow the last core to have
3877 * reduced threads as a compatibility hack for when we allowed
3878 * total vcpus not a multiple of threads-per-core.
3880 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3881 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3882 cc
->nr_threads
, smp_threads
);
3886 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3888 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3892 if (core_slot
->cpu
) {
3893 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3897 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3900 error_propagate(errp
, local_err
);
3903 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3904 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3906 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3909 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3910 if (intc_phandle
<= 0) {
3914 if (spapr_dt_phb(sphb
, intc_phandle
, fdt
, spapr
->irq
->nr_msis
,
3915 fdt_start_offset
)) {
3916 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
3920 /* generally SLOF creates these, for hotplug it's up to QEMU */
3921 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
3926 static void spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3929 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3930 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3931 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3932 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
3934 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
3935 error_setg(errp
, "PHB hotplug not supported for this machine");
3939 if (sphb
->index
== (uint32_t)-1) {
3940 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
3945 * This will check that sphb->index doesn't exceed the maximum number of
3946 * PHBs for the current machine type.
3948 smc
->phb_placement(spapr
, sphb
->index
,
3949 &sphb
->buid
, &sphb
->io_win_addr
,
3950 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
3951 windows_supported
, sphb
->dma_liobn
,
3952 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
3956 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3959 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3960 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3961 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3963 bool hotplugged
= spapr_drc_hotplugged(dev
);
3964 Error
*local_err
= NULL
;
3966 if (!smc
->dr_phb_enabled
) {
3970 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3971 /* hotplug hooks should check it's enabled before getting this far */
3974 spapr_drc_attach(drc
, DEVICE(dev
), &local_err
);
3976 error_propagate(errp
, local_err
);
3981 spapr_hotplug_req_add_by_index(drc
);
3983 spapr_drc_reset(drc
);
3987 void spapr_phb_release(DeviceState
*dev
)
3989 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3991 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3992 object_unparent(OBJECT(dev
));
3995 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3997 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4000 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4001 DeviceState
*dev
, Error
**errp
)
4003 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4006 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4009 if (!spapr_drc_unplug_requested(drc
)) {
4010 spapr_drc_detach(drc
);
4011 spapr_hotplug_req_remove_by_index(drc
);
4015 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4018 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4019 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4021 if (spapr
->tpm_proxy
!= NULL
) {
4022 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4026 spapr
->tpm_proxy
= tpm_proxy
;
4029 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4031 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4033 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4034 object_unparent(OBJECT(dev
));
4035 spapr
->tpm_proxy
= NULL
;
4038 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4039 DeviceState
*dev
, Error
**errp
)
4041 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4042 spapr_memory_plug(hotplug_dev
, dev
, errp
);
4043 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4044 spapr_core_plug(hotplug_dev
, dev
, errp
);
4045 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4046 spapr_phb_plug(hotplug_dev
, dev
, errp
);
4047 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4048 spapr_tpm_proxy_plug(hotplug_dev
, dev
, errp
);
4052 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4053 DeviceState
*dev
, Error
**errp
)
4055 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4056 spapr_memory_unplug(hotplug_dev
, dev
);
4057 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4058 spapr_core_unplug(hotplug_dev
, dev
);
4059 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4060 spapr_phb_unplug(hotplug_dev
, dev
);
4061 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4062 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4066 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4067 DeviceState
*dev
, Error
**errp
)
4069 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4070 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4071 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4073 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4074 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
4075 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4077 /* NOTE: this means there is a window after guest reset, prior to
4078 * CAS negotiation, where unplug requests will fail due to the
4079 * capability not being detected yet. This is a bit different than
4080 * the case with PCI unplug, where the events will be queued and
4081 * eventually handled by the guest after boot
4083 error_setg(errp
, "Memory hot unplug not supported for this guest");
4085 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4086 if (!mc
->has_hotpluggable_cpus
) {
4087 error_setg(errp
, "CPU hot unplug not supported on this machine");
4090 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4091 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4092 if (!smc
->dr_phb_enabled
) {
4093 error_setg(errp
, "PHB hot unplug not supported on this machine");
4096 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4097 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4098 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4102 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4103 DeviceState
*dev
, Error
**errp
)
4105 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4106 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4107 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4108 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4109 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4110 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4114 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4117 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4118 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4119 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4120 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4121 return HOTPLUG_HANDLER(machine
);
4123 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4124 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4125 PCIBus
*root
= pci_device_root_bus(pcidev
);
4126 SpaprPhbState
*phb
=
4127 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4128 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4131 return HOTPLUG_HANDLER(phb
);
4137 static CpuInstanceProperties
4138 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4140 CPUArchId
*core_slot
;
4141 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4143 /* make sure possible_cpu are intialized */
4144 mc
->possible_cpu_arch_ids(machine
);
4145 /* get CPU core slot containing thread that matches cpu_index */
4146 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4148 return core_slot
->props
;
4151 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4153 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4156 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4159 unsigned int smp_threads
= machine
->smp
.threads
;
4160 unsigned int smp_cpus
= machine
->smp
.cpus
;
4161 const char *core_type
;
4162 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4163 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4165 if (!mc
->has_hotpluggable_cpus
) {
4166 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4168 if (machine
->possible_cpus
) {
4169 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4170 return machine
->possible_cpus
;
4173 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4175 error_report("Unable to find sPAPR CPU Core definition");
4179 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4180 sizeof(CPUArchId
) * spapr_max_cores
);
4181 machine
->possible_cpus
->len
= spapr_max_cores
;
4182 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4183 int core_id
= i
* smp_threads
;
4185 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4186 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4187 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4188 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4189 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4191 return machine
->possible_cpus
;
4194 static void spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4195 uint64_t *buid
, hwaddr
*pio
,
4196 hwaddr
*mmio32
, hwaddr
*mmio64
,
4197 unsigned n_dma
, uint32_t *liobns
,
4198 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4201 * New-style PHB window placement.
4203 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4204 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4207 * Some guest kernels can't work with MMIO windows above 1<<46
4208 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4210 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4211 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4212 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4213 * 1TiB 64-bit MMIO windows for each PHB.
4215 const uint64_t base_buid
= 0x800000020000000ULL
;
4218 /* Sanity check natural alignments */
4219 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4220 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4221 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4222 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4223 /* Sanity check bounds */
4224 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4225 SPAPR_PCI_MEM32_WIN_SIZE
);
4226 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4227 SPAPR_PCI_MEM64_WIN_SIZE
);
4229 if (index
>= SPAPR_MAX_PHBS
) {
4230 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4231 SPAPR_MAX_PHBS
- 1);
4235 *buid
= base_buid
+ index
;
4236 for (i
= 0; i
< n_dma
; ++i
) {
4237 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4240 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4241 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4242 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4244 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4245 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4248 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4250 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4252 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4255 static void spapr_ics_resend(XICSFabric
*dev
)
4257 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4259 ics_resend(spapr
->ics
);
4262 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4264 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4266 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4269 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4272 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4274 spapr
->irq
->print_info(spapr
, mon
);
4275 monitor_printf(mon
, "irqchip: %s\n",
4276 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4279 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4281 return cpu
->vcpu_id
;
4284 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4286 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4287 MachineState
*ms
= MACHINE(spapr
);
4290 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4292 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4293 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4294 error_append_hint(errp
, "Adjust the number of cpus to %d "
4295 "or try to raise the number of threads per core\n",
4296 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4300 cpu
->vcpu_id
= vcpu_id
;
4303 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4308 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4310 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4318 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4320 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4322 /* These are only called by TCG, KVM maintains dispatch state */
4324 spapr_cpu
->prod
= false;
4325 if (spapr_cpu
->vpa_addr
) {
4326 CPUState
*cs
= CPU(cpu
);
4329 dispatch
= ldl_be_phys(cs
->as
,
4330 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4332 if ((dispatch
& 1) != 0) {
4333 qemu_log_mask(LOG_GUEST_ERROR
,
4334 "VPA: incorrect dispatch counter value for "
4335 "dispatched partition %u, correcting.\n", dispatch
);
4339 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4343 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4345 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4347 if (spapr_cpu
->vpa_addr
) {
4348 CPUState
*cs
= CPU(cpu
);
4351 dispatch
= ldl_be_phys(cs
->as
,
4352 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4354 if ((dispatch
& 1) != 1) {
4355 qemu_log_mask(LOG_GUEST_ERROR
,
4356 "VPA: incorrect dispatch counter value for "
4357 "preempted partition %u, correcting.\n", dispatch
);
4361 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4365 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4367 MachineClass
*mc
= MACHINE_CLASS(oc
);
4368 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4369 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4370 NMIClass
*nc
= NMI_CLASS(oc
);
4371 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4372 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4373 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4374 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4376 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4377 mc
->ignore_boot_device_suffixes
= true;
4380 * We set up the default / latest behaviour here. The class_init
4381 * functions for the specific versioned machine types can override
4382 * these details for backwards compatibility
4384 mc
->init
= spapr_machine_init
;
4385 mc
->reset
= spapr_machine_reset
;
4386 mc
->block_default_type
= IF_SCSI
;
4387 mc
->max_cpus
= 1024;
4388 mc
->no_parallel
= 1;
4389 mc
->default_boot_order
= "";
4390 mc
->default_ram_size
= 512 * MiB
;
4391 mc
->default_display
= "std";
4392 mc
->kvm_type
= spapr_kvm_type
;
4393 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4394 mc
->pci_allow_0_address
= true;
4395 assert(!mc
->get_hotplug_handler
);
4396 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4397 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4398 hc
->plug
= spapr_machine_device_plug
;
4399 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4400 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4401 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4402 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4403 hc
->unplug
= spapr_machine_device_unplug
;
4405 smc
->dr_lmb_enabled
= true;
4406 smc
->update_dt_enabled
= true;
4407 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4408 mc
->has_hotpluggable_cpus
= true;
4409 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4410 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4411 nc
->nmi_monitor_handler
= spapr_nmi
;
4412 smc
->phb_placement
= spapr_phb_placement
;
4413 vhc
->hypercall
= emulate_spapr_hypercall
;
4414 vhc
->hpt_mask
= spapr_hpt_mask
;
4415 vhc
->map_hptes
= spapr_map_hptes
;
4416 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4417 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4418 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4419 vhc
->get_pate
= spapr_get_pate
;
4420 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4421 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4422 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4423 xic
->ics_get
= spapr_ics_get
;
4424 xic
->ics_resend
= spapr_ics_resend
;
4425 xic
->icp_get
= spapr_icp_get
;
4426 ispc
->print_info
= spapr_pic_print_info
;
4427 /* Force NUMA node memory size to be a multiple of
4428 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4429 * in which LMBs are represented and hot-added
4431 mc
->numa_mem_align_shift
= 28;
4432 mc
->numa_mem_supported
= true;
4434 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4435 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4436 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4437 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4438 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4439 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4440 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4441 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4442 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4443 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4444 spapr_caps_add_properties(smc
, &error_abort
);
4445 smc
->irq
= &spapr_irq_dual
;
4446 smc
->dr_phb_enabled
= true;
4447 smc
->linux_pci_probe
= true;
4450 static const TypeInfo spapr_machine_info
= {
4451 .name
= TYPE_SPAPR_MACHINE
,
4452 .parent
= TYPE_MACHINE
,
4454 .instance_size
= sizeof(SpaprMachineState
),
4455 .instance_init
= spapr_instance_init
,
4456 .instance_finalize
= spapr_machine_finalizefn
,
4457 .class_size
= sizeof(SpaprMachineClass
),
4458 .class_init
= spapr_machine_class_init
,
4459 .interfaces
= (InterfaceInfo
[]) {
4460 { TYPE_FW_PATH_PROVIDER
},
4462 { TYPE_HOTPLUG_HANDLER
},
4463 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4464 { TYPE_XICS_FABRIC
},
4465 { TYPE_INTERRUPT_STATS_PROVIDER
},
4470 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4471 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4474 MachineClass *mc = MACHINE_CLASS(oc); \
4475 spapr_machine_##suffix##_class_options(mc); \
4477 mc->alias = "pseries"; \
4478 mc->is_default = 1; \
4481 static const TypeInfo spapr_machine_##suffix##_info = { \
4482 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4483 .parent = TYPE_SPAPR_MACHINE, \
4484 .class_init = spapr_machine_##suffix##_class_init, \
4486 static void spapr_machine_register_##suffix(void) \
4488 type_register(&spapr_machine_##suffix##_info); \
4490 type_init(spapr_machine_register_##suffix)
4495 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4497 /* Defaults for the latest behaviour inherited from the base class */
4500 DEFINE_SPAPR_MACHINE(4_2
, "4.2", true);
4505 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4507 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4508 static GlobalProperty compat
[] = {
4509 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4510 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4513 spapr_machine_4_2_class_options(mc
);
4514 smc
->linux_pci_probe
= false;
4515 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4516 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4519 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4524 static void phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4525 uint64_t *buid
, hwaddr
*pio
,
4526 hwaddr
*mmio32
, hwaddr
*mmio64
,
4527 unsigned n_dma
, uint32_t *liobns
,
4528 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4530 spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
, liobns
,
4531 nv2gpa
, nv2atsd
, errp
);
4536 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4538 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4540 spapr_machine_4_1_class_options(mc
);
4541 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4542 smc
->phb_placement
= phb_placement_4_0
;
4543 smc
->irq
= &spapr_irq_xics
;
4544 smc
->pre_4_1_migration
= true;
4547 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4552 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4554 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4556 spapr_machine_4_0_class_options(mc
);
4557 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4559 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4560 smc
->update_dt_enabled
= false;
4561 smc
->dr_phb_enabled
= false;
4562 smc
->broken_host_serial_model
= true;
4563 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4564 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4565 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4566 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4569 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4575 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4577 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4579 spapr_machine_3_1_class_options(mc
);
4580 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4582 smc
->legacy_irq_allocation
= true;
4583 smc
->irq
= &spapr_irq_xics_legacy
;
4586 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4591 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4593 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4594 static GlobalProperty compat
[] = {
4595 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4596 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4599 spapr_machine_3_0_class_options(mc
);
4600 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4601 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4603 /* We depend on kvm_enabled() to choose a default value for the
4604 * hpt-max-page-size capability. Of course we can't do it here
4605 * because this is too early and the HW accelerator isn't initialzed
4606 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4608 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4611 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4613 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4615 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4617 spapr_machine_2_12_class_options(mc
);
4618 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4619 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4620 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4623 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4629 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4631 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4633 spapr_machine_2_12_class_options(mc
);
4634 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4635 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4638 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4644 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4646 spapr_machine_2_11_class_options(mc
);
4647 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4650 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4656 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4658 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4659 static GlobalProperty compat
[] = {
4660 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4663 spapr_machine_2_10_class_options(mc
);
4664 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4665 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4666 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4667 smc
->pre_2_10_has_unused_icps
= true;
4668 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4671 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4677 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4679 static GlobalProperty compat
[] = {
4680 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4683 spapr_machine_2_9_class_options(mc
);
4684 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4685 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4686 mc
->numa_mem_align_shift
= 23;
4689 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4695 static void phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4696 uint64_t *buid
, hwaddr
*pio
,
4697 hwaddr
*mmio32
, hwaddr
*mmio64
,
4698 unsigned n_dma
, uint32_t *liobns
,
4699 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4701 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4702 const uint64_t base_buid
= 0x800000020000000ULL
;
4703 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4704 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4705 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4706 const uint32_t max_index
= 255;
4707 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4709 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4710 hwaddr phb0_base
, phb_base
;
4713 /* Do we have device memory? */
4714 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4715 /* Can't just use maxram_size, because there may be an
4716 * alignment gap between normal and device memory regions
4718 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4719 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4722 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4724 if (index
> max_index
) {
4725 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4730 *buid
= base_buid
+ index
;
4731 for (i
= 0; i
< n_dma
; ++i
) {
4732 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4735 phb_base
= phb0_base
+ index
* phb_spacing
;
4736 *pio
= phb_base
+ pio_offset
;
4737 *mmio32
= phb_base
+ mmio_offset
;
4739 * We don't set the 64-bit MMIO window, relying on the PHB's
4740 * fallback behaviour of automatically splitting a large "32-bit"
4741 * window into contiguous 32-bit and 64-bit windows
4748 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4750 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4751 static GlobalProperty compat
[] = {
4752 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4753 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4754 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4755 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4758 spapr_machine_2_8_class_options(mc
);
4759 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4760 mc
->default_machine_opts
= "modern-hotplug-events=off";
4761 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4762 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4763 smc
->phb_placement
= phb_placement_2_7
;
4766 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4772 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4774 static GlobalProperty compat
[] = {
4775 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4778 spapr_machine_2_7_class_options(mc
);
4779 mc
->has_hotpluggable_cpus
= false;
4780 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4781 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4784 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4790 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4792 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4793 static GlobalProperty compat
[] = {
4794 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4797 spapr_machine_2_6_class_options(mc
);
4798 smc
->use_ohci_by_default
= true;
4799 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4800 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4803 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4809 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4811 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4813 spapr_machine_2_5_class_options(mc
);
4814 smc
->dr_lmb_enabled
= false;
4815 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4818 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4824 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4826 static GlobalProperty compat
[] = {
4827 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4829 spapr_machine_2_4_class_options(mc
);
4830 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4831 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4833 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4839 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4841 static GlobalProperty compat
[] = {
4842 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4845 spapr_machine_2_3_class_options(mc
);
4846 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4847 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4848 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4850 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4856 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4858 spapr_machine_2_2_class_options(mc
);
4859 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4861 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4863 static void spapr_machine_register_types(void)
4865 type_register_static(&spapr_machine_info
);
4868 type_init(spapr_machine_register_types
)