target-xtensa/op_helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "helper.h"
  30 #include "qemu/host-utils.h"
  31 #include "exec/softmmu_exec.h"
  32 #include "exec/address-spaces.h"
  33
  34 static void do_unaligned_access(CPUXtensaState *env,
  35         target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
  36
  37 #define ALIGNED_ONLY
  38 #define MMUSUFFIX _mmu
  39
  40 #define SHIFT 0
  41 #include "exec/softmmu_template.h"
  42
  43 #define SHIFT 1
  44 #include "exec/softmmu_template.h"
  45
  46 #define SHIFT 2
  47 #include "exec/softmmu_template.h"
  48
  49 #define SHIFT 3
  50 #include "exec/softmmu_template.h"
  51
  52 static void do_unaligned_access(CPUXtensaState *env,
  53         target_ulong addr, int is_write, int is_user, uintptr_t retaddr)
  54 {
  55     if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
  56             !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
  57         cpu_restore_state(env, retaddr);
  58         HELPER(exception_cause_vaddr)(env,
  59                 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
  60     }
  61 }
  62
  63 void tlb_fill(CPUXtensaState *env,
  64         target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
  65 {
  66     uint32_t paddr;
  67     uint32_t page_size;
  68     unsigned access;
  69     int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx,
  70             &paddr, &page_size, &access);
  71
  72     qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
  73             vaddr, is_write, mmu_idx, paddr, ret);
  74
  75     if (ret == 0) {
  76         tlb_set_page(env,
  77                 vaddr & TARGET_PAGE_MASK,
  78                 paddr & TARGET_PAGE_MASK,
  79                 access, mmu_idx, page_size);
  80     } else {
  81         cpu_restore_state(env, retaddr);
  82         HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
  83     }
  84 }
  85
  86 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
  87 {
  88     uint32_t paddr;
  89     uint32_t page_size;
  90     unsigned access;
  91     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
  92             &paddr, &page_size, &access);
  93     if (ret == 0) {
  94         tb_invalidate_phys_addr(&address_space_memory, paddr);
  95     }
  96 }
  97
  98 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
  99 {
 100     env->exception_index = excp;
 101     if (excp == EXCP_DEBUG) {
 102         env->exception_taken = 0;
 103     }
 104     cpu_loop_exit(env);
 105 }
 106
 107 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 108 {
 109     uint32_t vector;
 110
 111     env->pc = pc;
 112     if (env->sregs[PS] & PS_EXCM) {
 113         if (env->config->ndepc) {
 114             env->sregs[DEPC] = pc;
 115         } else {
 116             env->sregs[EPC1] = pc;
 117         }
 118         vector = EXC_DOUBLE;
 119     } else {
 120         env->sregs[EPC1] = pc;
 121         vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 122     }
 123
 124     env->sregs[EXCCAUSE] = cause;
 125     env->sregs[PS] |= PS_EXCM;
 126
 127     HELPER(exception)(env, vector);
 128 }
 129
 130 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
 131         uint32_t pc, uint32_t cause, uint32_t vaddr)
 132 {
 133     env->sregs[EXCVADDR] = vaddr;
 134     HELPER(exception_cause)(env, pc, cause);
 135 }
 136
 137 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
 138 {
 139     if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 140         HELPER(debug_exception)(env, env->pc, cause);
 141     }
 142 }
 143
 144 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 145 {
 146     unsigned level = env->config->debug_level;
 147
 148     env->pc = pc;
 149     env->sregs[DEBUGCAUSE] = cause;
 150     env->sregs[EPC1 + level - 1] = pc;
 151     env->sregs[EPS2 + level - 2] = env->sregs[PS];
 152     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
 153         (level << PS_INTLEVEL_SHIFT);
 154     HELPER(exception)(env, EXC_DEBUG);
 155 }
 156
 157 uint32_t HELPER(nsa)(uint32_t v)
 158 {
 159     if (v & 0x80000000) {
 160         v = ~v;
 161     }
 162     return v ? clz32(v) - 1 : 31;
 163 }
 164
 165 uint32_t HELPER(nsau)(uint32_t v)
 166 {
 167     return v ? clz32(v) : 32;
 168 }
 169
 170 static void copy_window_from_phys(CPUXtensaState *env,
 171         uint32_t window, uint32_t phys, uint32_t n)
 172 {
 173     assert(phys < env->config->nareg);
 174     if (phys + n <= env->config->nareg) {
 175         memcpy(env->regs + window, env->phys_regs + phys,
 176                 n * sizeof(uint32_t));
 177     } else {
 178         uint32_t n1 = env->config->nareg - phys;
 179         memcpy(env->regs + window, env->phys_regs + phys,
 180                 n1 * sizeof(uint32_t));
 181         memcpy(env->regs + window + n1, env->phys_regs,
 182                 (n - n1) * sizeof(uint32_t));
 183     }
 184 }
 185
 186 static void copy_phys_from_window(CPUXtensaState *env,
 187         uint32_t phys, uint32_t window, uint32_t n)
 188 {
 189     assert(phys < env->config->nareg);
 190     if (phys + n <= env->config->nareg) {
 191         memcpy(env->phys_regs + phys, env->regs + window,
 192                 n * sizeof(uint32_t));
 193     } else {
 194         uint32_t n1 = env->config->nareg - phys;
 195         memcpy(env->phys_regs + phys, env->regs + window,
 196                 n1 * sizeof(uint32_t));
 197         memcpy(env->phys_regs, env->regs + window + n1,
 198                 (n - n1) * sizeof(uint32_t));
 199     }
 200 }
 201
 202
 203 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
 204 {
 205     return a & (env->config->nareg / 4 - 1);
 206 }
 207
 208 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
 209 {
 210     return 1 << windowbase_bound(a, env);
 211 }
 212
 213 void xtensa_sync_window_from_phys(CPUXtensaState *env)
 214 {
 215     copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
 216 }
 217
 218 void xtensa_sync_phys_from_window(CPUXtensaState *env)
 219 {
 220     copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
 221 }
 222
 223 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
 224 {
 225     xtensa_sync_phys_from_window(env);
 226     env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
 227     xtensa_sync_window_from_phys(env);
 228 }
 229
 230 static void rotate_window(CPUXtensaState *env, uint32_t delta)
 231 {
 232     rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
 233 }
 234
 235 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
 236 {
 237     rotate_window_abs(env, v);
 238 }
 239
 240 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
 241 {
 242     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
 243     if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 244         qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
 245                 pc, env->sregs[PS]);
 246         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 247     } else {
 248         env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
 249         rotate_window(env, callinc);
 250         env->sregs[WINDOW_START] |=
 251             windowstart_bit(env->sregs[WINDOW_BASE], env);
 252     }
 253 }
 254
 255 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
 256 {
 257     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 258     uint32_t windowstart = env->sregs[WINDOW_START];
 259     uint32_t m, n;
 260
 261     if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
 262         return;
 263     }
 264
 265     for (n = 1; ; ++n) {
 266         if (n > w) {
 267             return;
 268         }
 269         if (windowstart & windowstart_bit(windowbase + n, env)) {
 270             break;
 271         }
 272     }
 273
 274     m = windowbase_bound(windowbase + n, env);
 275     rotate_window(env, n);
 276     env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 277         (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 278     env->sregs[EPC1] = env->pc = pc;
 279
 280     if (windowstart & windowstart_bit(m + 1, env)) {
 281         HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
 282     } else if (windowstart & windowstart_bit(m + 2, env)) {
 283         HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
 284     } else {
 285         HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
 286     }
 287 }
 288
 289 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
 290 {
 291     int n = (env->regs[0] >> 30) & 0x3;
 292     int m = 0;
 293     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 294     uint32_t windowstart = env->sregs[WINDOW_START];
 295     uint32_t ret_pc = 0;
 296
 297     if (windowstart & windowstart_bit(windowbase - 1, env)) {
 298         m = 1;
 299     } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
 300         m = 2;
 301     } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
 302         m = 3;
 303     }
 304
 305     if (n == 0 || (m != 0 && m != n) ||
 306             ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 307         qemu_log("Illegal retw instruction(pc = %08x), "
 308                 "PS = %08x, m = %d, n = %d\n",
 309                 pc, env->sregs[PS], m, n);
 310         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 311     } else {
 312         int owb = windowbase;
 313
 314         ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
 315
 316         rotate_window(env, -n);
 317         if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
 318             env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
 319         } else {
 320             /* window underflow */
 321             env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 322                 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 323             env->sregs[EPC1] = env->pc = pc;
 324
 325             if (n == 1) {
 326                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
 327             } else if (n == 2) {
 328                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
 329             } else if (n == 3) {
 330                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
 331             }
 332         }
 333     }
 334     return ret_pc;
 335 }
 336
 337 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
 338 {
 339     rotate_window(env, imm4);
 340 }
 341
 342 void HELPER(restore_owb)(CPUXtensaState *env)
 343 {
 344     rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
 345 }
 346
 347 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
 348 {
 349     if ((env->sregs[WINDOW_START] &
 350             (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
 351              windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
 352              windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
 353         HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
 354     }
 355 }
 356
 357 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
 358 {
 359     if (env->sregs[LBEG] != v) {
 360         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 361         env->sregs[LBEG] = v;
 362     }
 363 }
 364
 365 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
 366 {
 367     if (env->sregs[LEND] != v) {
 368         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 369         env->sregs[LEND] = v;
 370         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 371     }
 372 }
 373
 374 void HELPER(dump_state)(CPUXtensaState *env)
 375 {
 376     XtensaCPU *cpu = xtensa_env_get_cpu(env);
 377
 378     cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
 379 }
 380
 381 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
 382 {
 383     CPUState *cpu;
 384
 385     env->pc = pc;
 386     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
 387         (intlevel << PS_INTLEVEL_SHIFT);
 388     check_interrupts(env);
 389     if (env->pending_irq_level) {
 390         cpu_loop_exit(env);
 391         return;
 392     }
 393
 394     cpu = CPU(xtensa_env_get_cpu(env));
 395     env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 396     cpu->halted = 1;
 397     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 398         xtensa_rearm_ccompare_timer(env);
 399     }
 400     HELPER(exception)(env, EXCP_HLT);
 401 }
 402
 403 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active)
 404 {
 405     xtensa_timer_irq(env, id, active);
 406 }
 407
 408 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d)
 409 {
 410     xtensa_advance_ccount(env, d);
 411 }
 412
 413 void HELPER(check_interrupts)(CPUXtensaState *env)
 414 {
 415     check_interrupts(env);
 416 }
 417
 418 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
 419 {
 420     get_page_addr_code(env, vaddr);
 421 }
 422
 423 /*!
 424  * Check vaddr accessibility/cache attributes and raise an exception if
 425  * specified by the ATOMCTL SR.
 426  *
 427  * Note: local memory exclusion is not implemented
 428  */
 429 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
 430 {
 431     uint32_t paddr, page_size, access;
 432     uint32_t atomctl = env->sregs[ATOMCTL];
 433     int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
 434             xtensa_get_cring(env), &paddr, &page_size, &access);
 435
 436     /*
 437      * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
 438      * see opcode description in the ISA
 439      */
 440     if (rc == 0 &&
 441             (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
 442         rc = STORE_PROHIBITED_CAUSE;
 443     }
 444
 445     if (rc) {
 446         HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
 447     }
 448
 449     /*
 450      * When data cache is not configured use ATOMCTL bypass field.
 451      * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
 452      * under the Conditional Store Option.
 453      */
 454     if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
 455         access = PAGE_CACHE_BYPASS;
 456     }
 457
 458     switch (access & PAGE_CACHE_MASK) {
 459     case PAGE_CACHE_WB:
 460         atomctl >>= 2;
 461         /* fall through */
 462     case PAGE_CACHE_WT:
 463         atomctl >>= 2;
 464         /* fall through */
 465     case PAGE_CACHE_BYPASS:
 466         if ((atomctl & 0x3) == 0) {
 467             HELPER(exception_cause_vaddr)(env, pc,
 468                     LOAD_STORE_ERROR_CAUSE, vaddr);
 469         }
 470         break;
 471
 472     case PAGE_CACHE_ISOLATE:
 473         HELPER(exception_cause_vaddr)(env, pc,
 474                 LOAD_STORE_ERROR_CAUSE, vaddr);
 475         break;
 476
 477     default:
 478         break;
 479     }
 480 }
 481
 482 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
 483 {
 484     v = (v & 0xffffff00) | 0x1;
 485     if (v != env->sregs[RASID]) {
 486         env->sregs[RASID] = v;
 487         tlb_flush(env, 1);
 488     }
 489 }
 490
 491 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
 492 {
 493     uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
 494
 495     switch (way) {
 496     case 4:
 497         return (tlbcfg >> 16) & 0x3;
 498
 499     case 5:
 500         return (tlbcfg >> 20) & 0x1;
 501
 502     case 6:
 503         return (tlbcfg >> 24) & 0x1;
 504
 505     default:
 506         return 0;
 507     }
 508 }
 509
 510 /*!
 511  * Get bit mask for the virtual address bits translated by the TLB way
 512  */
 513 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 514 {
 515     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 516         bool varway56 = dtlb ?
 517             env->config->dtlb.varway56 :
 518             env->config->itlb.varway56;
 519
 520         switch (way) {
 521         case 4:
 522             return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
 523
 524         case 5:
 525             if (varway56) {
 526                 return 0xf8000000 << get_page_size(env, dtlb, way);
 527             } else {
 528                 return 0xf8000000;
 529             }
 530
 531         case 6:
 532             if (varway56) {
 533                 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
 534             } else {
 535                 return 0xf0000000;
 536             }
 537
 538         default:
 539             return 0xfffff000;
 540         }
 541     } else {
 542         return REGION_PAGE_MASK;
 543     }
 544 }
 545
 546 /*!
 547  * Get bit mask for the 'VPN without index' field.
 548  * See ISA, 4.6.5.6, data format for RxTLB0
 549  */
 550 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 551 {
 552     if (way < 4) {
 553         bool is32 = (dtlb ?
 554                 env->config->dtlb.nrefillentries :
 555                 env->config->itlb.nrefillentries) == 32;
 556         return is32 ? 0xffff8000 : 0xffffc000;
 557     } else if (way == 4) {
 558         return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
 559     } else if (way <= 6) {
 560         uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
 561         bool varway56 = dtlb ?
 562             env->config->dtlb.varway56 :
 563             env->config->itlb.varway56;
 564
 565         if (varway56) {
 566             return mask << (way == 5 ? 2 : 3);
 567         } else {
 568             return mask << 1;
 569         }
 570     } else {
 571         return 0xfffff000;
 572     }
 573 }
 574
 575 /*!
 576  * Split virtual address into VPN (with index) and entry index
 577  * for the given TLB way
 578  */
 579 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 580         uint32_t *vpn, uint32_t wi, uint32_t *ei)
 581 {
 582     bool varway56 = dtlb ?
 583         env->config->dtlb.varway56 :
 584         env->config->itlb.varway56;
 585
 586     if (!dtlb) {
 587         wi &= 7;
 588     }
 589
 590     if (wi < 4) {
 591         bool is32 = (dtlb ?
 592                 env->config->dtlb.nrefillentries :
 593                 env->config->itlb.nrefillentries) == 32;
 594         *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
 595     } else {
 596         switch (wi) {
 597         case 4:
 598             {
 599                 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
 600                 *ei = (v >> eibase) & 0x3;
 601             }
 602             break;
 603
 604         case 5:
 605             if (varway56) {
 606                 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
 607                 *ei = (v >> eibase) & 0x3;
 608             } else {
 609                 *ei = (v >> 27) & 0x1;
 610             }
 611             break;
 612
 613         case 6:
 614             if (varway56) {
 615                 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
 616                 *ei = (v >> eibase) & 0x7;
 617             } else {
 618                 *ei = (v >> 28) & 0x1;
 619             }
 620             break;
 621
 622         default:
 623             *ei = 0;
 624             break;
 625         }
 626     }
 627     *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 628 }
 629
 630 /*!
 631  * Split TLB address into TLB way, entry index and VPN (with index).
 632  * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
 633  */
 634 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
 635         uint32_t *vpn, uint32_t *wi, uint32_t *ei)
 636 {
 637     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 638         *wi = v & (dtlb ? 0xf : 0x7);
 639         split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
 640     } else {
 641         *vpn = v & REGION_PAGE_MASK;
 642         *wi = 0;
 643         *ei = (v >> 29) & 0x7;
 644     }
 645 }
 646
 647 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
 648         uint32_t v, bool dtlb, uint32_t *pwi)
 649 {
 650     uint32_t vpn;
 651     uint32_t wi;
 652     uint32_t ei;
 653
 654     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 655     if (pwi) {
 656         *pwi = wi;
 657     }
 658     return xtensa_tlb_get_entry(env, dtlb, wi, ei);
 659 }
 660
 661 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 662 {
 663     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 664         uint32_t wi;
 665         const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 666         return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
 667     } else {
 668         return v & REGION_PAGE_MASK;
 669     }
 670 }
 671
 672 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 673 {
 674     const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
 675     return entry->paddr | entry->attr;
 676 }
 677
 678 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 679 {
 680     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 681         uint32_t wi;
 682         xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 683         if (entry->variable && entry->asid) {
 684             tlb_flush_page(env, entry->vaddr);
 685             entry->asid = 0;
 686         }
 687     }
 688 }
 689
 690 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 691 {
 692     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 693         uint32_t wi;
 694         uint32_t ei;
 695         uint8_t ring;
 696         int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
 697
 698         switch (res) {
 699         case 0:
 700             if (ring >= xtensa_get_ring(env)) {
 701                 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
 702             }
 703             break;
 704
 705         case INST_TLB_MULTI_HIT_CAUSE:
 706         case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
 707             HELPER(exception_cause_vaddr)(env, env->pc, res, v);
 708             break;
 709         }
 710         return 0;
 711     } else {
 712         return (v & REGION_PAGE_MASK) | 0x1;
 713     }
 714 }
 715
 716 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 717         xtensa_tlb_entry *entry, bool dtlb,
 718         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 719 {
 720     entry->vaddr = vpn;
 721     entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 722     entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
 723     entry->attr = pte & 0xf;
 724 }
 725
 726 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 727         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 728 {
 729     xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 730
 731     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 732         if (entry->variable) {
 733             if (entry->asid) {
 734                 tlb_flush_page(env, entry->vaddr);
 735             }
 736             xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
 737             tlb_flush_page(env, entry->vaddr);
 738         } else {
 739             qemu_log("%s %d, %d, %d trying to set immutable entry\n",
 740                     __func__, dtlb, wi, ei);
 741         }
 742     } else {
 743         tlb_flush_page(env, entry->vaddr);
 744         if (xtensa_option_enabled(env->config,
 745                     XTENSA_OPTION_REGION_TRANSLATION)) {
 746             entry->paddr = pte & REGION_PAGE_MASK;
 747         }
 748         entry->attr = pte & 0xf;
 749     }
 750 }
 751
 752 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
 753 {
 754     uint32_t vpn;
 755     uint32_t wi;
 756     uint32_t ei;
 757     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 758     xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
 759 }
 760
 761
 762 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
 763 {
 764     uint32_t change = v ^ env->sregs[IBREAKENABLE];
 765     unsigned i;
 766
 767     for (i = 0; i < env->config->nibreak; ++i) {
 768         if (change & (1 << i)) {
 769             tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 770         }
 771     }
 772     env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
 773 }
 774
 775 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 776 {
 777     if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
 778         tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 779         tb_invalidate_virtual_addr(env, v);
 780     }
 781     env->sregs[IBREAKA + i] = v;
 782 }
 783
 784 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
 785         uint32_t dbreakc)
 786 {
 787     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 788     uint32_t mask = dbreakc | ~DBREAKC_MASK;
 789
 790     if (env->cpu_watchpoint[i]) {
 791         cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 792     }
 793     if (dbreakc & DBREAKC_SB) {
 794         flags |= BP_MEM_WRITE;
 795     }
 796     if (dbreakc & DBREAKC_LB) {
 797         flags |= BP_MEM_READ;
 798     }
 799     /* contiguous mask after inversion is one less than some power of 2 */
 800     if ((~mask + 1) & ~mask) {
 801         qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
 802         /* cut mask after the first zero bit */
 803         mask = 0xffffffff << (32 - clo32(mask));
 804     }
 805     if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1,
 806             flags, &env->cpu_watchpoint[i])) {
 807         env->cpu_watchpoint[i] = NULL;
 808         qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
 809                 dbreaka & mask, ~mask + 1);
 810     }
 811 }
 812
 813 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 814 {
 815     uint32_t dbreakc = env->sregs[DBREAKC + i];
 816
 817     if ((dbreakc & DBREAKC_SB_LB) &&
 818             env->sregs[DBREAKA + i] != v) {
 819         set_dbreak(env, i, v, dbreakc);
 820     }
 821     env->sregs[DBREAKA + i] = v;
 822 }
 823
 824 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
 825 {
 826     if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 827         if (v & DBREAKC_SB_LB) {
 828             set_dbreak(env, i, env->sregs[DBREAKA + i], v);
 829         } else {
 830             if (env->cpu_watchpoint[i]) {
 831                 cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 832                 env->cpu_watchpoint[i] = NULL;
 833             }
 834         }
 835     }
 836     env->sregs[DBREAKC + i] = v;
 837 }
 838
 839 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
 840 {
 841     static const int rounding_mode[] = {
 842         float_round_nearest_even,
 843         float_round_to_zero,
 844         float_round_up,
 845         float_round_down,
 846     };
 847
 848     env->uregs[FCR] = v & 0xfffff07f;
 849     set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
 850 }
 851
 852 float32 HELPER(abs_s)(float32 v)
 853 {
 854     return float32_abs(v);
 855 }
 856
 857 float32 HELPER(neg_s)(float32 v)
 858 {
 859     return float32_chs(v);
 860 }
 861
 862 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
 863 {
 864     return float32_add(a, b, &env->fp_status);
 865 }
 866
 867 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
 868 {
 869     return float32_sub(a, b, &env->fp_status);
 870 }
 871
 872 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
 873 {
 874     return float32_mul(a, b, &env->fp_status);
 875 }
 876
 877 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 878 {
 879     return float32_muladd(b, c, a, 0,
 880             &env->fp_status);
 881 }
 882
 883 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 884 {
 885     return float32_muladd(b, c, a, float_muladd_negate_product,
 886             &env->fp_status);
 887 }
 888
 889 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
 890 {
 891     float_status fp_status = {0};
 892
 893     set_float_rounding_mode(rounding_mode, &fp_status);
 894     return float32_to_int32(
 895             float32_scalbn(v, scale, &fp_status), &fp_status);
 896 }
 897
 898 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
 899 {
 900     float_status fp_status = {0};
 901     float32 res;
 902
 903     set_float_rounding_mode(rounding_mode, &fp_status);
 904
 905     res = float32_scalbn(v, scale, &fp_status);
 906
 907     if (float32_is_neg(v) && !float32_is_any_nan(v)) {
 908         return float32_to_int32(res, &fp_status);
 909     } else {
 910         return float32_to_uint32(res, &fp_status);
 911     }
 912 }
 913
 914 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 915 {
 916     return float32_scalbn(int32_to_float32(v, &env->fp_status),
 917             (int32_t)scale, &env->fp_status);
 918 }
 919
 920 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 921 {
 922     return float32_scalbn(uint32_to_float32(v, &env->fp_status),
 923             (int32_t)scale, &env->fp_status);
 924 }
 925
 926 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
 927 {
 928     if (v) {
 929         env->sregs[BR] |= br;
 930     } else {
 931         env->sregs[BR] &= ~br;
 932     }
 933 }
 934
 935 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 936 {
 937     set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
 938 }
 939
 940 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 941 {
 942     set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
 943 }
 944
 945 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 946 {
 947     int v = float32_compare_quiet(a, b, &env->fp_status);
 948     set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
 949 }
 950
 951 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 952 {
 953     set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
 954 }
 955
 956 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 957 {
 958     int v = float32_compare_quiet(a, b, &env->fp_status);
 959     set_br(env, v == float_relation_less || v == float_relation_unordered, br);
 960 }
 961
 962 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 963 {
 964     set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
 965 }
 966
 967 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 968 {
 969     int v = float32_compare_quiet(a, b, &env->fp_status);
 970     set_br(env, v != float_relation_greater, br);
 971 }