2 * MIPS TLB (Translation lookaside buffer) helpers.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
26 #include "hw/mips/cpudevs.h"
38 #if !defined(CONFIG_USER_ONLY)
40 /* no MMU emulation */
41 int no_mmu_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
42 target_ulong address
, int rw
)
45 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
49 /* fixed mapping MMU emulation */
50 int fixed_mmu_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
51 target_ulong address
, int rw
)
53 if (address
<= (int32_t)0x7FFFFFFFUL
) {
54 if (!(env
->CP0_Status
& (1 << CP0St_ERL
))) {
55 *physical
= address
+ 0x40000000UL
;
59 } else if (address
<= (int32_t)0xBFFFFFFFUL
) {
60 *physical
= address
& 0x1FFFFFFF;
65 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
69 /* MIPS32/MIPS64 R4000-style MMU emulation */
70 int r4k_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
71 target_ulong address
, int rw
)
73 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
74 uint32_t MMID
= env
->CP0_MemoryMapID
;
75 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
79 MMID
= mi
? MMID
: (uint32_t) ASID
;
81 for (i
= 0; i
< env
->tlb
->tlb_in_use
; i
++) {
82 r4k_tlb_t
*tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
83 /* 1k pages are not supported. */
84 target_ulong mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
85 target_ulong tag
= address
& ~mask
;
86 target_ulong VPN
= tlb
->VPN
& ~mask
;
87 #if defined(TARGET_MIPS64)
91 /* Check ASID/MMID, virtual page number & size */
92 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
93 if ((tlb
->G
== 1 || tlb_mmid
== MMID
) && VPN
== tag
&& !tlb
->EHINV
) {
95 int n
= !!(address
& mask
& ~(mask
>> 1));
96 /* Check access rights */
97 if (!(n
? tlb
->V1
: tlb
->V0
)) {
98 return TLBRET_INVALID
;
100 if (rw
== MMU_INST_FETCH
&& (n
? tlb
->XI1
: tlb
->XI0
)) {
103 if (rw
== MMU_DATA_LOAD
&& (n
? tlb
->RI1
: tlb
->RI0
)) {
106 if (rw
!= MMU_DATA_STORE
|| (n
? tlb
->D1
: tlb
->D0
)) {
107 *physical
= tlb
->PFN
[n
] | (address
& (mask
>> 1));
109 if (n
? tlb
->D1
: tlb
->D0
) {
112 if (!(n
? tlb
->XI1
: tlb
->XI0
)) {
120 return TLBRET_NOMATCH
;
123 static void no_mmu_init(CPUMIPSState
*env
, const mips_def_t
*def
)
125 env
->tlb
->nb_tlb
= 1;
126 env
->tlb
->map_address
= &no_mmu_map_address
;
129 static void fixed_mmu_init(CPUMIPSState
*env
, const mips_def_t
*def
)
131 env
->tlb
->nb_tlb
= 1;
132 env
->tlb
->map_address
= &fixed_mmu_map_address
;
135 static void r4k_mmu_init(CPUMIPSState
*env
, const mips_def_t
*def
)
137 env
->tlb
->nb_tlb
= 1 + ((def
->CP0_Config1
>> CP0C1_MMU
) & 63);
138 env
->tlb
->map_address
= &r4k_map_address
;
139 env
->tlb
->helper_tlbwi
= r4k_helper_tlbwi
;
140 env
->tlb
->helper_tlbwr
= r4k_helper_tlbwr
;
141 env
->tlb
->helper_tlbp
= r4k_helper_tlbp
;
142 env
->tlb
->helper_tlbr
= r4k_helper_tlbr
;
143 env
->tlb
->helper_tlbinv
= r4k_helper_tlbinv
;
144 env
->tlb
->helper_tlbinvf
= r4k_helper_tlbinvf
;
147 void mmu_init(CPUMIPSState
*env
, const mips_def_t
*def
)
149 env
->tlb
= g_malloc0(sizeof(CPUMIPSTLBContext
));
151 switch (def
->mmu_type
) {
153 no_mmu_init(env
, def
);
156 r4k_mmu_init(env
, def
);
159 fixed_mmu_init(env
, def
);
165 cpu_abort(env_cpu(env
), "MMU type not supported\n");
169 static int is_seg_am_mapped(unsigned int am
, bool eu
, int mmu_idx
)
172 * Interpret access control mode and mmu_idx.
175 * UK 0 0 1 1 0 0 - - 0
176 * MK 1 0 1 1 0 1 - - !eu
177 * MSK 2 0 0 1 0 1 1 - !eu
178 * MUSK 3 0 0 0 0 1 1 1 !eu
179 * MUSUK 4 0 0 0 0 0 1 1 0
180 * USK 5 0 0 1 0 0 0 - 0
181 * - 6 - - - - - - - -
182 * UUSK 7 0 0 0 0 0 0 0 0
188 /* If EU is set, always unmapped */
194 /* Never AdE, TLB mapped if AM={1,2,3} */
195 adetlb_mask
= 0x70000000;
199 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
200 adetlb_mask
= 0xc0380000;
204 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
205 adetlb_mask
= 0xe4180000;
208 /* does this AM cause AdE in current execution mode */
209 if ((adetlb_mask
<< am
) < 0) {
210 return TLBRET_BADADDR
;
215 /* is this AM mapped in current execution mode */
216 return ((adetlb_mask
<< am
) < 0);
219 return TLBRET_BADADDR
;
223 static int get_seg_physical_address(CPUMIPSState
*env
, hwaddr
*physical
,
224 int *prot
, target_ulong real_address
,
226 unsigned int am
, bool eu
,
227 target_ulong segmask
,
228 hwaddr physical_base
)
230 int mapped
= is_seg_am_mapped(am
, eu
, mmu_idx
);
233 /* is_seg_am_mapped can report TLBRET_BADADDR */
236 /* The segment is TLB mapped */
237 return env
->tlb
->map_address(env
, physical
, prot
, real_address
, rw
);
239 /* The segment is unmapped */
240 *physical
= physical_base
| (real_address
& segmask
);
241 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
246 static int get_segctl_physical_address(CPUMIPSState
*env
, hwaddr
*physical
,
247 int *prot
, target_ulong real_address
,
249 uint16_t segctl
, target_ulong segmask
)
251 unsigned int am
= (segctl
& CP0SC_AM_MASK
) >> CP0SC_AM
;
252 bool eu
= (segctl
>> CP0SC_EU
) & 1;
253 hwaddr pa
= ((hwaddr
)segctl
& CP0SC_PA_MASK
) << 20;
255 return get_seg_physical_address(env
, physical
, prot
, real_address
, rw
,
256 mmu_idx
, am
, eu
, segmask
,
257 pa
& ~(hwaddr
)segmask
);
260 static int get_physical_address(CPUMIPSState
*env
, hwaddr
*physical
,
261 int *prot
, target_ulong real_address
,
264 /* User mode can only access useg/xuseg */
265 #if defined(TARGET_MIPS64)
266 int user_mode
= mmu_idx
== MIPS_HFLAG_UM
;
267 int supervisor_mode
= mmu_idx
== MIPS_HFLAG_SM
;
268 int kernel_mode
= !user_mode
&& !supervisor_mode
;
269 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
270 int SX
= (env
->CP0_Status
& (1 << CP0St_SX
)) != 0;
271 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
273 int ret
= TLBRET_MATCH
;
274 /* effective address (modified for KVM T&E kernel segments) */
275 target_ulong address
= real_address
;
277 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
278 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
279 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
280 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
281 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
283 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
284 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
286 if (mips_um_ksegs_enabled()) {
287 /* KVM T&E adds guest kernel segments in useg */
288 if (real_address
>= KVM_KSEG0_BASE
) {
289 if (real_address
< KVM_KSEG2_BASE
) {
291 address
+= KSEG0_BASE
- KVM_KSEG0_BASE
;
292 } else if (real_address
<= USEG_LIMIT
) {
294 address
+= KSEG2_BASE
- KVM_KSEG2_BASE
;
299 if (address
<= USEG_LIMIT
) {
303 if (address
>= 0x40000000UL
) {
304 segctl
= env
->CP0_SegCtl2
;
306 segctl
= env
->CP0_SegCtl2
>> 16;
308 ret
= get_segctl_physical_address(env
, physical
, prot
,
310 mmu_idx
, segctl
, 0x3FFFFFFF);
311 #if defined(TARGET_MIPS64)
312 } else if (address
< 0x4000000000000000ULL
) {
314 if (UX
&& address
<= (0x3FFFFFFFFFFFFFFFULL
& env
->SEGMask
)) {
315 ret
= env
->tlb
->map_address(env
, physical
, prot
,
318 ret
= TLBRET_BADADDR
;
320 } else if (address
< 0x8000000000000000ULL
) {
322 if ((supervisor_mode
|| kernel_mode
) &&
323 SX
&& address
<= (0x7FFFFFFFFFFFFFFFULL
& env
->SEGMask
)) {
324 ret
= env
->tlb
->map_address(env
, physical
, prot
,
327 ret
= TLBRET_BADADDR
;
329 } else if (address
< 0xC000000000000000ULL
) {
331 if ((address
& 0x07FFFFFFFFFFFFFFULL
) <= env
->PAMask
) {
332 /* KX/SX/UX bit to check for each xkphys EVA access mode */
333 static const uint8_t am_ksux
[8] = {
334 [CP0SC_AM_UK
] = (1u << CP0St_KX
),
335 [CP0SC_AM_MK
] = (1u << CP0St_KX
),
336 [CP0SC_AM_MSK
] = (1u << CP0St_SX
),
337 [CP0SC_AM_MUSK
] = (1u << CP0St_UX
),
338 [CP0SC_AM_MUSUK
] = (1u << CP0St_UX
),
339 [CP0SC_AM_USK
] = (1u << CP0St_SX
),
340 [6] = (1u << CP0St_KX
),
341 [CP0SC_AM_UUSK
] = (1u << CP0St_UX
),
343 unsigned int am
= CP0SC_AM_UK
;
344 unsigned int xr
= (env
->CP0_SegCtl2
& CP0SC2_XR_MASK
) >> CP0SC2_XR
;
346 if (xr
& (1 << ((address
>> 59) & 0x7))) {
347 am
= (env
->CP0_SegCtl1
& CP0SC1_XAM_MASK
) >> CP0SC1_XAM
;
349 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
350 if (env
->CP0_Status
& am_ksux
[am
]) {
351 ret
= get_seg_physical_address(env
, physical
, prot
,
353 mmu_idx
, am
, false, env
->PAMask
,
356 ret
= TLBRET_BADADDR
;
359 ret
= TLBRET_BADADDR
;
361 } else if (address
< 0xFFFFFFFF80000000ULL
) {
363 if (kernel_mode
&& KX
&&
364 address
<= (0xFFFFFFFF7FFFFFFFULL
& env
->SEGMask
)) {
365 ret
= env
->tlb
->map_address(env
, physical
, prot
,
368 ret
= TLBRET_BADADDR
;
371 } else if (address
< KSEG1_BASE
) {
373 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
,
375 env
->CP0_SegCtl1
>> 16, 0x1FFFFFFF);
376 } else if (address
< KSEG2_BASE
) {
378 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
,
380 env
->CP0_SegCtl1
, 0x1FFFFFFF);
381 } else if (address
< KSEG3_BASE
) {
383 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
,
385 env
->CP0_SegCtl0
>> 16, 0x1FFFFFFF);
389 * XXX: debug segment is not emulated
391 ret
= get_segctl_physical_address(env
, physical
, prot
, real_address
,
393 env
->CP0_SegCtl0
, 0x1FFFFFFF);
398 void cpu_mips_tlb_flush(CPUMIPSState
*env
)
400 /* Flush qemu's TLB and discard all shadowed entries. */
401 tlb_flush(env_cpu(env
));
402 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
405 #endif /* !CONFIG_USER_ONLY */
407 static void raise_mmu_exception(CPUMIPSState
*env
, target_ulong address
,
408 MMUAccessType access_type
, int tlb_error
)
410 CPUState
*cs
= env_cpu(env
);
411 int exception
= 0, error_code
= 0;
413 if (access_type
== MMU_INST_FETCH
) {
414 error_code
|= EXCP_INST_NOTAVAIL
;
420 /* Reference to kernel address from user mode or supervisor mode */
421 /* Reference to supervisor address from user mode */
422 if (access_type
== MMU_DATA_STORE
) {
423 exception
= EXCP_AdES
;
425 exception
= EXCP_AdEL
;
429 /* No TLB match for a mapped address */
430 if (access_type
== MMU_DATA_STORE
) {
431 exception
= EXCP_TLBS
;
433 exception
= EXCP_TLBL
;
435 error_code
|= EXCP_TLB_NOMATCH
;
438 /* TLB match with no valid bit */
439 if (access_type
== MMU_DATA_STORE
) {
440 exception
= EXCP_TLBS
;
442 exception
= EXCP_TLBL
;
446 /* TLB match but 'D' bit is cleared */
447 exception
= EXCP_LTLBL
;
450 /* Execute-Inhibit Exception */
451 if (env
->CP0_PageGrain
& (1 << CP0PG_IEC
)) {
452 exception
= EXCP_TLBXI
;
454 exception
= EXCP_TLBL
;
458 /* Read-Inhibit Exception */
459 if (env
->CP0_PageGrain
& (1 << CP0PG_IEC
)) {
460 exception
= EXCP_TLBRI
;
462 exception
= EXCP_TLBL
;
466 /* Raise exception */
467 if (!(env
->hflags
& MIPS_HFLAG_DM
)) {
468 env
->CP0_BadVAddr
= address
;
470 env
->CP0_Context
= (env
->CP0_Context
& ~0x007fffff) |
471 ((address
>> 9) & 0x007ffff0);
472 env
->CP0_EntryHi
= (env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
) |
473 (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) |
474 (address
& (TARGET_PAGE_MASK
<< 1));
475 #if defined(TARGET_MIPS64)
476 env
->CP0_EntryHi
&= env
->SEGMask
;
478 (env
->CP0_XContext
& ((~0ULL) << (env
->SEGBITS
- 7))) | /* PTEBase */
479 (extract64(address
, 62, 2) << (env
->SEGBITS
- 9)) | /* R */
480 (extract64(address
, 13, env
->SEGBITS
- 13) << 4); /* BadVPN2 */
482 cs
->exception_index
= exception
;
483 env
->error_code
= error_code
;
486 #if !defined(CONFIG_USER_ONLY)
488 hwaddr
mips_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
490 MIPSCPU
*cpu
= MIPS_CPU(cs
);
491 CPUMIPSState
*env
= &cpu
->env
;
495 if (get_physical_address(env
, &phys_addr
, &prot
, addr
, MMU_DATA_LOAD
,
496 cpu_mmu_index(env
, false)) != 0) {
502 #if !defined(TARGET_MIPS64)
505 * Perform hardware page table walk
507 * Memory accesses are performed using the KERNEL privilege level.
508 * Synchronous exceptions detected on memory accesses cause a silent exit
509 * from page table walking, resulting in a TLB or XTLB Refill exception.
511 * Implementations are not required to support page table walk memory
512 * accesses from mapped memory regions. When an unsupported access is
513 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
516 * Note that if an exception is caused by AddressTranslation or LoadMemory
517 * functions, the exception is not taken, a silent exit is taken,
518 * resulting in a TLB or XTLB Refill exception.
521 static bool get_pte(CPUMIPSState
*env
, uint64_t vaddr
, int entry_size
,
524 if ((vaddr
& ((entry_size
>> 3) - 1)) != 0) {
527 if (entry_size
== 64) {
528 *pte
= cpu_ldq_code(env
, vaddr
);
530 *pte
= cpu_ldl_code(env
, vaddr
);
535 static uint64_t get_tlb_entry_layout(CPUMIPSState
*env
, uint64_t entry
,
536 int entry_size
, int ptei
)
538 uint64_t result
= entry
;
540 if (ptei
> entry_size
) {
543 result
>>= (ptei
- 2);
546 result
|= rixi
<< CP0EnLo_XI
;
550 static int walk_directory(CPUMIPSState
*env
, uint64_t *vaddr
,
551 int directory_index
, bool *huge_page
, bool *hgpg_directory_hit
,
552 uint64_t *pw_entrylo0
, uint64_t *pw_entrylo1
)
554 int dph
= (env
->CP0_PWCtl
>> CP0PC_DPH
) & 0x1;
555 int psn
= (env
->CP0_PWCtl
>> CP0PC_PSN
) & 0x3F;
556 int hugepg
= (env
->CP0_PWCtl
>> CP0PC_HUGEPG
) & 0x1;
557 int pf_ptew
= (env
->CP0_PWField
>> CP0PF_PTEW
) & 0x3F;
558 int ptew
= (env
->CP0_PWSize
>> CP0PS_PTEW
) & 0x3F;
559 int native_shift
= (((env
->CP0_PWSize
>> CP0PS_PS
) & 1) == 0) ? 2 : 3;
560 int directory_shift
= (ptew
> 1) ? -1 :
561 (hugepg
&& (ptew
== 1)) ? native_shift
+ 1 : native_shift
;
562 int leaf_shift
= (ptew
> 1) ? -1 :
563 (ptew
== 1) ? native_shift
+ 1 : native_shift
;
564 uint32_t direntry_size
= 1 << (directory_shift
+ 3);
565 uint32_t leafentry_size
= 1 << (leaf_shift
+ 3);
572 if (get_physical_address(env
, &paddr
, &prot
, *vaddr
, MMU_DATA_LOAD
,
573 cpu_mmu_index(env
, false)) !=
575 /* wrong base address */
578 if (!get_pte(env
, *vaddr
, direntry_size
, &entry
)) {
582 if ((entry
& (1 << psn
)) && hugepg
) {
584 *hgpg_directory_hit
= true;
585 entry
= get_tlb_entry_layout(env
, entry
, leafentry_size
, pf_ptew
);
586 w
= directory_index
- 1;
587 if (directory_index
& 0x1) {
588 /* Generate adjacent page from same PTE for odd TLB page */
590 *pw_entrylo0
= entry
& ~lsb
; /* even page */
591 *pw_entrylo1
= entry
| lsb
; /* odd page */
593 int oddpagebit
= 1 << leaf_shift
;
594 uint64_t vaddr2
= *vaddr
^ oddpagebit
;
595 if (*vaddr
& oddpagebit
) {
596 *pw_entrylo1
= entry
;
598 *pw_entrylo0
= entry
;
600 if (get_physical_address(env
, &paddr
, &prot
, vaddr2
, MMU_DATA_LOAD
,
601 cpu_mmu_index(env
, false)) !=
605 if (!get_pte(env
, vaddr2
, leafentry_size
, &entry
)) {
608 entry
= get_tlb_entry_layout(env
, entry
, leafentry_size
, pf_ptew
);
609 if (*vaddr
& oddpagebit
) {
610 *pw_entrylo0
= entry
;
612 *pw_entrylo1
= entry
;
624 static bool page_table_walk_refill(CPUMIPSState
*env
, vaddr address
, int rw
,
627 int gdw
= (env
->CP0_PWSize
>> CP0PS_GDW
) & 0x3F;
628 int udw
= (env
->CP0_PWSize
>> CP0PS_UDW
) & 0x3F;
629 int mdw
= (env
->CP0_PWSize
>> CP0PS_MDW
) & 0x3F;
630 int ptw
= (env
->CP0_PWSize
>> CP0PS_PTW
) & 0x3F;
631 int ptew
= (env
->CP0_PWSize
>> CP0PS_PTEW
) & 0x3F;
634 bool huge_page
= false;
635 bool hgpg_bdhit
= false;
636 bool hgpg_gdhit
= false;
637 bool hgpg_udhit
= false;
638 bool hgpg_mdhit
= false;
640 int32_t pw_pagemask
= 0;
641 target_ulong pw_entryhi
= 0;
642 uint64_t pw_entrylo0
= 0;
643 uint64_t pw_entrylo1
= 0;
645 /* Native pointer size */
646 /*For the 32-bit architectures, this bit is fixed to 0.*/
647 int native_shift
= (((env
->CP0_PWSize
>> CP0PS_PS
) & 1) == 0) ? 2 : 3;
649 /* Indices from PWField */
650 int pf_gdw
= (env
->CP0_PWField
>> CP0PF_GDW
) & 0x3F;
651 int pf_udw
= (env
->CP0_PWField
>> CP0PF_UDW
) & 0x3F;
652 int pf_mdw
= (env
->CP0_PWField
>> CP0PF_MDW
) & 0x3F;
653 int pf_ptw
= (env
->CP0_PWField
>> CP0PF_PTW
) & 0x3F;
654 int pf_ptew
= (env
->CP0_PWField
>> CP0PF_PTEW
) & 0x3F;
656 /* Indices computed from faulting address */
657 int gindex
= (address
>> pf_gdw
) & ((1 << gdw
) - 1);
658 int uindex
= (address
>> pf_udw
) & ((1 << udw
) - 1);
659 int mindex
= (address
>> pf_mdw
) & ((1 << mdw
) - 1);
660 int ptindex
= (address
>> pf_ptw
) & ((1 << ptw
) - 1);
662 /* Other HTW configs */
663 int hugepg
= (env
->CP0_PWCtl
>> CP0PC_HUGEPG
) & 0x1;
665 /* HTW Shift values (depend on entry size) */
666 int directory_shift
= (ptew
> 1) ? -1 :
667 (hugepg
&& (ptew
== 1)) ? native_shift
+ 1 : native_shift
;
668 int leaf_shift
= (ptew
> 1) ? -1 :
669 (ptew
== 1) ? native_shift
+ 1 : native_shift
;
671 /* Offsets into tables */
672 int goffset
= gindex
<< directory_shift
;
673 int uoffset
= uindex
<< directory_shift
;
674 int moffset
= mindex
<< directory_shift
;
675 int ptoffset0
= (ptindex
>> 1) << (leaf_shift
+ 1);
676 int ptoffset1
= ptoffset0
| (1 << (leaf_shift
));
678 uint32_t leafentry_size
= 1 << (leaf_shift
+ 3);
680 /* Starting address - Page Table Base */
681 uint64_t vaddr
= env
->CP0_PWBase
;
688 if (!(env
->CP0_Config3
& (1 << CP0C3_PW
))) {
689 /* walker is unimplemented */
692 if (!(env
->CP0_PWCtl
& (1 << CP0PC_PWEN
))) {
693 /* walker is disabled */
696 if (!(gdw
> 0 || udw
> 0 || mdw
> 0)) {
697 /* no structure to walk */
700 if ((directory_shift
== -1) || (leaf_shift
== -1)) {
704 /* Global Directory */
707 switch (walk_directory(env
, &vaddr
, pf_gdw
, &huge_page
, &hgpg_gdhit
,
708 &pw_entrylo0
, &pw_entrylo1
))
720 /* Upper directory */
723 switch (walk_directory(env
, &vaddr
, pf_udw
, &huge_page
, &hgpg_udhit
,
724 &pw_entrylo0
, &pw_entrylo1
))
736 /* Middle directory */
739 switch (walk_directory(env
, &vaddr
, pf_mdw
, &huge_page
, &hgpg_mdhit
,
740 &pw_entrylo0
, &pw_entrylo1
))
752 /* Leaf Level Page Table - First half of PTE pair */
754 if (get_physical_address(env
, &paddr
, &prot
, vaddr
, MMU_DATA_LOAD
,
755 cpu_mmu_index(env
, false)) !=
759 if (!get_pte(env
, vaddr
, leafentry_size
, &dir_entry
)) {
762 dir_entry
= get_tlb_entry_layout(env
, dir_entry
, leafentry_size
, pf_ptew
);
763 pw_entrylo0
= dir_entry
;
765 /* Leaf Level Page Table - Second half of PTE pair */
767 if (get_physical_address(env
, &paddr
, &prot
, vaddr
, MMU_DATA_LOAD
,
768 cpu_mmu_index(env
, false)) !=
772 if (!get_pte(env
, vaddr
, leafentry_size
, &dir_entry
)) {
775 dir_entry
= get_tlb_entry_layout(env
, dir_entry
, leafentry_size
, pf_ptew
);
776 pw_entrylo1
= dir_entry
;
780 m
= (1 << pf_ptw
) - 1;
783 switch (hgpg_bdhit
<< 3 | hgpg_gdhit
<< 2 | hgpg_udhit
<< 1 |
787 m
= (1 << pf_gdw
) - 1;
793 m
= (1 << pf_udw
) - 1;
799 m
= (1 << pf_mdw
) - 1;
806 pw_pagemask
= m
>> TARGET_PAGE_BITS_MIN
;
807 update_pagemask(env
, pw_pagemask
<< CP0PM_MASK
, &pw_pagemask
);
808 pw_entryhi
= (address
& ~0x1fff) | (env
->CP0_EntryHi
& 0xFF);
810 target_ulong tmp_entryhi
= env
->CP0_EntryHi
;
811 int32_t tmp_pagemask
= env
->CP0_PageMask
;
812 uint64_t tmp_entrylo0
= env
->CP0_EntryLo0
;
813 uint64_t tmp_entrylo1
= env
->CP0_EntryLo1
;
815 env
->CP0_EntryHi
= pw_entryhi
;
816 env
->CP0_PageMask
= pw_pagemask
;
817 env
->CP0_EntryLo0
= pw_entrylo0
;
818 env
->CP0_EntryLo1
= pw_entrylo1
;
821 * The hardware page walker inserts a page into the TLB in a manner
822 * identical to a TLBWR instruction as executed by the software refill
825 r4k_helper_tlbwr(env
);
827 env
->CP0_EntryHi
= tmp_entryhi
;
828 env
->CP0_PageMask
= tmp_pagemask
;
829 env
->CP0_EntryLo0
= tmp_entrylo0
;
830 env
->CP0_EntryLo1
= tmp_entrylo1
;
835 #endif /* !CONFIG_USER_ONLY */
837 bool mips_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
838 MMUAccessType access_type
, int mmu_idx
,
839 bool probe
, uintptr_t retaddr
)
841 MIPSCPU
*cpu
= MIPS_CPU(cs
);
842 CPUMIPSState
*env
= &cpu
->env
;
843 #if !defined(CONFIG_USER_ONLY)
847 int ret
= TLBRET_BADADDR
;
850 #if !defined(CONFIG_USER_ONLY)
851 /* XXX: put correct access by using cpu_restore_state() correctly */
852 ret
= get_physical_address(env
, &physical
, &prot
, address
,
853 access_type
, mmu_idx
);
856 qemu_log_mask(CPU_LOG_MMU
,
857 "%s address=%" VADDR_PRIx
" physical " TARGET_FMT_plx
858 " prot %d\n", __func__
, address
, physical
, prot
);
861 qemu_log_mask(CPU_LOG_MMU
,
862 "%s address=%" VADDR_PRIx
" ret %d\n", __func__
, address
,
866 if (ret
== TLBRET_MATCH
) {
867 tlb_set_page(cs
, address
& TARGET_PAGE_MASK
,
868 physical
& TARGET_PAGE_MASK
, prot
,
869 mmu_idx
, TARGET_PAGE_SIZE
);
872 #if !defined(TARGET_MIPS64)
873 if ((ret
== TLBRET_NOMATCH
) && (env
->tlb
->nb_tlb
> 1)) {
875 * Memory reads during hardware page table walking are performed
876 * as if they were kernel-mode load instructions.
878 int mode
= (env
->hflags
& MIPS_HFLAG_KSU
);
880 env
->hflags
&= ~MIPS_HFLAG_KSU
;
881 ret_walker
= page_table_walk_refill(env
, address
, access_type
, mmu_idx
);
884 ret
= get_physical_address(env
, &physical
, &prot
, address
,
885 access_type
, mmu_idx
);
886 if (ret
== TLBRET_MATCH
) {
887 tlb_set_page(cs
, address
& TARGET_PAGE_MASK
,
888 physical
& TARGET_PAGE_MASK
, prot
,
889 mmu_idx
, TARGET_PAGE_SIZE
);
900 raise_mmu_exception(env
, address
, access_type
, ret
);
901 do_raise_exception_err(env
, cs
->exception_index
, env
->error_code
, retaddr
);
904 #ifndef CONFIG_USER_ONLY
905 hwaddr
cpu_mips_translate_address(CPUMIPSState
*env
, target_ulong address
,
906 MMUAccessType access_type
)
913 ret
= get_physical_address(env
, &physical
, &prot
, address
, access_type
,
914 cpu_mmu_index(env
, false));
915 if (ret
!= TLBRET_MATCH
) {
916 raise_mmu_exception(env
, address
, access_type
, ret
);
923 static void set_hflags_for_handler(CPUMIPSState
*env
)
925 /* Exception handlers are entered in 32-bit mode. */
926 env
->hflags
&= ~(MIPS_HFLAG_M16
);
927 /* ...except that microMIPS lets you choose. */
928 if (env
->insn_flags
& ASE_MICROMIPS
) {
929 env
->hflags
|= (!!(env
->CP0_Config3
&
930 (1 << CP0C3_ISA_ON_EXC
))
931 << MIPS_HFLAG_M16_SHIFT
);
935 static inline void set_badinstr_registers(CPUMIPSState
*env
)
937 if (env
->insn_flags
& ISA_NANOMIPS32
) {
938 if (env
->CP0_Config3
& (1 << CP0C3_BI
)) {
939 uint32_t instr
= (cpu_lduw_code(env
, env
->active_tc
.PC
)) << 16;
940 if ((instr
& 0x10000000) == 0) {
941 instr
|= cpu_lduw_code(env
, env
->active_tc
.PC
+ 2);
943 env
->CP0_BadInstr
= instr
;
945 if ((instr
& 0xFC000000) == 0x60000000) {
946 instr
= cpu_lduw_code(env
, env
->active_tc
.PC
+ 4) << 16;
947 env
->CP0_BadInstrX
= instr
;
953 if (env
->hflags
& MIPS_HFLAG_M16
) {
954 /* TODO: add BadInstr support for microMIPS */
957 if (env
->CP0_Config3
& (1 << CP0C3_BI
)) {
958 env
->CP0_BadInstr
= cpu_ldl_code(env
, env
->active_tc
.PC
);
960 if ((env
->CP0_Config3
& (1 << CP0C3_BP
)) &&
961 (env
->hflags
& MIPS_HFLAG_BMASK
)) {
962 env
->CP0_BadInstrP
= cpu_ldl_code(env
, env
->active_tc
.PC
- 4);
966 #endif /* !CONFIG_USER_ONLY */
968 void mips_cpu_do_interrupt(CPUState
*cs
)
970 #if !defined(CONFIG_USER_ONLY)
971 MIPSCPU
*cpu
= MIPS_CPU(cs
);
972 CPUMIPSState
*env
= &cpu
->env
;
973 bool update_badinstr
= 0;
977 if (qemu_loglevel_mask(CPU_LOG_INT
)
978 && cs
->exception_index
!= EXCP_EXT_INTERRUPT
) {
979 qemu_log("%s enter: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
981 __func__
, env
->active_tc
.PC
, env
->CP0_EPC
,
982 mips_exception_name(cs
->exception_index
));
984 if (cs
->exception_index
== EXCP_EXT_INTERRUPT
&&
985 (env
->hflags
& MIPS_HFLAG_DM
)) {
986 cs
->exception_index
= EXCP_DINT
;
989 switch (cs
->exception_index
) {
991 env
->CP0_Debug
|= 1 << CP0DB_DSS
;
993 * Debug single step cannot be raised inside a delay slot and
994 * resume will always occur on the next instruction
995 * (but we assume the pc has always been updated during
998 env
->CP0_DEPC
= env
->active_tc
.PC
| !!(env
->hflags
& MIPS_HFLAG_M16
);
999 goto enter_debug_mode
;
1001 env
->CP0_Debug
|= 1 << CP0DB_DINT
;
1004 env
->CP0_Debug
|= 1 << CP0DB_DIB
;
1007 env
->CP0_Debug
|= 1 << CP0DB_DBp
;
1008 /* Setup DExcCode - SDBBP instruction */
1009 env
->CP0_Debug
= (env
->CP0_Debug
& ~(0x1fULL
<< CP0DB_DEC
)) |
1013 env
->CP0_Debug
|= 1 << CP0DB_DDBS
;
1016 env
->CP0_Debug
|= 1 << CP0DB_DDBL
;
1018 env
->CP0_DEPC
= exception_resume_pc(env
);
1019 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
1021 if (env
->insn_flags
& ISA_MIPS3
) {
1022 env
->hflags
|= MIPS_HFLAG_64
;
1023 if (!(env
->insn_flags
& ISA_MIPS_R6
) ||
1024 env
->CP0_Status
& (1 << CP0St_KX
)) {
1025 env
->hflags
&= ~MIPS_HFLAG_AWRAP
;
1028 env
->hflags
|= MIPS_HFLAG_DM
| MIPS_HFLAG_CP0
;
1029 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
1030 /* EJTAG probe trap enable is not implemented... */
1031 if (!(env
->CP0_Status
& (1 << CP0St_EXL
))) {
1032 env
->CP0_Cause
&= ~(1U << CP0Ca_BD
);
1034 env
->active_tc
.PC
= env
->exception_base
+ 0x480;
1035 set_hflags_for_handler(env
);
1038 cpu_reset(CPU(cpu
));
1041 env
->CP0_Status
|= (1 << CP0St_SR
);
1042 memset(env
->CP0_WatchLo
, 0, sizeof(env
->CP0_WatchLo
));
1045 env
->CP0_Status
|= (1 << CP0St_NMI
);
1047 env
->CP0_ErrorEPC
= exception_resume_pc(env
);
1048 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
1049 env
->CP0_Status
|= (1 << CP0St_ERL
) | (1 << CP0St_BEV
);
1050 if (env
->insn_flags
& ISA_MIPS3
) {
1051 env
->hflags
|= MIPS_HFLAG_64
;
1052 if (!(env
->insn_flags
& ISA_MIPS_R6
) ||
1053 env
->CP0_Status
& (1 << CP0St_KX
)) {
1054 env
->hflags
&= ~MIPS_HFLAG_AWRAP
;
1057 env
->hflags
|= MIPS_HFLAG_CP0
;
1058 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
1059 if (!(env
->CP0_Status
& (1 << CP0St_EXL
))) {
1060 env
->CP0_Cause
&= ~(1U << CP0Ca_BD
);
1062 env
->active_tc
.PC
= env
->exception_base
;
1063 set_hflags_for_handler(env
);
1065 case EXCP_EXT_INTERRUPT
:
1067 if (env
->CP0_Cause
& (1 << CP0Ca_IV
)) {
1068 uint32_t spacing
= (env
->CP0_IntCtl
>> CP0IntCtl_VS
) & 0x1f;
1070 if ((env
->CP0_Status
& (1 << CP0St_BEV
)) || spacing
== 0) {
1073 uint32_t vector
= 0;
1074 uint32_t pending
= (env
->CP0_Cause
& CP0Ca_IP_mask
) >> CP0Ca_IP
;
1076 if (env
->CP0_Config3
& (1 << CP0C3_VEIC
)) {
1078 * For VEIC mode, the external interrupt controller feeds
1079 * the vector through the CP0Cause IP lines.
1084 * Vectored Interrupts
1085 * Mask with Status.IM7-IM0 to get enabled interrupts.
1087 pending
&= (env
->CP0_Status
>> CP0St_IM
) & 0xff;
1088 /* Find the highest-priority interrupt. */
1089 while (pending
>>= 1) {
1093 offset
= 0x200 + (vector
* (spacing
<< 5));
1099 update_badinstr
= !(env
->error_code
& EXCP_INST_NOTAVAIL
);
1103 update_badinstr
= !(env
->error_code
& EXCP_INST_NOTAVAIL
);
1104 if ((env
->error_code
& EXCP_TLB_NOMATCH
) &&
1105 !(env
->CP0_Status
& (1 << CP0St_EXL
))) {
1106 #if defined(TARGET_MIPS64)
1107 int R
= env
->CP0_BadVAddr
>> 62;
1108 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
1109 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
1111 if ((R
!= 0 || UX
) && (R
!= 3 || KX
) &&
1112 (!(env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
)))) {
1117 #if defined(TARGET_MIPS64)
1124 update_badinstr
= 1;
1125 if ((env
->error_code
& EXCP_TLB_NOMATCH
) &&
1126 !(env
->CP0_Status
& (1 << CP0St_EXL
))) {
1127 #if defined(TARGET_MIPS64)
1128 int R
= env
->CP0_BadVAddr
>> 62;
1129 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
1130 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
1132 if ((R
!= 0 || UX
) && (R
!= 3 || KX
) &&
1133 (!(env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
)))) {
1138 #if defined(TARGET_MIPS64)
1145 update_badinstr
= !(env
->error_code
& EXCP_INST_NOTAVAIL
);
1149 update_badinstr
= 1;
1159 update_badinstr
= 1;
1163 update_badinstr
= 1;
1167 update_badinstr
= 1;
1171 update_badinstr
= 1;
1172 env
->CP0_Cause
= (env
->CP0_Cause
& ~(0x3 << CP0Ca_CE
)) |
1173 (env
->error_code
<< CP0Ca_CE
);
1177 update_badinstr
= 1;
1181 update_badinstr
= 1;
1185 update_badinstr
= 1;
1189 update_badinstr
= 1;
1196 update_badinstr
= 1;
1203 update_badinstr
= 1;
1210 /* XXX: TODO: manage deferred watch exceptions */
1225 if (!(env
->CP0_Status
& (1 << CP0St_EXL
))) {
1226 env
->CP0_EPC
= exception_resume_pc(env
);
1227 if (update_badinstr
) {
1228 set_badinstr_registers(env
);
1230 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
1231 env
->CP0_Cause
|= (1U << CP0Ca_BD
);
1233 env
->CP0_Cause
&= ~(1U << CP0Ca_BD
);
1235 env
->CP0_Status
|= (1 << CP0St_EXL
);
1236 if (env
->insn_flags
& ISA_MIPS3
) {
1237 env
->hflags
|= MIPS_HFLAG_64
;
1238 if (!(env
->insn_flags
& ISA_MIPS_R6
) ||
1239 env
->CP0_Status
& (1 << CP0St_KX
)) {
1240 env
->hflags
&= ~MIPS_HFLAG_AWRAP
;
1243 env
->hflags
|= MIPS_HFLAG_CP0
;
1244 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
1246 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
1247 if (env
->CP0_Status
& (1 << CP0St_BEV
)) {
1248 env
->active_tc
.PC
= env
->exception_base
+ 0x200;
1249 } else if (cause
== 30 && !(env
->CP0_Config3
& (1 << CP0C3_SC
) &&
1250 env
->CP0_Config5
& (1 << CP0C5_CV
))) {
1251 /* Force KSeg1 for cache errors */
1252 env
->active_tc
.PC
= KSEG1_BASE
| (env
->CP0_EBase
& 0x1FFFF000);
1254 env
->active_tc
.PC
= env
->CP0_EBase
& ~0xfff;
1257 env
->active_tc
.PC
+= offset
;
1258 set_hflags_for_handler(env
);
1259 env
->CP0_Cause
= (env
->CP0_Cause
& ~(0x1f << CP0Ca_EC
)) |
1260 (cause
<< CP0Ca_EC
);
1265 if (qemu_loglevel_mask(CPU_LOG_INT
)
1266 && cs
->exception_index
!= EXCP_EXT_INTERRUPT
) {
1267 qemu_log("%s: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
" cause %d\n"
1268 " S %08x C %08x A " TARGET_FMT_lx
" D " TARGET_FMT_lx
"\n",
1269 __func__
, env
->active_tc
.PC
, env
->CP0_EPC
, cause
,
1270 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_BadVAddr
,
1274 cs
->exception_index
= EXCP_NONE
;
1277 #if !defined(CONFIG_USER_ONLY)
1278 void r4k_invalidate_tlb(CPUMIPSState
*env
, int idx
, int use_extra
)
1280 CPUState
*cs
= env_cpu(env
);
1284 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
1285 uint32_t MMID
= env
->CP0_MemoryMapID
;
1286 bool mi
= !!((env
->CP0_Config5
>> CP0C5_MI
) & 1);
1290 MMID
= mi
? MMID
: (uint32_t) ASID
;
1292 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1294 * The qemu TLB is flushed when the ASID/MMID changes, so no need to
1295 * flush these entries again.
1297 tlb_mmid
= mi
? tlb
->MMID
: (uint32_t) tlb
->ASID
;
1298 if (tlb
->G
== 0 && tlb_mmid
!= MMID
) {
1302 if (use_extra
&& env
->tlb
->tlb_in_use
< MIPS_TLB_MAX
) {
1304 * For tlbwr, we can shadow the discarded entry into
1305 * a new (fake) TLB entry, as long as the guest can not
1306 * tell that it's there.
1308 env
->tlb
->mmu
.r4k
.tlb
[env
->tlb
->tlb_in_use
] = *tlb
;
1309 env
->tlb
->tlb_in_use
++;
1313 /* 1k pages are not supported. */
1314 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1316 addr
= tlb
->VPN
& ~mask
;
1317 #if defined(TARGET_MIPS64)
1318 if (addr
>= (0xFFFFFFFF80000000ULL
& env
->SEGMask
)) {
1319 addr
|= 0x3FFFFF0000000000ULL
;
1322 end
= addr
| (mask
>> 1);
1323 while (addr
< end
) {
1324 tlb_flush_page(cs
, addr
);
1325 addr
+= TARGET_PAGE_SIZE
;
1329 addr
= (tlb
->VPN
& ~mask
) | ((mask
>> 1) + 1);
1330 #if defined(TARGET_MIPS64)
1331 if (addr
>= (0xFFFFFFFF80000000ULL
& env
->SEGMask
)) {
1332 addr
|= 0x3FFFFF0000000000ULL
;
1336 while (addr
- 1 < end
) {
1337 tlb_flush_page(cs
, addr
);
1338 addr
+= TARGET_PAGE_SIZE
;
1342 #endif /* !CONFIG_USER_ONLY */