hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu-common.h"
  31 #include "cpu.h"
  32 #include "hw/hw.h"
  33 #include "trace.h"
  34 #include "qemu/timer.h"
  35 #include "hw/ppc/xics.h"
  36 #include "qemu/error-report.h"
  37 #include "qapi/visitor.h"
  38 #include "monitor/monitor.h"
  39 #include "hw/intc/intc.h"
  40
  41 int xics_get_cpu_index_by_dt_id(int cpu_dt_id)
  42 {
  43     PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
  44
  45     if (cpu) {
  46         return cpu->parent_obj.cpu_index;
  47     }
  48
  49     return -1;
  50 }
  51
  52 void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu)
  53 {
  54     CPUState *cs = CPU(cpu);
  55     ICPState *icp = xics_icp_get(xi, cs->cpu_index);
  56
  57     assert(icp);
  58     assert(cs == icp->cs);
  59
  60     icp->output = NULL;
  61     icp->cs = NULL;
  62 }
  63
  64 void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu)
  65 {
  66     CPUState *cs = CPU(cpu);
  67     CPUPPCState *env = &cpu->env;
  68     ICPState *icp = xics_icp_get(xi, cs->cpu_index);
  69     ICPStateClass *icpc;
  70
  71     assert(icp);
  72
  73     icp->cs = cs;
  74
  75     icpc = ICP_GET_CLASS(icp);
  76     if (icpc->cpu_setup) {
  77         icpc->cpu_setup(icp, cpu);
  78     }
  79
  80     switch (PPC_INPUT(env)) {
  81     case PPC_FLAGS_INPUT_POWER7:
  82         icp->output = env->irq_inputs[POWER7_INPUT_INT];
  83         break;
  84
  85     case PPC_FLAGS_INPUT_970:
  86         icp->output = env->irq_inputs[PPC970_INPUT_INT];
  87         break;
  88
  89     default:
  90         error_report("XICS interrupt controller does not support this CPU "
  91                      "bus model");
  92         abort();
  93     }
  94 }
  95
  96 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  97 {
  98     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  99
 100     if (!icp->output) {
 101         return;
 102     }
 103     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
 104                    cpu_index, icp->xirr, icp->xirr_owner,
 105                    icp->pending_priority, icp->mfrr);
 106 }
 107
 108 void ics_pic_print_info(ICSState *ics, Monitor *mon)
 109 {
 110     uint32_t i;
 111
 112     monitor_printf(mon, "ICS %4x..%4x %p\n",
 113                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
 114
 115     if (!ics->irqs) {
 116         return;
 117     }
 118
 119     for (i = 0; i < ics->nr_irqs; i++) {
 120         ICSIRQState *irq = ics->irqs + i;
 121
 122         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
 123             continue;
 124         }
 125         monitor_printf(mon, "  %4x %s %02x %02x\n",
 126                        ics->offset + i,
 127                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
 128                        "LSI" : "MSI",
 129                        irq->priority, irq->status);
 130     }
 131 }
 132
 133 /*
 134  * ICP: Presentation layer
 135  */
 136
 137 #define XISR_MASK  0x00ffffff
 138 #define CPPR_MASK  0xff000000
 139
 140 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
 141 #define CPPR(icp)   (((icp)->xirr) >> 24)
 142
 143 static void ics_reject(ICSState *ics, uint32_t nr)
 144 {
 145     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 146
 147     if (k->reject) {
 148         k->reject(ics, nr);
 149     }
 150 }
 151
 152 void ics_resend(ICSState *ics)
 153 {
 154     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 155
 156     if (k->resend) {
 157         k->resend(ics);
 158     }
 159 }
 160
 161 static void ics_eoi(ICSState *ics, int nr)
 162 {
 163     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 164
 165     if (k->eoi) {
 166         k->eoi(ics, nr);
 167     }
 168 }
 169
 170 static void icp_check_ipi(ICPState *icp)
 171 {
 172     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 173         return;
 174     }
 175
 176     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 177
 178     if (XISR(icp) && icp->xirr_owner) {
 179         ics_reject(icp->xirr_owner, XISR(icp));
 180     }
 181
 182     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 183     icp->pending_priority = icp->mfrr;
 184     icp->xirr_owner = NULL;
 185     qemu_irq_raise(icp->output);
 186 }
 187
 188 void icp_resend(ICPState *icp)
 189 {
 190     XICSFabric *xi = icp->xics;
 191     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 192
 193     if (icp->mfrr < CPPR(icp)) {
 194         icp_check_ipi(icp);
 195     }
 196
 197     xic->ics_resend(xi);
 198 }
 199
 200 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 201 {
 202     uint8_t old_cppr;
 203     uint32_t old_xisr;
 204
 205     old_cppr = CPPR(icp);
 206     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 207
 208     if (cppr < old_cppr) {
 209         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 210             old_xisr = XISR(icp);
 211             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 212             icp->pending_priority = 0xff;
 213             qemu_irq_lower(icp->output);
 214             if (icp->xirr_owner) {
 215                 ics_reject(icp->xirr_owner, old_xisr);
 216                 icp->xirr_owner = NULL;
 217             }
 218         }
 219     } else {
 220         if (!XISR(icp)) {
 221             icp_resend(icp);
 222         }
 223     }
 224 }
 225
 226 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 227 {
 228     icp->mfrr = mfrr;
 229     if (mfrr < CPPR(icp)) {
 230         icp_check_ipi(icp);
 231     }
 232 }
 233
 234 uint32_t icp_accept(ICPState *icp)
 235 {
 236     uint32_t xirr = icp->xirr;
 237
 238     qemu_irq_lower(icp->output);
 239     icp->xirr = icp->pending_priority << 24;
 240     icp->pending_priority = 0xff;
 241     icp->xirr_owner = NULL;
 242
 243     trace_xics_icp_accept(xirr, icp->xirr);
 244
 245     return xirr;
 246 }
 247
 248 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 249 {
 250     if (mfrr) {
 251         *mfrr = icp->mfrr;
 252     }
 253     return icp->xirr;
 254 }
 255
 256 void icp_eoi(ICPState *icp, uint32_t xirr)
 257 {
 258     XICSFabric *xi = icp->xics;
 259     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 260     ICSState *ics;
 261     uint32_t irq;
 262
 263     /* Send EOI -> ICS */
 264     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 265     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 266     irq = xirr & XISR_MASK;
 267
 268     ics = xic->ics_get(xi, irq);
 269     if (ics) {
 270         ics_eoi(ics, irq);
 271     }
 272     if (!XISR(icp)) {
 273         icp_resend(icp);
 274     }
 275 }
 276
 277 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 278 {
 279     ICPState *icp = xics_icp_get(ics->xics, server);
 280
 281     trace_xics_icp_irq(server, nr, priority);
 282
 283     if ((priority >= CPPR(icp))
 284         || (XISR(icp) && (icp->pending_priority <= priority))) {
 285         ics_reject(ics, nr);
 286     } else {
 287         if (XISR(icp) && icp->xirr_owner) {
 288             ics_reject(icp->xirr_owner, XISR(icp));
 289             icp->xirr_owner = NULL;
 290         }
 291         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 292         icp->xirr_owner = ics;
 293         icp->pending_priority = priority;
 294         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 295         qemu_irq_raise(icp->output);
 296     }
 297 }
 298
 299 static void icp_dispatch_pre_save(void *opaque)
 300 {
 301     ICPState *icp = opaque;
 302     ICPStateClass *info = ICP_GET_CLASS(icp);
 303
 304     if (info->pre_save) {
 305         info->pre_save(icp);
 306     }
 307 }
 308
 309 static int icp_dispatch_post_load(void *opaque, int version_id)
 310 {
 311     ICPState *icp = opaque;
 312     ICPStateClass *info = ICP_GET_CLASS(icp);
 313
 314     if (info->post_load) {
 315         return info->post_load(icp, version_id);
 316     }
 317
 318     return 0;
 319 }
 320
 321 static const VMStateDescription vmstate_icp_server = {
 322     .name = "icp/server",
 323     .version_id = 1,
 324     .minimum_version_id = 1,
 325     .pre_save = icp_dispatch_pre_save,
 326     .post_load = icp_dispatch_post_load,
 327     .fields = (VMStateField[]) {
 328         /* Sanity check */
 329         VMSTATE_UINT32(xirr, ICPState),
 330         VMSTATE_UINT8(pending_priority, ICPState),
 331         VMSTATE_UINT8(mfrr, ICPState),
 332         VMSTATE_END_OF_LIST()
 333     },
 334 };
 335
 336 static void icp_reset(DeviceState *dev)
 337 {
 338     ICPState *icp = ICP(dev);
 339
 340     icp->xirr = 0;
 341     icp->pending_priority = 0xff;
 342     icp->mfrr = 0xff;
 343
 344     /* Make all outputs are deasserted */
 345     qemu_set_irq(icp->output, 0);
 346 }
 347
 348 static void icp_realize(DeviceState *dev, Error **errp)
 349 {
 350     ICPState *icp = ICP(dev);
 351     Object *obj;
 352     Error *err = NULL;
 353
 354     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 355     if (!obj) {
 356         error_setg(errp, "%s: required link 'xics' not found: %s",
 357                    __func__, error_get_pretty(err));
 358         return;
 359     }
 360
 361     icp->xics = XICS_FABRIC(obj);
 362 }
 363
 364
 365 static void icp_class_init(ObjectClass *klass, void *data)
 366 {
 367     DeviceClass *dc = DEVICE_CLASS(klass);
 368
 369     dc->reset = icp_reset;
 370     dc->vmsd = &vmstate_icp_server;
 371     dc->realize = icp_realize;
 372 }
 373
 374 static const TypeInfo icp_info = {
 375     .name = TYPE_ICP,
 376     .parent = TYPE_DEVICE,
 377     .instance_size = sizeof(ICPState),
 378     .class_init = icp_class_init,
 379     .class_size = sizeof(ICPStateClass),
 380 };
 381
 382 /*
 383  * ICS: Source layer
 384  */
 385 static void ics_simple_resend_msi(ICSState *ics, int srcno)
 386 {
 387     ICSIRQState *irq = ics->irqs + srcno;
 388
 389     /* FIXME: filter by server#? */
 390     if (irq->status & XICS_STATUS_REJECTED) {
 391         irq->status &= ~XICS_STATUS_REJECTED;
 392         if (irq->priority != 0xff) {
 393             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 394         }
 395     }
 396 }
 397
 398 static void ics_simple_resend_lsi(ICSState *ics, int srcno)
 399 {
 400     ICSIRQState *irq = ics->irqs + srcno;
 401
 402     if ((irq->priority != 0xff)
 403         && (irq->status & XICS_STATUS_ASSERTED)
 404         && !(irq->status & XICS_STATUS_SENT)) {
 405         irq->status |= XICS_STATUS_SENT;
 406         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 407     }
 408 }
 409
 410 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
 411 {
 412     ICSIRQState *irq = ics->irqs + srcno;
 413
 414     trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
 415
 416     if (val) {
 417         if (irq->priority == 0xff) {
 418             irq->status |= XICS_STATUS_MASKED_PENDING;
 419             trace_xics_masked_pending();
 420         } else  {
 421             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 422         }
 423     }
 424 }
 425
 426 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
 427 {
 428     ICSIRQState *irq = ics->irqs + srcno;
 429
 430     trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
 431     if (val) {
 432         irq->status |= XICS_STATUS_ASSERTED;
 433     } else {
 434         irq->status &= ~XICS_STATUS_ASSERTED;
 435     }
 436     ics_simple_resend_lsi(ics, srcno);
 437 }
 438
 439 static void ics_simple_set_irq(void *opaque, int srcno, int val)
 440 {
 441     ICSState *ics = (ICSState *)opaque;
 442
 443     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 444         ics_simple_set_irq_lsi(ics, srcno, val);
 445     } else {
 446         ics_simple_set_irq_msi(ics, srcno, val);
 447     }
 448 }
 449
 450 static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
 451 {
 452     ICSIRQState *irq = ics->irqs + srcno;
 453
 454     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 455         || (irq->priority == 0xff)) {
 456         return;
 457     }
 458
 459     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 460     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 461 }
 462
 463 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
 464 {
 465     ics_simple_resend_lsi(ics, srcno);
 466 }
 467
 468 void ics_simple_write_xive(ICSState *ics, int srcno, int server,
 469                            uint8_t priority, uint8_t saved_priority)
 470 {
 471     ICSIRQState *irq = ics->irqs + srcno;
 472
 473     irq->server = server;
 474     irq->priority = priority;
 475     irq->saved_priority = saved_priority;
 476
 477     trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
 478                                      priority);
 479
 480     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 481         ics_simple_write_xive_lsi(ics, srcno);
 482     } else {
 483         ics_simple_write_xive_msi(ics, srcno);
 484     }
 485 }
 486
 487 static void ics_simple_reject(ICSState *ics, uint32_t nr)
 488 {
 489     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 490
 491     trace_xics_ics_simple_reject(nr, nr - ics->offset);
 492     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 493         irq->status |= XICS_STATUS_REJECTED;
 494     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 495         irq->status &= ~XICS_STATUS_SENT;
 496     }
 497 }
 498
 499 static void ics_simple_resend(ICSState *ics)
 500 {
 501     int i;
 502
 503     for (i = 0; i < ics->nr_irqs; i++) {
 504         /* FIXME: filter by server#? */
 505         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 506             ics_simple_resend_lsi(ics, i);
 507         } else {
 508             ics_simple_resend_msi(ics, i);
 509         }
 510     }
 511 }
 512
 513 static void ics_simple_eoi(ICSState *ics, uint32_t nr)
 514 {
 515     int srcno = nr - ics->offset;
 516     ICSIRQState *irq = ics->irqs + srcno;
 517
 518     trace_xics_ics_simple_eoi(nr);
 519
 520     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 521         irq->status &= ~XICS_STATUS_SENT;
 522     }
 523 }
 524
 525 static void ics_simple_reset(DeviceState *dev)
 526 {
 527     ICSState *ics = ICS_SIMPLE(dev);
 528     int i;
 529     uint8_t flags[ics->nr_irqs];
 530
 531     for (i = 0; i < ics->nr_irqs; i++) {
 532         flags[i] = ics->irqs[i].flags;
 533     }
 534
 535     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 536
 537     for (i = 0; i < ics->nr_irqs; i++) {
 538         ics->irqs[i].priority = 0xff;
 539         ics->irqs[i].saved_priority = 0xff;
 540         ics->irqs[i].flags = flags[i];
 541     }
 542 }
 543
 544 static void ics_simple_dispatch_pre_save(void *opaque)
 545 {
 546     ICSState *ics = opaque;
 547     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 548
 549     if (info->pre_save) {
 550         info->pre_save(ics);
 551     }
 552 }
 553
 554 static int ics_simple_dispatch_post_load(void *opaque, int version_id)
 555 {
 556     ICSState *ics = opaque;
 557     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 558
 559     if (info->post_load) {
 560         return info->post_load(ics, version_id);
 561     }
 562
 563     return 0;
 564 }
 565
 566 static const VMStateDescription vmstate_ics_simple_irq = {
 567     .name = "ics/irq",
 568     .version_id = 2,
 569     .minimum_version_id = 1,
 570     .fields = (VMStateField[]) {
 571         VMSTATE_UINT32(server, ICSIRQState),
 572         VMSTATE_UINT8(priority, ICSIRQState),
 573         VMSTATE_UINT8(saved_priority, ICSIRQState),
 574         VMSTATE_UINT8(status, ICSIRQState),
 575         VMSTATE_UINT8(flags, ICSIRQState),
 576         VMSTATE_END_OF_LIST()
 577     },
 578 };
 579
 580 static const VMStateDescription vmstate_ics_simple = {
 581     .name = "ics",
 582     .version_id = 1,
 583     .minimum_version_id = 1,
 584     .pre_save = ics_simple_dispatch_pre_save,
 585     .post_load = ics_simple_dispatch_post_load,
 586     .fields = (VMStateField[]) {
 587         /* Sanity check */
 588         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
 589
 590         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 591                                              vmstate_ics_simple_irq,
 592                                              ICSIRQState),
 593         VMSTATE_END_OF_LIST()
 594     },
 595 };
 596
 597 static void ics_simple_initfn(Object *obj)
 598 {
 599     ICSState *ics = ICS_SIMPLE(obj);
 600
 601     ics->offset = XICS_IRQ_BASE;
 602 }
 603
 604 static void ics_simple_realize(DeviceState *dev, Error **errp)
 605 {
 606     ICSState *ics = ICS_SIMPLE(dev);
 607
 608     if (!ics->nr_irqs) {
 609         error_setg(errp, "Number of interrupts needs to be greater 0");
 610         return;
 611     }
 612     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 613     ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
 614 }
 615
 616 static Property ics_simple_properties[] = {
 617     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 618     DEFINE_PROP_END_OF_LIST(),
 619 };
 620
 621 static void ics_simple_class_init(ObjectClass *klass, void *data)
 622 {
 623     DeviceClass *dc = DEVICE_CLASS(klass);
 624     ICSStateClass *isc = ICS_BASE_CLASS(klass);
 625
 626     isc->realize = ics_simple_realize;
 627     dc->props = ics_simple_properties;
 628     dc->vmsd = &vmstate_ics_simple;
 629     dc->reset = ics_simple_reset;
 630     isc->reject = ics_simple_reject;
 631     isc->resend = ics_simple_resend;
 632     isc->eoi = ics_simple_eoi;
 633 }
 634
 635 static const TypeInfo ics_simple_info = {
 636     .name = TYPE_ICS_SIMPLE,
 637     .parent = TYPE_ICS_BASE,
 638     .instance_size = sizeof(ICSState),
 639     .class_init = ics_simple_class_init,
 640     .class_size = sizeof(ICSStateClass),
 641     .instance_init = ics_simple_initfn,
 642 };
 643
 644 static void ics_base_realize(DeviceState *dev, Error **errp)
 645 {
 646     ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
 647     ICSState *ics = ICS_BASE(dev);
 648     Object *obj;
 649     Error *err = NULL;
 650
 651     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 652     if (!obj) {
 653         error_setg(errp, "%s: required link 'xics' not found: %s",
 654                    __func__, error_get_pretty(err));
 655         return;
 656     }
 657     ics->xics = XICS_FABRIC(obj);
 658
 659
 660     if (icsc->realize) {
 661         icsc->realize(dev, errp);
 662     }
 663 }
 664
 665 static void ics_base_class_init(ObjectClass *klass, void *data)
 666 {
 667     DeviceClass *dc = DEVICE_CLASS(klass);
 668
 669     dc->realize = ics_base_realize;
 670 }
 671
 672 static const TypeInfo ics_base_info = {
 673     .name = TYPE_ICS_BASE,
 674     .parent = TYPE_DEVICE,
 675     .abstract = true,
 676     .instance_size = sizeof(ICSState),
 677     .class_init = ics_base_class_init,
 678     .class_size = sizeof(ICSStateClass),
 679 };
 680
 681 static const TypeInfo xics_fabric_info = {
 682     .name = TYPE_XICS_FABRIC,
 683     .parent = TYPE_INTERFACE,
 684     .class_size = sizeof(XICSFabricClass),
 685 };
 686
 687 /*
 688  * Exported functions
 689  */
 690 qemu_irq xics_get_qirq(XICSFabric *xi, int irq)
 691 {
 692     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 693     ICSState *ics = xic->ics_get(xi, irq);
 694
 695     if (ics) {
 696         return ics->qirqs[irq - ics->offset];
 697     }
 698
 699     return NULL;
 700 }
 701
 702 ICPState *xics_icp_get(XICSFabric *xi, int server)
 703 {
 704     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 705
 706     return xic->icp_get(xi, server);
 707 }
 708
 709 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 710 {
 711     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 712
 713     ics->irqs[srcno].flags |=
 714         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 715 }
 716
 717 static void xics_register_types(void)
 718 {
 719     type_register_static(&ics_simple_info);
 720     type_register_static(&ics_base_info);
 721     type_register_static(&icp_info);
 722     type_register_static(&xics_fabric_info);
 723 }
 724
 725 type_init(xics_register_types)