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hw/acpi: fix a DSDT table issue when a pxb is present.
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob5c0d643331a42a9028da0f65737f6315c2bd88d2
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
48
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/x86-iommu.h"
56 #include "hw/timer/hpet.h"
57
58 #include "hw/acpi/aml-build.h"
59
60 #include "qapi/qmp/qint.h"
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/x86-iommu.h"
63
64 #include "hw/acpi/ipmi.h"
65
66 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
67 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
68 * a little bit, there should be plenty of free space since the DSDT
69 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
70 */
71 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
72 #define ACPI_BUILD_ALIGN_SIZE 0x1000
73
74 #define ACPI_BUILD_TABLE_SIZE 0x20000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 /* Default IOAPIC ID */
85 #define ACPI_BUILD_IOAPIC_ID 0x0
86
87 typedef struct AcpiMcfgInfo {
88 uint64_t mcfg_base;
89 uint32_t mcfg_size;
90 } AcpiMcfgInfo;
91
92 typedef struct AcpiPmInfo {
93 bool s3_disabled;
94 bool s4_disabled;
95 bool pcihp_bridge_en;
96 uint8_t s4_val;
97 uint16_t sci_int;
98 uint8_t acpi_enable_cmd;
99 uint8_t acpi_disable_cmd;
100 uint32_t gpe0_blk;
101 uint32_t gpe0_blk_len;
102 uint32_t io_base;
103 uint16_t cpu_hp_io_base;
104 uint16_t mem_hp_io_base;
105 uint16_t mem_hp_io_len;
106 uint16_t pcihp_io_base;
107 uint16_t pcihp_io_len;
108 } AcpiPmInfo;
109
110 typedef struct AcpiMiscInfo {
111 bool is_piix4;
112 bool has_hpet;
113 TPMVersion tpm_version;
114 const unsigned char *dsdt_code;
115 unsigned dsdt_size;
116 uint16_t pvpanic_port;
117 uint16_t applesmc_io_base;
118 } AcpiMiscInfo;
119
120 typedef struct AcpiBuildPciBusHotplugState {
121 GArray *device_table;
122 GArray *notify_table;
123 struct AcpiBuildPciBusHotplugState *parent;
124 bool pcihp_bridge_en;
125 } AcpiBuildPciBusHotplugState;
126
127 static void acpi_get_pm_info(AcpiPmInfo *pm)
128 {
129 Object *piix = piix4_pm_find();
130 Object *lpc = ich9_lpc_find();
131 Object *obj = NULL;
132 QObject *o;
133
134 pm->cpu_hp_io_base = 0;
135 pm->pcihp_io_base = 0;
136 pm->pcihp_io_len = 0;
137 if (piix) {
138 obj = piix;
139 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
140 pm->pcihp_io_base =
141 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
142 pm->pcihp_io_len =
143 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
144 }
145 if (lpc) {
146 obj = lpc;
147 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
148 }
149 assert(obj);
150
151 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
152 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
153
154 /* Fill in optional s3/s4 related properties */
155 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
156 if (o) {
157 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
158 } else {
159 pm->s3_disabled = false;
160 }
161 qobject_decref(o);
162 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
163 if (o) {
164 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
165 } else {
166 pm->s4_disabled = false;
167 }
168 qobject_decref(o);
169 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
170 if (o) {
171 pm->s4_val = qint_get_int(qobject_to_qint(o));
172 } else {
173 pm->s4_val = false;
174 }
175 qobject_decref(o);
176
177 /* Fill in mandatory properties */
178 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
179
180 pm->acpi_enable_cmd = object_property_get_int(obj,
181 ACPI_PM_PROP_ACPI_ENABLE_CMD,
182 NULL);
183 pm->acpi_disable_cmd = object_property_get_int(obj,
184 ACPI_PM_PROP_ACPI_DISABLE_CMD,
185 NULL);
186 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
187 NULL);
188 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
189 NULL);
190 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
191 NULL);
192 pm->pcihp_bridge_en =
193 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
194 NULL);
195 }
196
197 static void acpi_get_misc_info(AcpiMiscInfo *info)
198 {
199 Object *piix = piix4_pm_find();
200 Object *lpc = ich9_lpc_find();
201 assert(!!piix != !!lpc);
202
203 if (piix) {
204 info->is_piix4 = true;
205 }
206 if (lpc) {
207 info->is_piix4 = false;
208 }
209
210 info->has_hpet = hpet_find();
211 info->tpm_version = tpm_get_version();
212 info->pvpanic_port = pvpanic_port();
213 info->applesmc_io_base = applesmc_port();
214 }
215
216 /*
217 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
218 * On i386 arch we only have two pci hosts, so we can look only for them.
219 */
220 static Object *acpi_get_i386_pci_host(void)
221 {
222 PCIHostState *host;
223
224 host = OBJECT_CHECK(PCIHostState,
225 object_resolve_path("/machine/i440fx", NULL),
226 TYPE_PCI_HOST_BRIDGE);
227 if (!host) {
228 host = OBJECT_CHECK(PCIHostState,
229 object_resolve_path("/machine/q35", NULL),
230 TYPE_PCI_HOST_BRIDGE);
231 }
232
233 return OBJECT(host);
234 }
235
236 static void acpi_get_pci_holes(Range *hole, Range *hole64)
237 {
238 Object *pci_host;
239
240 pci_host = acpi_get_i386_pci_host();
241 g_assert(pci_host);
242
243 range_set_bounds1(hole,
244 object_property_get_int(pci_host,
245 PCI_HOST_PROP_PCI_HOLE_START,
246 NULL),
247 object_property_get_int(pci_host,
248 PCI_HOST_PROP_PCI_HOLE_END,
249 NULL));
250 range_set_bounds1(hole64,
251 object_property_get_int(pci_host,
252 PCI_HOST_PROP_PCI_HOLE64_START,
253 NULL),
254 object_property_get_int(pci_host,
255 PCI_HOST_PROP_PCI_HOLE64_END,
256 NULL));
257 }
258
259 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
260
261 static void acpi_align_size(GArray *blob, unsigned align)
262 {
263 /* Align size to multiple of given size. This reduces the chance
264 * we need to change size in the future (breaking cross version migration).
265 */
266 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
267 }
268
269 /* FACS */
270 static void
271 build_facs(GArray *table_data, BIOSLinker *linker)
272 {
273 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
274 memcpy(&facs->signature, "FACS", 4);
275 facs->length = cpu_to_le32(sizeof(*facs));
276 }
277
278 /* Load chipset information in FADT */
279 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
280 {
281 fadt->model = 1;
282 fadt->reserved1 = 0;
283 fadt->sci_int = cpu_to_le16(pm->sci_int);
284 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
285 fadt->acpi_enable = pm->acpi_enable_cmd;
286 fadt->acpi_disable = pm->acpi_disable_cmd;
287 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
288 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
289 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
290 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
291 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
292 /* EVT, CNT, TMR length matches hw/acpi/core.c */
293 fadt->pm1_evt_len = 4;
294 fadt->pm1_cnt_len = 2;
295 fadt->pm_tmr_len = 4;
296 fadt->gpe0_blk_len = pm->gpe0_blk_len;
297 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
298 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
299 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
300 (1 << ACPI_FADT_F_PROC_C1) |
301 (1 << ACPI_FADT_F_SLP_BUTTON) |
302 (1 << ACPI_FADT_F_RTC_S4));
303 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
304 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
305 * For more than 8 CPUs, "Clustered Logical" mode has to be used
306 */
307 if (max_cpus > 8) {
308 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
309 }
310 fadt->century = RTC_CENTURY;
311 }
312
313
314 /* FADT */
315 static void
316 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
317 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
318 const char *oem_id, const char *oem_table_id)
319 {
320 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
321 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
322 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
323
324 /* FACS address to be filled by Guest linker */
325 bios_linker_loader_add_pointer(linker,
326 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
327 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
328
329 /* DSDT address to be filled by Guest linker */
330 fadt_setup(fadt, pm);
331 bios_linker_loader_add_pointer(linker,
332 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
333 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
334
335 build_header(linker, table_data,
336 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
337 }
338
339 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
340 CPUArchIdList *apic_ids, GArray *entry)
341 {
342 int apic_id;
343 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
344
345 apic_id = apic_ids->cpus[uid].arch_id;
346 apic->type = ACPI_APIC_PROCESSOR;
347 apic->length = sizeof(*apic);
348 apic->processor_id = uid;
349 apic->local_apic_id = apic_id;
350 if (apic_ids->cpus[uid].cpu != NULL) {
351 apic->flags = cpu_to_le32(1);
352 } else {
353 /* ACPI spec says that LAPIC entry for non present
354 * CPU may be omitted from MADT or it must be marked
355 * as disabled. However omitting non present CPU from
356 * MADT breaks hotplug on linux. So possible CPUs
357 * should be put in MADT but kept disabled.
358 */
359 apic->flags = cpu_to_le32(0);
360 }
361 }
362
363 static void
364 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
365 {
366 MachineClass *mc = MACHINE_GET_CLASS(pcms);
367 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
368 int madt_start = table_data->len;
369 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
370 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
371
372 AcpiMultipleApicTable *madt;
373 AcpiMadtIoApic *io_apic;
374 AcpiMadtIntsrcovr *intsrcovr;
375 AcpiMadtLocalNmi *local_nmi;
376 int i;
377
378 madt = acpi_data_push(table_data, sizeof *madt);
379 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
380 madt->flags = cpu_to_le32(1);
381
382 for (i = 0; i < apic_ids->len; i++) {
383 adevc->madt_cpu(adev, i, apic_ids, table_data);
384 }
385 g_free(apic_ids);
386
387 io_apic = acpi_data_push(table_data, sizeof *io_apic);
388 io_apic->type = ACPI_APIC_IO;
389 io_apic->length = sizeof(*io_apic);
390 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
391 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
392 io_apic->interrupt = cpu_to_le32(0);
393
394 if (pcms->apic_xrupt_override) {
395 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
396 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
397 intsrcovr->length = sizeof(*intsrcovr);
398 intsrcovr->source = 0;
399 intsrcovr->gsi = cpu_to_le32(2);
400 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
401 }
402 for (i = 1; i < 16; i++) {
403 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
404 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
405 /* No need for a INT source override structure. */
406 continue;
407 }
408 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
409 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
410 intsrcovr->length = sizeof(*intsrcovr);
411 intsrcovr->source = i;
412 intsrcovr->gsi = cpu_to_le32(i);
413 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
414 }
415
416 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
417 local_nmi->type = ACPI_APIC_LOCAL_NMI;
418 local_nmi->length = sizeof(*local_nmi);
419 local_nmi->processor_id = 0xff; /* all processors */
420 local_nmi->flags = cpu_to_le16(0);
421 local_nmi->lint = 1; /* ACPI_LINT1 */
422
423 build_header(linker, table_data,
424 (void *)(table_data->data + madt_start), "APIC",
425 table_data->len - madt_start, 1, NULL, NULL);
426 }
427
428 /* Assign BSEL property to all buses. In the future, this can be changed
429 * to only assign to buses that support hotplug.
430 */
431 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
432 {
433 unsigned *bsel_alloc = opaque;
434 unsigned *bus_bsel;
435
436 if (qbus_is_hotpluggable(BUS(bus))) {
437 bus_bsel = g_malloc(sizeof *bus_bsel);
438
439 *bus_bsel = (*bsel_alloc)++;
440 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
441 bus_bsel, NULL);
442 }
443
444 return bsel_alloc;
445 }
446
447 static void acpi_set_pci_info(void)
448 {
449 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
450 unsigned bsel_alloc = 0;
451
452 if (bus) {
453 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
454 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
455 }
456 }
457
458 static void build_append_pcihp_notify_entry(Aml *method, int slot)
459 {
460 Aml *if_ctx;
461 int32_t devfn = PCI_DEVFN(slot, 0);
462
463 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
464 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
465 aml_append(method, if_ctx);
466 }
467
468 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
469 bool pcihp_bridge_en)
470 {
471 Aml *dev, *notify_method, *method;
472 QObject *bsel;
473 PCIBus *sec;
474 int i;
475
476 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
477 if (bsel) {
478 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
479
480 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
481 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
482 }
483
484 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
485 DeviceClass *dc;
486 PCIDeviceClass *pc;
487 PCIDevice *pdev = bus->devices[i];
488 int slot = PCI_SLOT(i);
489 bool hotplug_enabled_dev;
490 bool bridge_in_acpi;
491
492 if (!pdev) {
493 if (bsel) { /* add hotplug slots for non present devices */
494 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
495 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
496 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
497 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
498 aml_append(method,
499 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
500 );
501 aml_append(dev, method);
502 aml_append(parent_scope, dev);
503
504 build_append_pcihp_notify_entry(notify_method, slot);
505 }
506 continue;
507 }
508
509 pc = PCI_DEVICE_GET_CLASS(pdev);
510 dc = DEVICE_GET_CLASS(pdev);
511
512 /* When hotplug for bridges is enabled, bridges are
513 * described in ACPI separately (see build_pci_bus_end).
514 * In this case they aren't themselves hot-pluggable.
515 * Hotplugged bridges *are* hot-pluggable.
516 */
517 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
518 !DEVICE(pdev)->hotplugged;
519
520 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
521
522 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
523 continue;
524 }
525
526 /* start to compose PCI slot descriptor */
527 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
528 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
529
530 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
531 /* add VGA specific AML methods */
532 int s3d;
533
534 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
535 s3d = 3;
536 } else {
537 s3d = 0;
538 }
539
540 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
541 aml_append(method, aml_return(aml_int(0)));
542 aml_append(dev, method);
543
544 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
545 aml_append(method, aml_return(aml_int(0)));
546 aml_append(dev, method);
547
548 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
549 aml_append(method, aml_return(aml_int(s3d)));
550 aml_append(dev, method);
551 } else if (hotplug_enabled_dev) {
552 /* add _SUN/_EJ0 to make slot hotpluggable */
553 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
554
555 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
556 aml_append(method,
557 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
558 );
559 aml_append(dev, method);
560
561 if (bsel) {
562 build_append_pcihp_notify_entry(notify_method, slot);
563 }
564 } else if (bridge_in_acpi) {
565 /*
566 * device is coldplugged bridge,
567 * add child device descriptions into its scope
568 */
569 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
570
571 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
572 }
573 /* slot descriptor has been composed, add it into parent context */
574 aml_append(parent_scope, dev);
575 }
576
577 if (bsel) {
578 aml_append(parent_scope, notify_method);
579 }
580
581 /* Append PCNT method to notify about events on local and child buses.
582 * Add unconditionally for root since DSDT expects it.
583 */
584 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
585
586 /* If bus supports hotplug select it and notify about local events */
587 if (bsel) {
588 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
589 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
590 aml_append(method,
591 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
592 );
593 aml_append(method,
594 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
595 );
596 }
597
598 /* Notify about child bus events in any case */
599 if (pcihp_bridge_en) {
600 QLIST_FOREACH(sec, &bus->child, sibling) {
601 int32_t devfn = sec->parent_dev->devfn;
602
603 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
604 continue;
605 }
606
607 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
608 }
609 }
610 aml_append(parent_scope, method);
611 qobject_decref(bsel);
612 }
613
614 /**
615 * build_prt_entry:
616 * @link_name: link name for PCI route entry
617 *
618 * build AML package containing a PCI route entry for @link_name
619 */
620 static Aml *build_prt_entry(const char *link_name)
621 {
622 Aml *a_zero = aml_int(0);
623 Aml *pkg = aml_package(4);
624 aml_append(pkg, a_zero);
625 aml_append(pkg, a_zero);
626 aml_append(pkg, aml_name("%s", link_name));
627 aml_append(pkg, a_zero);
628 return pkg;
629 }
630
631 /*
632 * initialize_route - Initialize the interrupt routing rule
633 * through a specific LINK:
634 * if (lnk_idx == idx)
635 * route using link 'link_name'
636 */
637 static Aml *initialize_route(Aml *route, const char *link_name,
638 Aml *lnk_idx, int idx)
639 {
640 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
641 Aml *pkg = build_prt_entry(link_name);
642
643 aml_append(if_ctx, aml_store(pkg, route));
644
645 return if_ctx;
646 }
647
648 /*
649 * build_prt - Define interrupt rounting rules
650 *
651 * Returns an array of 128 routes, one for each device,
652 * based on device location.
653 * The main goal is to equaly distribute the interrupts
654 * over the 4 existing ACPI links (works only for i440fx).
655 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
656 *
657 */
658 static Aml *build_prt(bool is_pci0_prt)
659 {
660 Aml *method, *while_ctx, *pin, *res;
661
662 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
663 res = aml_local(0);
664 pin = aml_local(1);
665 aml_append(method, aml_store(aml_package(128), res));
666 aml_append(method, aml_store(aml_int(0), pin));
667
668 /* while (pin < 128) */
669 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
670 {
671 Aml *slot = aml_local(2);
672 Aml *lnk_idx = aml_local(3);
673 Aml *route = aml_local(4);
674
675 /* slot = pin >> 2 */
676 aml_append(while_ctx,
677 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
678 /* lnk_idx = (slot + pin) & 3 */
679 aml_append(while_ctx,
680 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
681 lnk_idx));
682
683 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
684 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
685 if (is_pci0_prt) {
686 Aml *if_device_1, *if_pin_4, *else_pin_4;
687
688 /* device 1 is the power-management device, needs SCI */
689 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
690 {
691 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
692 {
693 aml_append(if_pin_4,
694 aml_store(build_prt_entry("LNKS"), route));
695 }
696 aml_append(if_device_1, if_pin_4);
697 else_pin_4 = aml_else();
698 {
699 aml_append(else_pin_4,
700 aml_store(build_prt_entry("LNKA"), route));
701 }
702 aml_append(if_device_1, else_pin_4);
703 }
704 aml_append(while_ctx, if_device_1);
705 } else {
706 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
707 }
708 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
709 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
710
711 /* route[0] = 0x[slot]FFFF */
712 aml_append(while_ctx,
713 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
714 NULL),
715 aml_index(route, aml_int(0))));
716 /* route[1] = pin & 3 */
717 aml_append(while_ctx,
718 aml_store(aml_and(pin, aml_int(3), NULL),
719 aml_index(route, aml_int(1))));
720 /* res[pin] = route */
721 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
722 /* pin++ */
723 aml_append(while_ctx, aml_increment(pin));
724 }
725 aml_append(method, while_ctx);
726 /* return res*/
727 aml_append(method, aml_return(res));
728
729 return method;
730 }
731
732 typedef struct CrsRangeEntry {
733 uint64_t base;
734 uint64_t limit;
735 } CrsRangeEntry;
736
737 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
738 {
739 CrsRangeEntry *entry;
740
741 entry = g_malloc(sizeof(*entry));
742 entry->base = base;
743 entry->limit = limit;
744
745 g_ptr_array_add(ranges, entry);
746 }
747
748 static void crs_range_free(gpointer data)
749 {
750 CrsRangeEntry *entry = (CrsRangeEntry *)data;
751 g_free(entry);
752 }
753
754 static gint crs_range_compare(gconstpointer a, gconstpointer b)
755 {
756 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
757 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
758
759 return (int64_t)entry_a->base - (int64_t)entry_b->base;
760 }
761
762 /*
763 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
764 * interval, computes the 'free' ranges from the same interval.
765 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
766 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
767 */
768 static void crs_replace_with_free_ranges(GPtrArray *ranges,
769 uint64_t start, uint64_t end)
770 {
771 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
772 uint64_t free_base = start;
773 int i;
774
775 g_ptr_array_sort(ranges, crs_range_compare);
776 for (i = 0; i < ranges->len; i++) {
777 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
778
779 if (free_base < used->base) {
780 crs_range_insert(free_ranges, free_base, used->base - 1);
781 }
782
783 free_base = used->limit + 1;
784 }
785
786 if (free_base < end) {
787 crs_range_insert(free_ranges, free_base, end);
788 }
789
790 g_ptr_array_set_size(ranges, 0);
791 for (i = 0; i < free_ranges->len; i++) {
792 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
793 }
794
795 g_ptr_array_free(free_ranges, false);
796 }
797
798 /*
799 * crs_range_merge - merges adjacent ranges in the given array.
800 * Array elements are deleted and replaced with the merged ranges.
801 */
802 static void crs_range_merge(GPtrArray *range)
803 {
804 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
805 CrsRangeEntry *entry;
806 uint64_t range_base, range_limit;
807 int i;
808
809 if (!range->len) {
810 return;
811 }
812
813 g_ptr_array_sort(range, crs_range_compare);
814
815 entry = g_ptr_array_index(range, 0);
816 range_base = entry->base;
817 range_limit = entry->limit;
818 for (i = 1; i < range->len; i++) {
819 entry = g_ptr_array_index(range, i);
820 if (entry->base - 1 == range_limit) {
821 range_limit = entry->limit;
822 } else {
823 crs_range_insert(tmp, range_base, range_limit);
824 range_base = entry->base;
825 range_limit = entry->limit;
826 }
827 }
828 crs_range_insert(tmp, range_base, range_limit);
829
830 g_ptr_array_set_size(range, 0);
831 for (i = 0; i < tmp->len; i++) {
832 entry = g_ptr_array_index(tmp, i);
833 crs_range_insert(range, entry->base, entry->limit);
834 }
835 g_ptr_array_free(tmp, true);
836 }
837
838 static Aml *build_crs(PCIHostState *host,
839 GPtrArray *io_ranges, GPtrArray *mem_ranges)
840 {
841 Aml *crs = aml_resource_template();
842 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
843 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
844 CrsRangeEntry *entry;
845 uint8_t max_bus = pci_bus_num(host->bus);
846 uint8_t type;
847 int devfn;
848 int i;
849
850 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
851 uint64_t range_base, range_limit;
852 PCIDevice *dev = host->bus->devices[devfn];
853
854 if (!dev) {
855 continue;
856 }
857
858 for (i = 0; i < PCI_NUM_REGIONS; i++) {
859 PCIIORegion *r = &dev->io_regions[i];
860
861 range_base = r->addr;
862 range_limit = r->addr + r->size - 1;
863
864 /*
865 * Work-around for old bioses
866 * that do not support multiple root buses
867 */
868 if (!range_base || range_base > range_limit) {
869 continue;
870 }
871
872 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
873 crs_range_insert(host_io_ranges, range_base, range_limit);
874 } else { /* "memory" */
875 crs_range_insert(host_mem_ranges, range_base, range_limit);
876 }
877 }
878
879 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
880 if (type == PCI_HEADER_TYPE_BRIDGE) {
881 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
882 if (subordinate > max_bus) {
883 max_bus = subordinate;
884 }
885
886 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
887 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
888
889 /*
890 * Work-around for old bioses
891 * that do not support multiple root buses
892 */
893 if (range_base && range_base <= range_limit) {
894 crs_range_insert(host_io_ranges, range_base, range_limit);
895 }
896
897 range_base =
898 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
899 range_limit =
900 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
901
902 /*
903 * Work-around for old bioses
904 * that do not support multiple root buses
905 */
906 if (range_base && range_base <= range_limit) {
907 crs_range_insert(host_mem_ranges, range_base, range_limit);
908 }
909
910 range_base =
911 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
912 range_limit =
913 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
914
915 /*
916 * Work-around for old bioses
917 * that do not support multiple root buses
918 */
919 if (range_base && range_base <= range_limit) {
920 crs_range_insert(host_mem_ranges, range_base, range_limit);
921 }
922 }
923 }
924
925 crs_range_merge(host_io_ranges);
926 for (i = 0; i < host_io_ranges->len; i++) {
927 entry = g_ptr_array_index(host_io_ranges, i);
928 aml_append(crs,
929 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
930 AML_POS_DECODE, AML_ENTIRE_RANGE,
931 0, entry->base, entry->limit, 0,
932 entry->limit - entry->base + 1));
933 crs_range_insert(io_ranges, entry->base, entry->limit);
934 }
935 g_ptr_array_free(host_io_ranges, true);
936
937 crs_range_merge(host_mem_ranges);
938 for (i = 0; i < host_mem_ranges->len; i++) {
939 entry = g_ptr_array_index(host_mem_ranges, i);
940 aml_append(crs,
941 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
942 AML_MAX_FIXED, AML_NON_CACHEABLE,
943 AML_READ_WRITE,
944 0, entry->base, entry->limit, 0,
945 entry->limit - entry->base + 1));
946 crs_range_insert(mem_ranges, entry->base, entry->limit);
947 }
948 g_ptr_array_free(host_mem_ranges, true);
949
950 aml_append(crs,
951 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
952 0,
953 pci_bus_num(host->bus),
954 max_bus,
955 0,
956 max_bus - pci_bus_num(host->bus) + 1));
957
958 return crs;
959 }
960
961 static void build_memory_devices(Aml *sb_scope, int nr_mem,
962 uint16_t io_base, uint16_t io_len)
963 {
964 int i;
965 Aml *scope;
966 Aml *crs;
967 Aml *field;
968 Aml *dev;
969 Aml *method;
970 Aml *ifctx;
971
972 /* build memory devices */
973 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
974 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
975 aml_append(scope,
976 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
977 );
978
979 crs = aml_resource_template();
980 aml_append(crs,
981 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
982 );
983 aml_append(scope, aml_name_decl("_CRS", crs));
984
985 aml_append(scope, aml_operation_region(
986 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
987 aml_int(io_base), io_len)
988 );
989
990 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
991 AML_NOLOCK, AML_PRESERVE);
992 aml_append(field, /* read only */
993 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
994 aml_append(field, /* read only */
995 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
996 aml_append(field, /* read only */
997 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
998 aml_append(field, /* read only */
999 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1000 aml_append(field, /* read only */
1001 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1002 aml_append(scope, field);
1003
1004 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1005 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1006 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1007 aml_append(field, /* 1 if enabled, read only */
1008 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1009 aml_append(field,
1010 /*(read) 1 if has a insert event. (write) 1 to clear event */
1011 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1012 aml_append(field,
1013 /* (read) 1 if has a remove event. (write) 1 to clear event */
1014 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1015 aml_append(field,
1016 /* initiates device eject, write only */
1017 aml_named_field(MEMORY_SLOT_EJECT, 1));
1018 aml_append(scope, field);
1019
1020 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1021 AML_NOLOCK, AML_PRESERVE);
1022 aml_append(field, /* DIMM selector, write only */
1023 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1024 aml_append(field, /* _OST event code, write only */
1025 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1026 aml_append(field, /* _OST status code, write only */
1027 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1028 aml_append(scope, field);
1029 aml_append(sb_scope, scope);
1030
1031 for (i = 0; i < nr_mem; i++) {
1032 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1033 const char *s;
1034
1035 dev = aml_device("MP%02X", i);
1036 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1037 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1038
1039 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1040 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1041 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1042 aml_append(dev, method);
1043
1044 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1045 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1046 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1047 aml_append(dev, method);
1048
1049 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1050 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1051 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1052 aml_append(dev, method);
1053
1054 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1055 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1056
1057 aml_append(method, aml_return(aml_call4(
1058 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1059 )));
1060 aml_append(dev, method);
1061
1062 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1063 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1064 aml_append(method, aml_return(aml_call2(
1065 s, aml_name("_UID"), aml_arg(0))));
1066 aml_append(dev, method);
1067
1068 aml_append(sb_scope, dev);
1069 }
1070
1071 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1072 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1073 */
1074 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1075 for (i = 0; i < nr_mem; i++) {
1076 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1077 aml_append(ifctx,
1078 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1079 );
1080 aml_append(method, ifctx);
1081 }
1082 aml_append(sb_scope, method);
1083 }
1084
1085 static void build_hpet_aml(Aml *table)
1086 {
1087 Aml *crs;
1088 Aml *field;
1089 Aml *method;
1090 Aml *if_ctx;
1091 Aml *scope = aml_scope("_SB");
1092 Aml *dev = aml_device("HPET");
1093 Aml *zero = aml_int(0);
1094 Aml *id = aml_local(0);
1095 Aml *period = aml_local(1);
1096
1097 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1098 aml_append(dev, aml_name_decl("_UID", zero));
1099
1100 aml_append(dev,
1101 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1102 HPET_LEN));
1103 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1104 aml_append(field, aml_named_field("VEND", 32));
1105 aml_append(field, aml_named_field("PRD", 32));
1106 aml_append(dev, field);
1107
1108 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1109 aml_append(method, aml_store(aml_name("VEND"), id));
1110 aml_append(method, aml_store(aml_name("PRD"), period));
1111 aml_append(method, aml_shiftright(id, aml_int(16), id));
1112 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1113 aml_equal(id, aml_int(0xffff))));
1114 {
1115 aml_append(if_ctx, aml_return(zero));
1116 }
1117 aml_append(method, if_ctx);
1118
1119 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1120 aml_lgreater(period, aml_int(100000000))));
1121 {
1122 aml_append(if_ctx, aml_return(zero));
1123 }
1124 aml_append(method, if_ctx);
1125
1126 aml_append(method, aml_return(aml_int(0x0F)));
1127 aml_append(dev, method);
1128
1129 crs = aml_resource_template();
1130 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1131 aml_append(dev, aml_name_decl("_CRS", crs));
1132
1133 aml_append(scope, dev);
1134 aml_append(table, scope);
1135 }
1136
1137 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1138 {
1139 Aml *dev, *fdi;
1140 uint8_t maxc, maxh, maxs;
1141
1142 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1143
1144 dev = aml_device("FLP%c", 'A' + idx);
1145
1146 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1147
1148 fdi = aml_package(16);
1149 aml_append(fdi, aml_int(idx)); /* Drive Number */
1150 aml_append(fdi,
1151 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1152 /*
1153 * the values below are the limits of the drive, and are thus independent
1154 * of the inserted media
1155 */
1156 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1157 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1158 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1159 /*
1160 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1161 * the drive type, so shall we
1162 */
1163 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1164 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1165 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1166 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1167 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1168 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1169 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1170 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1171 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1172 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1173 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1174
1175 aml_append(dev, aml_name_decl("_FDI", fdi));
1176 return dev;
1177 }
1178
1179 static Aml *build_fdc_device_aml(ISADevice *fdc)
1180 {
1181 int i;
1182 Aml *dev;
1183 Aml *crs;
1184
1185 #define ACPI_FDE_MAX_FD 4
1186 uint32_t fde_buf[5] = {
1187 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1188 cpu_to_le32(2) /* tape presence (2 == never present) */
1189 };
1190
1191 dev = aml_device("FDC0");
1192 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1193
1194 crs = aml_resource_template();
1195 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1196 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1197 aml_append(crs, aml_irq_no_flags(6));
1198 aml_append(crs,
1199 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1200 aml_append(dev, aml_name_decl("_CRS", crs));
1201
1202 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1203 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1204
1205 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1206 fde_buf[i] = cpu_to_le32(1); /* drive present */
1207 aml_append(dev, build_fdinfo_aml(i, type));
1208 }
1209 }
1210 aml_append(dev, aml_name_decl("_FDE",
1211 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1212
1213 return dev;
1214 }
1215
1216 static Aml *build_rtc_device_aml(void)
1217 {
1218 Aml *dev;
1219 Aml *crs;
1220
1221 dev = aml_device("RTC");
1222 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1223 crs = aml_resource_template();
1224 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1225 aml_append(crs, aml_irq_no_flags(8));
1226 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1227 aml_append(dev, aml_name_decl("_CRS", crs));
1228
1229 return dev;
1230 }
1231
1232 static Aml *build_kbd_device_aml(void)
1233 {
1234 Aml *dev;
1235 Aml *crs;
1236 Aml *method;
1237
1238 dev = aml_device("KBD");
1239 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1240
1241 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1242 aml_append(method, aml_return(aml_int(0x0f)));
1243 aml_append(dev, method);
1244
1245 crs = aml_resource_template();
1246 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1247 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1248 aml_append(crs, aml_irq_no_flags(1));
1249 aml_append(dev, aml_name_decl("_CRS", crs));
1250
1251 return dev;
1252 }
1253
1254 static Aml *build_mouse_device_aml(void)
1255 {
1256 Aml *dev;
1257 Aml *crs;
1258 Aml *method;
1259
1260 dev = aml_device("MOU");
1261 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1262
1263 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1264 aml_append(method, aml_return(aml_int(0x0f)));
1265 aml_append(dev, method);
1266
1267 crs = aml_resource_template();
1268 aml_append(crs, aml_irq_no_flags(12));
1269 aml_append(dev, aml_name_decl("_CRS", crs));
1270
1271 return dev;
1272 }
1273
1274 static Aml *build_lpt_device_aml(void)
1275 {
1276 Aml *dev;
1277 Aml *crs;
1278 Aml *method;
1279 Aml *if_ctx;
1280 Aml *else_ctx;
1281 Aml *zero = aml_int(0);
1282 Aml *is_present = aml_local(0);
1283
1284 dev = aml_device("LPT");
1285 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1286
1287 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1288 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1289 if_ctx = aml_if(aml_equal(is_present, zero));
1290 {
1291 aml_append(if_ctx, aml_return(aml_int(0x00)));
1292 }
1293 aml_append(method, if_ctx);
1294 else_ctx = aml_else();
1295 {
1296 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1297 }
1298 aml_append(method, else_ctx);
1299 aml_append(dev, method);
1300
1301 crs = aml_resource_template();
1302 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1303 aml_append(crs, aml_irq_no_flags(7));
1304 aml_append(dev, aml_name_decl("_CRS", crs));
1305
1306 return dev;
1307 }
1308
1309 static Aml *build_com_device_aml(uint8_t uid)
1310 {
1311 Aml *dev;
1312 Aml *crs;
1313 Aml *method;
1314 Aml *if_ctx;
1315 Aml *else_ctx;
1316 Aml *zero = aml_int(0);
1317 Aml *is_present = aml_local(0);
1318 const char *enabled_field = "CAEN";
1319 uint8_t irq = 4;
1320 uint16_t io_port = 0x03F8;
1321
1322 assert(uid == 1 || uid == 2);
1323 if (uid == 2) {
1324 enabled_field = "CBEN";
1325 irq = 3;
1326 io_port = 0x02F8;
1327 }
1328
1329 dev = aml_device("COM%d", uid);
1330 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1331 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1332
1333 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1334 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1335 if_ctx = aml_if(aml_equal(is_present, zero));
1336 {
1337 aml_append(if_ctx, aml_return(aml_int(0x00)));
1338 }
1339 aml_append(method, if_ctx);
1340 else_ctx = aml_else();
1341 {
1342 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1343 }
1344 aml_append(method, else_ctx);
1345 aml_append(dev, method);
1346
1347 crs = aml_resource_template();
1348 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1349 aml_append(crs, aml_irq_no_flags(irq));
1350 aml_append(dev, aml_name_decl("_CRS", crs));
1351
1352 return dev;
1353 }
1354
1355 static void build_isa_devices_aml(Aml *table)
1356 {
1357 ISADevice *fdc = pc_find_fdc0();
1358 bool ambiguous;
1359
1360 Aml *scope = aml_scope("_SB.PCI0.ISA");
1361 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1362
1363 aml_append(scope, build_rtc_device_aml());
1364 aml_append(scope, build_kbd_device_aml());
1365 aml_append(scope, build_mouse_device_aml());
1366 if (fdc) {
1367 aml_append(scope, build_fdc_device_aml(fdc));
1368 }
1369 aml_append(scope, build_lpt_device_aml());
1370 aml_append(scope, build_com_device_aml(1));
1371 aml_append(scope, build_com_device_aml(2));
1372
1373 if (ambiguous) {
1374 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1375 } else if (!obj) {
1376 error_report("No ISA bus, unable to define IPMI ACPI data");
1377 } else {
1378 build_acpi_ipmi_devices(scope, BUS(obj));
1379 }
1380
1381 aml_append(table, scope);
1382 }
1383
1384 static void build_dbg_aml(Aml *table)
1385 {
1386 Aml *field;
1387 Aml *method;
1388 Aml *while_ctx;
1389 Aml *scope = aml_scope("\\");
1390 Aml *buf = aml_local(0);
1391 Aml *len = aml_local(1);
1392 Aml *idx = aml_local(2);
1393
1394 aml_append(scope,
1395 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1396 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1397 aml_append(field, aml_named_field("DBGB", 8));
1398 aml_append(scope, field);
1399
1400 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1401
1402 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1403 aml_append(method, aml_to_buffer(buf, buf));
1404 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1405 aml_append(method, aml_store(aml_int(0), idx));
1406
1407 while_ctx = aml_while(aml_lless(idx, len));
1408 aml_append(while_ctx,
1409 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1410 aml_append(while_ctx, aml_increment(idx));
1411 aml_append(method, while_ctx);
1412
1413 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1414 aml_append(scope, method);
1415
1416 aml_append(table, scope);
1417 }
1418
1419 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1420 {
1421 Aml *dev;
1422 Aml *crs;
1423 Aml *method;
1424 uint32_t irqs[] = {5, 10, 11};
1425
1426 dev = aml_device("%s", name);
1427 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1428 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1429
1430 crs = aml_resource_template();
1431 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1432 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1433 aml_append(dev, aml_name_decl("_PRS", crs));
1434
1435 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1436 aml_append(method, aml_return(aml_call1("IQST", reg)));
1437 aml_append(dev, method);
1438
1439 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1440 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1441 aml_append(dev, method);
1442
1443 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1444 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1445 aml_append(dev, method);
1446
1447 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1448 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1449 aml_append(method, aml_store(aml_name("PRRI"), reg));
1450 aml_append(dev, method);
1451
1452 return dev;
1453 }
1454
1455 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1456 {
1457 Aml *dev;
1458 Aml *crs;
1459 Aml *method;
1460 uint32_t irqs;
1461
1462 dev = aml_device("%s", name);
1463 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1464 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1465
1466 crs = aml_resource_template();
1467 irqs = gsi;
1468 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1469 AML_SHARED, &irqs, 1));
1470 aml_append(dev, aml_name_decl("_PRS", crs));
1471
1472 aml_append(dev, aml_name_decl("_CRS", crs));
1473
1474 /*
1475 * _DIS can be no-op because the interrupt cannot be disabled.
1476 */
1477 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1478 aml_append(dev, method);
1479
1480 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1481 aml_append(dev, method);
1482
1483 return dev;
1484 }
1485
1486 /* _CRS method - get current settings */
1487 static Aml *build_iqcr_method(bool is_piix4)
1488 {
1489 Aml *if_ctx;
1490 uint32_t irqs;
1491 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1492 Aml *crs = aml_resource_template();
1493
1494 irqs = 0;
1495 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1496 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1497 aml_append(method, aml_name_decl("PRR0", crs));
1498
1499 aml_append(method,
1500 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1501
1502 if (is_piix4) {
1503 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1504 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1505 aml_append(method, if_ctx);
1506 } else {
1507 aml_append(method,
1508 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1509 aml_name("PRRI")));
1510 }
1511
1512 aml_append(method, aml_return(aml_name("PRR0")));
1513 return method;
1514 }
1515
1516 /* _STA method - get status */
1517 static Aml *build_irq_status_method(void)
1518 {
1519 Aml *if_ctx;
1520 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1521
1522 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1523 aml_append(if_ctx, aml_return(aml_int(0x09)));
1524 aml_append(method, if_ctx);
1525 aml_append(method, aml_return(aml_int(0x0B)));
1526 return method;
1527 }
1528
1529 static void build_piix4_pci0_int(Aml *table)
1530 {
1531 Aml *dev;
1532 Aml *crs;
1533 Aml *field;
1534 Aml *method;
1535 uint32_t irqs;
1536 Aml *sb_scope = aml_scope("_SB");
1537 Aml *pci0_scope = aml_scope("PCI0");
1538
1539 aml_append(pci0_scope, build_prt(true));
1540 aml_append(sb_scope, pci0_scope);
1541
1542 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1543 aml_append(field, aml_named_field("PRQ0", 8));
1544 aml_append(field, aml_named_field("PRQ1", 8));
1545 aml_append(field, aml_named_field("PRQ2", 8));
1546 aml_append(field, aml_named_field("PRQ3", 8));
1547 aml_append(sb_scope, field);
1548
1549 aml_append(sb_scope, build_irq_status_method());
1550 aml_append(sb_scope, build_iqcr_method(true));
1551
1552 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1553 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1554 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1555 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1556
1557 dev = aml_device("LNKS");
1558 {
1559 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1560 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1561
1562 crs = aml_resource_template();
1563 irqs = 9;
1564 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1565 AML_ACTIVE_HIGH, AML_SHARED,
1566 &irqs, 1));
1567 aml_append(dev, aml_name_decl("_PRS", crs));
1568
1569 /* The SCI cannot be disabled and is always attached to GSI 9,
1570 * so these are no-ops. We only need this link to override the
1571 * polarity to active high and match the content of the MADT.
1572 */
1573 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1574 aml_append(method, aml_return(aml_int(0x0b)));
1575 aml_append(dev, method);
1576
1577 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1578 aml_append(dev, method);
1579
1580 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1581 aml_append(method, aml_return(aml_name("_PRS")));
1582 aml_append(dev, method);
1583
1584 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1585 aml_append(dev, method);
1586 }
1587 aml_append(sb_scope, dev);
1588
1589 aml_append(table, sb_scope);
1590 }
1591
1592 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1593 {
1594 int i;
1595 int head;
1596 Aml *pkg;
1597 char base = name[3] < 'E' ? 'A' : 'E';
1598 char *s = g_strdup(name);
1599 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1600
1601 assert(strlen(s) == 4);
1602
1603 head = name[3] - base;
1604 for (i = 0; i < 4; i++) {
1605 if (head + i > 3) {
1606 head = i * -1;
1607 }
1608 s[3] = base + head + i;
1609 pkg = aml_package(4);
1610 aml_append(pkg, a_nr);
1611 aml_append(pkg, aml_int(i));
1612 aml_append(pkg, aml_name("%s", s));
1613 aml_append(pkg, aml_int(0));
1614 aml_append(ctx, pkg);
1615 }
1616 g_free(s);
1617 }
1618
1619 static Aml *build_q35_routing_table(const char *str)
1620 {
1621 int i;
1622 Aml *pkg;
1623 char *name = g_strdup_printf("%s ", str);
1624
1625 pkg = aml_package(128);
1626 for (i = 0; i < 0x18; i++) {
1627 name[3] = 'E' + (i & 0x3);
1628 append_q35_prt_entry(pkg, i, name);
1629 }
1630
1631 name[3] = 'E';
1632 append_q35_prt_entry(pkg, 0x18, name);
1633
1634 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1635 for (i = 0x0019; i < 0x1e; i++) {
1636 name[3] = 'A';
1637 append_q35_prt_entry(pkg, i, name);
1638 }
1639
1640 /* PCIe->PCI bridge. use PIRQ[E-H] */
1641 name[3] = 'E';
1642 append_q35_prt_entry(pkg, 0x1e, name);
1643 name[3] = 'A';
1644 append_q35_prt_entry(pkg, 0x1f, name);
1645
1646 g_free(name);
1647 return pkg;
1648 }
1649
1650 static void build_q35_pci0_int(Aml *table)
1651 {
1652 Aml *field;
1653 Aml *method;
1654 Aml *sb_scope = aml_scope("_SB");
1655 Aml *pci0_scope = aml_scope("PCI0");
1656
1657 /* Zero => PIC mode, One => APIC Mode */
1658 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1659 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1660 {
1661 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1662 }
1663 aml_append(table, method);
1664
1665 aml_append(pci0_scope,
1666 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1667 aml_append(pci0_scope,
1668 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1669
1670 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1671 {
1672 Aml *if_ctx;
1673 Aml *else_ctx;
1674
1675 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1676 section 6.2.8.1 */
1677 /* Note: we provide the same info as the PCI routing
1678 table of the Bochs BIOS */
1679 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1680 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1681 aml_append(method, if_ctx);
1682 else_ctx = aml_else();
1683 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1684 aml_append(method, else_ctx);
1685 }
1686 aml_append(pci0_scope, method);
1687 aml_append(sb_scope, pci0_scope);
1688
1689 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1690 aml_append(field, aml_named_field("PRQA", 8));
1691 aml_append(field, aml_named_field("PRQB", 8));
1692 aml_append(field, aml_named_field("PRQC", 8));
1693 aml_append(field, aml_named_field("PRQD", 8));
1694 aml_append(field, aml_reserved_field(0x20));
1695 aml_append(field, aml_named_field("PRQE", 8));
1696 aml_append(field, aml_named_field("PRQF", 8));
1697 aml_append(field, aml_named_field("PRQG", 8));
1698 aml_append(field, aml_named_field("PRQH", 8));
1699 aml_append(sb_scope, field);
1700
1701 aml_append(sb_scope, build_irq_status_method());
1702 aml_append(sb_scope, build_iqcr_method(false));
1703
1704 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1705 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1706 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1707 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1708 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1709 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1710 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1711 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1712
1713 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1714 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1715 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1716 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1717 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1718 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1719 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1720 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1721
1722 aml_append(table, sb_scope);
1723 }
1724
1725 static void build_q35_isa_bridge(Aml *table)
1726 {
1727 Aml *dev;
1728 Aml *scope;
1729 Aml *field;
1730
1731 scope = aml_scope("_SB.PCI0");
1732 dev = aml_device("ISA");
1733 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1734
1735 /* ICH9 PCI to ISA irq remapping */
1736 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1737 aml_int(0x60), 0x0C));
1738
1739 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1740 aml_int(0x80), 0x02));
1741 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1742 aml_append(field, aml_named_field("COMA", 3));
1743 aml_append(field, aml_reserved_field(1));
1744 aml_append(field, aml_named_field("COMB", 3));
1745 aml_append(field, aml_reserved_field(1));
1746 aml_append(field, aml_named_field("LPTD", 2));
1747 aml_append(dev, field);
1748
1749 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1750 aml_int(0x82), 0x02));
1751 /* enable bits */
1752 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1753 aml_append(field, aml_named_field("CAEN", 1));
1754 aml_append(field, aml_named_field("CBEN", 1));
1755 aml_append(field, aml_named_field("LPEN", 1));
1756 aml_append(dev, field);
1757
1758 aml_append(scope, dev);
1759 aml_append(table, scope);
1760 }
1761
1762 static void build_piix4_pm(Aml *table)
1763 {
1764 Aml *dev;
1765 Aml *scope;
1766
1767 scope = aml_scope("_SB.PCI0");
1768 dev = aml_device("PX13");
1769 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1770
1771 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1772 aml_int(0x00), 0xff));
1773 aml_append(scope, dev);
1774 aml_append(table, scope);
1775 }
1776
1777 static void build_piix4_isa_bridge(Aml *table)
1778 {
1779 Aml *dev;
1780 Aml *scope;
1781 Aml *field;
1782
1783 scope = aml_scope("_SB.PCI0");
1784 dev = aml_device("ISA");
1785 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1786
1787 /* PIIX PCI to ISA irq remapping */
1788 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1789 aml_int(0x60), 0x04));
1790 /* enable bits */
1791 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1792 /* Offset(0x5f),, 7, */
1793 aml_append(field, aml_reserved_field(0x2f8));
1794 aml_append(field, aml_reserved_field(7));
1795 aml_append(field, aml_named_field("LPEN", 1));
1796 /* Offset(0x67),, 3, */
1797 aml_append(field, aml_reserved_field(0x38));
1798 aml_append(field, aml_reserved_field(3));
1799 aml_append(field, aml_named_field("CAEN", 1));
1800 aml_append(field, aml_reserved_field(3));
1801 aml_append(field, aml_named_field("CBEN", 1));
1802 aml_append(dev, field);
1803
1804 aml_append(scope, dev);
1805 aml_append(table, scope);
1806 }
1807
1808 static void build_piix4_pci_hotplug(Aml *table)
1809 {
1810 Aml *scope;
1811 Aml *field;
1812 Aml *method;
1813
1814 scope = aml_scope("_SB.PCI0");
1815
1816 aml_append(scope,
1817 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1818 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1819 aml_append(field, aml_named_field("PCIU", 32));
1820 aml_append(field, aml_named_field("PCID", 32));
1821 aml_append(scope, field);
1822
1823 aml_append(scope,
1824 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1825 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1826 aml_append(field, aml_named_field("B0EJ", 32));
1827 aml_append(scope, field);
1828
1829 aml_append(scope,
1830 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1831 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1832 aml_append(field, aml_named_field("BNUM", 32));
1833 aml_append(scope, field);
1834
1835 aml_append(scope, aml_mutex("BLCK", 0));
1836
1837 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1838 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1839 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1840 aml_append(method,
1841 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1842 aml_append(method, aml_release(aml_name("BLCK")));
1843 aml_append(method, aml_return(aml_int(0)));
1844 aml_append(scope, method);
1845
1846 aml_append(table, scope);
1847 }
1848
1849 static Aml *build_q35_osc_method(void)
1850 {
1851 Aml *if_ctx;
1852 Aml *if_ctx2;
1853 Aml *else_ctx;
1854 Aml *method;
1855 Aml *a_cwd1 = aml_name("CDW1");
1856 Aml *a_ctrl = aml_name("CTRL");
1857
1858 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1859 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1860
1861 if_ctx = aml_if(aml_equal(
1862 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1863 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1864 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1865
1866 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1867 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1868
1869 /*
1870 * Always allow native PME, AER (no dependencies)
1871 * Never allow SHPC (no SHPC controller in this system)
1872 */
1873 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1874
1875 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1876 /* Unknown revision */
1877 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1878 aml_append(if_ctx, if_ctx2);
1879
1880 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1881 /* Capabilities bits were masked */
1882 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1883 aml_append(if_ctx, if_ctx2);
1884
1885 /* Update DWORD3 in the buffer */
1886 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1887 aml_append(method, if_ctx);
1888
1889 else_ctx = aml_else();
1890 /* Unrecognized UUID */
1891 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1892 aml_append(method, else_ctx);
1893
1894 aml_append(method, aml_return(aml_arg(3)));
1895 return method;
1896 }
1897
1898 static void
1899 build_dsdt(GArray *table_data, BIOSLinker *linker,
1900 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1901 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1902 {
1903 CrsRangeEntry *entry;
1904 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1905 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1906 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1907 PCMachineState *pcms = PC_MACHINE(machine);
1908 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1909 uint32_t nr_mem = machine->ram_slots;
1910 int root_bus_limit = 0xFF;
1911 PCIBus *bus = NULL;
1912 int i;
1913
1914 dsdt = init_aml_allocator();
1915
1916 /* Reserve space for header */
1917 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1918
1919 build_dbg_aml(dsdt);
1920 if (misc->is_piix4) {
1921 sb_scope = aml_scope("_SB");
1922 dev = aml_device("PCI0");
1923 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1924 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1925 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1926 aml_append(sb_scope, dev);
1927 aml_append(dsdt, sb_scope);
1928
1929 build_hpet_aml(dsdt);
1930 build_piix4_pm(dsdt);
1931 build_piix4_isa_bridge(dsdt);
1932 build_isa_devices_aml(dsdt);
1933 build_piix4_pci_hotplug(dsdt);
1934 build_piix4_pci0_int(dsdt);
1935 } else {
1936 sb_scope = aml_scope("_SB");
1937 aml_append(sb_scope,
1938 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
1939 aml_append(sb_scope,
1940 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
1941 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1942 aml_append(field, aml_named_field("PCIB", 8));
1943 aml_append(sb_scope, field);
1944 aml_append(dsdt, sb_scope);
1945
1946 sb_scope = aml_scope("_SB");
1947 dev = aml_device("PCI0");
1948 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1949 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1950 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1951 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1952 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1953 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1954 aml_append(dev, build_q35_osc_method());
1955 aml_append(sb_scope, dev);
1956 aml_append(dsdt, sb_scope);
1957
1958 build_hpet_aml(dsdt);
1959 build_q35_isa_bridge(dsdt);
1960 build_isa_devices_aml(dsdt);
1961 build_q35_pci0_int(dsdt);
1962 }
1963
1964 if (pcmc->legacy_cpu_hotplug) {
1965 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1966 } else {
1967 CPUHotplugFeatures opts = {
1968 .apci_1_compatible = true, .has_legacy_cphp = true
1969 };
1970 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1971 "\\_SB.PCI0", "\\_GPE._E02");
1972 }
1973 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
1974 pm->mem_hp_io_len);
1975
1976 scope = aml_scope("_GPE");
1977 {
1978 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1979
1980 if (misc->is_piix4) {
1981 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1982 aml_append(method,
1983 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1984 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1985 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1986 aml_append(scope, method);
1987 }
1988
1989 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1990 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1991 aml_append(scope, method);
1992 }
1993 aml_append(dsdt, scope);
1994
1995 bus = PC_MACHINE(machine)->bus;
1996 if (bus) {
1997 QLIST_FOREACH(bus, &bus->child, sibling) {
1998 uint8_t bus_num = pci_bus_num(bus);
1999 uint8_t numa_node = pci_bus_numa_node(bus);
2000
2001 /* look only for expander root buses */
2002 if (!pci_bus_is_root(bus)) {
2003 continue;
2004 }
2005
2006 if (bus_num < root_bus_limit) {
2007 root_bus_limit = bus_num - 1;
2008 }
2009
2010 scope = aml_scope("\\_SB");
2011 dev = aml_device("PC%.02X", bus_num);
2012 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2013 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2014 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
2015
2016 if (numa_node != NUMA_NODE_UNASSIGNED) {
2017 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2018 }
2019
2020 aml_append(dev, build_prt(false));
2021 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2022 io_ranges, mem_ranges);
2023 aml_append(dev, aml_name_decl("_CRS", crs));
2024 aml_append(scope, dev);
2025 aml_append(dsdt, scope);
2026 }
2027 }
2028
2029 scope = aml_scope("\\_SB.PCI0");
2030 /* build PCI0._CRS */
2031 crs = aml_resource_template();
2032 aml_append(crs,
2033 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2034 0x0000, 0x0, root_bus_limit,
2035 0x0000, root_bus_limit + 1));
2036 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2037
2038 aml_append(crs,
2039 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2040 AML_POS_DECODE, AML_ENTIRE_RANGE,
2041 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2042
2043 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2044 for (i = 0; i < io_ranges->len; i++) {
2045 entry = g_ptr_array_index(io_ranges, i);
2046 aml_append(crs,
2047 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2048 AML_POS_DECODE, AML_ENTIRE_RANGE,
2049 0x0000, entry->base, entry->limit,
2050 0x0000, entry->limit - entry->base + 1));
2051 }
2052
2053 aml_append(crs,
2054 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2055 AML_CACHEABLE, AML_READ_WRITE,
2056 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2057
2058 crs_replace_with_free_ranges(mem_ranges,
2059 range_lob(pci_hole),
2060 range_upb(pci_hole));
2061 for (i = 0; i < mem_ranges->len; i++) {
2062 entry = g_ptr_array_index(mem_ranges, i);
2063 aml_append(crs,
2064 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2065 AML_NON_CACHEABLE, AML_READ_WRITE,
2066 0, entry->base, entry->limit,
2067 0, entry->limit - entry->base + 1));
2068 }
2069
2070 if (!range_is_empty(pci_hole64)) {
2071 aml_append(crs,
2072 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2073 AML_CACHEABLE, AML_READ_WRITE,
2074 0, range_lob(pci_hole64), range_upb(pci_hole64), 0,
2075 range_upb(pci_hole64) + 1 - range_lob(pci_hole64)));
2076 }
2077
2078 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2079 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2080 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2081 }
2082 aml_append(scope, aml_name_decl("_CRS", crs));
2083
2084 /* reserve GPE0 block resources */
2085 dev = aml_device("GPE0");
2086 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2087 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2088 /* device present, functioning, decoding, not shown in UI */
2089 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2090 crs = aml_resource_template();
2091 aml_append(crs,
2092 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2093 );
2094 aml_append(dev, aml_name_decl("_CRS", crs));
2095 aml_append(scope, dev);
2096
2097 g_ptr_array_free(io_ranges, true);
2098 g_ptr_array_free(mem_ranges, true);
2099
2100 /* reserve PCIHP resources */
2101 if (pm->pcihp_io_len) {
2102 dev = aml_device("PHPR");
2103 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2104 aml_append(dev,
2105 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2106 /* device present, functioning, decoding, not shown in UI */
2107 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2108 crs = aml_resource_template();
2109 aml_append(crs,
2110 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2111 pm->pcihp_io_len)
2112 );
2113 aml_append(dev, aml_name_decl("_CRS", crs));
2114 aml_append(scope, dev);
2115 }
2116 aml_append(dsdt, scope);
2117
2118 /* create S3_ / S4_ / S5_ packages if necessary */
2119 scope = aml_scope("\\");
2120 if (!pm->s3_disabled) {
2121 pkg = aml_package(4);
2122 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2123 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2124 aml_append(pkg, aml_int(0)); /* reserved */
2125 aml_append(pkg, aml_int(0)); /* reserved */
2126 aml_append(scope, aml_name_decl("_S3", pkg));
2127 }
2128
2129 if (!pm->s4_disabled) {
2130 pkg = aml_package(4);
2131 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2132 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2133 aml_append(pkg, aml_int(pm->s4_val));
2134 aml_append(pkg, aml_int(0)); /* reserved */
2135 aml_append(pkg, aml_int(0)); /* reserved */
2136 aml_append(scope, aml_name_decl("_S4", pkg));
2137 }
2138
2139 pkg = aml_package(4);
2140 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2141 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2142 aml_append(pkg, aml_int(0)); /* reserved */
2143 aml_append(pkg, aml_int(0)); /* reserved */
2144 aml_append(scope, aml_name_decl("_S5", pkg));
2145 aml_append(dsdt, scope);
2146
2147 /* create fw_cfg node, unconditionally */
2148 {
2149 /* when using port i/o, the 8-bit data register *always* overlaps
2150 * with half of the 16-bit control register. Hence, the total size
2151 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2152 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2153 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2154 "dma_enabled", NULL) ?
2155 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2156 FW_CFG_CTL_SIZE;
2157
2158 scope = aml_scope("\\_SB.PCI0");
2159 dev = aml_device("FWCF");
2160
2161 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2162
2163 /* device present, functioning, decoding, not shown in UI */
2164 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2165
2166 crs = aml_resource_template();
2167 aml_append(crs,
2168 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2169 );
2170 aml_append(dev, aml_name_decl("_CRS", crs));
2171
2172 aml_append(scope, dev);
2173 aml_append(dsdt, scope);
2174 }
2175
2176 if (misc->applesmc_io_base) {
2177 scope = aml_scope("\\_SB.PCI0.ISA");
2178 dev = aml_device("SMC");
2179
2180 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2181 /* device present, functioning, decoding, not shown in UI */
2182 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2183
2184 crs = aml_resource_template();
2185 aml_append(crs,
2186 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2187 0x01, APPLESMC_MAX_DATA_LENGTH)
2188 );
2189 aml_append(crs, aml_irq_no_flags(6));
2190 aml_append(dev, aml_name_decl("_CRS", crs));
2191
2192 aml_append(scope, dev);
2193 aml_append(dsdt, scope);
2194 }
2195
2196 if (misc->pvpanic_port) {
2197 scope = aml_scope("\\_SB.PCI0.ISA");
2198
2199 dev = aml_device("PEVT");
2200 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2201
2202 crs = aml_resource_template();
2203 aml_append(crs,
2204 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2205 );
2206 aml_append(dev, aml_name_decl("_CRS", crs));
2207
2208 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2209 aml_int(misc->pvpanic_port), 1));
2210 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2211 aml_append(field, aml_named_field("PEPT", 8));
2212 aml_append(dev, field);
2213
2214 /* device present, functioning, decoding, shown in UI */
2215 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2216
2217 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2218 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2219 aml_append(method, aml_return(aml_local(0)));
2220 aml_append(dev, method);
2221
2222 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2223 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2224 aml_append(dev, method);
2225
2226 aml_append(scope, dev);
2227 aml_append(dsdt, scope);
2228 }
2229
2230 sb_scope = aml_scope("\\_SB");
2231 {
2232 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2233 pm->mem_hp_io_len);
2234
2235 {
2236 Object *pci_host;
2237 PCIBus *bus = NULL;
2238
2239 pci_host = acpi_get_i386_pci_host();
2240 if (pci_host) {
2241 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2242 }
2243
2244 if (bus) {
2245 Aml *scope = aml_scope("PCI0");
2246 /* Scan all PCI buses. Generate tables to support hotplug. */
2247 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2248
2249 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2250 dev = aml_device("ISA.TPM");
2251 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2252 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2253 crs = aml_resource_template();
2254 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2255 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2256 /*
2257 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2258 Rewrite to take IRQ from TPM device model and
2259 fix default IRQ value there to use some unused IRQ
2260 */
2261 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2262 aml_append(dev, aml_name_decl("_CRS", crs));
2263 aml_append(scope, dev);
2264 }
2265
2266 aml_append(sb_scope, scope);
2267 }
2268 }
2269 aml_append(dsdt, sb_scope);
2270 }
2271
2272 /* copy AML table into ACPI tables blob and patch header there */
2273 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2274 build_header(linker, table_data,
2275 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2276 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2277 free_aml_allocator();
2278 }
2279
2280 static void
2281 build_hpet(GArray *table_data, BIOSLinker *linker)
2282 {
2283 Acpi20Hpet *hpet;
2284
2285 hpet = acpi_data_push(table_data, sizeof(*hpet));
2286 /* Note timer_block_id value must be kept in sync with value advertised by
2287 * emulated hpet
2288 */
2289 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2290 hpet->addr.address = cpu_to_le64(HPET_BASE);
2291 build_header(linker, table_data,
2292 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2293 }
2294
2295 static void
2296 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2297 {
2298 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2299 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2300 unsigned log_addr_offset =
2301 (char *)&tcpa->log_area_start_address - table_data->data;
2302
2303 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2304 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2305 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2306
2307 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2308 false /* high memory */);
2309
2310 /* log area start address to be filled by Guest linker */
2311 bios_linker_loader_add_pointer(linker,
2312 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2313 ACPI_BUILD_TPMLOG_FILE, 0);
2314
2315 build_header(linker, table_data,
2316 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2317 }
2318
2319 static void
2320 build_tpm2(GArray *table_data, BIOSLinker *linker)
2321 {
2322 Acpi20TPM2 *tpm2_ptr;
2323
2324 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2325
2326 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2327 tpm2_ptr->control_area_address = cpu_to_le64(0);
2328 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2329
2330 build_header(linker, table_data,
2331 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2332 }
2333
2334 static void
2335 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2336 {
2337 AcpiSystemResourceAffinityTable *srat;
2338 AcpiSratProcessorAffinity *core;
2339 AcpiSratMemoryAffinity *numamem;
2340
2341 int i;
2342 int srat_start, numa_start, slots;
2343 uint64_t mem_len, mem_base, next_base;
2344 MachineClass *mc = MACHINE_GET_CLASS(machine);
2345 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2346 PCMachineState *pcms = PC_MACHINE(machine);
2347 ram_addr_t hotplugabble_address_space_size =
2348 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2349 NULL);
2350
2351 srat_start = table_data->len;
2352
2353 srat = acpi_data_push(table_data, sizeof *srat);
2354 srat->reserved1 = cpu_to_le32(1);
2355
2356 for (i = 0; i < apic_ids->len; i++) {
2357 int j;
2358 int apic_id = apic_ids->cpus[i].arch_id;
2359
2360 core = acpi_data_push(table_data, sizeof *core);
2361 core->type = ACPI_SRAT_PROCESSOR_APIC;
2362 core->length = sizeof(*core);
2363 core->local_apic_id = apic_id;
2364 for (j = 0; j < nb_numa_nodes; j++) {
2365 if (test_bit(i, numa_info[j].node_cpu)) {
2366 core->proximity_lo = j;
2367 break;
2368 }
2369 }
2370 memset(core->proximity_hi, 0, 3);
2371 core->local_sapic_eid = 0;
2372 core->flags = cpu_to_le32(1);
2373 }
2374
2375
2376 /* the memory map is a bit tricky, it contains at least one hole
2377 * from 640k-1M and possibly another one from 3.5G-4G.
2378 */
2379 next_base = 0;
2380 numa_start = table_data->len;
2381
2382 numamem = acpi_data_push(table_data, sizeof *numamem);
2383 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2384 next_base = 1024 * 1024;
2385 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2386 mem_base = next_base;
2387 mem_len = pcms->node_mem[i - 1];
2388 if (i == 1) {
2389 mem_len -= 1024 * 1024;
2390 }
2391 next_base = mem_base + mem_len;
2392
2393 /* Cut out the ACPI_PCI hole */
2394 if (mem_base <= pcms->below_4g_mem_size &&
2395 next_base > pcms->below_4g_mem_size) {
2396 mem_len -= next_base - pcms->below_4g_mem_size;
2397 if (mem_len > 0) {
2398 numamem = acpi_data_push(table_data, sizeof *numamem);
2399 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2400 MEM_AFFINITY_ENABLED);
2401 }
2402 mem_base = 1ULL << 32;
2403 mem_len = next_base - pcms->below_4g_mem_size;
2404 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2405 }
2406 numamem = acpi_data_push(table_data, sizeof *numamem);
2407 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2408 MEM_AFFINITY_ENABLED);
2409 }
2410 slots = (table_data->len - numa_start) / sizeof *numamem;
2411 for (; slots < pcms->numa_nodes + 2; slots++) {
2412 numamem = acpi_data_push(table_data, sizeof *numamem);
2413 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2414 }
2415
2416 /*
2417 * Entry is required for Windows to enable memory hotplug in OS.
2418 * Memory devices may override proximity set by this entry,
2419 * providing _PXM method if necessary.
2420 */
2421 if (hotplugabble_address_space_size) {
2422 numamem = acpi_data_push(table_data, sizeof *numamem);
2423 build_srat_memory(numamem, pcms->hotplug_memory.base,
2424 hotplugabble_address_space_size, 0,
2425 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2426 }
2427
2428 build_header(linker, table_data,
2429 (void *)(table_data->data + srat_start),
2430 "SRAT",
2431 table_data->len - srat_start, 1, NULL, NULL);
2432 g_free(apic_ids);
2433 }
2434
2435 static void
2436 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2437 {
2438 AcpiTableMcfg *mcfg;
2439 const char *sig;
2440 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2441
2442 mcfg = acpi_data_push(table_data, len);
2443 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2444 /* Only a single allocation so no need to play with segments */
2445 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2446 mcfg->allocation[0].start_bus_number = 0;
2447 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2448
2449 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2450 * To avoid table size changes (which create migration issues),
2451 * always create the table even if there are no allocations,
2452 * but set the signature to a reserved value in this case.
2453 * ACPI spec requires OSPMs to ignore such tables.
2454 */
2455 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2456 /* Reserved signature: ignored by OSPM */
2457 sig = "QEMU";
2458 } else {
2459 sig = "MCFG";
2460 }
2461 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2462 }
2463
2464 /*
2465 * VT-d spec 8.1 DMA Remapping Reporting Structure
2466 * (version Oct. 2014 or later)
2467 */
2468 static void
2469 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2470 {
2471 int dmar_start = table_data->len;
2472
2473 AcpiTableDmar *dmar;
2474 AcpiDmarHardwareUnit *drhd;
2475 uint8_t dmar_flags = 0;
2476 X86IOMMUState *iommu = x86_iommu_get_default();
2477 AcpiDmarDeviceScope *scope = NULL;
2478 /* Root complex IOAPIC use one path[0] only */
2479 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2480
2481 assert(iommu);
2482 if (iommu->intr_supported) {
2483 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2484 }
2485
2486 dmar = acpi_data_push(table_data, sizeof(*dmar));
2487 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2488 dmar->flags = dmar_flags;
2489
2490 /* DMAR Remapping Hardware Unit Definition structure */
2491 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2492 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2493 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2494 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2495 drhd->pci_segment = cpu_to_le16(0);
2496 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2497
2498 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2499 * 8.3.1 (version Oct. 2014 or later). */
2500 scope = &drhd->scope[0];
2501 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2502 scope->length = ioapic_scope_size;
2503 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2504 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2505 scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC);
2506
2507 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2508 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2509 }
2510
2511 static GArray *
2512 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2513 {
2514 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2515 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2516 unsigned rsdt_pa_offset =
2517 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2518
2519 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2520 true /* fseg memory */);
2521
2522 memcpy(&rsdp->signature, "RSD PTR ", 8);
2523 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2524 /* Address to be filled by Guest linker */
2525 bios_linker_loader_add_pointer(linker,
2526 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2527 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2528
2529 /* Checksum to be filled by Guest linker */
2530 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2531 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2532 (char *)&rsdp->checksum - rsdp_table->data);
2533
2534 return rsdp_table;
2535 }
2536
2537 typedef
2538 struct AcpiBuildState {
2539 /* Copy of table in RAM (for patching). */
2540 MemoryRegion *table_mr;
2541 /* Is table patched? */
2542 uint8_t patched;
2543 void *rsdp;
2544 MemoryRegion *rsdp_mr;
2545 MemoryRegion *linker_mr;
2546 } AcpiBuildState;
2547
2548 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2549 {
2550 Object *pci_host;
2551 QObject *o;
2552
2553 pci_host = acpi_get_i386_pci_host();
2554 g_assert(pci_host);
2555
2556 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2557 if (!o) {
2558 return false;
2559 }
2560 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2561 qobject_decref(o);
2562
2563 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2564 assert(o);
2565 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2566 qobject_decref(o);
2567 return true;
2568 }
2569
2570 static bool acpi_has_iommu(void)
2571 {
2572 return !!x86_iommu_get_default();
2573 }
2574
2575 static
2576 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2577 {
2578 PCMachineState *pcms = PC_MACHINE(machine);
2579 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2580 GArray *table_offsets;
2581 unsigned facs, dsdt, rsdt, fadt;
2582 AcpiPmInfo pm;
2583 AcpiMiscInfo misc;
2584 AcpiMcfgInfo mcfg;
2585 Range pci_hole, pci_hole64;
2586 uint8_t *u;
2587 size_t aml_len = 0;
2588 GArray *tables_blob = tables->table_data;
2589 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2590
2591 acpi_get_pm_info(&pm);
2592 acpi_get_misc_info(&misc);
2593 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2594 acpi_get_slic_oem(&slic_oem);
2595
2596 table_offsets = g_array_new(false, true /* clear */,
2597 sizeof(uint32_t));
2598 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2599
2600 bios_linker_loader_alloc(tables->linker,
2601 ACPI_BUILD_TABLE_FILE, tables_blob,
2602 64 /* Ensure FACS is aligned */,
2603 false /* high memory */);
2604
2605 /*
2606 * FACS is pointed to by FADT.
2607 * We place it first since it's the only table that has alignment
2608 * requirements.
2609 */
2610 facs = tables_blob->len;
2611 build_facs(tables_blob, tables->linker);
2612
2613 /* DSDT is pointed to by FADT */
2614 dsdt = tables_blob->len;
2615 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2616 &pci_hole, &pci_hole64, machine);
2617
2618 /* Count the size of the DSDT and SSDT, we will need it for legacy
2619 * sizing of ACPI tables.
2620 */
2621 aml_len += tables_blob->len - dsdt;
2622
2623 /* ACPI tables pointed to by RSDT */
2624 fadt = tables_blob->len;
2625 acpi_add_table(table_offsets, tables_blob);
2626 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2627 slic_oem.id, slic_oem.table_id);
2628 aml_len += tables_blob->len - fadt;
2629
2630 acpi_add_table(table_offsets, tables_blob);
2631 build_madt(tables_blob, tables->linker, pcms);
2632
2633 if (misc.has_hpet) {
2634 acpi_add_table(table_offsets, tables_blob);
2635 build_hpet(tables_blob, tables->linker);
2636 }
2637 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2638 acpi_add_table(table_offsets, tables_blob);
2639 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2640
2641 if (misc.tpm_version == TPM_VERSION_2_0) {
2642 acpi_add_table(table_offsets, tables_blob);
2643 build_tpm2(tables_blob, tables->linker);
2644 }
2645 }
2646 if (pcms->numa_nodes) {
2647 acpi_add_table(table_offsets, tables_blob);
2648 build_srat(tables_blob, tables->linker, machine);
2649 }
2650 if (acpi_get_mcfg(&mcfg)) {
2651 acpi_add_table(table_offsets, tables_blob);
2652 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2653 }
2654 if (acpi_has_iommu()) {
2655 acpi_add_table(table_offsets, tables_blob);
2656 build_dmar_q35(tables_blob, tables->linker);
2657 }
2658 if (pcms->acpi_nvdimm_state.is_enabled) {
2659 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2660 pcms->acpi_nvdimm_state.dsm_mem);
2661 }
2662
2663 /* Add tables supplied by user (if any) */
2664 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2665 unsigned len = acpi_table_len(u);
2666
2667 acpi_add_table(table_offsets, tables_blob);
2668 g_array_append_vals(tables_blob, u, len);
2669 }
2670
2671 /* RSDT is pointed to by RSDP */
2672 rsdt = tables_blob->len;
2673 build_rsdt(tables_blob, tables->linker, table_offsets,
2674 slic_oem.id, slic_oem.table_id);
2675
2676 /* RSDP is in FSEG memory, so allocate it separately */
2677 build_rsdp(tables->rsdp, tables->linker, rsdt);
2678
2679 /* We'll expose it all to Guest so we want to reduce
2680 * chance of size changes.
2681 *
2682 * We used to align the tables to 4k, but of course this would
2683 * too simple to be enough. 4k turned out to be too small an
2684 * alignment very soon, and in fact it is almost impossible to
2685 * keep the table size stable for all (max_cpus, max_memory_slots)
2686 * combinations. So the table size is always 64k for pc-i440fx-2.1
2687 * and we give an error if the table grows beyond that limit.
2688 *
2689 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2690 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2691 * than 2.0 and we can always pad the smaller tables with zeros. We can
2692 * then use the exact size of the 2.0 tables.
2693 *
2694 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2695 */
2696 if (pcmc->legacy_acpi_table_size) {
2697 /* Subtracting aml_len gives the size of fixed tables. Then add the
2698 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2699 */
2700 int legacy_aml_len =
2701 pcmc->legacy_acpi_table_size +
2702 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2703 int legacy_table_size =
2704 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2705 ACPI_BUILD_ALIGN_SIZE);
2706 if (tables_blob->len > legacy_table_size) {
2707 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2708 error_report("Warning: migration may not work.");
2709 }
2710 g_array_set_size(tables_blob, legacy_table_size);
2711 } else {
2712 /* Make sure we have a buffer in case we need to resize the tables. */
2713 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2714 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2715 error_report("Warning: ACPI tables are larger than 64k.");
2716 error_report("Warning: migration may not work.");
2717 error_report("Warning: please remove CPUs, NUMA nodes, "
2718 "memory slots or PCI bridges.");
2719 }
2720 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2721 }
2722
2723 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2724
2725 /* Cleanup memory that's no longer used. */
2726 g_array_free(table_offsets, true);
2727 }
2728
2729 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2730 {
2731 uint32_t size = acpi_data_len(data);
2732
2733 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2734 memory_region_ram_resize(mr, size, &error_abort);
2735
2736 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2737 memory_region_set_dirty(mr, 0, size);
2738 }
2739
2740 static void acpi_build_update(void *build_opaque)
2741 {
2742 AcpiBuildState *build_state = build_opaque;
2743 AcpiBuildTables tables;
2744
2745 /* No state to update or already patched? Nothing to do. */
2746 if (!build_state || build_state->patched) {
2747 return;
2748 }
2749 build_state->patched = 1;
2750
2751 acpi_build_tables_init(&tables);
2752
2753 acpi_build(&tables, MACHINE(qdev_get_machine()));
2754
2755 acpi_ram_update(build_state->table_mr, tables.table_data);
2756
2757 if (build_state->rsdp) {
2758 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2759 } else {
2760 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2761 }
2762
2763 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2764 acpi_build_tables_cleanup(&tables, true);
2765 }
2766
2767 static void acpi_build_reset(void *build_opaque)
2768 {
2769 AcpiBuildState *build_state = build_opaque;
2770 build_state->patched = 0;
2771 }
2772
2773 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2774 GArray *blob, const char *name,
2775 uint64_t max_size)
2776 {
2777 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2778 name, acpi_build_update, build_state);
2779 }
2780
2781 static const VMStateDescription vmstate_acpi_build = {
2782 .name = "acpi_build",
2783 .version_id = 1,
2784 .minimum_version_id = 1,
2785 .fields = (VMStateField[]) {
2786 VMSTATE_UINT8(patched, AcpiBuildState),
2787 VMSTATE_END_OF_LIST()
2788 },
2789 };
2790
2791 void acpi_setup(void)
2792 {
2793 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2794 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2795 AcpiBuildTables tables;
2796 AcpiBuildState *build_state;
2797
2798 if (!pcms->fw_cfg) {
2799 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2800 return;
2801 }
2802
2803 if (!pcmc->has_acpi_build) {
2804 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2805 return;
2806 }
2807
2808 if (!acpi_enabled) {
2809 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2810 return;
2811 }
2812
2813 build_state = g_malloc0(sizeof *build_state);
2814
2815 acpi_set_pci_info();
2816
2817 acpi_build_tables_init(&tables);
2818 acpi_build(&tables, MACHINE(pcms));
2819
2820 /* Now expose it all to Guest */
2821 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2822 ACPI_BUILD_TABLE_FILE,
2823 ACPI_BUILD_TABLE_MAX_SIZE);
2824 assert(build_state->table_mr != NULL);
2825
2826 build_state->linker_mr =
2827 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2828 "etc/table-loader", 0);
2829
2830 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2831 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2832
2833 if (!pcmc->rsdp_in_ram) {
2834 /*
2835 * Keep for compatibility with old machine types.
2836 * Though RSDP is small, its contents isn't immutable, so
2837 * we'll update it along with the rest of tables on guest access.
2838 */
2839 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2840
2841 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2842 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2843 acpi_build_update, build_state,
2844 build_state->rsdp, rsdp_size);
2845 build_state->rsdp_mr = NULL;
2846 } else {
2847 build_state->rsdp = NULL;
2848 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2849 ACPI_BUILD_RSDP_FILE, 0);
2850 }
2851
2852 qemu_register_reset(acpi_build_reset, build_state);
2853 acpi_build_reset(build_state);
2854 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2855
2856 /* Cleanup tables but don't free the memory: we track it
2857 * in build_state.
2858 */
2859 acpi_build_tables_cleanup(&tables, false);
2860 }
AR7 emulation for QEMU