memory: Introduce DEVICE_HOST_ENDIAN for ram device
[qemu/ar7.git] / include / exec / cpu-common.h
blobb62f0d82e49eca74950bb0c8d441a64dff0da650
1 #ifndef CPU_COMMON_H
2 #define CPU_COMMON_H
4 /* CPU interfaces that are target independent. */
6 #ifndef CONFIG_USER_ONLY
7 #include "exec/hwaddr.h"
8 #endif
10 #include "qemu/bswap.h"
11 #include "qemu/queue.h"
12 #include "qemu/fprintf-fn.h"
14 /**
15 * CPUListState:
16 * @cpu_fprintf: Print function.
17 * @file: File to print to using @cpu_fprint.
19 * State commonly used for iterating over CPU models.
21 typedef struct CPUListState {
22 fprintf_function cpu_fprintf;
23 FILE *file;
24 } CPUListState;
26 /* The CPU list lock nests outside tb_lock/tb_unlock. */
27 void qemu_init_cpu_list(void);
28 void cpu_list_lock(void);
29 void cpu_list_unlock(void);
31 #if !defined(CONFIG_USER_ONLY)
33 enum device_endian {
34 DEVICE_NATIVE_ENDIAN,
35 DEVICE_BIG_ENDIAN,
36 DEVICE_LITTLE_ENDIAN,
39 #if defined(HOST_WORDS_BIGENDIAN)
40 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
41 #else
42 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
43 #endif
45 /* address in the RAM (different from a physical address) */
46 #if defined(CONFIG_XEN_BACKEND)
47 typedef uint64_t ram_addr_t;
48 # define RAM_ADDR_MAX UINT64_MAX
49 # define RAM_ADDR_FMT "%" PRIx64
50 #else
51 typedef uintptr_t ram_addr_t;
52 # define RAM_ADDR_MAX UINTPTR_MAX
53 # define RAM_ADDR_FMT "%" PRIxPTR
54 #endif
56 extern ram_addr_t ram_size;
58 /* memory API */
60 typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
61 typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
63 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
64 /* This should not be used by devices. */
65 ram_addr_t qemu_ram_addr_from_host(void *ptr);
66 RAMBlock *qemu_ram_block_by_name(const char *name);
67 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
68 ram_addr_t *offset);
69 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
70 void qemu_ram_unset_idstr(RAMBlock *block);
71 const char *qemu_ram_get_idstr(RAMBlock *rb);
72 size_t qemu_ram_pagesize(RAMBlock *block);
73 size_t qemu_ram_pagesize_largest(void);
75 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
76 int len, int is_write);
77 static inline void cpu_physical_memory_read(hwaddr addr,
78 void *buf, int len)
80 cpu_physical_memory_rw(addr, buf, len, 0);
82 static inline void cpu_physical_memory_write(hwaddr addr,
83 const void *buf, int len)
85 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
87 void *cpu_physical_memory_map(hwaddr addr,
88 hwaddr *plen,
89 int is_write);
90 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
91 int is_write, hwaddr access_len);
92 void cpu_register_map_client(QEMUBH *bh);
93 void cpu_unregister_map_client(QEMUBH *bh);
95 bool cpu_physical_memory_is_io(hwaddr phys_addr);
97 /* Coalesced MMIO regions are areas where write operations can be reordered.
98 * This usually implies that write operations are side-effect free. This allows
99 * batching which can make a major impact on performance when using
100 * virtualization.
102 void qemu_flush_coalesced_mmio_buffer(void);
104 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
105 const uint8_t *buf, int len);
106 void cpu_flush_icache_range(hwaddr start, int len);
108 extern struct MemoryRegion io_mem_rom;
109 extern struct MemoryRegion io_mem_notdirty;
111 typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
112 ram_addr_t offset, ram_addr_t length, void *opaque);
114 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
115 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
117 #endif
119 #endif /* CPU_COMMON_H */