hw/display/tcx.c

   1 /*
   2  * QEMU TCX Frame buffer
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu-common.h"
  27 #include "qemu/datadir.h"
  28 #include "qapi/error.h"
  29 #include "ui/console.h"
  30 #include "ui/pixel_ops.h"
  31 #include "hw/loader.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/sysbus.h"
  34 #include "migration/vmstate.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/module.h"
  37 #include "qom/object.h"
  38
  39 #define TCX_ROM_FILE "QEMU,tcx.bin"
  40 #define FCODE_MAX_ROM_SIZE 0x10000
  41
  42 #define MAXX 1024
  43 #define MAXY 768
  44 #define TCX_DAC_NREGS    16
  45 #define TCX_THC_NREGS    0x1000
  46 #define TCX_DHC_NREGS    0x4000
  47 #define TCX_TEC_NREGS    0x1000
  48 #define TCX_ALT_NREGS    0x8000
  49 #define TCX_STIP_NREGS   0x800000
  50 #define TCX_BLIT_NREGS   0x800000
  51 #define TCX_RSTIP_NREGS  0x800000
  52 #define TCX_RBLIT_NREGS  0x800000
  53
  54 #define TCX_THC_MISC     0x818
  55 #define TCX_THC_CURSXY   0x8fc
  56 #define TCX_THC_CURSMASK 0x900
  57 #define TCX_THC_CURSBITS 0x980
  58
  59 #define TYPE_TCX "SUNW,tcx"
  60 OBJECT_DECLARE_SIMPLE_TYPE(TCXState, TCX)
  61
  62 struct TCXState {
  63     SysBusDevice parent_obj;
  64
  65     QemuConsole *con;
  66     qemu_irq irq;
  67     uint8_t *vram;
  68     uint32_t *vram24, *cplane;
  69     hwaddr prom_addr;
  70     MemoryRegion rom;
  71     MemoryRegion vram_mem;
  72     MemoryRegion vram_8bit;
  73     MemoryRegion vram_24bit;
  74     MemoryRegion stip;
  75     MemoryRegion blit;
  76     MemoryRegion vram_cplane;
  77     MemoryRegion rstip;
  78     MemoryRegion rblit;
  79     MemoryRegion tec;
  80     MemoryRegion dac;
  81     MemoryRegion thc;
  82     MemoryRegion dhc;
  83     MemoryRegion alt;
  84     MemoryRegion thc24;
  85
  86     ram_addr_t vram24_offset, cplane_offset;
  87     uint32_t tmpblit;
  88     uint32_t vram_size;
  89     uint32_t palette[260];
  90     uint8_t r[260], g[260], b[260];
  91     uint16_t width, height, depth;
  92     uint8_t dac_index, dac_state;
  93     uint32_t thcmisc;
  94     uint32_t cursmask[32];
  95     uint32_t cursbits[32];
  96     uint16_t cursx;
  97     uint16_t cursy;
  98 };
  99
 100 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len)
 101 {
 102     memory_region_set_dirty(&s->vram_mem, addr, len);
 103
 104     if (s->depth == 24) {
 105         memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4,
 106                                 len * 4);
 107         memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4,
 108                                 len * 4);
 109     }
 110 }
 111
 112 static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap,
 113                            ram_addr_t addr, int len)
 114 {
 115     int ret;
 116
 117     ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len);
 118
 119     if (s->depth == 24) {
 120         ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
 121                                        s->vram24_offset + addr * 4, len * 4);
 122         ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
 123                                        s->cplane_offset + addr * 4, len * 4);
 124     }
 125
 126     return ret;
 127 }
 128
 129 static void update_palette_entries(TCXState *s, int start, int end)
 130 {
 131     DisplaySurface *surface = qemu_console_surface(s->con);
 132     int i;
 133
 134     for (i = start; i < end; i++) {
 135         if (is_surface_bgr(surface)) {
 136             s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
 137         } else {
 138             s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
 139         }
 140     }
 141     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 142 }
 143
 144 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
 145                             const uint8_t *s, int width)
 146 {
 147     int x;
 148     uint8_t val;
 149     uint32_t *p = (uint32_t *)d;
 150
 151     for (x = 0; x < width; x++) {
 152         val = *s++;
 153         *p++ = s1->palette[val];
 154     }
 155 }
 156
 157 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d,
 158                               int y, int width)
 159 {
 160     int x, len;
 161     uint32_t mask, bits;
 162     uint32_t *p = (uint32_t *)d;
 163
 164     y = y - s1->cursy;
 165     mask = s1->cursmask[y];
 166     bits = s1->cursbits[y];
 167     len = MIN(width - s1->cursx, 32);
 168     p = &p[s1->cursx];
 169     for (x = 0; x < len; x++) {
 170         if (mask & 0x80000000) {
 171             if (bits & 0x80000000) {
 172                 *p = s1->palette[259];
 173             } else {
 174                 *p = s1->palette[258];
 175             }
 176         }
 177         p++;
 178         mask <<= 1;
 179         bits <<= 1;
 180     }
 181 }
 182
 183 /*
 184   XXX Could be much more optimal:
 185   * detect if line/page/whole screen is in 24 bit mode
 186   * if destination is also BGR, use memcpy
 187   */
 188 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
 189                                      const uint8_t *s, int width,
 190                                      const uint32_t *cplane,
 191                                      const uint32_t *s24)
 192 {
 193     DisplaySurface *surface = qemu_console_surface(s1->con);
 194     int x, bgr, r, g, b;
 195     uint8_t val, *p8;
 196     uint32_t *p = (uint32_t *)d;
 197     uint32_t dval;
 198     bgr = is_surface_bgr(surface);
 199     for(x = 0; x < width; x++, s++, s24++) {
 200         if (be32_to_cpu(*cplane) & 0x03000000) {
 201             /* 24-bit direct, BGR order */
 202             p8 = (uint8_t *)s24;
 203             p8++;
 204             b = *p8++;
 205             g = *p8++;
 206             r = *p8;
 207             if (bgr)
 208                 dval = rgb_to_pixel32bgr(r, g, b);
 209             else
 210                 dval = rgb_to_pixel32(r, g, b);
 211         } else {
 212             /* 8-bit pseudocolor */
 213             val = *s;
 214             dval = s1->palette[val];
 215         }
 216         *p++ = dval;
 217         cplane++;
 218     }
 219 }
 220
 221 /* Fixed line length 1024 allows us to do nice tricks not possible on
 222    VGA... */
 223
 224 static void tcx_update_display(void *opaque)
 225 {
 226     TCXState *ts = opaque;
 227     DisplaySurface *surface = qemu_console_surface(ts->con);
 228     ram_addr_t page;
 229     DirtyBitmapSnapshot *snap = NULL;
 230     int y, y_start, dd, ds;
 231     uint8_t *d, *s;
 232
 233     if (surface_bits_per_pixel(surface) != 32) {
 234         return;
 235     }
 236
 237     page = 0;
 238     y_start = -1;
 239     d = surface_data(surface);
 240     s = ts->vram;
 241     dd = surface_stride(surface);
 242     ds = 1024;
 243
 244     snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
 245                                              memory_region_size(&ts->vram_mem),
 246                                              DIRTY_MEMORY_VGA);
 247
 248     for (y = 0; y < ts->height; y++, page += ds) {
 249         if (tcx_check_dirty(ts, snap, page, ds)) {
 250             if (y_start < 0)
 251                 y_start = y;
 252
 253             tcx_draw_line32(ts, d, s, ts->width);
 254             if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
 255                 tcx_draw_cursor32(ts, d, y, ts->width);
 256             }
 257         } else {
 258             if (y_start >= 0) {
 259                 /* flush to display */
 260                 dpy_gfx_update(ts->con, 0, y_start,
 261                                ts->width, y - y_start);
 262                 y_start = -1;
 263             }
 264         }
 265         s += ds;
 266         d += dd;
 267     }
 268     if (y_start >= 0) {
 269         /* flush to display */
 270         dpy_gfx_update(ts->con, 0, y_start,
 271                        ts->width, y - y_start);
 272     }
 273     g_free(snap);
 274 }
 275
 276 static void tcx24_update_display(void *opaque)
 277 {
 278     TCXState *ts = opaque;
 279     DisplaySurface *surface = qemu_console_surface(ts->con);
 280     ram_addr_t page;
 281     DirtyBitmapSnapshot *snap = NULL;
 282     int y, y_start, dd, ds;
 283     uint8_t *d, *s;
 284     uint32_t *cptr, *s24;
 285
 286     if (surface_bits_per_pixel(surface) != 32) {
 287             return;
 288     }
 289
 290     page = 0;
 291     y_start = -1;
 292     d = surface_data(surface);
 293     s = ts->vram;
 294     s24 = ts->vram24;
 295     cptr = ts->cplane;
 296     dd = surface_stride(surface);
 297     ds = 1024;
 298
 299     snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
 300                                              memory_region_size(&ts->vram_mem),
 301                                              DIRTY_MEMORY_VGA);
 302
 303     for (y = 0; y < ts->height; y++, page += ds) {
 304         if (tcx_check_dirty(ts, snap, page, ds)) {
 305             if (y_start < 0)
 306                 y_start = y;
 307
 308             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 309             if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
 310                 tcx_draw_cursor32(ts, d, y, ts->width);
 311             }
 312         } else {
 313             if (y_start >= 0) {
 314                 /* flush to display */
 315                 dpy_gfx_update(ts->con, 0, y_start,
 316                                ts->width, y - y_start);
 317                 y_start = -1;
 318             }
 319         }
 320         d += dd;
 321         s += ds;
 322         cptr += ds;
 323         s24 += ds;
 324     }
 325     if (y_start >= 0) {
 326         /* flush to display */
 327         dpy_gfx_update(ts->con, 0, y_start,
 328                        ts->width, y - y_start);
 329     }
 330     g_free(snap);
 331 }
 332
 333 static void tcx_invalidate_display(void *opaque)
 334 {
 335     TCXState *s = opaque;
 336
 337     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 338     qemu_console_resize(s->con, s->width, s->height);
 339 }
 340
 341 static void tcx24_invalidate_display(void *opaque)
 342 {
 343     TCXState *s = opaque;
 344
 345     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 346     qemu_console_resize(s->con, s->width, s->height);
 347 }
 348
 349 static int vmstate_tcx_post_load(void *opaque, int version_id)
 350 {
 351     TCXState *s = opaque;
 352
 353     update_palette_entries(s, 0, 256);
 354     tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
 355     return 0;
 356 }
 357
 358 static const VMStateDescription vmstate_tcx = {
 359     .name ="tcx",
 360     .version_id = 4,
 361     .minimum_version_id = 4,
 362     .post_load = vmstate_tcx_post_load,
 363     .fields = (VMStateField[]) {
 364         VMSTATE_UINT16(height, TCXState),
 365         VMSTATE_UINT16(width, TCXState),
 366         VMSTATE_UINT16(depth, TCXState),
 367         VMSTATE_BUFFER(r, TCXState),
 368         VMSTATE_BUFFER(g, TCXState),
 369         VMSTATE_BUFFER(b, TCXState),
 370         VMSTATE_UINT8(dac_index, TCXState),
 371         VMSTATE_UINT8(dac_state, TCXState),
 372         VMSTATE_END_OF_LIST()
 373     }
 374 };
 375
 376 static void tcx_reset(DeviceState *d)
 377 {
 378     TCXState *s = TCX(d);
 379
 380     /* Initialize palette */
 381     memset(s->r, 0, 260);
 382     memset(s->g, 0, 260);
 383     memset(s->b, 0, 260);
 384     s->r[255] = s->g[255] = s->b[255] = 255;
 385     s->r[256] = s->g[256] = s->b[256] = 255;
 386     s->r[258] = s->g[258] = s->b[258] = 255;
 387     update_palette_entries(s, 0, 260);
 388     memset(s->vram, 0, MAXX*MAXY);
 389     memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
 390                               DIRTY_MEMORY_VGA);
 391     s->dac_index = 0;
 392     s->dac_state = 0;
 393     s->cursx = 0xf000; /* Put cursor off screen */
 394     s->cursy = 0xf000;
 395 }
 396
 397 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
 398                               unsigned size)
 399 {
 400     TCXState *s = opaque;
 401     uint32_t val = 0;
 402
 403     switch (s->dac_state) {
 404     case 0:
 405         val = s->r[s->dac_index] << 24;
 406         s->dac_state++;
 407         break;
 408     case 1:
 409         val = s->g[s->dac_index] << 24;
 410         s->dac_state++;
 411         break;
 412     case 2:
 413         val = s->b[s->dac_index] << 24;
 414         s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
 415         /* fall through */
 416     default:
 417         s->dac_state = 0;
 418         break;
 419     }
 420
 421     return val;
 422 }
 423
 424 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
 425                            unsigned size)
 426 {
 427     TCXState *s = opaque;
 428     unsigned index;
 429
 430     switch (addr) {
 431     case 0: /* Address */
 432         s->dac_index = val >> 24;
 433         s->dac_state = 0;
 434         break;
 435     case 4:  /* Pixel colours */
 436     case 12: /* Overlay (cursor) colours */
 437         if (addr & 8) {
 438             index = (s->dac_index & 3) + 256;
 439         } else {
 440             index = s->dac_index;
 441         }
 442         switch (s->dac_state) {
 443         case 0:
 444             s->r[index] = val >> 24;
 445             update_palette_entries(s, index, index + 1);
 446             s->dac_state++;
 447             break;
 448         case 1:
 449             s->g[index] = val >> 24;
 450             update_palette_entries(s, index, index + 1);
 451             s->dac_state++;
 452             break;
 453         case 2:
 454             s->b[index] = val >> 24;
 455             update_palette_entries(s, index, index + 1);
 456             s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
 457             /* fall through */
 458         default:
 459             s->dac_state = 0;
 460             break;
 461         }
 462         break;
 463     default: /* Control registers */
 464         break;
 465     }
 466 }
 467
 468 static const MemoryRegionOps tcx_dac_ops = {
 469     .read = tcx_dac_readl,
 470     .write = tcx_dac_writel,
 471     .endianness = DEVICE_NATIVE_ENDIAN,
 472     .valid = {
 473         .min_access_size = 4,
 474         .max_access_size = 4,
 475     },
 476 };
 477
 478 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr,
 479                                unsigned size)
 480 {
 481     return 0;
 482 }
 483
 484 static void tcx_stip_writel(void *opaque, hwaddr addr,
 485                             uint64_t val, unsigned size)
 486 {
 487     TCXState *s = opaque;
 488     int i;
 489     uint32_t col;
 490
 491     if (!(addr & 4)) {
 492         s->tmpblit = val;
 493     } else {
 494         addr = (addr >> 3) & 0xfffff;
 495         col = cpu_to_be32(s->tmpblit);
 496         if (s->depth == 24) {
 497             for (i = 0; i < 32; i++)  {
 498                 if (val & 0x80000000) {
 499                     s->vram[addr + i] = s->tmpblit;
 500                     s->vram24[addr + i] = col;
 501                 }
 502                 val <<= 1;
 503             }
 504         } else {
 505             for (i = 0; i < 32; i++)  {
 506                 if (val & 0x80000000) {
 507                     s->vram[addr + i] = s->tmpblit;
 508                 }
 509                 val <<= 1;
 510             }
 511         }
 512         tcx_set_dirty(s, addr, 32);
 513     }
 514 }
 515
 516 static void tcx_rstip_writel(void *opaque, hwaddr addr,
 517                              uint64_t val, unsigned size)
 518 {
 519     TCXState *s = opaque;
 520     int i;
 521     uint32_t col;
 522
 523     if (!(addr & 4)) {
 524         s->tmpblit = val;
 525     } else {
 526         addr = (addr >> 3) & 0xfffff;
 527         col = cpu_to_be32(s->tmpblit);
 528         if (s->depth == 24) {
 529             for (i = 0; i < 32; i++) {
 530                 if (val & 0x80000000) {
 531                     s->vram[addr + i] = s->tmpblit;
 532                     s->vram24[addr + i] = col;
 533                     s->cplane[addr + i] = col;
 534                 }
 535                 val <<= 1;
 536             }
 537         } else {
 538             for (i = 0; i < 32; i++)  {
 539                 if (val & 0x80000000) {
 540                     s->vram[addr + i] = s->tmpblit;
 541                 }
 542                 val <<= 1;
 543             }
 544         }
 545         tcx_set_dirty(s, addr, 32);
 546     }
 547 }
 548
 549 static const MemoryRegionOps tcx_stip_ops = {
 550     .read = tcx_stip_readl,
 551     .write = tcx_stip_writel,
 552     .endianness = DEVICE_NATIVE_ENDIAN,
 553     .impl = {
 554         .min_access_size = 4,
 555         .max_access_size = 4,
 556     },
 557     .valid = {
 558         .min_access_size = 4,
 559         .max_access_size = 8,
 560     },
 561 };
 562
 563 static const MemoryRegionOps tcx_rstip_ops = {
 564     .read = tcx_stip_readl,
 565     .write = tcx_rstip_writel,
 566     .endianness = DEVICE_NATIVE_ENDIAN,
 567     .impl = {
 568         .min_access_size = 4,
 569         .max_access_size = 4,
 570     },
 571     .valid = {
 572         .min_access_size = 4,
 573         .max_access_size = 8,
 574     },
 575 };
 576
 577 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
 578                                unsigned size)
 579 {
 580     return 0;
 581 }
 582
 583 static void tcx_blit_writel(void *opaque, hwaddr addr,
 584                             uint64_t val, unsigned size)
 585 {
 586     TCXState *s = opaque;
 587     uint32_t adsr, len;
 588     int i;
 589
 590     if (!(addr & 4)) {
 591         s->tmpblit = val;
 592     } else {
 593         addr = (addr >> 3) & 0xfffff;
 594         adsr = val & 0xffffff;
 595         len = ((val >> 24) & 0x1f) + 1;
 596         if (adsr == 0xffffff) {
 597             memset(&s->vram[addr], s->tmpblit, len);
 598             if (s->depth == 24) {
 599                 val = s->tmpblit & 0xffffff;
 600                 val = cpu_to_be32(val);
 601                 for (i = 0; i < len; i++) {
 602                     s->vram24[addr + i] = val;
 603                 }
 604             }
 605         } else {
 606             memcpy(&s->vram[addr], &s->vram[adsr], len);
 607             if (s->depth == 24) {
 608                 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
 609             }
 610         }
 611         tcx_set_dirty(s, addr, len);
 612     }
 613 }
 614
 615 static void tcx_rblit_writel(void *opaque, hwaddr addr,
 616                          uint64_t val, unsigned size)
 617 {
 618     TCXState *s = opaque;
 619     uint32_t adsr, len;
 620     int i;
 621
 622     if (!(addr & 4)) {
 623         s->tmpblit = val;
 624     } else {
 625         addr = (addr >> 3) & 0xfffff;
 626         adsr = val & 0xffffff;
 627         len = ((val >> 24) & 0x1f) + 1;
 628         if (adsr == 0xffffff) {
 629             memset(&s->vram[addr], s->tmpblit, len);
 630             if (s->depth == 24) {
 631                 val = s->tmpblit & 0xffffff;
 632                 val = cpu_to_be32(val);
 633                 for (i = 0; i < len; i++) {
 634                     s->vram24[addr + i] = val;
 635                     s->cplane[addr + i] = val;
 636                 }
 637             }
 638         } else {
 639             memcpy(&s->vram[addr], &s->vram[adsr], len);
 640             if (s->depth == 24) {
 641                 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
 642                 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4);
 643             }
 644         }
 645         tcx_set_dirty(s, addr, len);
 646     }
 647 }
 648
 649 static const MemoryRegionOps tcx_blit_ops = {
 650     .read = tcx_blit_readl,
 651     .write = tcx_blit_writel,
 652     .endianness = DEVICE_NATIVE_ENDIAN,
 653     .impl = {
 654         .min_access_size = 4,
 655         .max_access_size = 4,
 656     },
 657     .valid = {
 658         .min_access_size = 4,
 659         .max_access_size = 8,
 660     },
 661 };
 662
 663 static const MemoryRegionOps tcx_rblit_ops = {
 664     .read = tcx_blit_readl,
 665     .write = tcx_rblit_writel,
 666     .endianness = DEVICE_NATIVE_ENDIAN,
 667     .impl = {
 668         .min_access_size = 4,
 669         .max_access_size = 4,
 670     },
 671     .valid = {
 672         .min_access_size = 4,
 673         .max_access_size = 8,
 674     },
 675 };
 676
 677 static void tcx_invalidate_cursor_position(TCXState *s)
 678 {
 679     int ymin, ymax, start, end;
 680
 681     /* invalidate only near the cursor */
 682     ymin = s->cursy;
 683     if (ymin >= s->height) {
 684         return;
 685     }
 686     ymax = MIN(s->height, ymin + 32);
 687     start = ymin * 1024;
 688     end   = ymax * 1024;
 689
 690     tcx_set_dirty(s, start, end - start);
 691 }
 692
 693 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr,
 694                             unsigned size)
 695 {
 696     TCXState *s = opaque;
 697     uint64_t val;
 698
 699     if (addr == TCX_THC_MISC) {
 700         val = s->thcmisc | 0x02000000;
 701     } else {
 702         val = 0;
 703     }
 704     return val;
 705 }
 706
 707 static void tcx_thc_writel(void *opaque, hwaddr addr,
 708                          uint64_t val, unsigned size)
 709 {
 710     TCXState *s = opaque;
 711
 712     if (addr == TCX_THC_CURSXY) {
 713         tcx_invalidate_cursor_position(s);
 714         s->cursx = val >> 16;
 715         s->cursy = val;
 716         tcx_invalidate_cursor_position(s);
 717     } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) {
 718         s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val;
 719         tcx_invalidate_cursor_position(s);
 720     } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) {
 721         s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val;
 722         tcx_invalidate_cursor_position(s);
 723     } else if (addr == TCX_THC_MISC) {
 724         s->thcmisc = val;
 725     }
 726
 727 }
 728
 729 static const MemoryRegionOps tcx_thc_ops = {
 730     .read = tcx_thc_readl,
 731     .write = tcx_thc_writel,
 732     .endianness = DEVICE_NATIVE_ENDIAN,
 733     .valid = {
 734         .min_access_size = 4,
 735         .max_access_size = 4,
 736     },
 737 };
 738
 739 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr,
 740                             unsigned size)
 741 {
 742     return 0;
 743 }
 744
 745 static void tcx_dummy_writel(void *opaque, hwaddr addr,
 746                          uint64_t val, unsigned size)
 747 {
 748     return;
 749 }
 750
 751 static const MemoryRegionOps tcx_dummy_ops = {
 752     .read = tcx_dummy_readl,
 753     .write = tcx_dummy_writel,
 754     .endianness = DEVICE_NATIVE_ENDIAN,
 755     .valid = {
 756         .min_access_size = 4,
 757         .max_access_size = 4,
 758     },
 759 };
 760
 761 static const GraphicHwOps tcx_ops = {
 762     .invalidate = tcx_invalidate_display,
 763     .gfx_update = tcx_update_display,
 764 };
 765
 766 static const GraphicHwOps tcx24_ops = {
 767     .invalidate = tcx24_invalidate_display,
 768     .gfx_update = tcx24_update_display,
 769 };
 770
 771 static void tcx_initfn(Object *obj)
 772 {
 773     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 774     TCXState *s = TCX(obj);
 775
 776     memory_region_init_rom_nomigrate(&s->rom, obj, "tcx.prom",
 777                                      FCODE_MAX_ROM_SIZE, &error_fatal);
 778     sysbus_init_mmio(sbd, &s->rom);
 779
 780     /* 2/STIP : Stippler */
 781     memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip",
 782                           TCX_STIP_NREGS);
 783     sysbus_init_mmio(sbd, &s->stip);
 784
 785     /* 3/BLIT : Blitter */
 786     memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit",
 787                           TCX_BLIT_NREGS);
 788     sysbus_init_mmio(sbd, &s->blit);
 789
 790     /* 5/RSTIP : Raw Stippler */
 791     memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip",
 792                           TCX_RSTIP_NREGS);
 793     sysbus_init_mmio(sbd, &s->rstip);
 794
 795     /* 6/RBLIT : Raw Blitter */
 796     memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit",
 797                           TCX_RBLIT_NREGS);
 798     sysbus_init_mmio(sbd, &s->rblit);
 799
 800     /* 7/TEC : ??? */
 801     memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec",
 802                           TCX_TEC_NREGS);
 803     sysbus_init_mmio(sbd, &s->tec);
 804
 805     /* 8/CMAP : DAC */
 806     memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac",
 807                           TCX_DAC_NREGS);
 808     sysbus_init_mmio(sbd, &s->dac);
 809
 810     /* 9/THC : Cursor */
 811     memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc",
 812                           TCX_THC_NREGS);
 813     sysbus_init_mmio(sbd, &s->thc);
 814
 815     /* 11/DHC : ??? */
 816     memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc",
 817                           TCX_DHC_NREGS);
 818     sysbus_init_mmio(sbd, &s->dhc);
 819
 820     /* 12/ALT : ??? */
 821     memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt",
 822                           TCX_ALT_NREGS);
 823     sysbus_init_mmio(sbd, &s->alt);
 824 }
 825
 826 static void tcx_realizefn(DeviceState *dev, Error **errp)
 827 {
 828     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 829     TCXState *s = TCX(dev);
 830     ram_addr_t vram_offset = 0;
 831     int size, ret;
 832     uint8_t *vram_base;
 833     char *fcode_filename;
 834
 835     memory_region_init_ram_nomigrate(&s->vram_mem, OBJECT(s), "tcx.vram",
 836                            s->vram_size * (1 + 4 + 4), &error_fatal);
 837     vmstate_register_ram_global(&s->vram_mem);
 838     memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
 839     vram_base = memory_region_get_ram_ptr(&s->vram_mem);
 840
 841     /* 10/ROM : FCode ROM */
 842     vmstate_register_ram_global(&s->rom);
 843     fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
 844     if (fcode_filename) {
 845         ret = load_image_mr(fcode_filename, &s->rom);
 846         g_free(fcode_filename);
 847         if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
 848             warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE);
 849         }
 850     }
 851
 852     /* 0/DFB8 : 8-bit plane */
 853     s->vram = vram_base;
 854     size = s->vram_size;
 855     memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
 856                              &s->vram_mem, vram_offset, size);
 857     sysbus_init_mmio(sbd, &s->vram_8bit);
 858     vram_offset += size;
 859     vram_base += size;
 860
 861     /* 1/DFB24 : 24bit plane */
 862     size = s->vram_size * 4;
 863     s->vram24 = (uint32_t *)vram_base;
 864     s->vram24_offset = vram_offset;
 865     memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
 866                              &s->vram_mem, vram_offset, size);
 867     sysbus_init_mmio(sbd, &s->vram_24bit);
 868     vram_offset += size;
 869     vram_base += size;
 870
 871     /* 4/RDFB32 : Raw Framebuffer */
 872     size = s->vram_size * 4;
 873     s->cplane = (uint32_t *)vram_base;
 874     s->cplane_offset = vram_offset;
 875     memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
 876                              &s->vram_mem, vram_offset, size);
 877     sysbus_init_mmio(sbd, &s->vram_cplane);
 878
 879     /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
 880     if (s->depth == 8) {
 881         memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s,
 882                               "tcx.thc24", TCX_THC_NREGS);
 883         sysbus_init_mmio(sbd, &s->thc24);
 884     }
 885
 886     sysbus_init_irq(sbd, &s->irq);
 887
 888     if (s->depth == 8) {
 889         s->con = graphic_console_init(dev, 0, &tcx_ops, s);
 890     } else {
 891         s->con = graphic_console_init(dev, 0, &tcx24_ops, s);
 892     }
 893     s->thcmisc = 0;
 894
 895     qemu_console_resize(s->con, s->width, s->height);
 896 }
 897
 898 static Property tcx_properties[] = {
 899     DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1),
 900     DEFINE_PROP_UINT16("width",    TCXState, width,     -1),
 901     DEFINE_PROP_UINT16("height",   TCXState, height,    -1),
 902     DEFINE_PROP_UINT16("depth",    TCXState, depth,     -1),
 903     DEFINE_PROP_END_OF_LIST(),
 904 };
 905
 906 static void tcx_class_init(ObjectClass *klass, void *data)
 907 {
 908     DeviceClass *dc = DEVICE_CLASS(klass);
 909
 910     dc->realize = tcx_realizefn;
 911     dc->reset = tcx_reset;
 912     dc->vmsd = &vmstate_tcx;
 913     device_class_set_props(dc, tcx_properties);
 914 }
 915
 916 static const TypeInfo tcx_info = {
 917     .name          = TYPE_TCX,
 918     .parent        = TYPE_SYS_BUS_DEVICE,
 919     .instance_size = sizeof(TCXState),
 920     .instance_init = tcx_initfn,
 921     .class_init    = tcx_class_init,
 922 };
 923
 924 static void tcx_register_types(void)
 925 {
 926     type_register_static(&tcx_info);
 927 }
 928
 929 type_init(tcx_register_types)