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target/cris: Add DISAS_UPDATE_NEXT
[qemu/ar7.git] / target / cris / translate.c
bloba2124ffcd5a85fc6c97a1bb69e097448369fa476
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "qemu/osdep.h"
27 #include "cpu.h"
28 #include "disas/disas.h"
29 #include "exec/exec-all.h"
30 #include "tcg/tcg-op.h"
31 #include "exec/helper-proto.h"
32 #include "mmu.h"
33 #include "exec/cpu_ldst.h"
34 #include "exec/translator.h"
35 #include "crisv32-decode.h"
36 #include "qemu/qemu-print.h"
37
38 #include "exec/helper-gen.h"
39
40 #include "trace-tcg.h"
41 #include "exec/log.h"
42
43
44 #define DISAS_CRIS 0
45 #if DISAS_CRIS
46 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DIS(...) do { } while (0)
49 #endif
50
51 #define D(x)
52 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
53 #define BUG_ON(x) ({if (x) BUG();})
54
55 /*
56 * Target-specific is_jmp field values
57 */
58 /* Only pc was modified dynamically */
59 #define DISAS_JUMP DISAS_TARGET_0
60 /* Cpu state was modified dynamically, including pc */
61 #define DISAS_UPDATE DISAS_TARGET_1
62 /* Cpu state was modified dynamically, excluding pc -- use npc */
63 #define DISAS_UPDATE_NEXT DISAS_TARGET_2
64
65 /* Used by the decoder. */
66 #define EXTRACT_FIELD(src, start, end) \
67 (((src) >> start) & ((1 << (end - start + 1)) - 1))
68
69 #define CC_MASK_NZ 0xc
70 #define CC_MASK_NZV 0xe
71 #define CC_MASK_NZVC 0xf
72 #define CC_MASK_RNZV 0x10e
73
74 static TCGv cpu_R[16];
75 static TCGv cpu_PR[16];
76 static TCGv cc_x;
77 static TCGv cc_src;
78 static TCGv cc_dest;
79 static TCGv cc_result;
80 static TCGv cc_op;
81 static TCGv cc_size;
82 static TCGv cc_mask;
83
84 static TCGv env_btaken;
85 static TCGv env_btarget;
86 static TCGv env_pc;
87
88 #include "exec/gen-icount.h"
89
90 /* This is the state at translation time. */
91 typedef struct DisasContext {
92 DisasContextBase base;
93
94 CRISCPU *cpu;
95 target_ulong pc, ppc;
96
97 /* Decoder. */
98 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
99 uint32_t ir;
100 uint32_t opcode;
101 unsigned int op1;
102 unsigned int op2;
103 unsigned int zsize, zzsize;
104 unsigned int mode;
105 unsigned int postinc;
106
107 unsigned int size;
108 unsigned int src;
109 unsigned int dst;
110 unsigned int cond;
111
112 int update_cc;
113 int cc_op;
114 int cc_size;
115 uint32_t cc_mask;
116
117 int cc_size_uptodate; /* -1 invalid or last written value. */
118
119 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
120 int flags_uptodate; /* Whether or not $ccs is up-to-date. */
121 int flagx_known; /* Whether or not flags_x has the x flag known at
122 translation time. */
123 int flags_x;
124
125 int clear_x; /* Clear x after this insn? */
126 int clear_prefix; /* Clear prefix after this insn? */
127 int clear_locked_irq; /* Clear the irq lockout. */
128 int cpustate_changed;
129 unsigned int tb_flags; /* tb dependent flags. */
130
131 #define JMP_NOJMP 0
132 #define JMP_DIRECT 1
133 #define JMP_DIRECT_CC 2
134 #define JMP_INDIRECT 3
135 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
136 uint32_t jmp_pc;
137
138 int delayed_branch;
139 } DisasContext;
140
141 static void gen_BUG(DisasContext *dc, const char *file, int line)
142 {
143 cpu_abort(CPU(dc->cpu), "%s:%d pc=%x\n", file, line, dc->pc);
144 }
145
146 static const char * const regnames_v32[] =
147 {
148 "$r0", "$r1", "$r2", "$r3",
149 "$r4", "$r5", "$r6", "$r7",
150 "$r8", "$r9", "$r10", "$r11",
151 "$r12", "$r13", "$sp", "$acr",
152 };
153
154 static const char * const pregnames_v32[] =
155 {
156 "$bz", "$vr", "$pid", "$srs",
157 "$wz", "$exs", "$eda", "$mof",
158 "$dz", "$ebp", "$erp", "$srp",
159 "$nrp", "$ccs", "$usp", "$spc",
160 };
161
162 /* We need this table to handle preg-moves with implicit width. */
163 static const int preg_sizes[] = {
164 1, /* bz. */
165 1, /* vr. */
166 4, /* pid. */
167 1, /* srs. */
168 2, /* wz. */
169 4, 4, 4,
170 4, 4, 4, 4,
171 4, 4, 4, 4,
172 };
173
174 #define t_gen_mov_TN_env(tn, member) \
175 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
176 #define t_gen_mov_env_TN(member, tn) \
177 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
178 #define t_gen_movi_env_TN(member, c) \
179 do { \
180 TCGv tc = tcg_const_tl(c); \
181 t_gen_mov_env_TN(member, tc); \
182 tcg_temp_free(tc); \
183 } while (0)
184
185 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
186 {
187 assert(r >= 0 && r <= 15);
188 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
189 tcg_gen_movi_tl(tn, 0);
190 } else if (r == PR_VR) {
191 tcg_gen_movi_tl(tn, 32);
192 } else {
193 tcg_gen_mov_tl(tn, cpu_PR[r]);
194 }
195 }
196 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
197 {
198 assert(r >= 0 && r <= 15);
199 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
200 return;
201 } else if (r == PR_SRS) {
202 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
203 } else {
204 if (r == PR_PID) {
205 gen_helper_tlb_flush_pid(cpu_env, tn);
206 }
207 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
208 gen_helper_spc_write(cpu_env, tn);
209 } else if (r == PR_CCS) {
210 dc->cpustate_changed = 1;
211 }
212 tcg_gen_mov_tl(cpu_PR[r], tn);
213 }
214 }
215
216 /* Sign extend at translation time. */
217 static int sign_extend(unsigned int val, unsigned int width)
218 {
219 int sval;
220
221 /* LSL. */
222 val <<= 31 - width;
223 sval = val;
224 /* ASR. */
225 sval >>= 31 - width;
226 return sval;
227 }
228
229 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
230 unsigned int size, unsigned int sign)
231 {
232 int r;
233
234 switch (size) {
235 case 4:
236 {
237 r = cpu_ldl_code(env, addr);
238 break;
239 }
240 case 2:
241 {
242 if (sign) {
243 r = cpu_ldsw_code(env, addr);
244 } else {
245 r = cpu_lduw_code(env, addr);
246 }
247 break;
248 }
249 case 1:
250 {
251 if (sign) {
252 r = cpu_ldsb_code(env, addr);
253 } else {
254 r = cpu_ldub_code(env, addr);
255 }
256 break;
257 }
258 default:
259 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
260 break;
261 }
262 return r;
263 }
264
265 static void cris_lock_irq(DisasContext *dc)
266 {
267 dc->clear_locked_irq = 0;
268 t_gen_movi_env_TN(locked_irq, 1);
269 }
270
271 static inline void t_gen_raise_exception(uint32_t index)
272 {
273 TCGv_i32 tmp = tcg_const_i32(index);
274 gen_helper_raise_exception(cpu_env, tmp);
275 tcg_temp_free_i32(tmp);
276 }
277
278 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
279 {
280 TCGv t0, t_31;
281
282 t0 = tcg_temp_new();
283 t_31 = tcg_const_tl(31);
284 tcg_gen_shl_tl(d, a, b);
285
286 tcg_gen_sub_tl(t0, t_31, b);
287 tcg_gen_sar_tl(t0, t0, t_31);
288 tcg_gen_and_tl(t0, t0, d);
289 tcg_gen_xor_tl(d, d, t0);
290 tcg_temp_free(t0);
291 tcg_temp_free(t_31);
292 }
293
294 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
295 {
296 TCGv t0, t_31;
297
298 t0 = tcg_temp_new();
299 t_31 = tcg_temp_new();
300 tcg_gen_shr_tl(d, a, b);
301
302 tcg_gen_movi_tl(t_31, 31);
303 tcg_gen_sub_tl(t0, t_31, b);
304 tcg_gen_sar_tl(t0, t0, t_31);
305 tcg_gen_and_tl(t0, t0, d);
306 tcg_gen_xor_tl(d, d, t0);
307 tcg_temp_free(t0);
308 tcg_temp_free(t_31);
309 }
310
311 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
312 {
313 TCGv t0, t_31;
314
315 t0 = tcg_temp_new();
316 t_31 = tcg_temp_new();
317 tcg_gen_sar_tl(d, a, b);
318
319 tcg_gen_movi_tl(t_31, 31);
320 tcg_gen_sub_tl(t0, t_31, b);
321 tcg_gen_sar_tl(t0, t0, t_31);
322 tcg_gen_or_tl(d, d, t0);
323 tcg_temp_free(t0);
324 tcg_temp_free(t_31);
325 }
326
327 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
328 {
329 TCGv t = tcg_temp_new();
330
331 /*
332 * d <<= 1
333 * if (d >= s)
334 * d -= s;
335 */
336 tcg_gen_shli_tl(d, a, 1);
337 tcg_gen_sub_tl(t, d, b);
338 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d);
339 tcg_temp_free(t);
340 }
341
342 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
343 {
344 TCGv t;
345
346 /*
347 * d <<= 1
348 * if (n)
349 * d += s;
350 */
351 t = tcg_temp_new();
352 tcg_gen_shli_tl(d, a, 1);
353 tcg_gen_shli_tl(t, ccs, 31 - 3);
354 tcg_gen_sari_tl(t, t, 31);
355 tcg_gen_and_tl(t, t, b);
356 tcg_gen_add_tl(d, d, t);
357 tcg_temp_free(t);
358 }
359
360 /* Extended arithmetics on CRIS. */
361 static inline void t_gen_add_flag(TCGv d, int flag)
362 {
363 TCGv c;
364
365 c = tcg_temp_new();
366 t_gen_mov_TN_preg(c, PR_CCS);
367 /* Propagate carry into d. */
368 tcg_gen_andi_tl(c, c, 1 << flag);
369 if (flag) {
370 tcg_gen_shri_tl(c, c, flag);
371 }
372 tcg_gen_add_tl(d, d, c);
373 tcg_temp_free(c);
374 }
375
376 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
377 {
378 if (dc->flagx_known) {
379 if (dc->flags_x) {
380 TCGv c;
381
382 c = tcg_temp_new();
383 t_gen_mov_TN_preg(c, PR_CCS);
384 /* C flag is already at bit 0. */
385 tcg_gen_andi_tl(c, c, C_FLAG);
386 tcg_gen_add_tl(d, d, c);
387 tcg_temp_free(c);
388 }
389 } else {
390 TCGv x, c;
391
392 x = tcg_temp_new();
393 c = tcg_temp_new();
394 t_gen_mov_TN_preg(x, PR_CCS);
395 tcg_gen_mov_tl(c, x);
396
397 /* Propagate carry into d if X is set. Branch free. */
398 tcg_gen_andi_tl(c, c, C_FLAG);
399 tcg_gen_andi_tl(x, x, X_FLAG);
400 tcg_gen_shri_tl(x, x, 4);
401
402 tcg_gen_and_tl(x, x, c);
403 tcg_gen_add_tl(d, d, x);
404 tcg_temp_free(x);
405 tcg_temp_free(c);
406 }
407 }
408
409 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
410 {
411 if (dc->flagx_known) {
412 if (dc->flags_x) {
413 TCGv c;
414
415 c = tcg_temp_new();
416 t_gen_mov_TN_preg(c, PR_CCS);
417 /* C flag is already at bit 0. */
418 tcg_gen_andi_tl(c, c, C_FLAG);
419 tcg_gen_sub_tl(d, d, c);
420 tcg_temp_free(c);
421 }
422 } else {
423 TCGv x, c;
424
425 x = tcg_temp_new();
426 c = tcg_temp_new();
427 t_gen_mov_TN_preg(x, PR_CCS);
428 tcg_gen_mov_tl(c, x);
429
430 /* Propagate carry into d if X is set. Branch free. */
431 tcg_gen_andi_tl(c, c, C_FLAG);
432 tcg_gen_andi_tl(x, x, X_FLAG);
433 tcg_gen_shri_tl(x, x, 4);
434
435 tcg_gen_and_tl(x, x, c);
436 tcg_gen_sub_tl(d, d, x);
437 tcg_temp_free(x);
438 tcg_temp_free(c);
439 }
440 }
441
442 /* Swap the two bytes within each half word of the s operand.
443 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
444 static inline void t_gen_swapb(TCGv d, TCGv s)
445 {
446 TCGv t, org_s;
447
448 t = tcg_temp_new();
449 org_s = tcg_temp_new();
450
451 /* d and s may refer to the same object. */
452 tcg_gen_mov_tl(org_s, s);
453 tcg_gen_shli_tl(t, org_s, 8);
454 tcg_gen_andi_tl(d, t, 0xff00ff00);
455 tcg_gen_shri_tl(t, org_s, 8);
456 tcg_gen_andi_tl(t, t, 0x00ff00ff);
457 tcg_gen_or_tl(d, d, t);
458 tcg_temp_free(t);
459 tcg_temp_free(org_s);
460 }
461
462 /* Swap the halfwords of the s operand. */
463 static inline void t_gen_swapw(TCGv d, TCGv s)
464 {
465 TCGv t;
466 /* d and s refer the same object. */
467 t = tcg_temp_new();
468 tcg_gen_mov_tl(t, s);
469 tcg_gen_shli_tl(d, t, 16);
470 tcg_gen_shri_tl(t, t, 16);
471 tcg_gen_or_tl(d, d, t);
472 tcg_temp_free(t);
473 }
474
475 /* Reverse the within each byte.
476 T0 = (((T0 << 7) & 0x80808080) |
477 ((T0 << 5) & 0x40404040) |
478 ((T0 << 3) & 0x20202020) |
479 ((T0 << 1) & 0x10101010) |
480 ((T0 >> 1) & 0x08080808) |
481 ((T0 >> 3) & 0x04040404) |
482 ((T0 >> 5) & 0x02020202) |
483 ((T0 >> 7) & 0x01010101));
484 */
485 static void t_gen_swapr(TCGv d, TCGv s)
486 {
487 static const struct {
488 int shift; /* LSL when positive, LSR when negative. */
489 uint32_t mask;
490 } bitrev[] = {
491 {7, 0x80808080},
492 {5, 0x40404040},
493 {3, 0x20202020},
494 {1, 0x10101010},
495 {-1, 0x08080808},
496 {-3, 0x04040404},
497 {-5, 0x02020202},
498 {-7, 0x01010101}
499 };
500 int i;
501 TCGv t, org_s;
502
503 /* d and s refer the same object. */
504 t = tcg_temp_new();
505 org_s = tcg_temp_new();
506 tcg_gen_mov_tl(org_s, s);
507
508 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
509 tcg_gen_andi_tl(d, t, bitrev[0].mask);
510 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
511 if (bitrev[i].shift >= 0) {
512 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
513 } else {
514 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
515 }
516 tcg_gen_andi_tl(t, t, bitrev[i].mask);
517 tcg_gen_or_tl(d, d, t);
518 }
519 tcg_temp_free(t);
520 tcg_temp_free(org_s);
521 }
522
523 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
524 {
525 TCGLabel *l1 = gen_new_label();
526
527 /* Conditional jmp. */
528 tcg_gen_mov_tl(env_pc, pc_false);
529 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
530 tcg_gen_mov_tl(env_pc, pc_true);
531 gen_set_label(l1);
532 }
533
534 static bool use_goto_tb(DisasContext *dc, target_ulong dest)
535 {
536 return ((dest ^ dc->base.pc_first) & TARGET_PAGE_MASK) == 0;
537 }
538
539 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
540 {
541 if (use_goto_tb(dc, dest)) {
542 tcg_gen_goto_tb(n);
543 tcg_gen_movi_tl(env_pc, dest);
544 tcg_gen_exit_tb(dc->base.tb, n);
545 } else {
546 tcg_gen_movi_tl(env_pc, dest);
547 tcg_gen_exit_tb(NULL, 0);
548 }
549 }
550
551 static inline void cris_clear_x_flag(DisasContext *dc)
552 {
553 if (dc->flagx_known && dc->flags_x) {
554 dc->flags_uptodate = 0;
555 }
556
557 dc->flagx_known = 1;
558 dc->flags_x = 0;
559 }
560
561 static void cris_flush_cc_state(DisasContext *dc)
562 {
563 if (dc->cc_size_uptodate != dc->cc_size) {
564 tcg_gen_movi_tl(cc_size, dc->cc_size);
565 dc->cc_size_uptodate = dc->cc_size;
566 }
567 tcg_gen_movi_tl(cc_op, dc->cc_op);
568 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
569 }
570
571 static void cris_evaluate_flags(DisasContext *dc)
572 {
573 if (dc->flags_uptodate) {
574 return;
575 }
576
577 cris_flush_cc_state(dc);
578
579 switch (dc->cc_op) {
580 case CC_OP_MCP:
581 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
582 cpu_PR[PR_CCS], cc_src,
583 cc_dest, cc_result);
584 break;
585 case CC_OP_MULS:
586 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
587 cpu_PR[PR_CCS], cc_result,
588 cpu_PR[PR_MOF]);
589 break;
590 case CC_OP_MULU:
591 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
592 cpu_PR[PR_CCS], cc_result,
593 cpu_PR[PR_MOF]);
594 break;
595 case CC_OP_MOVE:
596 case CC_OP_AND:
597 case CC_OP_OR:
598 case CC_OP_XOR:
599 case CC_OP_ASR:
600 case CC_OP_LSR:
601 case CC_OP_LSL:
602 switch (dc->cc_size) {
603 case 4:
604 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
605 cpu_env, cpu_PR[PR_CCS], cc_result);
606 break;
607 case 2:
608 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
609 cpu_env, cpu_PR[PR_CCS], cc_result);
610 break;
611 default:
612 gen_helper_evaluate_flags(cpu_env);
613 break;
614 }
615 break;
616 case CC_OP_FLAGS:
617 /* live. */
618 break;
619 case CC_OP_SUB:
620 case CC_OP_CMP:
621 if (dc->cc_size == 4) {
622 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
623 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
624 } else {
625 gen_helper_evaluate_flags(cpu_env);
626 }
627
628 break;
629 default:
630 switch (dc->cc_size) {
631 case 4:
632 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
633 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
634 break;
635 default:
636 gen_helper_evaluate_flags(cpu_env);
637 break;
638 }
639 break;
640 }
641
642 if (dc->flagx_known) {
643 if (dc->flags_x) {
644 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
645 } else if (dc->cc_op == CC_OP_FLAGS) {
646 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
647 }
648 }
649 dc->flags_uptodate = 1;
650 }
651
652 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
653 {
654 uint32_t ovl;
655
656 if (!mask) {
657 dc->update_cc = 0;
658 return;
659 }
660
661 /* Check if we need to evaluate the condition codes due to
662 CC overlaying. */
663 ovl = (dc->cc_mask ^ mask) & ~mask;
664 if (ovl) {
665 /* TODO: optimize this case. It trigs all the time. */
666 cris_evaluate_flags(dc);
667 }
668 dc->cc_mask = mask;
669 dc->update_cc = 1;
670 }
671
672 static void cris_update_cc_op(DisasContext *dc, int op, int size)
673 {
674 dc->cc_op = op;
675 dc->cc_size = size;
676 dc->flags_uptodate = 0;
677 }
678
679 static inline void cris_update_cc_x(DisasContext *dc)
680 {
681 /* Save the x flag state at the time of the cc snapshot. */
682 if (dc->flagx_known) {
683 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
684 return;
685 }
686 tcg_gen_movi_tl(cc_x, dc->flags_x);
687 dc->cc_x_uptodate = 2 | dc->flags_x;
688 } else {
689 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
690 dc->cc_x_uptodate = 1;
691 }
692 }
693
694 /* Update cc prior to executing ALU op. Needs source operands untouched. */
695 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
696 TCGv dst, TCGv src, int size)
697 {
698 if (dc->update_cc) {
699 cris_update_cc_op(dc, op, size);
700 tcg_gen_mov_tl(cc_src, src);
701
702 if (op != CC_OP_MOVE
703 && op != CC_OP_AND
704 && op != CC_OP_OR
705 && op != CC_OP_XOR
706 && op != CC_OP_ASR
707 && op != CC_OP_LSR
708 && op != CC_OP_LSL) {
709 tcg_gen_mov_tl(cc_dest, dst);
710 }
711
712 cris_update_cc_x(dc);
713 }
714 }
715
716 /* Update cc after executing ALU op. needs the result. */
717 static inline void cris_update_result(DisasContext *dc, TCGv res)
718 {
719 if (dc->update_cc) {
720 tcg_gen_mov_tl(cc_result, res);
721 }
722 }
723
724 /* Returns one if the write back stage should execute. */
725 static void cris_alu_op_exec(DisasContext *dc, int op,
726 TCGv dst, TCGv a, TCGv b, int size)
727 {
728 /* Emit the ALU insns. */
729 switch (op) {
730 case CC_OP_ADD:
731 tcg_gen_add_tl(dst, a, b);
732 /* Extended arithmetics. */
733 t_gen_addx_carry(dc, dst);
734 break;
735 case CC_OP_ADDC:
736 tcg_gen_add_tl(dst, a, b);
737 t_gen_add_flag(dst, 0); /* C_FLAG. */
738 break;
739 case CC_OP_MCP:
740 tcg_gen_add_tl(dst, a, b);
741 t_gen_add_flag(dst, 8); /* R_FLAG. */
742 break;
743 case CC_OP_SUB:
744 tcg_gen_sub_tl(dst, a, b);
745 /* Extended arithmetics. */
746 t_gen_subx_carry(dc, dst);
747 break;
748 case CC_OP_MOVE:
749 tcg_gen_mov_tl(dst, b);
750 break;
751 case CC_OP_OR:
752 tcg_gen_or_tl(dst, a, b);
753 break;
754 case CC_OP_AND:
755 tcg_gen_and_tl(dst, a, b);
756 break;
757 case CC_OP_XOR:
758 tcg_gen_xor_tl(dst, a, b);
759 break;
760 case CC_OP_LSL:
761 t_gen_lsl(dst, a, b);
762 break;
763 case CC_OP_LSR:
764 t_gen_lsr(dst, a, b);
765 break;
766 case CC_OP_ASR:
767 t_gen_asr(dst, a, b);
768 break;
769 case CC_OP_NEG:
770 tcg_gen_neg_tl(dst, b);
771 /* Extended arithmetics. */
772 t_gen_subx_carry(dc, dst);
773 break;
774 case CC_OP_LZ:
775 tcg_gen_clzi_tl(dst, b, TARGET_LONG_BITS);
776 break;
777 case CC_OP_MULS:
778 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
779 break;
780 case CC_OP_MULU:
781 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
782 break;
783 case CC_OP_DSTEP:
784 t_gen_cris_dstep(dst, a, b);
785 break;
786 case CC_OP_MSTEP:
787 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
788 break;
789 case CC_OP_BOUND:
790 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b);
791 break;
792 case CC_OP_CMP:
793 tcg_gen_sub_tl(dst, a, b);
794 /* Extended arithmetics. */
795 t_gen_subx_carry(dc, dst);
796 break;
797 default:
798 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
799 BUG();
800 break;
801 }
802
803 if (size == 1) {
804 tcg_gen_andi_tl(dst, dst, 0xff);
805 } else if (size == 2) {
806 tcg_gen_andi_tl(dst, dst, 0xffff);
807 }
808 }
809
810 static void cris_alu(DisasContext *dc, int op,
811 TCGv d, TCGv op_a, TCGv op_b, int size)
812 {
813 TCGv tmp;
814 int writeback;
815
816 writeback = 1;
817
818 if (op == CC_OP_CMP) {
819 tmp = tcg_temp_new();
820 writeback = 0;
821 } else if (size == 4) {
822 tmp = d;
823 writeback = 0;
824 } else {
825 tmp = tcg_temp_new();
826 }
827
828
829 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
830 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
831 cris_update_result(dc, tmp);
832
833 /* Writeback. */
834 if (writeback) {
835 if (size == 1) {
836 tcg_gen_andi_tl(d, d, ~0xff);
837 } else {
838 tcg_gen_andi_tl(d, d, ~0xffff);
839 }
840 tcg_gen_or_tl(d, d, tmp);
841 }
842 if (tmp != d) {
843 tcg_temp_free(tmp);
844 }
845 }
846
847 static int arith_cc(DisasContext *dc)
848 {
849 if (dc->update_cc) {
850 switch (dc->cc_op) {
851 case CC_OP_ADDC: return 1;
852 case CC_OP_ADD: return 1;
853 case CC_OP_SUB: return 1;
854 case CC_OP_DSTEP: return 1;
855 case CC_OP_LSL: return 1;
856 case CC_OP_LSR: return 1;
857 case CC_OP_ASR: return 1;
858 case CC_OP_CMP: return 1;
859 case CC_OP_NEG: return 1;
860 case CC_OP_OR: return 1;
861 case CC_OP_AND: return 1;
862 case CC_OP_XOR: return 1;
863 case CC_OP_MULU: return 1;
864 case CC_OP_MULS: return 1;
865 default:
866 return 0;
867 }
868 }
869 return 0;
870 }
871
872 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
873 {
874 int arith_opt, move_opt;
875
876 /* TODO: optimize more condition codes. */
877
878 /*
879 * If the flags are live, we've gotta look into the bits of CCS.
880 * Otherwise, if we just did an arithmetic operation we try to
881 * evaluate the condition code faster.
882 *
883 * When this function is done, T0 should be non-zero if the condition
884 * code is true.
885 */
886 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
887 move_opt = (dc->cc_op == CC_OP_MOVE);
888 switch (cond) {
889 case CC_EQ:
890 if ((arith_opt || move_opt)
891 && dc->cc_x_uptodate != (2 | X_FLAG)) {
892 tcg_gen_setcondi_tl(TCG_COND_EQ, cc, cc_result, 0);
893 } else {
894 cris_evaluate_flags(dc);
895 tcg_gen_andi_tl(cc,
896 cpu_PR[PR_CCS], Z_FLAG);
897 }
898 break;
899 case CC_NE:
900 if ((arith_opt || move_opt)
901 && dc->cc_x_uptodate != (2 | X_FLAG)) {
902 tcg_gen_mov_tl(cc, cc_result);
903 } else {
904 cris_evaluate_flags(dc);
905 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
906 Z_FLAG);
907 tcg_gen_andi_tl(cc, cc, Z_FLAG);
908 }
909 break;
910 case CC_CS:
911 cris_evaluate_flags(dc);
912 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
913 break;
914 case CC_CC:
915 cris_evaluate_flags(dc);
916 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
917 tcg_gen_andi_tl(cc, cc, C_FLAG);
918 break;
919 case CC_VS:
920 cris_evaluate_flags(dc);
921 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
922 break;
923 case CC_VC:
924 cris_evaluate_flags(dc);
925 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
926 V_FLAG);
927 tcg_gen_andi_tl(cc, cc, V_FLAG);
928 break;
929 case CC_PL:
930 if (arith_opt || move_opt) {
931 int bits = 31;
932
933 if (dc->cc_size == 1) {
934 bits = 7;
935 } else if (dc->cc_size == 2) {
936 bits = 15;
937 }
938
939 tcg_gen_shri_tl(cc, cc_result, bits);
940 tcg_gen_xori_tl(cc, cc, 1);
941 } else {
942 cris_evaluate_flags(dc);
943 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
944 N_FLAG);
945 tcg_gen_andi_tl(cc, cc, N_FLAG);
946 }
947 break;
948 case CC_MI:
949 if (arith_opt || move_opt) {
950 int bits = 31;
951
952 if (dc->cc_size == 1) {
953 bits = 7;
954 } else if (dc->cc_size == 2) {
955 bits = 15;
956 }
957
958 tcg_gen_shri_tl(cc, cc_result, bits);
959 tcg_gen_andi_tl(cc, cc, 1);
960 } else {
961 cris_evaluate_flags(dc);
962 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
963 N_FLAG);
964 }
965 break;
966 case CC_LS:
967 cris_evaluate_flags(dc);
968 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
969 C_FLAG | Z_FLAG);
970 break;
971 case CC_HI:
972 cris_evaluate_flags(dc);
973 {
974 TCGv tmp;
975
976 tmp = tcg_temp_new();
977 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
978 C_FLAG | Z_FLAG);
979 /* Overlay the C flag on top of the Z. */
980 tcg_gen_shli_tl(cc, tmp, 2);
981 tcg_gen_and_tl(cc, tmp, cc);
982 tcg_gen_andi_tl(cc, cc, Z_FLAG);
983
984 tcg_temp_free(tmp);
985 }
986 break;
987 case CC_GE:
988 cris_evaluate_flags(dc);
989 /* Overlay the V flag on top of the N. */
990 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
991 tcg_gen_xor_tl(cc,
992 cpu_PR[PR_CCS], cc);
993 tcg_gen_andi_tl(cc, cc, N_FLAG);
994 tcg_gen_xori_tl(cc, cc, N_FLAG);
995 break;
996 case CC_LT:
997 cris_evaluate_flags(dc);
998 /* Overlay the V flag on top of the N. */
999 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1000 tcg_gen_xor_tl(cc,
1001 cpu_PR[PR_CCS], cc);
1002 tcg_gen_andi_tl(cc, cc, N_FLAG);
1003 break;
1004 case CC_GT:
1005 cris_evaluate_flags(dc);
1006 {
1007 TCGv n, z;
1008
1009 n = tcg_temp_new();
1010 z = tcg_temp_new();
1011
1012 /* To avoid a shift we overlay everything on
1013 the V flag. */
1014 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1015 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1016 /* invert Z. */
1017 tcg_gen_xori_tl(z, z, 2);
1018
1019 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1020 tcg_gen_xori_tl(n, n, 2);
1021 tcg_gen_and_tl(cc, z, n);
1022 tcg_gen_andi_tl(cc, cc, 2);
1023
1024 tcg_temp_free(n);
1025 tcg_temp_free(z);
1026 }
1027 break;
1028 case CC_LE:
1029 cris_evaluate_flags(dc);
1030 {
1031 TCGv n, z;
1032
1033 n = tcg_temp_new();
1034 z = tcg_temp_new();
1035
1036 /* To avoid a shift we overlay everything on
1037 the V flag. */
1038 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1039 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1040
1041 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1042 tcg_gen_or_tl(cc, z, n);
1043 tcg_gen_andi_tl(cc, cc, 2);
1044
1045 tcg_temp_free(n);
1046 tcg_temp_free(z);
1047 }
1048 break;
1049 case CC_P:
1050 cris_evaluate_flags(dc);
1051 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1052 break;
1053 case CC_A:
1054 tcg_gen_movi_tl(cc, 1);
1055 break;
1056 default:
1057 BUG();
1058 break;
1059 };
1060 }
1061
1062 static void cris_store_direct_jmp(DisasContext *dc)
1063 {
1064 /* Store the direct jmp state into the cpu-state. */
1065 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1066 if (dc->jmp == JMP_DIRECT) {
1067 tcg_gen_movi_tl(env_btaken, 1);
1068 }
1069 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1070 dc->jmp = JMP_INDIRECT;
1071 }
1072 }
1073
1074 static void cris_prepare_cc_branch (DisasContext *dc,
1075 int offset, int cond)
1076 {
1077 /* This helps us re-schedule the micro-code to insns in delay-slots
1078 before the actual jump. */
1079 dc->delayed_branch = 2;
1080 dc->jmp = JMP_DIRECT_CC;
1081 dc->jmp_pc = dc->pc + offset;
1082
1083 gen_tst_cc(dc, env_btaken, cond);
1084 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1085 }
1086
1087
1088 /* jumps, when the dest is in a live reg for example. Direct should be set
1089 when the dest addr is constant to allow tb chaining. */
1090 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1091 {
1092 /* This helps us re-schedule the micro-code to insns in delay-slots
1093 before the actual jump. */
1094 dc->delayed_branch = 2;
1095 dc->jmp = type;
1096 if (type == JMP_INDIRECT) {
1097 tcg_gen_movi_tl(env_btaken, 1);
1098 }
1099 }
1100
1101 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1102 {
1103 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1104
1105 /* If we get a fault on a delayslot we must keep the jmp state in
1106 the cpu-state to be able to re-execute the jmp. */
1107 if (dc->delayed_branch == 1) {
1108 cris_store_direct_jmp(dc);
1109 }
1110
1111 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
1112 }
1113
1114 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1115 unsigned int size, int sign)
1116 {
1117 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1118
1119 /* If we get a fault on a delayslot we must keep the jmp state in
1120 the cpu-state to be able to re-execute the jmp. */
1121 if (dc->delayed_branch == 1) {
1122 cris_store_direct_jmp(dc);
1123 }
1124
1125 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1126 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1127 }
1128
1129 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1130 unsigned int size)
1131 {
1132 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1133
1134 /* If we get a fault on a delayslot we must keep the jmp state in
1135 the cpu-state to be able to re-execute the jmp. */
1136 if (dc->delayed_branch == 1) {
1137 cris_store_direct_jmp(dc);
1138 }
1139
1140
1141 /* Conditional writes. We only support the kind were X and P are known
1142 at translation time. */
1143 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1144 dc->postinc = 0;
1145 cris_evaluate_flags(dc);
1146 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1147 return;
1148 }
1149
1150 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
1151
1152 if (dc->flagx_known && dc->flags_x) {
1153 cris_evaluate_flags(dc);
1154 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1155 }
1156 }
1157
1158 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1159 {
1160 if (size == 1) {
1161 tcg_gen_ext8s_i32(d, s);
1162 } else if (size == 2) {
1163 tcg_gen_ext16s_i32(d, s);
1164 } else {
1165 tcg_gen_mov_tl(d, s);
1166 }
1167 }
1168
1169 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1170 {
1171 if (size == 1) {
1172 tcg_gen_ext8u_i32(d, s);
1173 } else if (size == 2) {
1174 tcg_gen_ext16u_i32(d, s);
1175 } else {
1176 tcg_gen_mov_tl(d, s);
1177 }
1178 }
1179
1180 #if DISAS_CRIS
1181 static char memsize_char(int size)
1182 {
1183 switch (size) {
1184 case 1: return 'b';
1185 case 2: return 'w';
1186 case 4: return 'd';
1187 default:
1188 return 'x';
1189 }
1190 }
1191 #endif
1192
1193 static inline unsigned int memsize_z(DisasContext *dc)
1194 {
1195 return dc->zsize + 1;
1196 }
1197
1198 static inline unsigned int memsize_zz(DisasContext *dc)
1199 {
1200 switch (dc->zzsize) {
1201 case 0: return 1;
1202 case 1: return 2;
1203 default:
1204 return 4;
1205 }
1206 }
1207
1208 static inline void do_postinc (DisasContext *dc, int size)
1209 {
1210 if (dc->postinc) {
1211 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1212 }
1213 }
1214
1215 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1216 int size, int s_ext, TCGv dst)
1217 {
1218 if (s_ext) {
1219 t_gen_sext(dst, cpu_R[rs], size);
1220 } else {
1221 t_gen_zext(dst, cpu_R[rs], size);
1222 }
1223 }
1224
1225 /* Prepare T0 and T1 for a register alu operation.
1226 s_ext decides if the operand1 should be sign-extended or zero-extended when
1227 needed. */
1228 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1229 int size, int s_ext, TCGv dst, TCGv src)
1230 {
1231 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1232
1233 if (s_ext) {
1234 t_gen_sext(dst, cpu_R[rd], size);
1235 } else {
1236 t_gen_zext(dst, cpu_R[rd], size);
1237 }
1238 }
1239
1240 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1241 int s_ext, int memsize, TCGv dst)
1242 {
1243 unsigned int rs;
1244 uint32_t imm;
1245 int is_imm;
1246 int insn_len = 2;
1247
1248 rs = dc->op1;
1249 is_imm = rs == 15 && dc->postinc;
1250
1251 /* Load [$rs] onto T1. */
1252 if (is_imm) {
1253 insn_len = 2 + memsize;
1254 if (memsize == 1) {
1255 insn_len++;
1256 }
1257
1258 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1259 tcg_gen_movi_tl(dst, imm);
1260 dc->postinc = 0;
1261 } else {
1262 cris_flush_cc_state(dc);
1263 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1264 if (s_ext) {
1265 t_gen_sext(dst, dst, memsize);
1266 } else {
1267 t_gen_zext(dst, dst, memsize);
1268 }
1269 }
1270 return insn_len;
1271 }
1272
1273 /* Prepare T0 and T1 for a memory + alu operation.
1274 s_ext decides if the operand1 should be sign-extended or zero-extended when
1275 needed. */
1276 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1277 int s_ext, int memsize, TCGv dst, TCGv src)
1278 {
1279 int insn_len;
1280
1281 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1282 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1283 return insn_len;
1284 }
1285
1286 #if DISAS_CRIS
1287 static const char *cc_name(int cc)
1288 {
1289 static const char * const cc_names[16] = {
1290 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1291 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1292 };
1293 assert(cc < 16);
1294 return cc_names[cc];
1295 }
1296 #endif
1297
1298 /* Start of insn decoders. */
1299
1300 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1301 {
1302 int32_t offset;
1303 int sign;
1304 uint32_t cond = dc->op2;
1305
1306 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1307 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1308
1309 offset *= 2;
1310 offset |= sign << 8;
1311 offset = sign_extend(offset, 8);
1312
1313 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1314
1315 /* op2 holds the condition-code. */
1316 cris_cc_mask(dc, 0);
1317 cris_prepare_cc_branch(dc, offset, cond);
1318 return 2;
1319 }
1320 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1321 {
1322 int32_t imm;
1323
1324 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1325 imm = sign_extend(dc->op1, 7);
1326
1327 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1328 cris_cc_mask(dc, 0);
1329 /* Fetch register operand, */
1330 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1331
1332 return 2;
1333 }
1334 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1335 {
1336 TCGv c;
1337 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1338
1339 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1340
1341 cris_cc_mask(dc, CC_MASK_NZVC);
1342
1343 c = tcg_const_tl(dc->op1);
1344 cris_alu(dc, CC_OP_ADD,
1345 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1346 tcg_temp_free(c);
1347 return 2;
1348 }
1349 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1350 {
1351 uint32_t imm;
1352
1353 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1354 imm = sign_extend(dc->op1, 5);
1355 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1356
1357 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1358 return 2;
1359 }
1360 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1361 {
1362 TCGv c;
1363 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1364
1365 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1366
1367 cris_cc_mask(dc, CC_MASK_NZVC);
1368 c = tcg_const_tl(dc->op1);
1369 cris_alu(dc, CC_OP_SUB,
1370 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1371 tcg_temp_free(c);
1372 return 2;
1373 }
1374 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1375 {
1376 uint32_t imm;
1377 TCGv c;
1378 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1379 imm = sign_extend(dc->op1, 5);
1380
1381 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1382 cris_cc_mask(dc, CC_MASK_NZVC);
1383
1384 c = tcg_const_tl(imm);
1385 cris_alu(dc, CC_OP_CMP,
1386 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1387 tcg_temp_free(c);
1388 return 2;
1389 }
1390 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1391 {
1392 uint32_t imm;
1393 TCGv c;
1394 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1395 imm = sign_extend(dc->op1, 5);
1396
1397 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1398 cris_cc_mask(dc, CC_MASK_NZ);
1399
1400 c = tcg_const_tl(imm);
1401 cris_alu(dc, CC_OP_AND,
1402 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1403 tcg_temp_free(c);
1404 return 2;
1405 }
1406 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1407 {
1408 uint32_t imm;
1409 TCGv c;
1410 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1411 imm = sign_extend(dc->op1, 5);
1412 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1413 cris_cc_mask(dc, CC_MASK_NZ);
1414
1415 c = tcg_const_tl(imm);
1416 cris_alu(dc, CC_OP_OR,
1417 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1418 tcg_temp_free(c);
1419 return 2;
1420 }
1421 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1422 {
1423 TCGv c;
1424 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1425 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1426
1427 cris_cc_mask(dc, CC_MASK_NZ);
1428 c = tcg_const_tl(dc->op1);
1429 cris_evaluate_flags(dc);
1430 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1431 c, cpu_PR[PR_CCS]);
1432 tcg_temp_free(c);
1433 cris_alu(dc, CC_OP_MOVE,
1434 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1435 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1436 dc->flags_uptodate = 1;
1437 return 2;
1438 }
1439 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1440 {
1441 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1442 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1443 cris_cc_mask(dc, CC_MASK_NZ);
1444
1445 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1446 cris_alu(dc, CC_OP_MOVE,
1447 cpu_R[dc->op2],
1448 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1449 return 2;
1450 }
1451 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1452 {
1453 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1454 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1455
1456 cris_cc_mask(dc, CC_MASK_NZ);
1457
1458 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1459
1460 cris_alu(dc, CC_OP_MOVE,
1461 cpu_R[dc->op2],
1462 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1463 return 2;
1464 }
1465 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1466 {
1467 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1468 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1469
1470 cris_cc_mask(dc, CC_MASK_NZ);
1471
1472 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1473 cris_alu(dc, CC_OP_MOVE,
1474 cpu_R[dc->op2],
1475 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1476 return 2;
1477 }
1478
1479 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1480 {
1481 int size = memsize_zz(dc);
1482
1483 LOG_DIS("move.%c $r%u, $r%u\n",
1484 memsize_char(size), dc->op1, dc->op2);
1485
1486 cris_cc_mask(dc, CC_MASK_NZ);
1487 if (size == 4) {
1488 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1489 cris_cc_mask(dc, CC_MASK_NZ);
1490 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1491 cris_update_cc_x(dc);
1492 cris_update_result(dc, cpu_R[dc->op2]);
1493 } else {
1494 TCGv t0;
1495
1496 t0 = tcg_temp_new();
1497 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1498 cris_alu(dc, CC_OP_MOVE,
1499 cpu_R[dc->op2],
1500 cpu_R[dc->op2], t0, size);
1501 tcg_temp_free(t0);
1502 }
1503 return 2;
1504 }
1505
1506 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1507 {
1508 int cond = dc->op2;
1509
1510 LOG_DIS("s%s $r%u\n",
1511 cc_name(cond), dc->op1);
1512
1513 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1514 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0);
1515
1516 cris_cc_mask(dc, 0);
1517 return 2;
1518 }
1519
1520 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1521 {
1522 if (size == 4) {
1523 t[0] = cpu_R[dc->op2];
1524 t[1] = cpu_R[dc->op1];
1525 } else {
1526 t[0] = tcg_temp_new();
1527 t[1] = tcg_temp_new();
1528 }
1529 }
1530
1531 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1532 {
1533 if (size != 4) {
1534 tcg_temp_free(t[0]);
1535 tcg_temp_free(t[1]);
1536 }
1537 }
1538
1539 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1540 {
1541 TCGv t[2];
1542 int size = memsize_zz(dc);
1543
1544 LOG_DIS("and.%c $r%u, $r%u\n",
1545 memsize_char(size), dc->op1, dc->op2);
1546
1547 cris_cc_mask(dc, CC_MASK_NZ);
1548
1549 cris_alu_alloc_temps(dc, size, t);
1550 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1551 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1552 cris_alu_free_temps(dc, size, t);
1553 return 2;
1554 }
1555
1556 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1557 {
1558 TCGv t0;
1559 LOG_DIS("lz $r%u, $r%u\n",
1560 dc->op1, dc->op2);
1561 cris_cc_mask(dc, CC_MASK_NZ);
1562 t0 = tcg_temp_new();
1563 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1564 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1565 tcg_temp_free(t0);
1566 return 2;
1567 }
1568
1569 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1570 {
1571 TCGv t[2];
1572 int size = memsize_zz(dc);
1573
1574 LOG_DIS("lsl.%c $r%u, $r%u\n",
1575 memsize_char(size), dc->op1, dc->op2);
1576
1577 cris_cc_mask(dc, CC_MASK_NZ);
1578 cris_alu_alloc_temps(dc, size, t);
1579 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1580 tcg_gen_andi_tl(t[1], t[1], 63);
1581 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1582 cris_alu_free_temps(dc, size, t);
1583 return 2;
1584 }
1585
1586 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1587 {
1588 TCGv t[2];
1589 int size = memsize_zz(dc);
1590
1591 LOG_DIS("lsr.%c $r%u, $r%u\n",
1592 memsize_char(size), dc->op1, dc->op2);
1593
1594 cris_cc_mask(dc, CC_MASK_NZ);
1595 cris_alu_alloc_temps(dc, size, t);
1596 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1597 tcg_gen_andi_tl(t[1], t[1], 63);
1598 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1599 cris_alu_free_temps(dc, size, t);
1600 return 2;
1601 }
1602
1603 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1604 {
1605 TCGv t[2];
1606 int size = memsize_zz(dc);
1607
1608 LOG_DIS("asr.%c $r%u, $r%u\n",
1609 memsize_char(size), dc->op1, dc->op2);
1610
1611 cris_cc_mask(dc, CC_MASK_NZ);
1612 cris_alu_alloc_temps(dc, size, t);
1613 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1614 tcg_gen_andi_tl(t[1], t[1], 63);
1615 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1616 cris_alu_free_temps(dc, size, t);
1617 return 2;
1618 }
1619
1620 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1621 {
1622 TCGv t[2];
1623 int size = memsize_zz(dc);
1624
1625 LOG_DIS("muls.%c $r%u, $r%u\n",
1626 memsize_char(size), dc->op1, dc->op2);
1627 cris_cc_mask(dc, CC_MASK_NZV);
1628 cris_alu_alloc_temps(dc, size, t);
1629 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1630
1631 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1632 cris_alu_free_temps(dc, size, t);
1633 return 2;
1634 }
1635
1636 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1637 {
1638 TCGv t[2];
1639 int size = memsize_zz(dc);
1640
1641 LOG_DIS("mulu.%c $r%u, $r%u\n",
1642 memsize_char(size), dc->op1, dc->op2);
1643 cris_cc_mask(dc, CC_MASK_NZV);
1644 cris_alu_alloc_temps(dc, size, t);
1645 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1646
1647 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1648 cris_alu_free_temps(dc, size, t);
1649 return 2;
1650 }
1651
1652
1653 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1654 {
1655 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1656 cris_cc_mask(dc, CC_MASK_NZ);
1657 cris_alu(dc, CC_OP_DSTEP,
1658 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1659 return 2;
1660 }
1661
1662 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1663 {
1664 TCGv t[2];
1665 int size = memsize_zz(dc);
1666 LOG_DIS("xor.%c $r%u, $r%u\n",
1667 memsize_char(size), dc->op1, dc->op2);
1668 BUG_ON(size != 4); /* xor is dword. */
1669 cris_cc_mask(dc, CC_MASK_NZ);
1670 cris_alu_alloc_temps(dc, size, t);
1671 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1672
1673 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1674 cris_alu_free_temps(dc, size, t);
1675 return 2;
1676 }
1677
1678 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1679 {
1680 TCGv l0;
1681 int size = memsize_zz(dc);
1682 LOG_DIS("bound.%c $r%u, $r%u\n",
1683 memsize_char(size), dc->op1, dc->op2);
1684 cris_cc_mask(dc, CC_MASK_NZ);
1685 l0 = tcg_temp_local_new();
1686 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1687 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1688 tcg_temp_free(l0);
1689 return 2;
1690 }
1691
1692 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1693 {
1694 TCGv t[2];
1695 int size = memsize_zz(dc);
1696 LOG_DIS("cmp.%c $r%u, $r%u\n",
1697 memsize_char(size), dc->op1, dc->op2);
1698 cris_cc_mask(dc, CC_MASK_NZVC);
1699 cris_alu_alloc_temps(dc, size, t);
1700 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1701
1702 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1703 cris_alu_free_temps(dc, size, t);
1704 return 2;
1705 }
1706
1707 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1708 {
1709 LOG_DIS("abs $r%u, $r%u\n",
1710 dc->op1, dc->op2);
1711 cris_cc_mask(dc, CC_MASK_NZ);
1712
1713 tcg_gen_abs_tl(cpu_R[dc->op2], cpu_R[dc->op1]);
1714 cris_alu(dc, CC_OP_MOVE,
1715 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1716 return 2;
1717 }
1718
1719 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1720 {
1721 TCGv t[2];
1722 int size = memsize_zz(dc);
1723 LOG_DIS("add.%c $r%u, $r%u\n",
1724 memsize_char(size), dc->op1, dc->op2);
1725 cris_cc_mask(dc, CC_MASK_NZVC);
1726 cris_alu_alloc_temps(dc, size, t);
1727 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1728
1729 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1730 cris_alu_free_temps(dc, size, t);
1731 return 2;
1732 }
1733
1734 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1735 {
1736 LOG_DIS("addc $r%u, $r%u\n",
1737 dc->op1, dc->op2);
1738 cris_evaluate_flags(dc);
1739 /* Set for this insn. */
1740 dc->flagx_known = 1;
1741 dc->flags_x = X_FLAG;
1742
1743 cris_cc_mask(dc, CC_MASK_NZVC);
1744 cris_alu(dc, CC_OP_ADDC,
1745 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1746 return 2;
1747 }
1748
1749 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1750 {
1751 LOG_DIS("mcp $p%u, $r%u\n",
1752 dc->op2, dc->op1);
1753 cris_evaluate_flags(dc);
1754 cris_cc_mask(dc, CC_MASK_RNZV);
1755 cris_alu(dc, CC_OP_MCP,
1756 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1757 return 2;
1758 }
1759
1760 #if DISAS_CRIS
1761 static char * swapmode_name(int mode, char *modename) {
1762 int i = 0;
1763 if (mode & 8) {
1764 modename[i++] = 'n';
1765 }
1766 if (mode & 4) {
1767 modename[i++] = 'w';
1768 }
1769 if (mode & 2) {
1770 modename[i++] = 'b';
1771 }
1772 if (mode & 1) {
1773 modename[i++] = 'r';
1774 }
1775 modename[i++] = 0;
1776 return modename;
1777 }
1778 #endif
1779
1780 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1781 {
1782 TCGv t0;
1783 #if DISAS_CRIS
1784 char modename[4];
1785 #endif
1786 LOG_DIS("swap%s $r%u\n",
1787 swapmode_name(dc->op2, modename), dc->op1);
1788
1789 cris_cc_mask(dc, CC_MASK_NZ);
1790 t0 = tcg_temp_new();
1791 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
1792 if (dc->op2 & 8) {
1793 tcg_gen_not_tl(t0, t0);
1794 }
1795 if (dc->op2 & 4) {
1796 t_gen_swapw(t0, t0);
1797 }
1798 if (dc->op2 & 2) {
1799 t_gen_swapb(t0, t0);
1800 }
1801 if (dc->op2 & 1) {
1802 t_gen_swapr(t0, t0);
1803 }
1804 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1805 tcg_temp_free(t0);
1806 return 2;
1807 }
1808
1809 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1810 {
1811 TCGv t[2];
1812 int size = memsize_zz(dc);
1813 LOG_DIS("or.%c $r%u, $r%u\n",
1814 memsize_char(size), dc->op1, dc->op2);
1815 cris_cc_mask(dc, CC_MASK_NZ);
1816 cris_alu_alloc_temps(dc, size, t);
1817 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1818 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1819 cris_alu_free_temps(dc, size, t);
1820 return 2;
1821 }
1822
1823 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1824 {
1825 TCGv t0;
1826 LOG_DIS("addi.%c $r%u, $r%u\n",
1827 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1828 cris_cc_mask(dc, 0);
1829 t0 = tcg_temp_new();
1830 tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize);
1831 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1832 tcg_temp_free(t0);
1833 return 2;
1834 }
1835
1836 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1837 {
1838 TCGv t0;
1839 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1840 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1841 cris_cc_mask(dc, 0);
1842 t0 = tcg_temp_new();
1843 tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize);
1844 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1845 tcg_temp_free(t0);
1846 return 2;
1847 }
1848
1849 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1850 {
1851 TCGv t[2];
1852 int size = memsize_zz(dc);
1853 LOG_DIS("neg.%c $r%u, $r%u\n",
1854 memsize_char(size), dc->op1, dc->op2);
1855 cris_cc_mask(dc, CC_MASK_NZVC);
1856 cris_alu_alloc_temps(dc, size, t);
1857 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1858
1859 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1860 cris_alu_free_temps(dc, size, t);
1861 return 2;
1862 }
1863
1864 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1865 {
1866 LOG_DIS("btst $r%u, $r%u\n",
1867 dc->op1, dc->op2);
1868 cris_cc_mask(dc, CC_MASK_NZ);
1869 cris_evaluate_flags(dc);
1870 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1871 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1872 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1873 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1874 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1875 dc->flags_uptodate = 1;
1876 return 2;
1877 }
1878
1879 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1880 {
1881 TCGv t[2];
1882 int size = memsize_zz(dc);
1883 LOG_DIS("sub.%c $r%u, $r%u\n",
1884 memsize_char(size), dc->op1, dc->op2);
1885 cris_cc_mask(dc, CC_MASK_NZVC);
1886 cris_alu_alloc_temps(dc, size, t);
1887 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1888 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1889 cris_alu_free_temps(dc, size, t);
1890 return 2;
1891 }
1892
1893 /* Zero extension. From size to dword. */
1894 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1895 {
1896 TCGv t0;
1897 int size = memsize_z(dc);
1898 LOG_DIS("movu.%c $r%u, $r%u\n",
1899 memsize_char(size),
1900 dc->op1, dc->op2);
1901
1902 cris_cc_mask(dc, CC_MASK_NZ);
1903 t0 = tcg_temp_new();
1904 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1905 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1906 tcg_temp_free(t0);
1907 return 2;
1908 }
1909
1910 /* Sign extension. From size to dword. */
1911 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1912 {
1913 TCGv t0;
1914 int size = memsize_z(dc);
1915 LOG_DIS("movs.%c $r%u, $r%u\n",
1916 memsize_char(size),
1917 dc->op1, dc->op2);
1918
1919 cris_cc_mask(dc, CC_MASK_NZ);
1920 t0 = tcg_temp_new();
1921 /* Size can only be qi or hi. */
1922 t_gen_sext(t0, cpu_R[dc->op1], size);
1923 cris_alu(dc, CC_OP_MOVE,
1924 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1925 tcg_temp_free(t0);
1926 return 2;
1927 }
1928
1929 /* zero extension. From size to dword. */
1930 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1931 {
1932 TCGv t0;
1933 int size = memsize_z(dc);
1934 LOG_DIS("addu.%c $r%u, $r%u\n",
1935 memsize_char(size),
1936 dc->op1, dc->op2);
1937
1938 cris_cc_mask(dc, CC_MASK_NZVC);
1939 t0 = tcg_temp_new();
1940 /* Size can only be qi or hi. */
1941 t_gen_zext(t0, cpu_R[dc->op1], size);
1942 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1943 tcg_temp_free(t0);
1944 return 2;
1945 }
1946
1947 /* Sign extension. From size to dword. */
1948 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1949 {
1950 TCGv t0;
1951 int size = memsize_z(dc);
1952 LOG_DIS("adds.%c $r%u, $r%u\n",
1953 memsize_char(size),
1954 dc->op1, dc->op2);
1955
1956 cris_cc_mask(dc, CC_MASK_NZVC);
1957 t0 = tcg_temp_new();
1958 /* Size can only be qi or hi. */
1959 t_gen_sext(t0, cpu_R[dc->op1], size);
1960 cris_alu(dc, CC_OP_ADD,
1961 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1962 tcg_temp_free(t0);
1963 return 2;
1964 }
1965
1966 /* Zero extension. From size to dword. */
1967 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1968 {
1969 TCGv t0;
1970 int size = memsize_z(dc);
1971 LOG_DIS("subu.%c $r%u, $r%u\n",
1972 memsize_char(size),
1973 dc->op1, dc->op2);
1974
1975 cris_cc_mask(dc, CC_MASK_NZVC);
1976 t0 = tcg_temp_new();
1977 /* Size can only be qi or hi. */
1978 t_gen_zext(t0, cpu_R[dc->op1], size);
1979 cris_alu(dc, CC_OP_SUB,
1980 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1981 tcg_temp_free(t0);
1982 return 2;
1983 }
1984
1985 /* Sign extension. From size to dword. */
1986 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
1987 {
1988 TCGv t0;
1989 int size = memsize_z(dc);
1990 LOG_DIS("subs.%c $r%u, $r%u\n",
1991 memsize_char(size),
1992 dc->op1, dc->op2);
1993
1994 cris_cc_mask(dc, CC_MASK_NZVC);
1995 t0 = tcg_temp_new();
1996 /* Size can only be qi or hi. */
1997 t_gen_sext(t0, cpu_R[dc->op1], size);
1998 cris_alu(dc, CC_OP_SUB,
1999 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2000 tcg_temp_free(t0);
2001 return 2;
2002 }
2003
2004 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
2005 {
2006 uint32_t flags;
2007 int set = (~dc->opcode >> 2) & 1;
2008
2009
2010 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2011 | EXTRACT_FIELD(dc->ir, 0, 3);
2012 if (set && flags == 0) {
2013 LOG_DIS("nop\n");
2014 return 2;
2015 } else if (!set && (flags & 0x20)) {
2016 LOG_DIS("di\n");
2017 } else {
2018 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
2019 }
2020
2021 /* User space is not allowed to touch these. Silently ignore. */
2022 if (dc->tb_flags & U_FLAG) {
2023 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2024 }
2025
2026 if (flags & X_FLAG) {
2027 dc->flagx_known = 1;
2028 if (set) {
2029 dc->flags_x = X_FLAG;
2030 } else {
2031 dc->flags_x = 0;
2032 }
2033 }
2034
2035 /* Break the TB if any of the SPI flag changes. */
2036 if (flags & (P_FLAG | S_FLAG)) {
2037 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2038 dc->base.is_jmp = DISAS_UPDATE;
2039 dc->cpustate_changed = 1;
2040 }
2041
2042 /* For the I flag, only act on posedge. */
2043 if ((flags & I_FLAG)) {
2044 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2045 dc->base.is_jmp = DISAS_UPDATE;
2046 dc->cpustate_changed = 1;
2047 }
2048
2049
2050 /* Simply decode the flags. */
2051 cris_evaluate_flags(dc);
2052 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2053 cris_update_cc_x(dc);
2054 tcg_gen_movi_tl(cc_op, dc->cc_op);
2055
2056 if (set) {
2057 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2058 /* Enter user mode. */
2059 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2060 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2061 dc->cpustate_changed = 1;
2062 }
2063 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2064 } else {
2065 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2066 }
2067
2068 dc->flags_uptodate = 1;
2069 dc->clear_x = 0;
2070 return 2;
2071 }
2072
2073 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2074 {
2075 TCGv c2, c1;
2076 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2077 c1 = tcg_const_tl(dc->op1);
2078 c2 = tcg_const_tl(dc->op2);
2079 cris_cc_mask(dc, 0);
2080 gen_helper_movl_sreg_reg(cpu_env, c2, c1);
2081 tcg_temp_free(c1);
2082 tcg_temp_free(c2);
2083 return 2;
2084 }
2085 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2086 {
2087 TCGv c2, c1;
2088 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2089 c1 = tcg_const_tl(dc->op1);
2090 c2 = tcg_const_tl(dc->op2);
2091 cris_cc_mask(dc, 0);
2092 gen_helper_movl_reg_sreg(cpu_env, c1, c2);
2093 tcg_temp_free(c1);
2094 tcg_temp_free(c2);
2095 return 2;
2096 }
2097
2098 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2099 {
2100 TCGv t[2];
2101 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2102 cris_cc_mask(dc, 0);
2103
2104 t[0] = tcg_temp_new();
2105 if (dc->op2 == PR_CCS) {
2106 cris_evaluate_flags(dc);
2107 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2108 if (dc->tb_flags & U_FLAG) {
2109 t[1] = tcg_temp_new();
2110 /* User space is not allowed to touch all flags. */
2111 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2112 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2113 tcg_gen_or_tl(t[0], t[1], t[0]);
2114 tcg_temp_free(t[1]);
2115 }
2116 } else {
2117 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2118 }
2119
2120 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2121 if (dc->op2 == PR_CCS) {
2122 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2123 dc->flags_uptodate = 1;
2124 }
2125 tcg_temp_free(t[0]);
2126 return 2;
2127 }
2128 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2129 {
2130 TCGv t0;
2131 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2132 cris_cc_mask(dc, 0);
2133
2134 if (dc->op2 == PR_CCS) {
2135 cris_evaluate_flags(dc);
2136 }
2137
2138 if (dc->op2 == PR_DZ) {
2139 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2140 } else {
2141 t0 = tcg_temp_new();
2142 t_gen_mov_TN_preg(t0, dc->op2);
2143 cris_alu(dc, CC_OP_MOVE,
2144 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2145 preg_sizes[dc->op2]);
2146 tcg_temp_free(t0);
2147 }
2148 return 2;
2149 }
2150
2151 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2152 {
2153 int memsize = memsize_zz(dc);
2154 int insn_len;
2155 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2156 memsize_char(memsize),
2157 dc->op1, dc->postinc ? "+]" : "]",
2158 dc->op2);
2159
2160 if (memsize == 4) {
2161 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2162 cris_cc_mask(dc, CC_MASK_NZ);
2163 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2164 cris_update_cc_x(dc);
2165 cris_update_result(dc, cpu_R[dc->op2]);
2166 } else {
2167 TCGv t0;
2168
2169 t0 = tcg_temp_new();
2170 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2171 cris_cc_mask(dc, CC_MASK_NZ);
2172 cris_alu(dc, CC_OP_MOVE,
2173 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2174 tcg_temp_free(t0);
2175 }
2176 do_postinc(dc, memsize);
2177 return insn_len;
2178 }
2179
2180 static inline void cris_alu_m_alloc_temps(TCGv *t)
2181 {
2182 t[0] = tcg_temp_new();
2183 t[1] = tcg_temp_new();
2184 }
2185
2186 static inline void cris_alu_m_free_temps(TCGv *t)
2187 {
2188 tcg_temp_free(t[0]);
2189 tcg_temp_free(t[1]);
2190 }
2191
2192 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2193 {
2194 TCGv t[2];
2195 int memsize = memsize_z(dc);
2196 int insn_len;
2197 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2198 memsize_char(memsize),
2199 dc->op1, dc->postinc ? "+]" : "]",
2200 dc->op2);
2201
2202 cris_alu_m_alloc_temps(t);
2203 /* sign extend. */
2204 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2205 cris_cc_mask(dc, CC_MASK_NZ);
2206 cris_alu(dc, CC_OP_MOVE,
2207 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2208 do_postinc(dc, memsize);
2209 cris_alu_m_free_temps(t);
2210 return insn_len;
2211 }
2212
2213 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2214 {
2215 TCGv t[2];
2216 int memsize = memsize_z(dc);
2217 int insn_len;
2218 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2219 memsize_char(memsize),
2220 dc->op1, dc->postinc ? "+]" : "]",
2221 dc->op2);
2222
2223 cris_alu_m_alloc_temps(t);
2224 /* sign extend. */
2225 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2226 cris_cc_mask(dc, CC_MASK_NZVC);
2227 cris_alu(dc, CC_OP_ADD,
2228 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2229 do_postinc(dc, memsize);
2230 cris_alu_m_free_temps(t);
2231 return insn_len;
2232 }
2233
2234 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2235 {
2236 TCGv t[2];
2237 int memsize = memsize_z(dc);
2238 int insn_len;
2239 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2240 memsize_char(memsize),
2241 dc->op1, dc->postinc ? "+]" : "]",
2242 dc->op2);
2243
2244 cris_alu_m_alloc_temps(t);
2245 /* sign extend. */
2246 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2247 cris_cc_mask(dc, CC_MASK_NZVC);
2248 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2249 do_postinc(dc, memsize);
2250 cris_alu_m_free_temps(t);
2251 return insn_len;
2252 }
2253
2254 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2255 {
2256 TCGv t[2];
2257 int memsize = memsize_z(dc);
2258 int insn_len;
2259 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2260 memsize_char(memsize),
2261 dc->op1, dc->postinc ? "+]" : "]",
2262 dc->op2);
2263
2264 cris_alu_m_alloc_temps(t);
2265 /* sign extend. */
2266 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2267 cris_cc_mask(dc, CC_MASK_NZVC);
2268 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2269 do_postinc(dc, memsize);
2270 cris_alu_m_free_temps(t);
2271 return insn_len;
2272 }
2273
2274 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2275 {
2276 TCGv t[2];
2277 int memsize = memsize_z(dc);
2278 int insn_len;
2279 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2280 memsize_char(memsize),
2281 dc->op1, dc->postinc ? "+]" : "]",
2282 dc->op2);
2283
2284 cris_alu_m_alloc_temps(t);
2285 /* sign extend. */
2286 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2287 cris_cc_mask(dc, CC_MASK_NZVC);
2288 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2289 do_postinc(dc, memsize);
2290 cris_alu_m_free_temps(t);
2291 return insn_len;
2292 }
2293
2294 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2295 {
2296 TCGv t[2];
2297 int memsize = memsize_z(dc);
2298 int insn_len;
2299
2300 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2301 memsize_char(memsize),
2302 dc->op1, dc->postinc ? "+]" : "]",
2303 dc->op2);
2304
2305 cris_alu_m_alloc_temps(t);
2306 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2307 cris_cc_mask(dc, CC_MASK_NZ);
2308 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2309 do_postinc(dc, memsize);
2310 cris_alu_m_free_temps(t);
2311 return insn_len;
2312 }
2313
2314 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2315 {
2316 TCGv t[2];
2317 int memsize = memsize_z(dc);
2318 int insn_len;
2319 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2320 memsize_char(memsize),
2321 dc->op1, dc->postinc ? "+]" : "]",
2322 dc->op2);
2323
2324 cris_alu_m_alloc_temps(t);
2325 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2326 cris_cc_mask(dc, CC_MASK_NZVC);
2327 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2328 do_postinc(dc, memsize);
2329 cris_alu_m_free_temps(t);
2330 return insn_len;
2331 }
2332
2333 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2334 {
2335 TCGv t[2];
2336 int memsize = memsize_z(dc);
2337 int insn_len;
2338 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2339 memsize_char(memsize),
2340 dc->op1, dc->postinc ? "+]" : "]",
2341 dc->op2);
2342
2343 cris_alu_m_alloc_temps(t);
2344 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2345 cris_cc_mask(dc, CC_MASK_NZVC);
2346 cris_alu(dc, CC_OP_CMP,
2347 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2348 memsize_zz(dc));
2349 do_postinc(dc, memsize);
2350 cris_alu_m_free_temps(t);
2351 return insn_len;
2352 }
2353
2354 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2355 {
2356 TCGv t[2];
2357 int memsize = memsize_zz(dc);
2358 int insn_len;
2359 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2360 memsize_char(memsize),
2361 dc->op1, dc->postinc ? "+]" : "]",
2362 dc->op2);
2363
2364 cris_alu_m_alloc_temps(t);
2365 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2366 cris_cc_mask(dc, CC_MASK_NZVC);
2367 cris_alu(dc, CC_OP_CMP,
2368 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2369 memsize_zz(dc));
2370 do_postinc(dc, memsize);
2371 cris_alu_m_free_temps(t);
2372 return insn_len;
2373 }
2374
2375 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2376 {
2377 TCGv t[2], c;
2378 int memsize = memsize_zz(dc);
2379 int insn_len;
2380 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2381 memsize_char(memsize),
2382 dc->op1, dc->postinc ? "+]" : "]",
2383 dc->op2);
2384
2385 cris_evaluate_flags(dc);
2386
2387 cris_alu_m_alloc_temps(t);
2388 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2389 cris_cc_mask(dc, CC_MASK_NZ);
2390 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2391
2392 c = tcg_const_tl(0);
2393 cris_alu(dc, CC_OP_CMP,
2394 cpu_R[dc->op2], t[1], c, memsize_zz(dc));
2395 tcg_temp_free(c);
2396 do_postinc(dc, memsize);
2397 cris_alu_m_free_temps(t);
2398 return insn_len;
2399 }
2400
2401 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2402 {
2403 TCGv t[2];
2404 int memsize = memsize_zz(dc);
2405 int insn_len;
2406 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2407 memsize_char(memsize),
2408 dc->op1, dc->postinc ? "+]" : "]",
2409 dc->op2);
2410
2411 cris_alu_m_alloc_temps(t);
2412 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2413 cris_cc_mask(dc, CC_MASK_NZ);
2414 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2415 do_postinc(dc, memsize);
2416 cris_alu_m_free_temps(t);
2417 return insn_len;
2418 }
2419
2420 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2421 {
2422 TCGv t[2];
2423 int memsize = memsize_zz(dc);
2424 int insn_len;
2425 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2426 memsize_char(memsize),
2427 dc->op1, dc->postinc ? "+]" : "]",
2428 dc->op2);
2429
2430 cris_alu_m_alloc_temps(t);
2431 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2432 cris_cc_mask(dc, CC_MASK_NZVC);
2433 cris_alu(dc, CC_OP_ADD,
2434 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2435 do_postinc(dc, memsize);
2436 cris_alu_m_free_temps(t);
2437 return insn_len;
2438 }
2439
2440 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2441 {
2442 TCGv t[2];
2443 int memsize = memsize_zz(dc);
2444 int insn_len;
2445 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2446 memsize_char(memsize),
2447 dc->op1, dc->postinc ? "+]" : "]",
2448 dc->op2);
2449
2450 cris_alu_m_alloc_temps(t);
2451 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2452 cris_cc_mask(dc, 0);
2453 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2454 do_postinc(dc, memsize);
2455 cris_alu_m_free_temps(t);
2456 return insn_len;
2457 }
2458
2459 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2460 {
2461 TCGv l[2];
2462 int memsize = memsize_zz(dc);
2463 int insn_len;
2464 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2465 memsize_char(memsize),
2466 dc->op1, dc->postinc ? "+]" : "]",
2467 dc->op2);
2468
2469 l[0] = tcg_temp_local_new();
2470 l[1] = tcg_temp_local_new();
2471 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2472 cris_cc_mask(dc, CC_MASK_NZ);
2473 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2474 do_postinc(dc, memsize);
2475 tcg_temp_free(l[0]);
2476 tcg_temp_free(l[1]);
2477 return insn_len;
2478 }
2479
2480 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2481 {
2482 TCGv t[2];
2483 int insn_len = 2;
2484 LOG_DIS("addc [$r%u%s, $r%u\n",
2485 dc->op1, dc->postinc ? "+]" : "]",
2486 dc->op2);
2487
2488 cris_evaluate_flags(dc);
2489
2490 /* Set for this insn. */
2491 dc->flagx_known = 1;
2492 dc->flags_x = X_FLAG;
2493
2494 cris_alu_m_alloc_temps(t);
2495 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2496 cris_cc_mask(dc, CC_MASK_NZVC);
2497 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2498 do_postinc(dc, 4);
2499 cris_alu_m_free_temps(t);
2500 return insn_len;
2501 }
2502
2503 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2504 {
2505 TCGv t[2];
2506 int memsize = memsize_zz(dc);
2507 int insn_len;
2508 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2509 memsize_char(memsize),
2510 dc->op1, dc->postinc ? "+]" : "]",
2511 dc->op2, dc->ir, dc->zzsize);
2512
2513 cris_alu_m_alloc_temps(t);
2514 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2515 cris_cc_mask(dc, CC_MASK_NZVC);
2516 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2517 do_postinc(dc, memsize);
2518 cris_alu_m_free_temps(t);
2519 return insn_len;
2520 }
2521
2522 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2523 {
2524 TCGv t[2];
2525 int memsize = memsize_zz(dc);
2526 int insn_len;
2527 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2528 memsize_char(memsize),
2529 dc->op1, dc->postinc ? "+]" : "]",
2530 dc->op2, dc->pc);
2531
2532 cris_alu_m_alloc_temps(t);
2533 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2534 cris_cc_mask(dc, CC_MASK_NZ);
2535 cris_alu(dc, CC_OP_OR,
2536 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2537 do_postinc(dc, memsize);
2538 cris_alu_m_free_temps(t);
2539 return insn_len;
2540 }
2541
2542 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2543 {
2544 TCGv t[2];
2545 int memsize = memsize_zz(dc);
2546 int insn_len = 2;
2547
2548 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2549 memsize_char(memsize),
2550 dc->op1,
2551 dc->postinc ? "+]" : "]",
2552 dc->op2);
2553
2554 cris_alu_m_alloc_temps(t);
2555 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2556 cris_cc_mask(dc, 0);
2557 if (dc->op2 == PR_CCS) {
2558 cris_evaluate_flags(dc);
2559 if (dc->tb_flags & U_FLAG) {
2560 /* User space is not allowed to touch all flags. */
2561 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2562 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2563 tcg_gen_or_tl(t[1], t[0], t[1]);
2564 }
2565 }
2566
2567 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2568
2569 do_postinc(dc, memsize);
2570 cris_alu_m_free_temps(t);
2571 return insn_len;
2572 }
2573
2574 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2575 {
2576 TCGv t0;
2577 int memsize;
2578
2579 memsize = preg_sizes[dc->op2];
2580
2581 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2582 memsize_char(memsize),
2583 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2584
2585 /* prepare store. Address in T0, value in T1. */
2586 if (dc->op2 == PR_CCS) {
2587 cris_evaluate_flags(dc);
2588 }
2589 t0 = tcg_temp_new();
2590 t_gen_mov_TN_preg(t0, dc->op2);
2591 cris_flush_cc_state(dc);
2592 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2593 tcg_temp_free(t0);
2594
2595 cris_cc_mask(dc, 0);
2596 if (dc->postinc) {
2597 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2598 }
2599 return 2;
2600 }
2601
2602 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2603 {
2604 TCGv_i64 tmp[16];
2605 TCGv tmp32;
2606 TCGv addr;
2607 int i;
2608 int nr = dc->op2 + 1;
2609
2610 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2611 dc->postinc ? "+]" : "]", dc->op2);
2612
2613 addr = tcg_temp_new();
2614 /* There are probably better ways of doing this. */
2615 cris_flush_cc_state(dc);
2616 for (i = 0; i < (nr >> 1); i++) {
2617 tmp[i] = tcg_temp_new_i64();
2618 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2619 gen_load64(dc, tmp[i], addr);
2620 }
2621 if (nr & 1) {
2622 tmp32 = tcg_temp_new_i32();
2623 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2624 gen_load(dc, tmp32, addr, 4, 0);
2625 } else {
2626 tmp32 = NULL;
2627 }
2628 tcg_temp_free(addr);
2629
2630 for (i = 0; i < (nr >> 1); i++) {
2631 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]);
2632 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2633 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2634 tcg_temp_free_i64(tmp[i]);
2635 }
2636 if (nr & 1) {
2637 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2638 tcg_temp_free(tmp32);
2639 }
2640
2641 /* writeback the updated pointer value. */
2642 if (dc->postinc) {
2643 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2644 }
2645
2646 /* gen_load might want to evaluate the previous insns flags. */
2647 cris_cc_mask(dc, 0);
2648 return 2;
2649 }
2650
2651 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2652 {
2653 TCGv tmp;
2654 TCGv addr;
2655 int i;
2656
2657 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2658 dc->postinc ? "+]" : "]");
2659
2660 cris_flush_cc_state(dc);
2661
2662 tmp = tcg_temp_new();
2663 addr = tcg_temp_new();
2664 tcg_gen_movi_tl(tmp, 4);
2665 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2666 for (i = 0; i <= dc->op2; i++) {
2667 /* Displace addr. */
2668 /* Perform the store. */
2669 gen_store(dc, addr, cpu_R[i], 4);
2670 tcg_gen_add_tl(addr, addr, tmp);
2671 }
2672 if (dc->postinc) {
2673 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2674 }
2675 cris_cc_mask(dc, 0);
2676 tcg_temp_free(tmp);
2677 tcg_temp_free(addr);
2678 return 2;
2679 }
2680
2681 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2682 {
2683 int memsize;
2684
2685 memsize = memsize_zz(dc);
2686
2687 LOG_DIS("move.%c $r%u, [$r%u]\n",
2688 memsize_char(memsize), dc->op2, dc->op1);
2689
2690 /* prepare store. */
2691 cris_flush_cc_state(dc);
2692 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2693
2694 if (dc->postinc) {
2695 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2696 }
2697 cris_cc_mask(dc, 0);
2698 return 2;
2699 }
2700
2701 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2702 {
2703 LOG_DIS("lapcq %x, $r%u\n",
2704 dc->pc + dc->op1*2, dc->op2);
2705 cris_cc_mask(dc, 0);
2706 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2707 return 2;
2708 }
2709
2710 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2711 {
2712 unsigned int rd;
2713 int32_t imm;
2714 int32_t pc;
2715
2716 rd = dc->op2;
2717
2718 cris_cc_mask(dc, 0);
2719 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2720 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2721
2722 pc = dc->pc;
2723 pc += imm;
2724 tcg_gen_movi_tl(cpu_R[rd], pc);
2725 return 6;
2726 }
2727
2728 /* Jump to special reg. */
2729 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2730 {
2731 LOG_DIS("jump $p%u\n", dc->op2);
2732
2733 if (dc->op2 == PR_CCS) {
2734 cris_evaluate_flags(dc);
2735 }
2736 t_gen_mov_TN_preg(env_btarget, dc->op2);
2737 /* rete will often have low bit set to indicate delayslot. */
2738 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2739 cris_cc_mask(dc, 0);
2740 cris_prepare_jmp(dc, JMP_INDIRECT);
2741 return 2;
2742 }
2743
2744 /* Jump and save. */
2745 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2746 {
2747 TCGv c;
2748 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2749 cris_cc_mask(dc, 0);
2750 /* Store the return address in Pd. */
2751 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2752 if (dc->op2 > 15) {
2753 abort();
2754 }
2755 c = tcg_const_tl(dc->pc + 4);
2756 t_gen_mov_preg_TN(dc, dc->op2, c);
2757 tcg_temp_free(c);
2758
2759 cris_prepare_jmp(dc, JMP_INDIRECT);
2760 return 2;
2761 }
2762
2763 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2764 {
2765 uint32_t imm;
2766 TCGv c;
2767
2768 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2769
2770 LOG_DIS("jas 0x%x\n", imm);
2771 cris_cc_mask(dc, 0);
2772 c = tcg_const_tl(dc->pc + 8);
2773 /* Store the return address in Pd. */
2774 t_gen_mov_preg_TN(dc, dc->op2, c);
2775 tcg_temp_free(c);
2776
2777 dc->jmp_pc = imm;
2778 cris_prepare_jmp(dc, JMP_DIRECT);
2779 return 6;
2780 }
2781
2782 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2783 {
2784 uint32_t imm;
2785 TCGv c;
2786
2787 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2788
2789 LOG_DIS("jasc 0x%x\n", imm);
2790 cris_cc_mask(dc, 0);
2791 c = tcg_const_tl(dc->pc + 8 + 4);
2792 /* Store the return address in Pd. */
2793 t_gen_mov_preg_TN(dc, dc->op2, c);
2794 tcg_temp_free(c);
2795
2796 dc->jmp_pc = imm;
2797 cris_prepare_jmp(dc, JMP_DIRECT);
2798 return 6;
2799 }
2800
2801 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2802 {
2803 TCGv c;
2804 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2805 cris_cc_mask(dc, 0);
2806 /* Store the return address in Pd. */
2807 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2808 c = tcg_const_tl(dc->pc + 4 + 4);
2809 t_gen_mov_preg_TN(dc, dc->op2, c);
2810 tcg_temp_free(c);
2811 cris_prepare_jmp(dc, JMP_INDIRECT);
2812 return 2;
2813 }
2814
2815 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2816 {
2817 int32_t offset;
2818 uint32_t cond = dc->op2;
2819
2820 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2821
2822 LOG_DIS("b%s %d pc=%x dst=%x\n",
2823 cc_name(cond), offset,
2824 dc->pc, dc->pc + offset);
2825
2826 cris_cc_mask(dc, 0);
2827 /* op2 holds the condition-code. */
2828 cris_prepare_cc_branch(dc, offset, cond);
2829 return 4;
2830 }
2831
2832 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2833 {
2834 int32_t simm;
2835 TCGv c;
2836
2837 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2838
2839 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2840 cris_cc_mask(dc, 0);
2841 c = tcg_const_tl(dc->pc + 8);
2842 /* Store the return address in Pd. */
2843 t_gen_mov_preg_TN(dc, dc->op2, c);
2844 tcg_temp_free(c);
2845
2846 dc->jmp_pc = dc->pc + simm;
2847 cris_prepare_jmp(dc, JMP_DIRECT);
2848 return 6;
2849 }
2850
2851 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2852 {
2853 int32_t simm;
2854 TCGv c;
2855 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2856
2857 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2858 cris_cc_mask(dc, 0);
2859 c = tcg_const_tl(dc->pc + 12);
2860 /* Store the return address in Pd. */
2861 t_gen_mov_preg_TN(dc, dc->op2, c);
2862 tcg_temp_free(c);
2863
2864 dc->jmp_pc = dc->pc + simm;
2865 cris_prepare_jmp(dc, JMP_DIRECT);
2866 return 6;
2867 }
2868
2869 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2870 {
2871 cris_cc_mask(dc, 0);
2872
2873 if (dc->op2 == 15) {
2874 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2875 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2876 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2877 t_gen_raise_exception(EXCP_HLT);
2878 dc->base.is_jmp = DISAS_NORETURN;
2879 return 2;
2880 }
2881
2882 switch (dc->op2 & 7) {
2883 case 2:
2884 /* rfe. */
2885 LOG_DIS("rfe\n");
2886 cris_evaluate_flags(dc);
2887 gen_helper_rfe(cpu_env);
2888 dc->base.is_jmp = DISAS_UPDATE;
2889 dc->cpustate_changed = true;
2890 break;
2891 case 5:
2892 /* rfn. */
2893 LOG_DIS("rfn\n");
2894 cris_evaluate_flags(dc);
2895 gen_helper_rfn(cpu_env);
2896 dc->base.is_jmp = DISAS_UPDATE;
2897 dc->cpustate_changed = true;
2898 break;
2899 case 6:
2900 LOG_DIS("break %d\n", dc->op1);
2901 cris_evaluate_flags(dc);
2902 /* break. */
2903 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2904
2905 /* Breaks start at 16 in the exception vector. */
2906 t_gen_movi_env_TN(trap_vector, dc->op1 + 16);
2907 t_gen_raise_exception(EXCP_BREAK);
2908 dc->base.is_jmp = DISAS_NORETURN;
2909 break;
2910 default:
2911 printf("op2=%x\n", dc->op2);
2912 BUG();
2913 break;
2914
2915 }
2916 return 2;
2917 }
2918
2919 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2920 {
2921 return 2;
2922 }
2923
2924 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2925 {
2926 return 2;
2927 }
2928
2929 static int dec_null(CPUCRISState *env, DisasContext *dc)
2930 {
2931 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2932 dc->pc, dc->opcode, dc->op1, dc->op2);
2933 fflush(NULL);
2934 BUG();
2935 return 2;
2936 }
2937
2938 static const struct decoder_info {
2939 struct {
2940 uint32_t bits;
2941 uint32_t mask;
2942 };
2943 int (*dec)(CPUCRISState *env, DisasContext *dc);
2944 } decinfo[] = {
2945 /* Order matters here. */
2946 {DEC_MOVEQ, dec_moveq},
2947 {DEC_BTSTQ, dec_btstq},
2948 {DEC_CMPQ, dec_cmpq},
2949 {DEC_ADDOQ, dec_addoq},
2950 {DEC_ADDQ, dec_addq},
2951 {DEC_SUBQ, dec_subq},
2952 {DEC_ANDQ, dec_andq},
2953 {DEC_ORQ, dec_orq},
2954 {DEC_ASRQ, dec_asrq},
2955 {DEC_LSLQ, dec_lslq},
2956 {DEC_LSRQ, dec_lsrq},
2957 {DEC_BCCQ, dec_bccq},
2958
2959 {DEC_BCC_IM, dec_bcc_im},
2960 {DEC_JAS_IM, dec_jas_im},
2961 {DEC_JAS_R, dec_jas_r},
2962 {DEC_JASC_IM, dec_jasc_im},
2963 {DEC_JASC_R, dec_jasc_r},
2964 {DEC_BAS_IM, dec_bas_im},
2965 {DEC_BASC_IM, dec_basc_im},
2966 {DEC_JUMP_P, dec_jump_p},
2967 {DEC_LAPC_IM, dec_lapc_im},
2968 {DEC_LAPCQ, dec_lapcq},
2969
2970 {DEC_RFE_ETC, dec_rfe_etc},
2971 {DEC_ADDC_MR, dec_addc_mr},
2972
2973 {DEC_MOVE_MP, dec_move_mp},
2974 {DEC_MOVE_PM, dec_move_pm},
2975 {DEC_MOVEM_MR, dec_movem_mr},
2976 {DEC_MOVEM_RM, dec_movem_rm},
2977 {DEC_MOVE_PR, dec_move_pr},
2978 {DEC_SCC_R, dec_scc_r},
2979 {DEC_SETF, dec_setclrf},
2980 {DEC_CLEARF, dec_setclrf},
2981
2982 {DEC_MOVE_SR, dec_move_sr},
2983 {DEC_MOVE_RP, dec_move_rp},
2984 {DEC_SWAP_R, dec_swap_r},
2985 {DEC_ABS_R, dec_abs_r},
2986 {DEC_LZ_R, dec_lz_r},
2987 {DEC_MOVE_RS, dec_move_rs},
2988 {DEC_BTST_R, dec_btst_r},
2989 {DEC_ADDC_R, dec_addc_r},
2990
2991 {DEC_DSTEP_R, dec_dstep_r},
2992 {DEC_XOR_R, dec_xor_r},
2993 {DEC_MCP_R, dec_mcp_r},
2994 {DEC_CMP_R, dec_cmp_r},
2995
2996 {DEC_ADDI_R, dec_addi_r},
2997 {DEC_ADDI_ACR, dec_addi_acr},
2998
2999 {DEC_ADD_R, dec_add_r},
3000 {DEC_SUB_R, dec_sub_r},
3001
3002 {DEC_ADDU_R, dec_addu_r},
3003 {DEC_ADDS_R, dec_adds_r},
3004 {DEC_SUBU_R, dec_subu_r},
3005 {DEC_SUBS_R, dec_subs_r},
3006 {DEC_LSL_R, dec_lsl_r},
3007
3008 {DEC_AND_R, dec_and_r},
3009 {DEC_OR_R, dec_or_r},
3010 {DEC_BOUND_R, dec_bound_r},
3011 {DEC_ASR_R, dec_asr_r},
3012 {DEC_LSR_R, dec_lsr_r},
3013
3014 {DEC_MOVU_R, dec_movu_r},
3015 {DEC_MOVS_R, dec_movs_r},
3016 {DEC_NEG_R, dec_neg_r},
3017 {DEC_MOVE_R, dec_move_r},
3018
3019 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3020 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3021
3022 {DEC_MULS_R, dec_muls_r},
3023 {DEC_MULU_R, dec_mulu_r},
3024
3025 {DEC_ADDU_M, dec_addu_m},
3026 {DEC_ADDS_M, dec_adds_m},
3027 {DEC_SUBU_M, dec_subu_m},
3028 {DEC_SUBS_M, dec_subs_m},
3029
3030 {DEC_CMPU_M, dec_cmpu_m},
3031 {DEC_CMPS_M, dec_cmps_m},
3032 {DEC_MOVU_M, dec_movu_m},
3033 {DEC_MOVS_M, dec_movs_m},
3034
3035 {DEC_CMP_M, dec_cmp_m},
3036 {DEC_ADDO_M, dec_addo_m},
3037 {DEC_BOUND_M, dec_bound_m},
3038 {DEC_ADD_M, dec_add_m},
3039 {DEC_SUB_M, dec_sub_m},
3040 {DEC_AND_M, dec_and_m},
3041 {DEC_OR_M, dec_or_m},
3042 {DEC_MOVE_RM, dec_move_rm},
3043 {DEC_TEST_M, dec_test_m},
3044 {DEC_MOVE_MR, dec_move_mr},
3045
3046 {{0, 0}, dec_null}
3047 };
3048
3049 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
3050 {
3051 int insn_len = 2;
3052 int i;
3053
3054 /* Load a halfword onto the instruction register. */
3055 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3056
3057 /* Now decode it. */
3058 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3059 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3060 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3061 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3062 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3063 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3064
3065 /* Large switch for all insns. */
3066 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3067 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3068 insn_len = decinfo[i].dec(env, dc);
3069 break;
3070 }
3071 }
3072
3073 #if !defined(CONFIG_USER_ONLY)
3074 /* Single-stepping ? */
3075 if (dc->tb_flags & S_FLAG) {
3076 TCGLabel *l1 = gen_new_label();
3077 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3078 /* We treat SPC as a break with an odd trap vector. */
3079 cris_evaluate_flags(dc);
3080 t_gen_movi_env_TN(trap_vector, 3);
3081 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3082 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3083 t_gen_raise_exception(EXCP_BREAK);
3084 gen_set_label(l1);
3085 }
3086 #endif
3087 return insn_len;
3088 }
3089
3090 #include "translate_v10.c.inc"
3091
3092 /*
3093 * Delay slots on QEMU/CRIS.
3094 *
3095 * If an exception hits on a delayslot, the core will let ERP (the Exception
3096 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3097 * to give SW a hint that the exception actually hit on the dslot.
3098 *
3099 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3100 * the core and any jmp to an odd addresses will mask off that lsb. It is
3101 * simply there to let sw know there was an exception on a dslot.
3102 *
3103 * When the software returns from an exception, the branch will re-execute.
3104 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3105 * and the branch and delayslot don't share pages.
3106 *
3107 * The TB contaning the branch insn will set up env->btarget and evaluate
3108 * env->btaken. When the translation loop exits we will note that the branch
3109 * sequence is broken and let env->dslot be the size of the branch insn (those
3110 * vary in length).
3111 *
3112 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3113 * set). It will also expect to have env->dslot setup with the size of the
3114 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3115 * will execute the dslot and take the branch, either to btarget or just one
3116 * insn ahead.
3117 *
3118 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3119 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3120 * branch and set lsb). Then env->dslot gets cleared so that the exception
3121 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3122 * masked off and we will reexecute the branch insn.
3123 *
3124 */
3125
3126 static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
3127 {
3128 DisasContext *dc = container_of(dcbase, DisasContext, base);
3129 CPUCRISState *env = cs->env_ptr;
3130 uint32_t tb_flags = dc->base.tb->flags;
3131 uint32_t pc_start;
3132
3133 if (env->pregs[PR_VR] == 32) {
3134 dc->decoder = crisv32_decoder;
3135 dc->clear_locked_irq = 0;
3136 } else {
3137 dc->decoder = crisv10_decoder;
3138 dc->clear_locked_irq = 1;
3139 }
3140
3141 /*
3142 * Odd PC indicates that branch is rexecuting due to exception in the
3143 * delayslot, like in real hw.
3144 */
3145 pc_start = dc->base.pc_first & ~1;
3146 dc->base.pc_first = pc_start;
3147 dc->base.pc_next = pc_start;
3148
3149 dc->cpu = env_archcpu(env);
3150 dc->ppc = pc_start;
3151 dc->pc = pc_start;
3152 dc->flags_uptodate = 1;
3153 dc->flagx_known = 1;
3154 dc->flags_x = tb_flags & X_FLAG;
3155 dc->cc_x_uptodate = 0;
3156 dc->cc_mask = 0;
3157 dc->update_cc = 0;
3158 dc->clear_prefix = 0;
3159 dc->cpustate_changed = 0;
3160
3161 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3162 dc->cc_size_uptodate = -1;
3163
3164 /* Decode TB flags. */
3165 dc->tb_flags = tb_flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG | PFIX_FLAG);
3166 dc->delayed_branch = !!(tb_flags & 7);
3167 if (dc->delayed_branch) {
3168 dc->jmp = JMP_INDIRECT;
3169 } else {
3170 dc->jmp = JMP_NOJMP;
3171 }
3172 }
3173
3174 static void cris_tr_tb_start(DisasContextBase *db, CPUState *cpu)
3175 {
3176 }
3177
3178 static void cris_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
3179 {
3180 DisasContext *dc = container_of(dcbase, DisasContext, base);
3181
3182 tcg_gen_insn_start(dc->delayed_branch == 1 ? dc->ppc | 1 : dc->pc);
3183 }
3184
3185 static bool cris_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
3186 const CPUBreakpoint *bp)
3187 {
3188 DisasContext *dc = container_of(dcbase, DisasContext, base);
3189
3190 cris_evaluate_flags(dc);
3191 tcg_gen_movi_tl(env_pc, dc->pc);
3192 t_gen_raise_exception(EXCP_DEBUG);
3193 dc->base.is_jmp = DISAS_NORETURN;
3194 /*
3195 * The address covered by the breakpoint must be included in
3196 * [tb->pc, tb->pc + tb->size) in order to for it to be
3197 * properly cleared -- thus we increment the PC here so that
3198 * the logic setting tb->size below does the right thing.
3199 */
3200 dc->pc += 2;
3201 return true;
3202 }
3203
3204 static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
3205 {
3206 DisasContext *dc = container_of(dcbase, DisasContext, base);
3207 CPUCRISState *env = cs->env_ptr;
3208 unsigned int insn_len;
3209
3210 /* Pretty disas. */
3211 LOG_DIS("%8.8x:\t", dc->pc);
3212
3213 dc->clear_x = 1;
3214
3215 insn_len = dc->decoder(env, dc);
3216 dc->ppc = dc->pc;
3217 dc->pc += insn_len;
3218 dc->base.pc_next += insn_len;
3219
3220 if (dc->base.is_jmp == DISAS_NORETURN) {
3221 return;
3222 }
3223
3224 if (dc->clear_x) {
3225 cris_clear_x_flag(dc);
3226 }
3227
3228 /* Fold unhandled changes to X_FLAG into cpustate_changed. */
3229 dc->cpustate_changed |= !dc->flagx_known;
3230 dc->cpustate_changed |= dc->flags_x != (dc->base.tb->flags & X_FLAG);
3231
3232 /*
3233 * Check for delayed branches here. If we do it before
3234 * actually generating any host code, the simulator will just
3235 * loop doing nothing for on this program location.
3236 */
3237 if (dc->delayed_branch && --dc->delayed_branch == 0) {
3238 if (dc->base.tb->flags & 7) {
3239 t_gen_movi_env_TN(dslot, 0);
3240 }
3241
3242 if (dc->cpustate_changed) {
3243 cris_store_direct_jmp(dc);
3244 }
3245
3246 if (dc->clear_locked_irq) {
3247 dc->clear_locked_irq = 0;
3248 t_gen_movi_env_TN(locked_irq, 0);
3249 }
3250
3251 if (dc->jmp == JMP_DIRECT_CC) {
3252 TCGLabel *l1 = gen_new_label();
3253 cris_evaluate_flags(dc);
3254
3255 /* Conditional jmp. */
3256 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
3257 gen_goto_tb(dc, 1, dc->jmp_pc);
3258 gen_set_label(l1);
3259 gen_goto_tb(dc, 0, dc->pc);
3260 dc->base.is_jmp = DISAS_NORETURN;
3261 dc->jmp = JMP_NOJMP;
3262 } else if (dc->jmp == JMP_DIRECT) {
3263 cris_evaluate_flags(dc);
3264 gen_goto_tb(dc, 0, dc->jmp_pc);
3265 dc->base.is_jmp = DISAS_NORETURN;
3266 dc->jmp = JMP_NOJMP;
3267 } else {
3268 TCGv c = tcg_const_tl(dc->pc);
3269 t_gen_cc_jmp(env_btarget, c);
3270 tcg_temp_free(c);
3271 dc->base.is_jmp = DISAS_JUMP;
3272 }
3273 }
3274
3275 /* Force an update if the per-tb cpu state has changed. */
3276 if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) {
3277 dc->base.is_jmp = DISAS_UPDATE_NEXT;
3278 return;
3279 }
3280
3281 /*
3282 * FIXME: Only the first insn in the TB should cross a page boundary.
3283 * If we can detect the length of the next insn easily, we should.
3284 * In the meantime, simply stop when we do cross.
3285 */
3286 if (dc->base.is_jmp == DISAS_NEXT
3287 && ((dc->pc ^ dc->base.pc_first) & TARGET_PAGE_MASK) != 0) {
3288 dc->base.is_jmp = DISAS_TOO_MANY;
3289 }
3290 }
3291
3292 static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
3293 {
3294 DisasContext *dc = container_of(dcbase, DisasContext, base);
3295 DisasJumpType is_jmp = dc->base.is_jmp;
3296 target_ulong npc = dc->pc;
3297
3298 if (is_jmp == DISAS_NORETURN) {
3299 /* If we have a broken branch+delayslot sequence, it's too late. */
3300 assert(dc->delayed_branch != 1);
3301 return;
3302 }
3303
3304 if (dc->clear_locked_irq) {
3305 t_gen_movi_env_TN(locked_irq, 0);
3306 }
3307
3308 /* Broken branch+delayslot sequence. */
3309 if (dc->delayed_branch == 1) {
3310 /* Set env->dslot to the size of the branch insn. */
3311 t_gen_movi_env_TN(dslot, dc->pc - dc->ppc);
3312 cris_store_direct_jmp(dc);
3313 }
3314
3315 cris_evaluate_flags(dc);
3316
3317 if (unlikely(dc->base.singlestep_enabled)) {
3318 switch (is_jmp) {
3319 case DISAS_TOO_MANY:
3320 case DISAS_UPDATE_NEXT:
3321 tcg_gen_movi_tl(env_pc, npc);
3322 /* fall through */
3323 case DISAS_JUMP:
3324 case DISAS_UPDATE:
3325 t_gen_raise_exception(EXCP_DEBUG);
3326 return;
3327 default:
3328 break;
3329 }
3330 g_assert_not_reached();
3331 }
3332
3333 switch (is_jmp) {
3334 case DISAS_TOO_MANY:
3335 gen_goto_tb(dc, 0, npc);
3336 break;
3337 case DISAS_UPDATE_NEXT:
3338 tcg_gen_movi_tl(env_pc, npc);
3339 /* fall through */
3340 case DISAS_JUMP:
3341 case DISAS_UPDATE:
3342 /* Indicate that interupts must be re-evaluated before the next TB. */
3343 tcg_gen_exit_tb(NULL, 0);
3344 break;
3345 default:
3346 g_assert_not_reached();
3347 }
3348 }
3349
3350 static void cris_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
3351 {
3352 if (!DISAS_CRIS) {
3353 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
3354 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
3355 }
3356 }
3357
3358 static const TranslatorOps cris_tr_ops = {
3359 .init_disas_context = cris_tr_init_disas_context,
3360 .tb_start = cris_tr_tb_start,
3361 .insn_start = cris_tr_insn_start,
3362 .breakpoint_check = cris_tr_breakpoint_check,
3363 .translate_insn = cris_tr_translate_insn,
3364 .tb_stop = cris_tr_tb_stop,
3365 .disas_log = cris_tr_disas_log,
3366 };
3367
3368 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
3369 {
3370 DisasContext dc;
3371 translator_loop(&cris_tr_ops, &dc.base, cs, tb, max_insns);
3372 }
3373
3374 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags)
3375 {
3376 CRISCPU *cpu = CRIS_CPU(cs);
3377 CPUCRISState *env = &cpu->env;
3378 const char * const *regnames;
3379 const char * const *pregnames;
3380 int i;
3381
3382 if (!env) {
3383 return;
3384 }
3385 if (env->pregs[PR_VR] < 32) {
3386 pregnames = pregnames_v10;
3387 regnames = regnames_v10;
3388 } else {
3389 pregnames = pregnames_v32;
3390 regnames = regnames_v32;
3391 }
3392
3393 qemu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3394 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3395 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3396 env->cc_op,
3397 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3398
3399
3400 for (i = 0; i < 16; i++) {
3401 qemu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3402 if ((i + 1) % 4 == 0) {
3403 qemu_fprintf(f, "\n");
3404 }
3405 }
3406 qemu_fprintf(f, "\nspecial regs:\n");
3407 for (i = 0; i < 16; i++) {
3408 qemu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3409 if ((i + 1) % 4 == 0) {
3410 qemu_fprintf(f, "\n");
3411 }
3412 }
3413 if (env->pregs[PR_VR] >= 32) {
3414 uint32_t srs = env->pregs[PR_SRS];
3415 qemu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3416 if (srs < ARRAY_SIZE(env->sregs)) {
3417 for (i = 0; i < 16; i++) {
3418 qemu_fprintf(f, "s%2.2d=%8.8x ",
3419 i, env->sregs[srs][i]);
3420 if ((i + 1) % 4 == 0) {
3421 qemu_fprintf(f, "\n");
3422 }
3423 }
3424 }
3425 }
3426 qemu_fprintf(f, "\n\n");
3427
3428 }
3429
3430 void cris_initialize_tcg(void)
3431 {
3432 int i;
3433
3434 cc_x = tcg_global_mem_new(cpu_env,
3435 offsetof(CPUCRISState, cc_x), "cc_x");
3436 cc_src = tcg_global_mem_new(cpu_env,
3437 offsetof(CPUCRISState, cc_src), "cc_src");
3438 cc_dest = tcg_global_mem_new(cpu_env,
3439 offsetof(CPUCRISState, cc_dest),
3440 "cc_dest");
3441 cc_result = tcg_global_mem_new(cpu_env,
3442 offsetof(CPUCRISState, cc_result),
3443 "cc_result");
3444 cc_op = tcg_global_mem_new(cpu_env,
3445 offsetof(CPUCRISState, cc_op), "cc_op");
3446 cc_size = tcg_global_mem_new(cpu_env,
3447 offsetof(CPUCRISState, cc_size),
3448 "cc_size");
3449 cc_mask = tcg_global_mem_new(cpu_env,
3450 offsetof(CPUCRISState, cc_mask),
3451 "cc_mask");
3452
3453 env_pc = tcg_global_mem_new(cpu_env,
3454 offsetof(CPUCRISState, pc),
3455 "pc");
3456 env_btarget = tcg_global_mem_new(cpu_env,
3457 offsetof(CPUCRISState, btarget),
3458 "btarget");
3459 env_btaken = tcg_global_mem_new(cpu_env,
3460 offsetof(CPUCRISState, btaken),
3461 "btaken");
3462 for (i = 0; i < 16; i++) {
3463 cpu_R[i] = tcg_global_mem_new(cpu_env,
3464 offsetof(CPUCRISState, regs[i]),
3465 regnames_v32[i]);
3466 }
3467 for (i = 0; i < 16; i++) {
3468 cpu_PR[i] = tcg_global_mem_new(cpu_env,
3469 offsetof(CPUCRISState, pregs[i]),
3470 pregnames_v32[i]);
3471 }
3472 }
3473
3474 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb,
3475 target_ulong *data)
3476 {
3477 env->pc = data[0];
3478 }
AR7 emulation for QEMU