hw/char/cadence_uart.c

   1 /*
   2  * Device model for Cadence UART
   3  *
   4  * Copyright (c) 2010 Xilinx Inc.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
   6  * Copyright (c) 2012 PetaLogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *            M.Habib
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "hw/sysbus.h"
  21 #include "sysemu/char.h"
  22 #include "qemu/timer.h"
  23 #include "qemu/log.h"
  24 #include "hw/char/cadence_uart.h"
  25
  26 #ifdef CADENCE_UART_ERR_DEBUG
  27 #define DB_PRINT(...) do { \
  28     fprintf(stderr,  ": %s: ", __func__); \
  29     fprintf(stderr, ## __VA_ARGS__); \
  30     } while (0);
  31 #else
  32     #define DB_PRINT(...)
  33 #endif
  34
  35 #define UART_SR_INTR_RTRIG     0x00000001
  36 #define UART_SR_INTR_REMPTY    0x00000002
  37 #define UART_SR_INTR_RFUL      0x00000004
  38 #define UART_SR_INTR_TEMPTY    0x00000008
  39 #define UART_SR_INTR_TFUL      0x00000010
  40 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
  41 #define UART_SR_TTRIG          0x00002000
  42 #define UART_INTR_TTRIG        0x00000400
  43 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
  44  * SR, then the same bit in CISR is set high too */
  45 #define UART_SR_TO_CISR_MASK   0x0000001F
  46
  47 #define UART_INTR_ROVR         0x00000020
  48 #define UART_INTR_FRAME        0x00000040
  49 #define UART_INTR_PARE         0x00000080
  50 #define UART_INTR_TIMEOUT      0x00000100
  51 #define UART_INTR_DMSI         0x00000200
  52 #define UART_INTR_TOVR         0x00001000
  53
  54 #define UART_SR_RACTIVE    0x00000400
  55 #define UART_SR_TACTIVE    0x00000800
  56 #define UART_SR_FDELT      0x00001000
  57
  58 #define UART_CR_RXRST       0x00000001
  59 #define UART_CR_TXRST       0x00000002
  60 #define UART_CR_RX_EN       0x00000004
  61 #define UART_CR_RX_DIS      0x00000008
  62 #define UART_CR_TX_EN       0x00000010
  63 #define UART_CR_TX_DIS      0x00000020
  64 #define UART_CR_RST_TO      0x00000040
  65 #define UART_CR_STARTBRK    0x00000080
  66 #define UART_CR_STOPBRK     0x00000100
  67
  68 #define UART_MR_CLKS            0x00000001
  69 #define UART_MR_CHRL            0x00000006
  70 #define UART_MR_CHRL_SH         1
  71 #define UART_MR_PAR             0x00000038
  72 #define UART_MR_PAR_SH          3
  73 #define UART_MR_NBSTOP          0x000000C0
  74 #define UART_MR_NBSTOP_SH       6
  75 #define UART_MR_CHMODE          0x00000300
  76 #define UART_MR_CHMODE_SH       8
  77 #define UART_MR_UCLKEN          0x00000400
  78 #define UART_MR_IRMODE          0x00000800
  79
  80 #define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
  81 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
  82 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
  83 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
  84 #define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
  85 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
  86 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
  87 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
  88 #define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
  89 #define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
  90
  91 #define UART_INPUT_CLK         50000000
  92
  93 #define R_CR       (0x00/4)
  94 #define R_MR       (0x04/4)
  95 #define R_IER      (0x08/4)
  96 #define R_IDR      (0x0C/4)
  97 #define R_IMR      (0x10/4)
  98 #define R_CISR     (0x14/4)
  99 #define R_BRGR     (0x18/4)
 100 #define R_RTOR     (0x1C/4)
 101 #define R_RTRIG    (0x20/4)
 102 #define R_MCR      (0x24/4)
 103 #define R_MSR      (0x28/4)
 104 #define R_SR       (0x2C/4)
 105 #define R_TX_RX    (0x30/4)
 106 #define R_BDIV     (0x34/4)
 107 #define R_FDEL     (0x38/4)
 108 #define R_PMIN     (0x3C/4)
 109 #define R_PWID     (0x40/4)
 110 #define R_TTRIG    (0x44/4)
 111
 112
 113 static void uart_update_status(CadenceUARTState *s)
 114 {
 115     s->r[R_SR] = 0;
 116
 117     s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
 118                                                            : 0;
 119     s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
 120     s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
 121
 122     s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
 123                                                            : 0;
 124     s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
 125     s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
 126
 127     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
 128     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
 129     qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
 130 }
 131
 132 static void fifo_trigger_update(void *opaque)
 133 {
 134     CadenceUARTState *s = opaque;
 135
 136     s->r[R_CISR] |= UART_INTR_TIMEOUT;
 137
 138     uart_update_status(s);
 139 }
 140
 141 static void uart_rx_reset(CadenceUARTState *s)
 142 {
 143     s->rx_wpos = 0;
 144     s->rx_count = 0;
 145     if (s->chr) {
 146         qemu_chr_accept_input(s->chr);
 147     }
 148 }
 149
 150 static void uart_tx_reset(CadenceUARTState *s)
 151 {
 152     s->tx_count = 0;
 153 }
 154
 155 static void uart_send_breaks(CadenceUARTState *s)
 156 {
 157     int break_enabled = 1;
 158
 159     if (s->chr) {
 160         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 161                                    &break_enabled);
 162     }
 163 }
 164
 165 static void uart_parameters_setup(CadenceUARTState *s)
 166 {
 167     QEMUSerialSetParams ssp;
 168     unsigned int baud_rate, packet_size;
 169
 170     baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
 171             UART_INPUT_CLK / 8 : UART_INPUT_CLK;
 172
 173     ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
 174     packet_size = 1;
 175
 176     switch (s->r[R_MR] & UART_MR_PAR) {
 177     case UART_PARITY_EVEN:
 178         ssp.parity = 'E';
 179         packet_size++;
 180         break;
 181     case UART_PARITY_ODD:
 182         ssp.parity = 'O';
 183         packet_size++;
 184         break;
 185     default:
 186         ssp.parity = 'N';
 187         break;
 188     }
 189
 190     switch (s->r[R_MR] & UART_MR_CHRL) {
 191     case UART_DATA_BITS_6:
 192         ssp.data_bits = 6;
 193         break;
 194     case UART_DATA_BITS_7:
 195         ssp.data_bits = 7;
 196         break;
 197     default:
 198         ssp.data_bits = 8;
 199         break;
 200     }
 201
 202     switch (s->r[R_MR] & UART_MR_NBSTOP) {
 203     case UART_STOP_BITS_1:
 204         ssp.stop_bits = 1;
 205         break;
 206     default:
 207         ssp.stop_bits = 2;
 208         break;
 209     }
 210
 211     packet_size += ssp.data_bits + ssp.stop_bits;
 212     s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
 213     if (s->chr) {
 214         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 215     }
 216 }
 217
 218 static int uart_can_receive(void *opaque)
 219 {
 220     CadenceUARTState *s = opaque;
 221     int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
 222     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 223
 224     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 225         ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
 226     }
 227     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 228         ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
 229     }
 230     return ret;
 231 }
 232
 233 static void uart_ctrl_update(CadenceUARTState *s)
 234 {
 235     if (s->r[R_CR] & UART_CR_TXRST) {
 236         uart_tx_reset(s);
 237     }
 238
 239     if (s->r[R_CR] & UART_CR_RXRST) {
 240         uart_rx_reset(s);
 241     }
 242
 243     s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
 244
 245     if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
 246         uart_send_breaks(s);
 247     }
 248 }
 249
 250 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
 251 {
 252     CadenceUARTState *s = opaque;
 253     uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 254     int i;
 255
 256     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 257         return;
 258     }
 259
 260     if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
 261         s->r[R_CISR] |= UART_INTR_ROVR;
 262     } else {
 263         for (i = 0; i < size; i++) {
 264             s->rx_fifo[s->rx_wpos] = buf[i];
 265             s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
 266             s->rx_count++;
 267         }
 268         timer_mod(s->fifo_trigger_handle, new_rx_time +
 269                                                 (s->char_tx_time * 4));
 270     }
 271     uart_update_status(s);
 272 }
 273
 274 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
 275                                   void *opaque)
 276 {
 277     CadenceUARTState *s = opaque;
 278     int ret;
 279
 280     /* instant drain the fifo when there's no back-end */
 281     if (!s->chr) {
 282         s->tx_count = 0;
 283         return FALSE;
 284     }
 285
 286     if (!s->tx_count) {
 287         return FALSE;
 288     }
 289
 290     ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count);
 291     s->tx_count -= ret;
 292     memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
 293
 294     if (s->tx_count) {
 295         int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
 296                                       cadence_uart_xmit, s);
 297         assert(r);
 298     }
 299
 300     uart_update_status(s);
 301     return FALSE;
 302 }
 303
 304 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
 305                                int size)
 306 {
 307     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
 308         return;
 309     }
 310
 311     if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
 312         size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
 313         /*
 314          * This can only be a guest error via a bad tx fifo register push,
 315          * as can_receive() should stop remote loop and echo modes ever getting
 316          * us to here.
 317          */
 318         qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
 319         s->r[R_CISR] |= UART_INTR_ROVR;
 320     }
 321
 322     memcpy(s->tx_fifo + s->tx_count, buf, size);
 323     s->tx_count += size;
 324
 325     cadence_uart_xmit(NULL, G_IO_OUT, s);
 326 }
 327
 328 static void uart_receive(void *opaque, const uint8_t *buf, int size)
 329 {
 330     CadenceUARTState *s = opaque;
 331     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 332
 333     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 334         uart_write_rx_fifo(opaque, buf, size);
 335     }
 336     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 337         uart_write_tx_fifo(s, buf, size);
 338     }
 339 }
 340
 341 static void uart_event(void *opaque, int event)
 342 {
 343     CadenceUARTState *s = opaque;
 344     uint8_t buf = '\0';
 345
 346     if (event == CHR_EVENT_BREAK) {
 347         uart_write_rx_fifo(opaque, &buf, 1);
 348     }
 349
 350     uart_update_status(s);
 351 }
 352
 353 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
 354 {
 355     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 356         return;
 357     }
 358
 359     if (s->rx_count) {
 360         uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
 361                             s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
 362         *c = s->rx_fifo[rx_rpos];
 363         s->rx_count--;
 364
 365         if (s->chr) {
 366             qemu_chr_accept_input(s->chr);
 367         }
 368     } else {
 369         *c = 0;
 370     }
 371
 372     uart_update_status(s);
 373 }
 374
 375 static void uart_write(void *opaque, hwaddr offset,
 376                           uint64_t value, unsigned size)
 377 {
 378     CadenceUARTState *s = opaque;
 379
 380     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
 381     offset >>= 2;
 382     if (offset >= CADENCE_UART_R_MAX) {
 383         return;
 384     }
 385     switch (offset) {
 386     case R_IER: /* ier (wts imr) */
 387         s->r[R_IMR] |= value;
 388         break;
 389     case R_IDR: /* idr (wtc imr) */
 390         s->r[R_IMR] &= ~value;
 391         break;
 392     case R_IMR: /* imr (read only) */
 393         break;
 394     case R_CISR: /* cisr (wtc) */
 395         s->r[R_CISR] &= ~value;
 396         break;
 397     case R_TX_RX: /* UARTDR */
 398         switch (s->r[R_MR] & UART_MR_CHMODE) {
 399         case NORMAL_MODE:
 400             uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 401             break;
 402         case LOCAL_LOOPBACK:
 403             uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
 404             break;
 405         }
 406         break;
 407     default:
 408         s->r[offset] = value;
 409     }
 410
 411     switch (offset) {
 412     case R_CR:
 413         uart_ctrl_update(s);
 414         break;
 415     case R_MR:
 416         uart_parameters_setup(s);
 417         break;
 418     }
 419     uart_update_status(s);
 420 }
 421
 422 static uint64_t uart_read(void *opaque, hwaddr offset,
 423         unsigned size)
 424 {
 425     CadenceUARTState *s = opaque;
 426     uint32_t c = 0;
 427
 428     offset >>= 2;
 429     if (offset >= CADENCE_UART_R_MAX) {
 430         c = 0;
 431     } else if (offset == R_TX_RX) {
 432         uart_read_rx_fifo(s, &c);
 433     } else {
 434        c = s->r[offset];
 435     }
 436
 437     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
 438     return c;
 439 }
 440
 441 static const MemoryRegionOps uart_ops = {
 442     .read = uart_read,
 443     .write = uart_write,
 444     .endianness = DEVICE_NATIVE_ENDIAN,
 445 };
 446
 447 static void cadence_uart_reset(DeviceState *dev)
 448 {
 449     CadenceUARTState *s = CADENCE_UART(dev);
 450
 451     s->r[R_CR] = 0x00000128;
 452     s->r[R_IMR] = 0;
 453     s->r[R_CISR] = 0;
 454     s->r[R_RTRIG] = 0x00000020;
 455     s->r[R_BRGR] = 0x0000000F;
 456     s->r[R_TTRIG] = 0x00000020;
 457
 458     uart_rx_reset(s);
 459     uart_tx_reset(s);
 460
 461     uart_update_status(s);
 462 }
 463
 464 static void cadence_uart_realize(DeviceState *dev, Error **errp)
 465 {
 466     CadenceUARTState *s = CADENCE_UART(dev);
 467
 468     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 469                                           fifo_trigger_update, s);
 470
 471     if (s->chr) {
 472         qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
 473                               uart_event, s);
 474     }
 475 }
 476
 477 static void cadence_uart_init(Object *obj)
 478 {
 479     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 480     CadenceUARTState *s = CADENCE_UART(obj);
 481
 482     memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
 483     sysbus_init_mmio(sbd, &s->iomem);
 484     sysbus_init_irq(sbd, &s->irq);
 485
 486     s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
 487 }
 488
 489 static int cadence_uart_post_load(void *opaque, int version_id)
 490 {
 491     CadenceUARTState *s = opaque;
 492
 493     uart_parameters_setup(s);
 494     uart_update_status(s);
 495     return 0;
 496 }
 497
 498 static const VMStateDescription vmstate_cadence_uart = {
 499     .name = "cadence_uart",
 500     .version_id = 2,
 501     .minimum_version_id = 2,
 502     .post_load = cadence_uart_post_load,
 503     .fields = (VMStateField[]) {
 504         VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
 505         VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
 506                             CADENCE_UART_RX_FIFO_SIZE),
 507         VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
 508                             CADENCE_UART_TX_FIFO_SIZE),
 509         VMSTATE_UINT32(rx_count, CadenceUARTState),
 510         VMSTATE_UINT32(tx_count, CadenceUARTState),
 511         VMSTATE_UINT32(rx_wpos, CadenceUARTState),
 512         VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
 513         VMSTATE_END_OF_LIST()
 514     }
 515 };
 516
 517 static Property cadence_uart_properties[] = {
 518     DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
 519     DEFINE_PROP_END_OF_LIST(),
 520 };
 521
 522 static void cadence_uart_class_init(ObjectClass *klass, void *data)
 523 {
 524     DeviceClass *dc = DEVICE_CLASS(klass);
 525
 526     dc->realize = cadence_uart_realize;
 527     dc->vmsd = &vmstate_cadence_uart;
 528     dc->reset = cadence_uart_reset;
 529     dc->props = cadence_uart_properties;
 530   }
 531
 532 static const TypeInfo cadence_uart_info = {
 533     .name          = TYPE_CADENCE_UART,
 534     .parent        = TYPE_SYS_BUS_DEVICE,
 535     .instance_size = sizeof(CadenceUARTState),
 536     .instance_init = cadence_uart_init,
 537     .class_init    = cadence_uart_class_init,
 538 };
 539
 540 static void cadence_uart_register_types(void)
 541 {
 542     type_register_static(&cadence_uart_info);
 543 }
 544
 545 type_init(cadence_uart_register_types)