2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 /* Defining NDEBUG disables assertions (which makes the code faster). */
23 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
27 #include "qemu-common.h"
28 #include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
29 #include "exec/cpu_ldst.h"
32 /* Marker for missing code. */
35 fprintf(stderr, "TODO %s:%u: %s()\n", \
36 __FILE__, __LINE__, __func__); \
40 #if MAX_OPC_PARAM_IARGS != 5
41 # error Fix needed, number of supported input arguments changed!
43 #if TCG_TARGET_REG_BITS == 32
44 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
45 tcg_target_ulong
, tcg_target_ulong
,
46 tcg_target_ulong
, tcg_target_ulong
,
47 tcg_target_ulong
, tcg_target_ulong
,
48 tcg_target_ulong
, tcg_target_ulong
);
50 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
51 tcg_target_ulong
, tcg_target_ulong
,
55 /* Targets which don't use GETPC also don't need tci_tb_ptr
56 which makes them a little faster. */
61 static tcg_target_ulong tci_reg
[TCG_TARGET_NB_REGS
];
63 static tcg_target_ulong
tci_read_reg(TCGReg index
)
65 assert(index
< ARRAY_SIZE(tci_reg
));
66 return tci_reg
[index
];
69 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
70 static int8_t tci_read_reg8s(TCGReg index
)
72 return (int8_t)tci_read_reg(index
);
76 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
77 static int16_t tci_read_reg16s(TCGReg index
)
79 return (int16_t)tci_read_reg(index
);
83 #if TCG_TARGET_REG_BITS == 64
84 static int32_t tci_read_reg32s(TCGReg index
)
86 return (int32_t)tci_read_reg(index
);
90 static uint8_t tci_read_reg8(TCGReg index
)
92 return (uint8_t)tci_read_reg(index
);
95 static uint16_t tci_read_reg16(TCGReg index
)
97 return (uint16_t)tci_read_reg(index
);
100 static uint32_t tci_read_reg32(TCGReg index
)
102 return (uint32_t)tci_read_reg(index
);
105 #if TCG_TARGET_REG_BITS == 64
106 static uint64_t tci_read_reg64(TCGReg index
)
108 return tci_read_reg(index
);
112 static void tci_write_reg(TCGReg index
, tcg_target_ulong value
)
114 assert(index
< ARRAY_SIZE(tci_reg
));
115 assert(index
!= TCG_AREG0
);
116 assert(index
!= TCG_REG_CALL_STACK
);
117 tci_reg
[index
] = value
;
120 #if TCG_TARGET_REG_BITS == 64
121 static void tci_write_reg32s(TCGReg index
, int32_t value
)
123 tci_write_reg(index
, value
);
127 static void tci_write_reg8(TCGReg index
, uint8_t value
)
129 tci_write_reg(index
, value
);
132 static void tci_write_reg32(TCGReg index
, uint32_t value
)
134 tci_write_reg(index
, value
);
137 #if TCG_TARGET_REG_BITS == 32
138 static void tci_write_reg64(uint32_t high_index
, uint32_t low_index
,
141 tci_write_reg(low_index
, value
);
142 tci_write_reg(high_index
, value
>> 32);
144 #elif TCG_TARGET_REG_BITS == 64
145 static void tci_write_reg64(TCGReg index
, uint64_t value
)
147 tci_write_reg(index
, value
);
151 #if TCG_TARGET_REG_BITS == 32
152 /* Create a 64 bit value from two 32 bit values. */
153 static uint64_t tci_uint64(uint32_t high
, uint32_t low
)
155 return ((uint64_t)high
<< 32) + low
;
159 /* Read constant (native size) from bytecode. */
160 static tcg_target_ulong
tci_read_i(uint8_t **tb_ptr
)
162 tcg_target_ulong value
= *(tcg_target_ulong
*)(*tb_ptr
);
163 *tb_ptr
+= sizeof(value
);
167 /* Read unsigned constant (32 bit) from bytecode. */
168 static uint32_t tci_read_i32(uint8_t **tb_ptr
)
170 uint32_t value
= *(uint32_t *)(*tb_ptr
);
171 *tb_ptr
+= sizeof(value
);
175 /* Read signed constant (32 bit) from bytecode. */
176 static int32_t tci_read_s32(uint8_t **tb_ptr
)
178 int32_t value
= *(int32_t *)(*tb_ptr
);
179 *tb_ptr
+= sizeof(value
);
183 #if TCG_TARGET_REG_BITS == 64
184 /* Read constant (64 bit) from bytecode. */
185 static uint64_t tci_read_i64(uint8_t **tb_ptr
)
187 uint64_t value
= *(uint64_t *)(*tb_ptr
);
188 *tb_ptr
+= sizeof(value
);
193 /* Read indexed register (native size) from bytecode. */
194 static tcg_target_ulong
tci_read_r(uint8_t **tb_ptr
)
196 tcg_target_ulong value
= tci_read_reg(**tb_ptr
);
201 /* Read indexed register (8 bit) from bytecode. */
202 static uint8_t tci_read_r8(uint8_t **tb_ptr
)
204 uint8_t value
= tci_read_reg8(**tb_ptr
);
209 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
210 /* Read indexed register (8 bit signed) from bytecode. */
211 static int8_t tci_read_r8s(uint8_t **tb_ptr
)
213 int8_t value
= tci_read_reg8s(**tb_ptr
);
219 /* Read indexed register (16 bit) from bytecode. */
220 static uint16_t tci_read_r16(uint8_t **tb_ptr
)
222 uint16_t value
= tci_read_reg16(**tb_ptr
);
227 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
228 /* Read indexed register (16 bit signed) from bytecode. */
229 static int16_t tci_read_r16s(uint8_t **tb_ptr
)
231 int16_t value
= tci_read_reg16s(**tb_ptr
);
237 /* Read indexed register (32 bit) from bytecode. */
238 static uint32_t tci_read_r32(uint8_t **tb_ptr
)
240 uint32_t value
= tci_read_reg32(**tb_ptr
);
245 #if TCG_TARGET_REG_BITS == 32
246 /* Read two indexed registers (2 * 32 bit) from bytecode. */
247 static uint64_t tci_read_r64(uint8_t **tb_ptr
)
249 uint32_t low
= tci_read_r32(tb_ptr
);
250 return tci_uint64(tci_read_r32(tb_ptr
), low
);
252 #elif TCG_TARGET_REG_BITS == 64
253 /* Read indexed register (32 bit signed) from bytecode. */
254 static int32_t tci_read_r32s(uint8_t **tb_ptr
)
256 int32_t value
= tci_read_reg32s(**tb_ptr
);
261 /* Read indexed register (64 bit) from bytecode. */
262 static uint64_t tci_read_r64(uint8_t **tb_ptr
)
264 uint64_t value
= tci_read_reg64(**tb_ptr
);
270 /* Read indexed register(s) with target address from bytecode. */
271 static target_ulong
tci_read_ulong(uint8_t **tb_ptr
)
273 target_ulong taddr
= tci_read_r(tb_ptr
);
274 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
275 taddr
+= (uint64_t)tci_read_r(tb_ptr
) << 32;
280 /* Read indexed register or constant (native size) from bytecode. */
281 static tcg_target_ulong
tci_read_ri(uint8_t **tb_ptr
)
283 tcg_target_ulong value
;
286 if (r
== TCG_CONST
) {
287 value
= tci_read_i(tb_ptr
);
289 value
= tci_read_reg(r
);
294 /* Read indexed register or constant (32 bit) from bytecode. */
295 static uint32_t tci_read_ri32(uint8_t **tb_ptr
)
300 if (r
== TCG_CONST
) {
301 value
= tci_read_i32(tb_ptr
);
303 value
= tci_read_reg32(r
);
308 #if TCG_TARGET_REG_BITS == 32
309 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
310 static uint64_t tci_read_ri64(uint8_t **tb_ptr
)
312 uint32_t low
= tci_read_ri32(tb_ptr
);
313 return tci_uint64(tci_read_ri32(tb_ptr
), low
);
315 #elif TCG_TARGET_REG_BITS == 64
316 /* Read indexed register or constant (64 bit) from bytecode. */
317 static uint64_t tci_read_ri64(uint8_t **tb_ptr
)
322 if (r
== TCG_CONST
) {
323 value
= tci_read_i64(tb_ptr
);
325 value
= tci_read_reg64(r
);
331 static tcg_target_ulong
tci_read_label(uint8_t **tb_ptr
)
333 tcg_target_ulong label
= tci_read_i(tb_ptr
);
338 static bool tci_compare32(uint32_t u0
, uint32_t u1
, TCGCond condition
)
380 static bool tci_compare64(uint64_t u0
, uint64_t u1
, TCGCond condition
)
422 #ifdef CONFIG_SOFTMMU
423 # define mmuidx tci_read_i(&tb_ptr)
424 # define qemu_ld_ub \
425 helper_ret_ldub_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
426 # define qemu_ld_leuw \
427 helper_le_lduw_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
428 # define qemu_ld_leul \
429 helper_le_ldul_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
430 # define qemu_ld_leq \
431 helper_le_ldq_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
432 # define qemu_ld_beuw \
433 helper_be_lduw_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
434 # define qemu_ld_beul \
435 helper_be_ldul_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
436 # define qemu_ld_beq \
437 helper_be_ldq_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
438 # define qemu_st_b(X) \
439 helper_ret_stb_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
440 # define qemu_st_lew(X) \
441 helper_le_stw_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
442 # define qemu_st_lel(X) \
443 helper_le_stl_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
444 # define qemu_st_leq(X) \
445 helper_le_stq_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
446 # define qemu_st_bew(X) \
447 helper_be_stw_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
448 # define qemu_st_bel(X) \
449 helper_be_stl_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
450 # define qemu_st_beq(X) \
451 helper_be_stq_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
453 # define qemu_ld_ub ldub_p(g2h(taddr))
454 # define qemu_ld_leuw lduw_le_p(g2h(taddr))
455 # define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
456 # define qemu_ld_leq ldq_le_p(g2h(taddr))
457 # define qemu_ld_beuw lduw_be_p(g2h(taddr))
458 # define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
459 # define qemu_ld_beq ldq_be_p(g2h(taddr))
460 # define qemu_st_b(X) stb_p(g2h(taddr), X)
461 # define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
462 # define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
463 # define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
464 # define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
465 # define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
466 # define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
469 /* Interpret pseudo code in tb. */
470 uintptr_t tcg_qemu_tb_exec(CPUArchState
*env
, uint8_t *tb_ptr
)
472 long tcg_temps
[CPU_TEMP_BUF_NLONGS
];
473 uintptr_t sp_value
= (uintptr_t)(tcg_temps
+ CPU_TEMP_BUF_NLONGS
);
474 uintptr_t next_tb
= 0;
476 tci_reg
[TCG_AREG0
] = (tcg_target_ulong
)env
;
477 tci_reg
[TCG_REG_CALL_STACK
] = sp_value
;
481 TCGOpcode opc
= tb_ptr
[0];
483 uint8_t op_size
= tb_ptr
[1];
484 uint8_t *old_code_ptr
= tb_ptr
;
489 tcg_target_ulong label
;
496 #if TCG_TARGET_REG_BITS == 32
502 tci_tb_ptr
= (uintptr_t)tb_ptr
;
505 /* Skip opcode and size entry. */
516 case INDEX_op_discard
:
519 case INDEX_op_set_label
:
523 t0
= tci_read_ri(&tb_ptr
);
524 #if TCG_TARGET_REG_BITS == 32
525 tmp64
= ((helper_function
)t0
)(tci_read_reg(TCG_REG_R0
),
526 tci_read_reg(TCG_REG_R1
),
527 tci_read_reg(TCG_REG_R2
),
528 tci_read_reg(TCG_REG_R3
),
529 tci_read_reg(TCG_REG_R5
),
530 tci_read_reg(TCG_REG_R6
),
531 tci_read_reg(TCG_REG_R7
),
532 tci_read_reg(TCG_REG_R8
),
533 tci_read_reg(TCG_REG_R9
),
534 tci_read_reg(TCG_REG_R10
));
535 tci_write_reg(TCG_REG_R0
, tmp64
);
536 tci_write_reg(TCG_REG_R1
, tmp64
>> 32);
538 tmp64
= ((helper_function
)t0
)(tci_read_reg(TCG_REG_R0
),
539 tci_read_reg(TCG_REG_R1
),
540 tci_read_reg(TCG_REG_R2
),
541 tci_read_reg(TCG_REG_R3
),
542 tci_read_reg(TCG_REG_R5
));
543 tci_write_reg(TCG_REG_R0
, tmp64
);
547 label
= tci_read_label(&tb_ptr
);
548 assert(tb_ptr
== old_code_ptr
+ op_size
);
549 tb_ptr
= (uint8_t *)label
;
551 case INDEX_op_setcond_i32
:
553 t1
= tci_read_r32(&tb_ptr
);
554 t2
= tci_read_ri32(&tb_ptr
);
555 condition
= *tb_ptr
++;
556 tci_write_reg32(t0
, tci_compare32(t1
, t2
, condition
));
558 #if TCG_TARGET_REG_BITS == 32
559 case INDEX_op_setcond2_i32
:
561 tmp64
= tci_read_r64(&tb_ptr
);
562 v64
= tci_read_ri64(&tb_ptr
);
563 condition
= *tb_ptr
++;
564 tci_write_reg32(t0
, tci_compare64(tmp64
, v64
, condition
));
566 #elif TCG_TARGET_REG_BITS == 64
567 case INDEX_op_setcond_i64
:
569 t1
= tci_read_r64(&tb_ptr
);
570 t2
= tci_read_ri64(&tb_ptr
);
571 condition
= *tb_ptr
++;
572 tci_write_reg64(t0
, tci_compare64(t1
, t2
, condition
));
575 case INDEX_op_mov_i32
:
577 t1
= tci_read_r32(&tb_ptr
);
578 tci_write_reg32(t0
, t1
);
580 case INDEX_op_movi_i32
:
582 t1
= tci_read_i32(&tb_ptr
);
583 tci_write_reg32(t0
, t1
);
586 /* Load/store operations (32 bit). */
588 case INDEX_op_ld8u_i32
:
590 t1
= tci_read_r(&tb_ptr
);
591 t2
= tci_read_s32(&tb_ptr
);
592 tci_write_reg8(t0
, *(uint8_t *)(t1
+ t2
));
594 case INDEX_op_ld8s_i32
:
595 case INDEX_op_ld16u_i32
:
598 case INDEX_op_ld16s_i32
:
601 case INDEX_op_ld_i32
:
603 t1
= tci_read_r(&tb_ptr
);
604 t2
= tci_read_s32(&tb_ptr
);
605 tci_write_reg32(t0
, *(uint32_t *)(t1
+ t2
));
607 case INDEX_op_st8_i32
:
608 t0
= tci_read_r8(&tb_ptr
);
609 t1
= tci_read_r(&tb_ptr
);
610 t2
= tci_read_s32(&tb_ptr
);
611 *(uint8_t *)(t1
+ t2
) = t0
;
613 case INDEX_op_st16_i32
:
614 t0
= tci_read_r16(&tb_ptr
);
615 t1
= tci_read_r(&tb_ptr
);
616 t2
= tci_read_s32(&tb_ptr
);
617 *(uint16_t *)(t1
+ t2
) = t0
;
619 case INDEX_op_st_i32
:
620 t0
= tci_read_r32(&tb_ptr
);
621 t1
= tci_read_r(&tb_ptr
);
622 t2
= tci_read_s32(&tb_ptr
);
623 assert(t1
!= sp_value
|| (int32_t)t2
< 0);
624 *(uint32_t *)(t1
+ t2
) = t0
;
627 /* Arithmetic operations (32 bit). */
629 case INDEX_op_add_i32
:
631 t1
= tci_read_ri32(&tb_ptr
);
632 t2
= tci_read_ri32(&tb_ptr
);
633 tci_write_reg32(t0
, t1
+ t2
);
635 case INDEX_op_sub_i32
:
637 t1
= tci_read_ri32(&tb_ptr
);
638 t2
= tci_read_ri32(&tb_ptr
);
639 tci_write_reg32(t0
, t1
- t2
);
641 case INDEX_op_mul_i32
:
643 t1
= tci_read_ri32(&tb_ptr
);
644 t2
= tci_read_ri32(&tb_ptr
);
645 tci_write_reg32(t0
, t1
* t2
);
647 #if TCG_TARGET_HAS_div_i32
648 case INDEX_op_div_i32
:
650 t1
= tci_read_ri32(&tb_ptr
);
651 t2
= tci_read_ri32(&tb_ptr
);
652 tci_write_reg32(t0
, (int32_t)t1
/ (int32_t)t2
);
654 case INDEX_op_divu_i32
:
656 t1
= tci_read_ri32(&tb_ptr
);
657 t2
= tci_read_ri32(&tb_ptr
);
658 tci_write_reg32(t0
, t1
/ t2
);
660 case INDEX_op_rem_i32
:
662 t1
= tci_read_ri32(&tb_ptr
);
663 t2
= tci_read_ri32(&tb_ptr
);
664 tci_write_reg32(t0
, (int32_t)t1
% (int32_t)t2
);
666 case INDEX_op_remu_i32
:
668 t1
= tci_read_ri32(&tb_ptr
);
669 t2
= tci_read_ri32(&tb_ptr
);
670 tci_write_reg32(t0
, t1
% t2
);
672 #elif TCG_TARGET_HAS_div2_i32
673 case INDEX_op_div2_i32
:
674 case INDEX_op_divu2_i32
:
678 case INDEX_op_and_i32
:
680 t1
= tci_read_ri32(&tb_ptr
);
681 t2
= tci_read_ri32(&tb_ptr
);
682 tci_write_reg32(t0
, t1
& t2
);
684 case INDEX_op_or_i32
:
686 t1
= tci_read_ri32(&tb_ptr
);
687 t2
= tci_read_ri32(&tb_ptr
);
688 tci_write_reg32(t0
, t1
| t2
);
690 case INDEX_op_xor_i32
:
692 t1
= tci_read_ri32(&tb_ptr
);
693 t2
= tci_read_ri32(&tb_ptr
);
694 tci_write_reg32(t0
, t1
^ t2
);
697 /* Shift/rotate operations (32 bit). */
699 case INDEX_op_shl_i32
:
701 t1
= tci_read_ri32(&tb_ptr
);
702 t2
= tci_read_ri32(&tb_ptr
);
703 tci_write_reg32(t0
, t1
<< (t2
& 31));
705 case INDEX_op_shr_i32
:
707 t1
= tci_read_ri32(&tb_ptr
);
708 t2
= tci_read_ri32(&tb_ptr
);
709 tci_write_reg32(t0
, t1
>> (t2
& 31));
711 case INDEX_op_sar_i32
:
713 t1
= tci_read_ri32(&tb_ptr
);
714 t2
= tci_read_ri32(&tb_ptr
);
715 tci_write_reg32(t0
, ((int32_t)t1
>> (t2
& 31)));
717 #if TCG_TARGET_HAS_rot_i32
718 case INDEX_op_rotl_i32
:
720 t1
= tci_read_ri32(&tb_ptr
);
721 t2
= tci_read_ri32(&tb_ptr
);
722 tci_write_reg32(t0
, rol32(t1
, t2
& 31));
724 case INDEX_op_rotr_i32
:
726 t1
= tci_read_ri32(&tb_ptr
);
727 t2
= tci_read_ri32(&tb_ptr
);
728 tci_write_reg32(t0
, ror32(t1
, t2
& 31));
731 #if TCG_TARGET_HAS_deposit_i32
732 case INDEX_op_deposit_i32
:
734 t1
= tci_read_r32(&tb_ptr
);
735 t2
= tci_read_r32(&tb_ptr
);
738 tmp32
= (((1 << tmp8
) - 1) << tmp16
);
739 tci_write_reg32(t0
, (t1
& ~tmp32
) | ((t2
<< tmp16
) & tmp32
));
742 case INDEX_op_brcond_i32
:
743 t0
= tci_read_r32(&tb_ptr
);
744 t1
= tci_read_ri32(&tb_ptr
);
745 condition
= *tb_ptr
++;
746 label
= tci_read_label(&tb_ptr
);
747 if (tci_compare32(t0
, t1
, condition
)) {
748 assert(tb_ptr
== old_code_ptr
+ op_size
);
749 tb_ptr
= (uint8_t *)label
;
753 #if TCG_TARGET_REG_BITS == 32
754 case INDEX_op_add2_i32
:
757 tmp64
= tci_read_r64(&tb_ptr
);
758 tmp64
+= tci_read_r64(&tb_ptr
);
759 tci_write_reg64(t1
, t0
, tmp64
);
761 case INDEX_op_sub2_i32
:
764 tmp64
= tci_read_r64(&tb_ptr
);
765 tmp64
-= tci_read_r64(&tb_ptr
);
766 tci_write_reg64(t1
, t0
, tmp64
);
768 case INDEX_op_brcond2_i32
:
769 tmp64
= tci_read_r64(&tb_ptr
);
770 v64
= tci_read_ri64(&tb_ptr
);
771 condition
= *tb_ptr
++;
772 label
= tci_read_label(&tb_ptr
);
773 if (tci_compare64(tmp64
, v64
, condition
)) {
774 assert(tb_ptr
== old_code_ptr
+ op_size
);
775 tb_ptr
= (uint8_t *)label
;
779 case INDEX_op_mulu2_i32
:
782 t2
= tci_read_r32(&tb_ptr
);
783 tmp64
= tci_read_r32(&tb_ptr
);
784 tci_write_reg64(t1
, t0
, t2
* tmp64
);
786 #endif /* TCG_TARGET_REG_BITS == 32 */
787 #if TCG_TARGET_HAS_ext8s_i32
788 case INDEX_op_ext8s_i32
:
790 t1
= tci_read_r8s(&tb_ptr
);
791 tci_write_reg32(t0
, t1
);
794 #if TCG_TARGET_HAS_ext16s_i32
795 case INDEX_op_ext16s_i32
:
797 t1
= tci_read_r16s(&tb_ptr
);
798 tci_write_reg32(t0
, t1
);
801 #if TCG_TARGET_HAS_ext8u_i32
802 case INDEX_op_ext8u_i32
:
804 t1
= tci_read_r8(&tb_ptr
);
805 tci_write_reg32(t0
, t1
);
808 #if TCG_TARGET_HAS_ext16u_i32
809 case INDEX_op_ext16u_i32
:
811 t1
= tci_read_r16(&tb_ptr
);
812 tci_write_reg32(t0
, t1
);
815 #if TCG_TARGET_HAS_bswap16_i32
816 case INDEX_op_bswap16_i32
:
818 t1
= tci_read_r16(&tb_ptr
);
819 tci_write_reg32(t0
, bswap16(t1
));
822 #if TCG_TARGET_HAS_bswap32_i32
823 case INDEX_op_bswap32_i32
:
825 t1
= tci_read_r32(&tb_ptr
);
826 tci_write_reg32(t0
, bswap32(t1
));
829 #if TCG_TARGET_HAS_not_i32
830 case INDEX_op_not_i32
:
832 t1
= tci_read_r32(&tb_ptr
);
833 tci_write_reg32(t0
, ~t1
);
836 #if TCG_TARGET_HAS_neg_i32
837 case INDEX_op_neg_i32
:
839 t1
= tci_read_r32(&tb_ptr
);
840 tci_write_reg32(t0
, -t1
);
843 #if TCG_TARGET_REG_BITS == 64
844 case INDEX_op_mov_i64
:
846 t1
= tci_read_r64(&tb_ptr
);
847 tci_write_reg64(t0
, t1
);
849 case INDEX_op_movi_i64
:
851 t1
= tci_read_i64(&tb_ptr
);
852 tci_write_reg64(t0
, t1
);
855 /* Load/store operations (64 bit). */
857 case INDEX_op_ld8u_i64
:
859 t1
= tci_read_r(&tb_ptr
);
860 t2
= tci_read_s32(&tb_ptr
);
861 tci_write_reg8(t0
, *(uint8_t *)(t1
+ t2
));
863 case INDEX_op_ld8s_i64
:
864 case INDEX_op_ld16u_i64
:
865 case INDEX_op_ld16s_i64
:
868 case INDEX_op_ld32u_i64
:
870 t1
= tci_read_r(&tb_ptr
);
871 t2
= tci_read_s32(&tb_ptr
);
872 tci_write_reg32(t0
, *(uint32_t *)(t1
+ t2
));
874 case INDEX_op_ld32s_i64
:
876 t1
= tci_read_r(&tb_ptr
);
877 t2
= tci_read_s32(&tb_ptr
);
878 tci_write_reg32s(t0
, *(int32_t *)(t1
+ t2
));
880 case INDEX_op_ld_i64
:
882 t1
= tci_read_r(&tb_ptr
);
883 t2
= tci_read_s32(&tb_ptr
);
884 tci_write_reg64(t0
, *(uint64_t *)(t1
+ t2
));
886 case INDEX_op_st8_i64
:
887 t0
= tci_read_r8(&tb_ptr
);
888 t1
= tci_read_r(&tb_ptr
);
889 t2
= tci_read_s32(&tb_ptr
);
890 *(uint8_t *)(t1
+ t2
) = t0
;
892 case INDEX_op_st16_i64
:
893 t0
= tci_read_r16(&tb_ptr
);
894 t1
= tci_read_r(&tb_ptr
);
895 t2
= tci_read_s32(&tb_ptr
);
896 *(uint16_t *)(t1
+ t2
) = t0
;
898 case INDEX_op_st32_i64
:
899 t0
= tci_read_r32(&tb_ptr
);
900 t1
= tci_read_r(&tb_ptr
);
901 t2
= tci_read_s32(&tb_ptr
);
902 *(uint32_t *)(t1
+ t2
) = t0
;
904 case INDEX_op_st_i64
:
905 t0
= tci_read_r64(&tb_ptr
);
906 t1
= tci_read_r(&tb_ptr
);
907 t2
= tci_read_s32(&tb_ptr
);
908 assert(t1
!= sp_value
|| (int32_t)t2
< 0);
909 *(uint64_t *)(t1
+ t2
) = t0
;
912 /* Arithmetic operations (64 bit). */
914 case INDEX_op_add_i64
:
916 t1
= tci_read_ri64(&tb_ptr
);
917 t2
= tci_read_ri64(&tb_ptr
);
918 tci_write_reg64(t0
, t1
+ t2
);
920 case INDEX_op_sub_i64
:
922 t1
= tci_read_ri64(&tb_ptr
);
923 t2
= tci_read_ri64(&tb_ptr
);
924 tci_write_reg64(t0
, t1
- t2
);
926 case INDEX_op_mul_i64
:
928 t1
= tci_read_ri64(&tb_ptr
);
929 t2
= tci_read_ri64(&tb_ptr
);
930 tci_write_reg64(t0
, t1
* t2
);
932 #if TCG_TARGET_HAS_div_i64
933 case INDEX_op_div_i64
:
934 case INDEX_op_divu_i64
:
935 case INDEX_op_rem_i64
:
936 case INDEX_op_remu_i64
:
939 #elif TCG_TARGET_HAS_div2_i64
940 case INDEX_op_div2_i64
:
941 case INDEX_op_divu2_i64
:
945 case INDEX_op_and_i64
:
947 t1
= tci_read_ri64(&tb_ptr
);
948 t2
= tci_read_ri64(&tb_ptr
);
949 tci_write_reg64(t0
, t1
& t2
);
951 case INDEX_op_or_i64
:
953 t1
= tci_read_ri64(&tb_ptr
);
954 t2
= tci_read_ri64(&tb_ptr
);
955 tci_write_reg64(t0
, t1
| t2
);
957 case INDEX_op_xor_i64
:
959 t1
= tci_read_ri64(&tb_ptr
);
960 t2
= tci_read_ri64(&tb_ptr
);
961 tci_write_reg64(t0
, t1
^ t2
);
964 /* Shift/rotate operations (64 bit). */
966 case INDEX_op_shl_i64
:
968 t1
= tci_read_ri64(&tb_ptr
);
969 t2
= tci_read_ri64(&tb_ptr
);
970 tci_write_reg64(t0
, t1
<< (t2
& 63));
972 case INDEX_op_shr_i64
:
974 t1
= tci_read_ri64(&tb_ptr
);
975 t2
= tci_read_ri64(&tb_ptr
);
976 tci_write_reg64(t0
, t1
>> (t2
& 63));
978 case INDEX_op_sar_i64
:
980 t1
= tci_read_ri64(&tb_ptr
);
981 t2
= tci_read_ri64(&tb_ptr
);
982 tci_write_reg64(t0
, ((int64_t)t1
>> (t2
& 63)));
984 #if TCG_TARGET_HAS_rot_i64
985 case INDEX_op_rotl_i64
:
987 t1
= tci_read_ri64(&tb_ptr
);
988 t2
= tci_read_ri64(&tb_ptr
);
989 tci_write_reg64(t0
, rol64(t1
, t2
& 63));
991 case INDEX_op_rotr_i64
:
993 t1
= tci_read_ri64(&tb_ptr
);
994 t2
= tci_read_ri64(&tb_ptr
);
995 tci_write_reg64(t0
, ror64(t1
, t2
& 63));
998 #if TCG_TARGET_HAS_deposit_i64
999 case INDEX_op_deposit_i64
:
1001 t1
= tci_read_r64(&tb_ptr
);
1002 t2
= tci_read_r64(&tb_ptr
);
1005 tmp64
= (((1ULL << tmp8
) - 1) << tmp16
);
1006 tci_write_reg64(t0
, (t1
& ~tmp64
) | ((t2
<< tmp16
) & tmp64
));
1009 case INDEX_op_brcond_i64
:
1010 t0
= tci_read_r64(&tb_ptr
);
1011 t1
= tci_read_ri64(&tb_ptr
);
1012 condition
= *tb_ptr
++;
1013 label
= tci_read_label(&tb_ptr
);
1014 if (tci_compare64(t0
, t1
, condition
)) {
1015 assert(tb_ptr
== old_code_ptr
+ op_size
);
1016 tb_ptr
= (uint8_t *)label
;
1020 #if TCG_TARGET_HAS_ext8u_i64
1021 case INDEX_op_ext8u_i64
:
1023 t1
= tci_read_r8(&tb_ptr
);
1024 tci_write_reg64(t0
, t1
);
1027 #if TCG_TARGET_HAS_ext8s_i64
1028 case INDEX_op_ext8s_i64
:
1030 t1
= tci_read_r8s(&tb_ptr
);
1031 tci_write_reg64(t0
, t1
);
1034 #if TCG_TARGET_HAS_ext16s_i64
1035 case INDEX_op_ext16s_i64
:
1037 t1
= tci_read_r16s(&tb_ptr
);
1038 tci_write_reg64(t0
, t1
);
1041 #if TCG_TARGET_HAS_ext16u_i64
1042 case INDEX_op_ext16u_i64
:
1044 t1
= tci_read_r16(&tb_ptr
);
1045 tci_write_reg64(t0
, t1
);
1048 #if TCG_TARGET_HAS_ext32s_i64
1049 case INDEX_op_ext32s_i64
:
1051 t1
= tci_read_r32s(&tb_ptr
);
1052 tci_write_reg64(t0
, t1
);
1055 #if TCG_TARGET_HAS_ext32u_i64
1056 case INDEX_op_ext32u_i64
:
1058 t1
= tci_read_r32(&tb_ptr
);
1059 tci_write_reg64(t0
, t1
);
1062 #if TCG_TARGET_HAS_bswap16_i64
1063 case INDEX_op_bswap16_i64
:
1066 t1
= tci_read_r16(&tb_ptr
);
1067 tci_write_reg64(t0
, bswap16(t1
));
1070 #if TCG_TARGET_HAS_bswap32_i64
1071 case INDEX_op_bswap32_i64
:
1073 t1
= tci_read_r32(&tb_ptr
);
1074 tci_write_reg64(t0
, bswap32(t1
));
1077 #if TCG_TARGET_HAS_bswap64_i64
1078 case INDEX_op_bswap64_i64
:
1080 t1
= tci_read_r64(&tb_ptr
);
1081 tci_write_reg64(t0
, bswap64(t1
));
1084 #if TCG_TARGET_HAS_not_i64
1085 case INDEX_op_not_i64
:
1087 t1
= tci_read_r64(&tb_ptr
);
1088 tci_write_reg64(t0
, ~t1
);
1091 #if TCG_TARGET_HAS_neg_i64
1092 case INDEX_op_neg_i64
:
1094 t1
= tci_read_r64(&tb_ptr
);
1095 tci_write_reg64(t0
, -t1
);
1098 #endif /* TCG_TARGET_REG_BITS == 64 */
1100 /* QEMU specific operations. */
1102 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1103 case INDEX_op_debug_insn_start
:
1107 case INDEX_op_debug_insn_start
:
1111 case INDEX_op_exit_tb
:
1112 next_tb
= *(uint64_t *)tb_ptr
;
1115 case INDEX_op_goto_tb
:
1116 t0
= tci_read_i32(&tb_ptr
);
1117 assert(tb_ptr
== old_code_ptr
+ op_size
);
1118 tb_ptr
+= (int32_t)t0
;
1120 case INDEX_op_qemu_ld_i32
:
1122 taddr
= tci_read_ulong(&tb_ptr
);
1123 memop
= tci_read_i(&tb_ptr
);
1129 tmp32
= (int8_t)qemu_ld_ub
;
1132 tmp32
= qemu_ld_leuw
;
1135 tmp32
= (int16_t)qemu_ld_leuw
;
1138 tmp32
= qemu_ld_leul
;
1141 tmp32
= qemu_ld_beuw
;
1144 tmp32
= (int16_t)qemu_ld_beuw
;
1147 tmp32
= qemu_ld_beul
;
1152 tci_write_reg(t0
, tmp32
);
1154 case INDEX_op_qemu_ld_i64
:
1156 if (TCG_TARGET_REG_BITS
== 32) {
1159 taddr
= tci_read_ulong(&tb_ptr
);
1160 memop
= tci_read_i(&tb_ptr
);
1166 tmp64
= (int8_t)qemu_ld_ub
;
1169 tmp64
= qemu_ld_leuw
;
1172 tmp64
= (int16_t)qemu_ld_leuw
;
1175 tmp64
= qemu_ld_leul
;
1178 tmp64
= (int32_t)qemu_ld_leul
;
1181 tmp64
= qemu_ld_leq
;
1184 tmp64
= qemu_ld_beuw
;
1187 tmp64
= (int16_t)qemu_ld_beuw
;
1190 tmp64
= qemu_ld_beul
;
1193 tmp64
= (int32_t)qemu_ld_beul
;
1196 tmp64
= qemu_ld_beq
;
1201 tci_write_reg(t0
, tmp64
);
1202 if (TCG_TARGET_REG_BITS
== 32) {
1203 tci_write_reg(t1
, tmp64
>> 32);
1206 case INDEX_op_qemu_st_i32
:
1207 t0
= tci_read_r(&tb_ptr
);
1208 taddr
= tci_read_ulong(&tb_ptr
);
1209 memop
= tci_read_i(&tb_ptr
);
1230 case INDEX_op_qemu_st_i64
:
1231 tmp64
= tci_read_r64(&tb_ptr
);
1232 taddr
= tci_read_ulong(&tb_ptr
);
1233 memop
= tci_read_i(&tb_ptr
);
1264 assert(tb_ptr
== old_code_ptr
+ op_size
);