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target-i386: Convert 'hv_spinlocks' to static property
[qemu/ar7.git] / target-i386 / cpu.c
blob39c57f89e723fc7cffb0cab0093254666e87beef
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
49 #endif
50
51
52 /* Cache topology CPUID constants: */
53
54 /* CPUID Leaf 2 Descriptors */
55
56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
58 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61 /* CPUID Leaf 4 constants: */
62
63 /* EAX: */
64 #define CPUID_4_TYPE_DCACHE 1
65 #define CPUID_4_TYPE_ICACHE 2
66 #define CPUID_4_TYPE_UNIFIED 3
67
68 #define CPUID_4_LEVEL(l) ((l) << 5)
69
70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71 #define CPUID_4_FULLY_ASSOC (1 << 9)
72
73 /* EDX: */
74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
75 #define CPUID_4_INCLUSIVE (1 << 1)
76 #define CPUID_4_COMPLEX_IDX (1 << 2)
77
78 #define ASSOC_FULL 0xFF
79
80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95 /* Definitions of the hardcoded cache entries we expose: */
96
97 /* L1 data cache: */
98 #define L1D_LINE_SIZE 64
99 #define L1D_ASSOCIATIVITY 8
100 #define L1D_SETS 64
101 #define L1D_PARTITIONS 1
102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105 #define L1D_LINES_PER_TAG 1
106 #define L1D_SIZE_KB_AMD 64
107 #define L1D_ASSOCIATIVITY_AMD 2
108
109 /* L1 instruction cache: */
110 #define L1I_LINE_SIZE 64
111 #define L1I_ASSOCIATIVITY 8
112 #define L1I_SETS 64
113 #define L1I_PARTITIONS 1
114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117 #define L1I_LINES_PER_TAG 1
118 #define L1I_SIZE_KB_AMD 64
119 #define L1I_ASSOCIATIVITY_AMD 2
120
121 /* Level 2 unified cache: */
122 #define L2_LINE_SIZE 64
123 #define L2_ASSOCIATIVITY 16
124 #define L2_SETS 4096
125 #define L2_PARTITIONS 1
126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130 #define L2_LINES_PER_TAG 1
131 #define L2_SIZE_KB_AMD 512
132
133 /* No L3 cache: */
134 #define L3_SIZE_KB 0 /* disabled */
135 #define L3_ASSOCIATIVITY 0 /* disabled */
136 #define L3_LINES_PER_TAG 0 /* disabled */
137 #define L3_LINE_SIZE 0 /* disabled */
138
139 /* TLB definitions: */
140
141 #define L1_DTLB_2M_ASSOC 1
142 #define L1_DTLB_2M_ENTRIES 255
143 #define L1_DTLB_4K_ASSOC 1
144 #define L1_DTLB_4K_ENTRIES 255
145
146 #define L1_ITLB_2M_ASSOC 1
147 #define L1_ITLB_2M_ENTRIES 255
148 #define L1_ITLB_4K_ASSOC 1
149 #define L1_ITLB_4K_ENTRIES 255
150
151 #define L2_DTLB_2M_ASSOC 0 /* disabled */
152 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
153 #define L2_DTLB_4K_ASSOC 4
154 #define L2_DTLB_4K_ENTRIES 512
155
156 #define L2_ITLB_2M_ASSOC 0 /* disabled */
157 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
158 #define L2_ITLB_4K_ASSOC 4
159 #define L2_ITLB_4K_ENTRIES 512
160
161
162
163 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165 {
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173 }
174
175 /* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179 static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188 };
189 static const char *ext_feature_name[] = {
190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
191 "ds_cpl", "vmx", "smx", "est",
192 "tm2", "ssse3", "cid", NULL,
193 "fma", "cx16", "xtpr", "pdcm",
194 NULL, "pcid", "dca", "sse4.1|sse4_1",
195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
196 "tsc-deadline", "aes", "xsave", "osxsave",
197 "avx", "f16c", "rdrand", "hypervisor",
198 };
199 /* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
204 static const char *ext2_feature_name[] = {
205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
212 NULL, "lm|i64", "3dnowext", "3dnow",
213 };
214 static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
217 "3dnowprefetch", "osvw", "ibs", "xop",
218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
222 NULL, NULL, NULL, NULL,
223 };
224
225 static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 };
235
236 static const char *kvm_feature_name[] = {
237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 };
246
247 static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 };
257
258 static const char *cpuid_7_0_ebx_feature_name[] = {
259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263 };
264
265 typedef struct FeatureWordInfo {
266 const char **feat_names;
267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
271 } FeatureWordInfo;
272
273 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
307 },
308 };
309
310 typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315 } X86RegisterInfo32;
316
317 #define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
319 X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328 };
329 #undef REGISTER
330
331 typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334 } ExtSaveArea;
335
336 static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
338 .offset = 0x240, .size = 0x100 },
339 };
340
341 const char *get_register_name_32(unsigned int reg)
342 {
343 if (reg >= CPU_NB_REGS32) {
344 return NULL;
345 }
346 return x86_reg_info_32[reg].name;
347 }
348
349 /* collects per-function cpuid data
350 */
351 typedef struct model_features_t {
352 uint32_t *guest_feat;
353 uint32_t *host_feat;
354 FeatureWord feat_word;
355 } model_features_t;
356
357 int check_cpuid = 0;
358 int enforce_cpuid = 0;
359
360 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
361 (1 << KVM_FEATURE_NOP_IO_DELAY) |
362 (1 << KVM_FEATURE_CLOCKSOURCE2) |
363 (1 << KVM_FEATURE_ASYNC_PF) |
364 (1 << KVM_FEATURE_STEAL_TIME) |
365 (1 << KVM_FEATURE_PV_EOI) |
366 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
367
368 void disable_kvm_pv_eoi(void)
369 {
370 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
371 }
372
373 void host_cpuid(uint32_t function, uint32_t count,
374 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
375 {
376 #if defined(CONFIG_KVM)
377 uint32_t vec[4];
378
379 #ifdef __x86_64__
380 asm volatile("cpuid"
381 : "=a"(vec[0]), "=b"(vec[1]),
382 "=c"(vec[2]), "=d"(vec[3])
383 : "0"(function), "c"(count) : "cc");
384 #else
385 asm volatile("pusha \n\t"
386 "cpuid \n\t"
387 "mov %%eax, 0(%2) \n\t"
388 "mov %%ebx, 4(%2) \n\t"
389 "mov %%ecx, 8(%2) \n\t"
390 "mov %%edx, 12(%2) \n\t"
391 "popa"
392 : : "a"(function), "c"(count), "S"(vec)
393 : "memory", "cc");
394 #endif
395
396 if (eax)
397 *eax = vec[0];
398 if (ebx)
399 *ebx = vec[1];
400 if (ecx)
401 *ecx = vec[2];
402 if (edx)
403 *edx = vec[3];
404 #endif
405 }
406
407 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
408
409 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
410 * a substring. ex if !NULL points to the first char after a substring,
411 * otherwise the string is assumed to sized by a terminating nul.
412 * Return lexical ordering of *s1:*s2.
413 */
414 static int sstrcmp(const char *s1, const char *e1, const char *s2,
415 const char *e2)
416 {
417 for (;;) {
418 if (!*s1 || !*s2 || *s1 != *s2)
419 return (*s1 - *s2);
420 ++s1, ++s2;
421 if (s1 == e1 && s2 == e2)
422 return (0);
423 else if (s1 == e1)
424 return (*s2);
425 else if (s2 == e2)
426 return (*s1);
427 }
428 }
429
430 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
431 * '|' delimited (possibly empty) strings in which case search for a match
432 * within the alternatives proceeds left to right. Return 0 for success,
433 * non-zero otherwise.
434 */
435 static int altcmp(const char *s, const char *e, const char *altstr)
436 {
437 const char *p, *q;
438
439 for (q = p = altstr; ; ) {
440 while (*p && *p != '|')
441 ++p;
442 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
443 return (0);
444 if (!*p)
445 return (1);
446 else
447 q = ++p;
448 }
449 }
450
451 /* search featureset for flag *[s..e), if found set corresponding bit in
452 * *pval and return true, otherwise return false
453 */
454 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
455 const char **featureset)
456 {
457 uint32_t mask;
458 const char **ppc;
459 bool found = false;
460
461 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
462 if (*ppc && !altcmp(s, e, *ppc)) {
463 *pval |= mask;
464 found = true;
465 }
466 }
467 return found;
468 }
469
470 static void add_flagname_to_bitmaps(const char *flagname,
471 FeatureWordArray words)
472 {
473 FeatureWord w;
474 for (w = 0; w < FEATURE_WORDS; w++) {
475 FeatureWordInfo *wi = &feature_word_info[w];
476 if (wi->feat_names &&
477 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
478 break;
479 }
480 }
481 if (w == FEATURE_WORDS) {
482 fprintf(stderr, "CPU feature %s not found\n", flagname);
483 }
484 }
485
486 typedef struct x86_def_t {
487 const char *name;
488 uint32_t level;
489 uint32_t xlevel;
490 uint32_t xlevel2;
491 /* vendor is zero-terminated, 12 character ASCII string */
492 char vendor[CPUID_VENDOR_SZ + 1];
493 int family;
494 int model;
495 int stepping;
496 FeatureWordArray features;
497 char model_id[48];
498 bool cache_info_passthrough;
499 } x86_def_t;
500
501 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
502 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
503 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
504 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
505 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
506 CPUID_PSE36 | CPUID_FXSR)
507 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
508 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
509 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
510 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
511 CPUID_PAE | CPUID_SEP | CPUID_APIC)
512
513 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
514 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
515 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
516 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
517 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
518 /* partly implemented:
519 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
520 CPUID_PSE36 (needed for Solaris) */
521 /* missing:
522 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
523 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
524 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
525 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
526 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
527 /* missing:
528 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
529 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
530 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
531 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
532 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
533 CPUID_EXT_RDRAND */
534 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
535 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
536 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
537 /* missing:
538 CPUID_EXT2_PDPE1GB */
539 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
540 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
541 #define TCG_SVM_FEATURES 0
542 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
543 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
544 /* missing:
545 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
546 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
547 CPUID_7_0_EBX_RDSEED */
548
549 /* built-in CPU model definitions
550 */
551 static x86_def_t builtin_x86_defs[] = {
552 {
553 .name = "qemu64",
554 .level = 4,
555 .vendor = CPUID_VENDOR_AMD,
556 .family = 6,
557 .model = 6,
558 .stepping = 3,
559 .features[FEAT_1_EDX] =
560 PPRO_FEATURES |
561 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
562 CPUID_PSE36,
563 .features[FEAT_1_ECX] =
564 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
565 .features[FEAT_8000_0001_EDX] =
566 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
567 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
568 .features[FEAT_8000_0001_ECX] =
569 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
570 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
571 .xlevel = 0x8000000A,
572 },
573 {
574 .name = "phenom",
575 .level = 5,
576 .vendor = CPUID_VENDOR_AMD,
577 .family = 16,
578 .model = 2,
579 .stepping = 3,
580 .features[FEAT_1_EDX] =
581 PPRO_FEATURES |
582 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
583 CPUID_PSE36 | CPUID_VME | CPUID_HT,
584 .features[FEAT_1_ECX] =
585 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
586 CPUID_EXT_POPCNT,
587 .features[FEAT_8000_0001_EDX] =
588 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
589 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
590 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
591 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
592 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
593 CPUID_EXT3_CR8LEG,
594 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
595 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
596 .features[FEAT_8000_0001_ECX] =
597 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
598 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
599 .features[FEAT_SVM] =
600 CPUID_SVM_NPT | CPUID_SVM_LBRV,
601 .xlevel = 0x8000001A,
602 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
603 },
604 {
605 .name = "core2duo",
606 .level = 10,
607 .vendor = CPUID_VENDOR_INTEL,
608 .family = 6,
609 .model = 15,
610 .stepping = 11,
611 .features[FEAT_1_EDX] =
612 PPRO_FEATURES |
613 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
614 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
615 CPUID_HT | CPUID_TM | CPUID_PBE,
616 .features[FEAT_1_ECX] =
617 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
618 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
619 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
620 .features[FEAT_8000_0001_EDX] =
621 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
622 .features[FEAT_8000_0001_ECX] =
623 CPUID_EXT3_LAHF_LM,
624 .xlevel = 0x80000008,
625 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
626 },
627 {
628 .name = "kvm64",
629 .level = 5,
630 .vendor = CPUID_VENDOR_INTEL,
631 .family = 15,
632 .model = 6,
633 .stepping = 1,
634 /* Missing: CPUID_VME, CPUID_HT */
635 .features[FEAT_1_EDX] =
636 PPRO_FEATURES |
637 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
638 CPUID_PSE36,
639 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
640 .features[FEAT_1_ECX] =
641 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
642 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
643 .features[FEAT_8000_0001_EDX] =
644 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
645 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
646 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
647 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
648 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
649 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
650 .features[FEAT_8000_0001_ECX] =
651 0,
652 .xlevel = 0x80000008,
653 .model_id = "Common KVM processor"
654 },
655 {
656 .name = "qemu32",
657 .level = 4,
658 .vendor = CPUID_VENDOR_INTEL,
659 .family = 6,
660 .model = 6,
661 .stepping = 3,
662 .features[FEAT_1_EDX] =
663 PPRO_FEATURES,
664 .features[FEAT_1_ECX] =
665 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
666 .xlevel = 0x80000004,
667 },
668 {
669 .name = "kvm32",
670 .level = 5,
671 .vendor = CPUID_VENDOR_INTEL,
672 .family = 15,
673 .model = 6,
674 .stepping = 1,
675 .features[FEAT_1_EDX] =
676 PPRO_FEATURES |
677 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
678 .features[FEAT_1_ECX] =
679 CPUID_EXT_SSE3,
680 .features[FEAT_8000_0001_EDX] =
681 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
682 .features[FEAT_8000_0001_ECX] =
683 0,
684 .xlevel = 0x80000008,
685 .model_id = "Common 32-bit KVM processor"
686 },
687 {
688 .name = "coreduo",
689 .level = 10,
690 .vendor = CPUID_VENDOR_INTEL,
691 .family = 6,
692 .model = 14,
693 .stepping = 8,
694 .features[FEAT_1_EDX] =
695 PPRO_FEATURES | CPUID_VME |
696 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
697 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
698 .features[FEAT_1_ECX] =
699 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
700 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
701 .features[FEAT_8000_0001_EDX] =
702 CPUID_EXT2_NX,
703 .xlevel = 0x80000008,
704 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
705 },
706 {
707 .name = "486",
708 .level = 1,
709 .vendor = CPUID_VENDOR_INTEL,
710 .family = 4,
711 .model = 8,
712 .stepping = 0,
713 .features[FEAT_1_EDX] =
714 I486_FEATURES,
715 .xlevel = 0,
716 },
717 {
718 .name = "pentium",
719 .level = 1,
720 .vendor = CPUID_VENDOR_INTEL,
721 .family = 5,
722 .model = 4,
723 .stepping = 3,
724 .features[FEAT_1_EDX] =
725 PENTIUM_FEATURES,
726 .xlevel = 0,
727 },
728 {
729 .name = "pentium2",
730 .level = 2,
731 .vendor = CPUID_VENDOR_INTEL,
732 .family = 6,
733 .model = 5,
734 .stepping = 2,
735 .features[FEAT_1_EDX] =
736 PENTIUM2_FEATURES,
737 .xlevel = 0,
738 },
739 {
740 .name = "pentium3",
741 .level = 2,
742 .vendor = CPUID_VENDOR_INTEL,
743 .family = 6,
744 .model = 7,
745 .stepping = 3,
746 .features[FEAT_1_EDX] =
747 PENTIUM3_FEATURES,
748 .xlevel = 0,
749 },
750 {
751 .name = "athlon",
752 .level = 2,
753 .vendor = CPUID_VENDOR_AMD,
754 .family = 6,
755 .model = 2,
756 .stepping = 3,
757 .features[FEAT_1_EDX] =
758 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
759 CPUID_MCA,
760 .features[FEAT_8000_0001_EDX] =
761 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
762 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
763 .xlevel = 0x80000008,
764 },
765 {
766 .name = "n270",
767 /* original is on level 10 */
768 .level = 5,
769 .vendor = CPUID_VENDOR_INTEL,
770 .family = 6,
771 .model = 28,
772 .stepping = 2,
773 .features[FEAT_1_EDX] =
774 PPRO_FEATURES |
775 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
776 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
777 /* Some CPUs got no CPUID_SEP */
778 .features[FEAT_1_ECX] =
779 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
780 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
781 CPUID_EXT_MOVBE,
782 .features[FEAT_8000_0001_EDX] =
783 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
784 CPUID_EXT2_NX,
785 .features[FEAT_8000_0001_ECX] =
786 CPUID_EXT3_LAHF_LM,
787 .xlevel = 0x8000000A,
788 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
789 },
790 {
791 .name = "Conroe",
792 .level = 4,
793 .vendor = CPUID_VENDOR_INTEL,
794 .family = 6,
795 .model = 15,
796 .stepping = 3,
797 .features[FEAT_1_EDX] =
798 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
799 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
800 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
801 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
802 CPUID_DE | CPUID_FP87,
803 .features[FEAT_1_ECX] =
804 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
805 .features[FEAT_8000_0001_EDX] =
806 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
807 .features[FEAT_8000_0001_ECX] =
808 CPUID_EXT3_LAHF_LM,
809 .xlevel = 0x8000000A,
810 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
811 },
812 {
813 .name = "Penryn",
814 .level = 4,
815 .vendor = CPUID_VENDOR_INTEL,
816 .family = 6,
817 .model = 23,
818 .stepping = 3,
819 .features[FEAT_1_EDX] =
820 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
821 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
822 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
823 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
824 CPUID_DE | CPUID_FP87,
825 .features[FEAT_1_ECX] =
826 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
827 CPUID_EXT_SSE3,
828 .features[FEAT_8000_0001_EDX] =
829 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
830 .features[FEAT_8000_0001_ECX] =
831 CPUID_EXT3_LAHF_LM,
832 .xlevel = 0x8000000A,
833 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
834 },
835 {
836 .name = "Nehalem",
837 .level = 4,
838 .vendor = CPUID_VENDOR_INTEL,
839 .family = 6,
840 .model = 26,
841 .stepping = 3,
842 .features[FEAT_1_EDX] =
843 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
844 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
845 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
846 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
847 CPUID_DE | CPUID_FP87,
848 .features[FEAT_1_ECX] =
849 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
850 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
851 .features[FEAT_8000_0001_EDX] =
852 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
853 .features[FEAT_8000_0001_ECX] =
854 CPUID_EXT3_LAHF_LM,
855 .xlevel = 0x8000000A,
856 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
857 },
858 {
859 .name = "Westmere",
860 .level = 11,
861 .vendor = CPUID_VENDOR_INTEL,
862 .family = 6,
863 .model = 44,
864 .stepping = 1,
865 .features[FEAT_1_EDX] =
866 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
867 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
868 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
869 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
870 CPUID_DE | CPUID_FP87,
871 .features[FEAT_1_ECX] =
872 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
873 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
874 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
875 .features[FEAT_8000_0001_EDX] =
876 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
877 .features[FEAT_8000_0001_ECX] =
878 CPUID_EXT3_LAHF_LM,
879 .xlevel = 0x8000000A,
880 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
881 },
882 {
883 .name = "SandyBridge",
884 .level = 0xd,
885 .vendor = CPUID_VENDOR_INTEL,
886 .family = 6,
887 .model = 42,
888 .stepping = 1,
889 .features[FEAT_1_EDX] =
890 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
891 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
892 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
893 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
894 CPUID_DE | CPUID_FP87,
895 .features[FEAT_1_ECX] =
896 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
897 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
898 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
899 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
900 CPUID_EXT_SSE3,
901 .features[FEAT_8000_0001_EDX] =
902 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
903 CPUID_EXT2_SYSCALL,
904 .features[FEAT_8000_0001_ECX] =
905 CPUID_EXT3_LAHF_LM,
906 .xlevel = 0x8000000A,
907 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
908 },
909 {
910 .name = "Haswell",
911 .level = 0xd,
912 .vendor = CPUID_VENDOR_INTEL,
913 .family = 6,
914 .model = 60,
915 .stepping = 1,
916 .features[FEAT_1_EDX] =
917 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
918 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
919 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
920 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
921 CPUID_DE | CPUID_FP87,
922 .features[FEAT_1_ECX] =
923 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
924 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
925 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
926 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
927 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
928 CPUID_EXT_PCID,
929 .features[FEAT_8000_0001_EDX] =
930 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
931 CPUID_EXT2_SYSCALL,
932 .features[FEAT_8000_0001_ECX] =
933 CPUID_EXT3_LAHF_LM,
934 .features[FEAT_7_0_EBX] =
935 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
936 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
937 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
938 CPUID_7_0_EBX_RTM,
939 .xlevel = 0x8000000A,
940 .model_id = "Intel Core Processor (Haswell)",
941 },
942 {
943 .name = "Opteron_G1",
944 .level = 5,
945 .vendor = CPUID_VENDOR_AMD,
946 .family = 15,
947 .model = 6,
948 .stepping = 1,
949 .features[FEAT_1_EDX] =
950 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
954 CPUID_DE | CPUID_FP87,
955 .features[FEAT_1_ECX] =
956 CPUID_EXT_SSE3,
957 .features[FEAT_8000_0001_EDX] =
958 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
959 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
960 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
961 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
962 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
963 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
964 .xlevel = 0x80000008,
965 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
966 },
967 {
968 .name = "Opteron_G2",
969 .level = 5,
970 .vendor = CPUID_VENDOR_AMD,
971 .family = 15,
972 .model = 6,
973 .stepping = 1,
974 .features[FEAT_1_EDX] =
975 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
976 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
977 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
978 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
979 CPUID_DE | CPUID_FP87,
980 .features[FEAT_1_ECX] =
981 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
982 .features[FEAT_8000_0001_EDX] =
983 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
984 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
985 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
986 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
987 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
988 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
989 CPUID_EXT2_DE | CPUID_EXT2_FPU,
990 .features[FEAT_8000_0001_ECX] =
991 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
992 .xlevel = 0x80000008,
993 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
994 },
995 {
996 .name = "Opteron_G3",
997 .level = 5,
998 .vendor = CPUID_VENDOR_AMD,
999 .family = 15,
1000 .model = 6,
1001 .stepping = 1,
1002 .features[FEAT_1_EDX] =
1003 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1004 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1005 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1006 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1007 CPUID_DE | CPUID_FP87,
1008 .features[FEAT_1_ECX] =
1009 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1010 CPUID_EXT_SSE3,
1011 .features[FEAT_8000_0001_EDX] =
1012 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1013 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1014 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1015 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1016 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1017 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1018 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1019 .features[FEAT_8000_0001_ECX] =
1020 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1021 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1022 .xlevel = 0x80000008,
1023 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1024 },
1025 {
1026 .name = "Opteron_G4",
1027 .level = 0xd,
1028 .vendor = CPUID_VENDOR_AMD,
1029 .family = 21,
1030 .model = 1,
1031 .stepping = 2,
1032 .features[FEAT_1_EDX] =
1033 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1034 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1035 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1036 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1037 CPUID_DE | CPUID_FP87,
1038 .features[FEAT_1_ECX] =
1039 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1040 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1041 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1042 CPUID_EXT_SSE3,
1043 .features[FEAT_8000_0001_EDX] =
1044 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1045 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1046 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1047 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1048 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1049 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1050 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1051 .features[FEAT_8000_0001_ECX] =
1052 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1053 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1054 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1055 CPUID_EXT3_LAHF_LM,
1056 .xlevel = 0x8000001A,
1057 .model_id = "AMD Opteron 62xx class CPU",
1058 },
1059 {
1060 .name = "Opteron_G5",
1061 .level = 0xd,
1062 .vendor = CPUID_VENDOR_AMD,
1063 .family = 21,
1064 .model = 2,
1065 .stepping = 0,
1066 .features[FEAT_1_EDX] =
1067 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1068 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1069 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1070 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1071 CPUID_DE | CPUID_FP87,
1072 .features[FEAT_1_ECX] =
1073 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1074 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1075 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1076 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1077 .features[FEAT_8000_0001_EDX] =
1078 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1079 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1080 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1081 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1082 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1083 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1084 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1085 .features[FEAT_8000_0001_ECX] =
1086 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1087 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1088 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1089 CPUID_EXT3_LAHF_LM,
1090 .xlevel = 0x8000001A,
1091 .model_id = "AMD Opteron 63xx class CPU",
1092 },
1093 };
1094
1095 /**
1096 * x86_cpu_compat_set_features:
1097 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1098 * @w: Identifies the feature word to be changed.
1099 * @feat_add: Feature bits to be added to feature word
1100 * @feat_remove: Feature bits to be removed from feature word
1101 *
1102 * Change CPU model feature bits for compatibility.
1103 *
1104 * This function may be used by machine-type compatibility functions
1105 * to enable or disable feature bits on specific CPU models.
1106 */
1107 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1108 uint32_t feat_add, uint32_t feat_remove)
1109 {
1110 x86_def_t *def;
1111 int i;
1112 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1113 def = &builtin_x86_defs[i];
1114 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1115 def->features[w] |= feat_add;
1116 def->features[w] &= ~feat_remove;
1117 }
1118 }
1119 }
1120
1121 #ifdef CONFIG_KVM
1122 static int cpu_x86_fill_model_id(char *str)
1123 {
1124 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1125 int i;
1126
1127 for (i = 0; i < 3; i++) {
1128 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1129 memcpy(str + i * 16 + 0, &eax, 4);
1130 memcpy(str + i * 16 + 4, &ebx, 4);
1131 memcpy(str + i * 16 + 8, &ecx, 4);
1132 memcpy(str + i * 16 + 12, &edx, 4);
1133 }
1134 return 0;
1135 }
1136 #endif
1137
1138 /* Fill a x86_def_t struct with information about the host CPU, and
1139 * the CPU features supported by the host hardware + host kernel
1140 *
1141 * This function may be called only if KVM is enabled.
1142 */
1143 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
1144 {
1145 #ifdef CONFIG_KVM
1146 KVMState *s = kvm_state;
1147 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1148
1149 assert(kvm_enabled());
1150
1151 x86_cpu_def->name = "host";
1152 x86_cpu_def->cache_info_passthrough = true;
1153 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1154 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1155
1156 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1157 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1158 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1159 x86_cpu_def->stepping = eax & 0x0F;
1160
1161 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1162 x86_cpu_def->features[FEAT_1_EDX] =
1163 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
1164 x86_cpu_def->features[FEAT_1_ECX] =
1165 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
1166
1167 if (x86_cpu_def->level >= 7) {
1168 x86_cpu_def->features[FEAT_7_0_EBX] =
1169 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
1170 } else {
1171 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
1172 }
1173
1174 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1175 x86_cpu_def->features[FEAT_8000_0001_EDX] =
1176 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1177 x86_cpu_def->features[FEAT_8000_0001_ECX] =
1178 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1179
1180 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1181
1182 /* Call Centaur's CPUID instruction. */
1183 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
1184 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
1185 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1186 if (eax >= 0xC0000001) {
1187 /* Support VIA max extended level */
1188 x86_cpu_def->xlevel2 = eax;
1189 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
1190 x86_cpu_def->features[FEAT_C000_0001_EDX] =
1191 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1192 }
1193 }
1194
1195 /* Other KVM-specific feature fields: */
1196 x86_cpu_def->features[FEAT_SVM] =
1197 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1198 x86_cpu_def->features[FEAT_KVM] =
1199 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1200
1201 #endif /* CONFIG_KVM */
1202 }
1203
1204 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1205 {
1206 int i;
1207
1208 for (i = 0; i < 32; ++i)
1209 if (1 << i & mask) {
1210 const char *reg = get_register_name_32(f->cpuid_reg);
1211 assert(reg);
1212 fprintf(stderr, "warning: host doesn't support requested feature: "
1213 "CPUID.%02XH:%s%s%s [bit %d]\n",
1214 f->cpuid_eax, reg,
1215 f->feat_names[i] ? "." : "",
1216 f->feat_names[i] ? f->feat_names[i] : "", i);
1217 break;
1218 }
1219 return 0;
1220 }
1221
1222 /* Check if all requested cpu flags are making their way to the guest
1223 *
1224 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1225 *
1226 * This function may be called only if KVM is enabled.
1227 */
1228 static int kvm_check_features_against_host(X86CPU *cpu)
1229 {
1230 CPUX86State *env = &cpu->env;
1231 x86_def_t host_def;
1232 uint32_t mask;
1233 int rv, i;
1234 struct model_features_t ft[] = {
1235 {&env->features[FEAT_1_EDX],
1236 &host_def.features[FEAT_1_EDX],
1237 FEAT_1_EDX },
1238 {&env->features[FEAT_1_ECX],
1239 &host_def.features[FEAT_1_ECX],
1240 FEAT_1_ECX },
1241 {&env->features[FEAT_8000_0001_EDX],
1242 &host_def.features[FEAT_8000_0001_EDX],
1243 FEAT_8000_0001_EDX },
1244 {&env->features[FEAT_8000_0001_ECX],
1245 &host_def.features[FEAT_8000_0001_ECX],
1246 FEAT_8000_0001_ECX },
1247 {&env->features[FEAT_C000_0001_EDX],
1248 &host_def.features[FEAT_C000_0001_EDX],
1249 FEAT_C000_0001_EDX },
1250 {&env->features[FEAT_7_0_EBX],
1251 &host_def.features[FEAT_7_0_EBX],
1252 FEAT_7_0_EBX },
1253 {&env->features[FEAT_SVM],
1254 &host_def.features[FEAT_SVM],
1255 FEAT_SVM },
1256 {&env->features[FEAT_KVM],
1257 &host_def.features[FEAT_KVM],
1258 FEAT_KVM },
1259 };
1260
1261 assert(kvm_enabled());
1262
1263 kvm_cpu_fill_host(&host_def);
1264 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1265 FeatureWord w = ft[i].feat_word;
1266 FeatureWordInfo *wi = &feature_word_info[w];
1267 for (mask = 1; mask; mask <<= 1) {
1268 if (*ft[i].guest_feat & mask &&
1269 !(*ft[i].host_feat & mask)) {
1270 unavailable_host_feature(wi, mask);
1271 rv = 1;
1272 }
1273 }
1274 }
1275 return rv;
1276 }
1277
1278 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1279 const char *name, Error **errp)
1280 {
1281 X86CPU *cpu = X86_CPU(obj);
1282 CPUX86State *env = &cpu->env;
1283 int64_t value;
1284
1285 value = (env->cpuid_version >> 8) & 0xf;
1286 if (value == 0xf) {
1287 value += (env->cpuid_version >> 20) & 0xff;
1288 }
1289 visit_type_int(v, &value, name, errp);
1290 }
1291
1292 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1293 const char *name, Error **errp)
1294 {
1295 X86CPU *cpu = X86_CPU(obj);
1296 CPUX86State *env = &cpu->env;
1297 const int64_t min = 0;
1298 const int64_t max = 0xff + 0xf;
1299 int64_t value;
1300
1301 visit_type_int(v, &value, name, errp);
1302 if (error_is_set(errp)) {
1303 return;
1304 }
1305 if (value < min || value > max) {
1306 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1307 name ? name : "null", value, min, max);
1308 return;
1309 }
1310
1311 env->cpuid_version &= ~0xff00f00;
1312 if (value > 0x0f) {
1313 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1314 } else {
1315 env->cpuid_version |= value << 8;
1316 }
1317 }
1318
1319 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1320 const char *name, Error **errp)
1321 {
1322 X86CPU *cpu = X86_CPU(obj);
1323 CPUX86State *env = &cpu->env;
1324 int64_t value;
1325
1326 value = (env->cpuid_version >> 4) & 0xf;
1327 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1328 visit_type_int(v, &value, name, errp);
1329 }
1330
1331 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1332 const char *name, Error **errp)
1333 {
1334 X86CPU *cpu = X86_CPU(obj);
1335 CPUX86State *env = &cpu->env;
1336 const int64_t min = 0;
1337 const int64_t max = 0xff;
1338 int64_t value;
1339
1340 visit_type_int(v, &value, name, errp);
1341 if (error_is_set(errp)) {
1342 return;
1343 }
1344 if (value < min || value > max) {
1345 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1346 name ? name : "null", value, min, max);
1347 return;
1348 }
1349
1350 env->cpuid_version &= ~0xf00f0;
1351 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1352 }
1353
1354 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1355 void *opaque, const char *name,
1356 Error **errp)
1357 {
1358 X86CPU *cpu = X86_CPU(obj);
1359 CPUX86State *env = &cpu->env;
1360 int64_t value;
1361
1362 value = env->cpuid_version & 0xf;
1363 visit_type_int(v, &value, name, errp);
1364 }
1365
1366 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1367 void *opaque, const char *name,
1368 Error **errp)
1369 {
1370 X86CPU *cpu = X86_CPU(obj);
1371 CPUX86State *env = &cpu->env;
1372 const int64_t min = 0;
1373 const int64_t max = 0xf;
1374 int64_t value;
1375
1376 visit_type_int(v, &value, name, errp);
1377 if (error_is_set(errp)) {
1378 return;
1379 }
1380 if (value < min || value > max) {
1381 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1382 name ? name : "null", value, min, max);
1383 return;
1384 }
1385
1386 env->cpuid_version &= ~0xf;
1387 env->cpuid_version |= value & 0xf;
1388 }
1389
1390 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1391 const char *name, Error **errp)
1392 {
1393 X86CPU *cpu = X86_CPU(obj);
1394
1395 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1396 }
1397
1398 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1399 const char *name, Error **errp)
1400 {
1401 X86CPU *cpu = X86_CPU(obj);
1402
1403 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1404 }
1405
1406 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1407 const char *name, Error **errp)
1408 {
1409 X86CPU *cpu = X86_CPU(obj);
1410
1411 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1412 }
1413
1414 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1415 const char *name, Error **errp)
1416 {
1417 X86CPU *cpu = X86_CPU(obj);
1418
1419 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1420 }
1421
1422 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1423 {
1424 X86CPU *cpu = X86_CPU(obj);
1425 CPUX86State *env = &cpu->env;
1426 char *value;
1427
1428 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1429 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1430 env->cpuid_vendor3);
1431 return value;
1432 }
1433
1434 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1435 Error **errp)
1436 {
1437 X86CPU *cpu = X86_CPU(obj);
1438 CPUX86State *env = &cpu->env;
1439 int i;
1440
1441 if (strlen(value) != CPUID_VENDOR_SZ) {
1442 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1443 "vendor", value);
1444 return;
1445 }
1446
1447 env->cpuid_vendor1 = 0;
1448 env->cpuid_vendor2 = 0;
1449 env->cpuid_vendor3 = 0;
1450 for (i = 0; i < 4; i++) {
1451 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1452 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1453 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1454 }
1455 }
1456
1457 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1458 {
1459 X86CPU *cpu = X86_CPU(obj);
1460 CPUX86State *env = &cpu->env;
1461 char *value;
1462 int i;
1463
1464 value = g_malloc(48 + 1);
1465 for (i = 0; i < 48; i++) {
1466 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1467 }
1468 value[48] = '\0';
1469 return value;
1470 }
1471
1472 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1473 Error **errp)
1474 {
1475 X86CPU *cpu = X86_CPU(obj);
1476 CPUX86State *env = &cpu->env;
1477 int c, len, i;
1478
1479 if (model_id == NULL) {
1480 model_id = "";
1481 }
1482 len = strlen(model_id);
1483 memset(env->cpuid_model, 0, 48);
1484 for (i = 0; i < 48; i++) {
1485 if (i >= len) {
1486 c = '\0';
1487 } else {
1488 c = (uint8_t)model_id[i];
1489 }
1490 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1491 }
1492 }
1493
1494 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1495 const char *name, Error **errp)
1496 {
1497 X86CPU *cpu = X86_CPU(obj);
1498 int64_t value;
1499
1500 value = cpu->env.tsc_khz * 1000;
1501 visit_type_int(v, &value, name, errp);
1502 }
1503
1504 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1505 const char *name, Error **errp)
1506 {
1507 X86CPU *cpu = X86_CPU(obj);
1508 const int64_t min = 0;
1509 const int64_t max = INT64_MAX;
1510 int64_t value;
1511
1512 visit_type_int(v, &value, name, errp);
1513 if (error_is_set(errp)) {
1514 return;
1515 }
1516 if (value < min || value > max) {
1517 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1518 name ? name : "null", value, min, max);
1519 return;
1520 }
1521
1522 cpu->env.tsc_khz = value / 1000;
1523 }
1524
1525 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1526 const char *name, Error **errp)
1527 {
1528 X86CPU *cpu = X86_CPU(obj);
1529 int64_t value = cpu->env.cpuid_apic_id;
1530
1531 visit_type_int(v, &value, name, errp);
1532 }
1533
1534 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1535 const char *name, Error **errp)
1536 {
1537 X86CPU *cpu = X86_CPU(obj);
1538 DeviceState *dev = DEVICE(obj);
1539 const int64_t min = 0;
1540 const int64_t max = UINT32_MAX;
1541 Error *error = NULL;
1542 int64_t value;
1543
1544 if (dev->realized) {
1545 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1546 "it was realized", name, object_get_typename(obj));
1547 return;
1548 }
1549
1550 visit_type_int(v, &value, name, &error);
1551 if (error) {
1552 error_propagate(errp, error);
1553 return;
1554 }
1555 if (value < min || value > max) {
1556 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1557 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1558 object_get_typename(obj), name, value, min, max);
1559 return;
1560 }
1561
1562 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1563 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1564 return;
1565 }
1566 cpu->env.cpuid_apic_id = value;
1567 }
1568
1569 /* Generic getter for "feature-words" and "filtered-features" properties */
1570 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1571 const char *name, Error **errp)
1572 {
1573 uint32_t *array = (uint32_t *)opaque;
1574 FeatureWord w;
1575 Error *err = NULL;
1576 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1577 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1578 X86CPUFeatureWordInfoList *list = NULL;
1579
1580 for (w = 0; w < FEATURE_WORDS; w++) {
1581 FeatureWordInfo *wi = &feature_word_info[w];
1582 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1583 qwi->cpuid_input_eax = wi->cpuid_eax;
1584 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1585 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1586 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1587 qwi->features = array[w];
1588
1589 /* List will be in reverse order, but order shouldn't matter */
1590 list_entries[w].next = list;
1591 list_entries[w].value = &word_infos[w];
1592 list = &list_entries[w];
1593 }
1594
1595 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1596 error_propagate(errp, err);
1597 }
1598
1599 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1600 const char *name, Error **errp)
1601 {
1602 X86CPU *cpu = X86_CPU(obj);
1603 int64_t value = cpu->hyperv_spinlock_attempts;
1604
1605 visit_type_int(v, &value, name, errp);
1606 }
1607
1608 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1609 const char *name, Error **errp)
1610 {
1611 const int64_t min = 0xFFF;
1612 const int64_t max = UINT_MAX;
1613 X86CPU *cpu = X86_CPU(obj);
1614 Error *err = NULL;
1615 int64_t value;
1616
1617 visit_type_int(v, &value, name, &err);
1618 if (err) {
1619 error_propagate(errp, err);
1620 return;
1621 }
1622
1623 if (value < min || value > max) {
1624 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1625 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1626 object_get_typename(obj), name ? name : "null",
1627 value, min, max);
1628 return;
1629 }
1630 cpu->hyperv_spinlock_attempts = value;
1631 }
1632
1633 static PropertyInfo qdev_prop_spinlocks = {
1634 .name = "int",
1635 .get = x86_get_hv_spinlocks,
1636 .set = x86_set_hv_spinlocks,
1637 };
1638
1639 static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1640 const char *name)
1641 {
1642 x86_def_t *def;
1643 Error *err = NULL;
1644 int i;
1645
1646 if (name == NULL) {
1647 return -1;
1648 }
1649 if (kvm_enabled() && strcmp(name, "host") == 0) {
1650 kvm_cpu_fill_host(x86_cpu_def);
1651 object_property_set_bool(OBJECT(cpu), true, "pmu", &err);
1652 assert_no_error(err);
1653 return 0;
1654 }
1655
1656 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1657 def = &builtin_x86_defs[i];
1658 if (strcmp(name, def->name) == 0) {
1659 memcpy(x86_cpu_def, def, sizeof(*def));
1660 /* sysenter isn't supported in compatibility mode on AMD,
1661 * syscall isn't supported in compatibility mode on Intel.
1662 * Normally we advertise the actual CPU vendor, but you can
1663 * override this using the 'vendor' property if you want to use
1664 * KVM's sysenter/syscall emulation in compatibility mode and
1665 * when doing cross vendor migration
1666 */
1667 if (kvm_enabled()) {
1668 uint32_t ebx = 0, ecx = 0, edx = 0;
1669 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1670 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1671 }
1672 return 0;
1673 }
1674 }
1675
1676 return -1;
1677 }
1678
1679 /* Convert all '_' in a feature string option name to '-', to make feature
1680 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1681 */
1682 static inline void feat2prop(char *s)
1683 {
1684 while ((s = strchr(s, '_'))) {
1685 *s = '-';
1686 }
1687 }
1688
1689 /* Parse "+feature,-feature,feature=foo" CPU feature string
1690 */
1691 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1692 {
1693 char *featurestr; /* Single 'key=value" string being parsed */
1694 /* Features to be added */
1695 FeatureWordArray plus_features = { 0 };
1696 /* Features to be removed */
1697 FeatureWordArray minus_features = { 0 };
1698 uint32_t numvalue;
1699 CPUX86State *env = &cpu->env;
1700
1701 featurestr = features ? strtok(features, ",") : NULL;
1702
1703 while (featurestr) {
1704 char *val;
1705 if (featurestr[0] == '+') {
1706 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1707 } else if (featurestr[0] == '-') {
1708 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1709 } else if ((val = strchr(featurestr, '='))) {
1710 *val = 0; val++;
1711 feat2prop(featurestr);
1712 if (!strcmp(featurestr, "family")) {
1713 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1714 } else if (!strcmp(featurestr, "model")) {
1715 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1716 } else if (!strcmp(featurestr, "stepping")) {
1717 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1718 } else if (!strcmp(featurestr, "level")) {
1719 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1720 } else if (!strcmp(featurestr, "xlevel")) {
1721 char *err;
1722 char num[32];
1723
1724 numvalue = strtoul(val, &err, 0);
1725 if (!*val || *err) {
1726 error_setg(errp, "bad numerical value %s", val);
1727 goto out;
1728 }
1729 if (numvalue < 0x80000000) {
1730 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1731 ", fixup will be removed in future versions\n");
1732 numvalue += 0x80000000;
1733 }
1734 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1735 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1736 } else if (!strcmp(featurestr, "vendor")) {
1737 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1738 } else if (!strcmp(featurestr, "model-id")) {
1739 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1740 } else if (!strcmp(featurestr, "tsc-freq")) {
1741 int64_t tsc_freq;
1742 char *err;
1743 char num[32];
1744
1745 tsc_freq = strtosz_suffix_unit(val, &err,
1746 STRTOSZ_DEFSUFFIX_B, 1000);
1747 if (tsc_freq < 0 || *err) {
1748 error_setg(errp, "bad numerical value %s", val);
1749 goto out;
1750 }
1751 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1752 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1753 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1754 char *err;
1755 const int min = 0xFFF;
1756 char num[32];
1757 numvalue = strtoul(val, &err, 0);
1758 if (!*val || *err) {
1759 error_setg(errp, "bad numerical value %s", val);
1760 goto out;
1761 }
1762 if (numvalue < min) {
1763 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1764 ", fixup will be removed in future versions\n",
1765 min);
1766 numvalue = min;
1767 }
1768 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1769 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1770 } else {
1771 error_setg(errp, "unrecognized feature %s", featurestr);
1772 goto out;
1773 }
1774 } else if (!strcmp(featurestr, "check")) {
1775 check_cpuid = 1;
1776 } else if (!strcmp(featurestr, "enforce")) {
1777 check_cpuid = enforce_cpuid = 1;
1778 } else if (!strcmp(featurestr, "hv_relaxed")) {
1779 object_property_parse(OBJECT(cpu), "on", "hv-relaxed", errp);
1780 } else if (!strcmp(featurestr, "hv_vapic")) {
1781 object_property_parse(OBJECT(cpu), "on", "hv-vapic", errp);
1782 } else {
1783 error_setg(errp, "feature string `%s' not in format (+feature|"
1784 "-feature|feature=xyz)", featurestr);
1785 goto out;
1786 }
1787 if (error_is_set(errp)) {
1788 goto out;
1789 }
1790 featurestr = strtok(NULL, ",");
1791 }
1792 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1793 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1794 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1795 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1796 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1797 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1798 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1799 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1800 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1801 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1802 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1803 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1804 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1805 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1806 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1807 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1808
1809 out:
1810 return;
1811 }
1812
1813 /* generate a composite string into buf of all cpuid names in featureset
1814 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1815 * if flags, suppress names undefined in featureset.
1816 */
1817 static void listflags(char *buf, int bufsize, uint32_t fbits,
1818 const char **featureset, uint32_t flags)
1819 {
1820 const char **p = &featureset[31];
1821 char *q, *b, bit;
1822 int nc;
1823
1824 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1825 *buf = '\0';
1826 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1827 if (fbits & 1 << bit && (*p || !flags)) {
1828 if (*p)
1829 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1830 else
1831 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1832 if (bufsize <= nc) {
1833 if (b) {
1834 memcpy(b, "...", sizeof("..."));
1835 }
1836 return;
1837 }
1838 q += nc;
1839 bufsize -= nc;
1840 }
1841 }
1842
1843 /* generate CPU information. */
1844 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1845 {
1846 x86_def_t *def;
1847 char buf[256];
1848 int i;
1849
1850 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1851 def = &builtin_x86_defs[i];
1852 snprintf(buf, sizeof(buf), "%s", def->name);
1853 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1854 }
1855 #ifdef CONFIG_KVM
1856 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1857 "KVM processor with all supported host features "
1858 "(only available in KVM mode)");
1859 #endif
1860
1861 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1862 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1863 FeatureWordInfo *fw = &feature_word_info[i];
1864
1865 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1866 (*cpu_fprintf)(f, " %s\n", buf);
1867 }
1868 }
1869
1870 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1871 {
1872 CpuDefinitionInfoList *cpu_list = NULL;
1873 x86_def_t *def;
1874 int i;
1875
1876 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1877 CpuDefinitionInfoList *entry;
1878 CpuDefinitionInfo *info;
1879
1880 def = &builtin_x86_defs[i];
1881 info = g_malloc0(sizeof(*info));
1882 info->name = g_strdup(def->name);
1883
1884 entry = g_malloc0(sizeof(*entry));
1885 entry->value = info;
1886 entry->next = cpu_list;
1887 cpu_list = entry;
1888 }
1889
1890 return cpu_list;
1891 }
1892
1893 #ifdef CONFIG_KVM
1894 static void filter_features_for_kvm(X86CPU *cpu)
1895 {
1896 CPUX86State *env = &cpu->env;
1897 KVMState *s = kvm_state;
1898 FeatureWord w;
1899
1900 for (w = 0; w < FEATURE_WORDS; w++) {
1901 FeatureWordInfo *wi = &feature_word_info[w];
1902 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1903 wi->cpuid_ecx,
1904 wi->cpuid_reg);
1905 uint32_t requested_features = env->features[w];
1906 env->features[w] &= host_feat;
1907 cpu->filtered_features[w] = requested_features & ~env->features[w];
1908 }
1909 }
1910 #endif
1911
1912 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1913 {
1914 CPUX86State *env = &cpu->env;
1915 x86_def_t def1, *def = &def1;
1916
1917 memset(def, 0, sizeof(*def));
1918
1919 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
1920 error_setg(errp, "Unable to find CPU definition: %s", name);
1921 return;
1922 }
1923
1924 if (kvm_enabled()) {
1925 def->features[FEAT_KVM] |= kvm_default_features;
1926 }
1927 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1928
1929 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1930 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1931 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1932 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1933 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1934 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1935 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1936 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1937 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1938 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1939 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1940 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1941 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1942 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1943 env->cpuid_xlevel2 = def->xlevel2;
1944 cpu->cache_info_passthrough = def->cache_info_passthrough;
1945
1946 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1947 }
1948
1949 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1950 Error **errp)
1951 {
1952 X86CPU *cpu = NULL;
1953 gchar **model_pieces;
1954 char *name, *features;
1955 char *typename;
1956 Error *error = NULL;
1957
1958 model_pieces = g_strsplit(cpu_model, ",", 2);
1959 if (!model_pieces[0]) {
1960 error_setg(&error, "Invalid/empty CPU model name");
1961 goto out;
1962 }
1963 name = model_pieces[0];
1964 features = model_pieces[1];
1965
1966 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1967 #ifndef CONFIG_USER_ONLY
1968 if (icc_bridge == NULL) {
1969 error_setg(&error, "Invalid icc-bridge value");
1970 goto out;
1971 }
1972 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1973 object_unref(OBJECT(cpu));
1974 #endif
1975
1976 cpu_x86_register(cpu, name, &error);
1977 if (error) {
1978 goto out;
1979 }
1980
1981 /* Emulate per-model subclasses for global properties */
1982 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1983 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1984 g_free(typename);
1985 if (error) {
1986 goto out;
1987 }
1988
1989 cpu_x86_parse_featurestr(cpu, features, &error);
1990 if (error) {
1991 goto out;
1992 }
1993
1994 out:
1995 if (error != NULL) {
1996 error_propagate(errp, error);
1997 object_unref(OBJECT(cpu));
1998 cpu = NULL;
1999 }
2000 g_strfreev(model_pieces);
2001 return cpu;
2002 }
2003
2004 X86CPU *cpu_x86_init(const char *cpu_model)
2005 {
2006 Error *error = NULL;
2007 X86CPU *cpu;
2008
2009 cpu = cpu_x86_create(cpu_model, NULL, &error);
2010 if (error) {
2011 goto out;
2012 }
2013
2014 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2015
2016 out:
2017 if (error) {
2018 error_report("%s", error_get_pretty(error));
2019 error_free(error);
2020 if (cpu != NULL) {
2021 object_unref(OBJECT(cpu));
2022 cpu = NULL;
2023 }
2024 }
2025 return cpu;
2026 }
2027
2028 #if !defined(CONFIG_USER_ONLY)
2029
2030 void cpu_clear_apic_feature(CPUX86State *env)
2031 {
2032 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2033 }
2034
2035 #endif /* !CONFIG_USER_ONLY */
2036
2037 /* Initialize list of CPU models, filling some non-static fields if necessary
2038 */
2039 void x86_cpudef_setup(void)
2040 {
2041 int i, j;
2042 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2043
2044 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2045 x86_def_t *def = &builtin_x86_defs[i];
2046
2047 /* Look for specific "cpudef" models that */
2048 /* have the QEMU version in .model_id */
2049 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2050 if (strcmp(model_with_versions[j], def->name) == 0) {
2051 pstrcpy(def->model_id, sizeof(def->model_id),
2052 "QEMU Virtual CPU version ");
2053 pstrcat(def->model_id, sizeof(def->model_id),
2054 qemu_get_version());
2055 break;
2056 }
2057 }
2058 }
2059 }
2060
2061 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2062 uint32_t *ecx, uint32_t *edx)
2063 {
2064 *ebx = env->cpuid_vendor1;
2065 *edx = env->cpuid_vendor2;
2066 *ecx = env->cpuid_vendor3;
2067 }
2068
2069 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2070 uint32_t *eax, uint32_t *ebx,
2071 uint32_t *ecx, uint32_t *edx)
2072 {
2073 X86CPU *cpu = x86_env_get_cpu(env);
2074 CPUState *cs = CPU(cpu);
2075
2076 /* test if maximum index reached */
2077 if (index & 0x80000000) {
2078 if (index > env->cpuid_xlevel) {
2079 if (env->cpuid_xlevel2 > 0) {
2080 /* Handle the Centaur's CPUID instruction. */
2081 if (index > env->cpuid_xlevel2) {
2082 index = env->cpuid_xlevel2;
2083 } else if (index < 0xC0000000) {
2084 index = env->cpuid_xlevel;
2085 }
2086 } else {
2087 /* Intel documentation states that invalid EAX input will
2088 * return the same information as EAX=cpuid_level
2089 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2090 */
2091 index = env->cpuid_level;
2092 }
2093 }
2094 } else {
2095 if (index > env->cpuid_level)
2096 index = env->cpuid_level;
2097 }
2098
2099 switch(index) {
2100 case 0:
2101 *eax = env->cpuid_level;
2102 get_cpuid_vendor(env, ebx, ecx, edx);
2103 break;
2104 case 1:
2105 *eax = env->cpuid_version;
2106 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2107 *ecx = env->features[FEAT_1_ECX];
2108 *edx = env->features[FEAT_1_EDX];
2109 if (cs->nr_cores * cs->nr_threads > 1) {
2110 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2111 *edx |= 1 << 28; /* HTT bit */
2112 }
2113 break;
2114 case 2:
2115 /* cache info: needed for Pentium Pro compatibility */
2116 if (cpu->cache_info_passthrough) {
2117 host_cpuid(index, 0, eax, ebx, ecx, edx);
2118 break;
2119 }
2120 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2121 *ebx = 0;
2122 *ecx = 0;
2123 *edx = (L1D_DESCRIPTOR << 16) | \
2124 (L1I_DESCRIPTOR << 8) | \
2125 (L2_DESCRIPTOR);
2126 break;
2127 case 4:
2128 /* cache info: needed for Core compatibility */
2129 if (cpu->cache_info_passthrough) {
2130 host_cpuid(index, count, eax, ebx, ecx, edx);
2131 *eax &= ~0xFC000000;
2132 } else {
2133 *eax = 0;
2134 switch (count) {
2135 case 0: /* L1 dcache info */
2136 *eax |= CPUID_4_TYPE_DCACHE | \
2137 CPUID_4_LEVEL(1) | \
2138 CPUID_4_SELF_INIT_LEVEL;
2139 *ebx = (L1D_LINE_SIZE - 1) | \
2140 ((L1D_PARTITIONS - 1) << 12) | \
2141 ((L1D_ASSOCIATIVITY - 1) << 22);
2142 *ecx = L1D_SETS - 1;
2143 *edx = CPUID_4_NO_INVD_SHARING;
2144 break;
2145 case 1: /* L1 icache info */
2146 *eax |= CPUID_4_TYPE_ICACHE | \
2147 CPUID_4_LEVEL(1) | \
2148 CPUID_4_SELF_INIT_LEVEL;
2149 *ebx = (L1I_LINE_SIZE - 1) | \
2150 ((L1I_PARTITIONS - 1) << 12) | \
2151 ((L1I_ASSOCIATIVITY - 1) << 22);
2152 *ecx = L1I_SETS - 1;
2153 *edx = CPUID_4_NO_INVD_SHARING;
2154 break;
2155 case 2: /* L2 cache info */
2156 *eax |= CPUID_4_TYPE_UNIFIED | \
2157 CPUID_4_LEVEL(2) | \
2158 CPUID_4_SELF_INIT_LEVEL;
2159 if (cs->nr_threads > 1) {
2160 *eax |= (cs->nr_threads - 1) << 14;
2161 }
2162 *ebx = (L2_LINE_SIZE - 1) | \
2163 ((L2_PARTITIONS - 1) << 12) | \
2164 ((L2_ASSOCIATIVITY - 1) << 22);
2165 *ecx = L2_SETS - 1;
2166 *edx = CPUID_4_NO_INVD_SHARING;
2167 break;
2168 default: /* end of info */
2169 *eax = 0;
2170 *ebx = 0;
2171 *ecx = 0;
2172 *edx = 0;
2173 break;
2174 }
2175 }
2176
2177 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2178 if ((*eax & 31) && cs->nr_cores > 1) {
2179 *eax |= (cs->nr_cores - 1) << 26;
2180 }
2181 break;
2182 case 5:
2183 /* mwait info: needed for Core compatibility */
2184 *eax = 0; /* Smallest monitor-line size in bytes */
2185 *ebx = 0; /* Largest monitor-line size in bytes */
2186 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2187 *edx = 0;
2188 break;
2189 case 6:
2190 /* Thermal and Power Leaf */
2191 *eax = 0;
2192 *ebx = 0;
2193 *ecx = 0;
2194 *edx = 0;
2195 break;
2196 case 7:
2197 /* Structured Extended Feature Flags Enumeration Leaf */
2198 if (count == 0) {
2199 *eax = 0; /* Maximum ECX value for sub-leaves */
2200 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2201 *ecx = 0; /* Reserved */
2202 *edx = 0; /* Reserved */
2203 } else {
2204 *eax = 0;
2205 *ebx = 0;
2206 *ecx = 0;
2207 *edx = 0;
2208 }
2209 break;
2210 case 9:
2211 /* Direct Cache Access Information Leaf */
2212 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2213 *ebx = 0;
2214 *ecx = 0;
2215 *edx = 0;
2216 break;
2217 case 0xA:
2218 /* Architectural Performance Monitoring Leaf */
2219 if (kvm_enabled() && cpu->enable_pmu) {
2220 KVMState *s = cs->kvm_state;
2221
2222 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2223 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2224 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2225 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2226 } else {
2227 *eax = 0;
2228 *ebx = 0;
2229 *ecx = 0;
2230 *edx = 0;
2231 }
2232 break;
2233 case 0xD: {
2234 KVMState *s = cs->kvm_state;
2235 uint64_t kvm_mask;
2236 int i;
2237
2238 /* Processor Extended State */
2239 *eax = 0;
2240 *ebx = 0;
2241 *ecx = 0;
2242 *edx = 0;
2243 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2244 break;
2245 }
2246 kvm_mask =
2247 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2248 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2249
2250 if (count == 0) {
2251 *ecx = 0x240;
2252 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2253 const ExtSaveArea *esa = &ext_save_areas[i];
2254 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2255 (kvm_mask & (1 << i)) != 0) {
2256 if (i < 32) {
2257 *eax |= 1 << i;
2258 } else {
2259 *edx |= 1 << (i - 32);
2260 }
2261 *ecx = MAX(*ecx, esa->offset + esa->size);
2262 }
2263 }
2264 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2265 *ebx = *ecx;
2266 } else if (count == 1) {
2267 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2268 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2269 const ExtSaveArea *esa = &ext_save_areas[count];
2270 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2271 (kvm_mask & (1 << count)) != 0) {
2272 *eax = esa->size;
2273 *ebx = esa->offset;
2274 }
2275 }
2276 break;
2277 }
2278 case 0x80000000:
2279 *eax = env->cpuid_xlevel;
2280 *ebx = env->cpuid_vendor1;
2281 *edx = env->cpuid_vendor2;
2282 *ecx = env->cpuid_vendor3;
2283 break;
2284 case 0x80000001:
2285 *eax = env->cpuid_version;
2286 *ebx = 0;
2287 *ecx = env->features[FEAT_8000_0001_ECX];
2288 *edx = env->features[FEAT_8000_0001_EDX];
2289
2290 /* The Linux kernel checks for the CMPLegacy bit and
2291 * discards multiple thread information if it is set.
2292 * So dont set it here for Intel to make Linux guests happy.
2293 */
2294 if (cs->nr_cores * cs->nr_threads > 1) {
2295 uint32_t tebx, tecx, tedx;
2296 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2297 if (tebx != CPUID_VENDOR_INTEL_1 ||
2298 tedx != CPUID_VENDOR_INTEL_2 ||
2299 tecx != CPUID_VENDOR_INTEL_3) {
2300 *ecx |= 1 << 1; /* CmpLegacy bit */
2301 }
2302 }
2303 break;
2304 case 0x80000002:
2305 case 0x80000003:
2306 case 0x80000004:
2307 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2308 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2309 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2310 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2311 break;
2312 case 0x80000005:
2313 /* cache info (L1 cache) */
2314 if (cpu->cache_info_passthrough) {
2315 host_cpuid(index, 0, eax, ebx, ecx, edx);
2316 break;
2317 }
2318 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2319 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2320 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2321 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2322 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2323 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2324 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2325 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2326 break;
2327 case 0x80000006:
2328 /* cache info (L2 cache) */
2329 if (cpu->cache_info_passthrough) {
2330 host_cpuid(index, 0, eax, ebx, ecx, edx);
2331 break;
2332 }
2333 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2334 (L2_DTLB_2M_ENTRIES << 16) | \
2335 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2336 (L2_ITLB_2M_ENTRIES);
2337 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2338 (L2_DTLB_4K_ENTRIES << 16) | \
2339 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2340 (L2_ITLB_4K_ENTRIES);
2341 *ecx = (L2_SIZE_KB_AMD << 16) | \
2342 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2343 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2344 *edx = ((L3_SIZE_KB/512) << 18) | \
2345 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2346 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2347 break;
2348 case 0x80000008:
2349 /* virtual & phys address size in low 2 bytes. */
2350 /* XXX: This value must match the one used in the MMU code. */
2351 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2352 /* 64 bit processor */
2353 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2354 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2355 } else {
2356 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2357 *eax = 0x00000024; /* 36 bits physical */
2358 } else {
2359 *eax = 0x00000020; /* 32 bits physical */
2360 }
2361 }
2362 *ebx = 0;
2363 *ecx = 0;
2364 *edx = 0;
2365 if (cs->nr_cores * cs->nr_threads > 1) {
2366 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2367 }
2368 break;
2369 case 0x8000000A:
2370 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2371 *eax = 0x00000001; /* SVM Revision */
2372 *ebx = 0x00000010; /* nr of ASIDs */
2373 *ecx = 0;
2374 *edx = env->features[FEAT_SVM]; /* optional features */
2375 } else {
2376 *eax = 0;
2377 *ebx = 0;
2378 *ecx = 0;
2379 *edx = 0;
2380 }
2381 break;
2382 case 0xC0000000:
2383 *eax = env->cpuid_xlevel2;
2384 *ebx = 0;
2385 *ecx = 0;
2386 *edx = 0;
2387 break;
2388 case 0xC0000001:
2389 /* Support for VIA CPU's CPUID instruction */
2390 *eax = env->cpuid_version;
2391 *ebx = 0;
2392 *ecx = 0;
2393 *edx = env->features[FEAT_C000_0001_EDX];
2394 break;
2395 case 0xC0000002:
2396 case 0xC0000003:
2397 case 0xC0000004:
2398 /* Reserved for the future, and now filled with zero */
2399 *eax = 0;
2400 *ebx = 0;
2401 *ecx = 0;
2402 *edx = 0;
2403 break;
2404 default:
2405 /* reserved values: zero */
2406 *eax = 0;
2407 *ebx = 0;
2408 *ecx = 0;
2409 *edx = 0;
2410 break;
2411 }
2412 }
2413
2414 /* CPUClass::reset() */
2415 static void x86_cpu_reset(CPUState *s)
2416 {
2417 X86CPU *cpu = X86_CPU(s);
2418 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2419 CPUX86State *env = &cpu->env;
2420 int i;
2421
2422 xcc->parent_reset(s);
2423
2424
2425 memset(env, 0, offsetof(CPUX86State, breakpoints));
2426
2427 tlb_flush(env, 1);
2428
2429 env->old_exception = -1;
2430
2431 /* init to reset state */
2432
2433 #ifdef CONFIG_SOFTMMU
2434 env->hflags |= HF_SOFTMMU_MASK;
2435 #endif
2436 env->hflags2 |= HF2_GIF_MASK;
2437
2438 cpu_x86_update_cr0(env, 0x60000010);
2439 env->a20_mask = ~0x0;
2440 env->smbase = 0x30000;
2441
2442 env->idt.limit = 0xffff;
2443 env->gdt.limit = 0xffff;
2444 env->ldt.limit = 0xffff;
2445 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2446 env->tr.limit = 0xffff;
2447 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2448
2449 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2450 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2451 DESC_R_MASK | DESC_A_MASK);
2452 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2453 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2454 DESC_A_MASK);
2455 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2456 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2457 DESC_A_MASK);
2458 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2459 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2460 DESC_A_MASK);
2461 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2462 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2463 DESC_A_MASK);
2464 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2465 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2466 DESC_A_MASK);
2467
2468 env->eip = 0xfff0;
2469 env->regs[R_EDX] = env->cpuid_version;
2470
2471 env->eflags = 0x2;
2472
2473 /* FPU init */
2474 for (i = 0; i < 8; i++) {
2475 env->fptags[i] = 1;
2476 }
2477 env->fpuc = 0x37f;
2478
2479 env->mxcsr = 0x1f80;
2480 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2481
2482 env->pat = 0x0007040600070406ULL;
2483 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2484
2485 memset(env->dr, 0, sizeof(env->dr));
2486 env->dr[6] = DR6_FIXED_1;
2487 env->dr[7] = DR7_FIXED_1;
2488 cpu_breakpoint_remove_all(env, BP_CPU);
2489 cpu_watchpoint_remove_all(env, BP_CPU);
2490
2491 #if !defined(CONFIG_USER_ONLY)
2492 /* We hard-wire the BSP to the first CPU. */
2493 if (s->cpu_index == 0) {
2494 apic_designate_bsp(cpu->apic_state);
2495 }
2496
2497 s->halted = !cpu_is_bsp(cpu);
2498 #endif
2499 }
2500
2501 #ifndef CONFIG_USER_ONLY
2502 bool cpu_is_bsp(X86CPU *cpu)
2503 {
2504 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2505 }
2506
2507 /* TODO: remove me, when reset over QOM tree is implemented */
2508 static void x86_cpu_machine_reset_cb(void *opaque)
2509 {
2510 X86CPU *cpu = opaque;
2511 cpu_reset(CPU(cpu));
2512 }
2513 #endif
2514
2515 static void mce_init(X86CPU *cpu)
2516 {
2517 CPUX86State *cenv = &cpu->env;
2518 unsigned int bank;
2519
2520 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2521 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2522 (CPUID_MCE | CPUID_MCA)) {
2523 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2524 cenv->mcg_ctl = ~(uint64_t)0;
2525 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2526 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2527 }
2528 }
2529 }
2530
2531 #ifndef CONFIG_USER_ONLY
2532 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2533 {
2534 CPUX86State *env = &cpu->env;
2535 DeviceState *dev = DEVICE(cpu);
2536 APICCommonState *apic;
2537 const char *apic_type = "apic";
2538
2539 if (kvm_irqchip_in_kernel()) {
2540 apic_type = "kvm-apic";
2541 } else if (xen_enabled()) {
2542 apic_type = "xen-apic";
2543 }
2544
2545 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2546 if (cpu->apic_state == NULL) {
2547 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2548 return;
2549 }
2550
2551 object_property_add_child(OBJECT(cpu), "apic",
2552 OBJECT(cpu->apic_state), NULL);
2553 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2554 /* TODO: convert to link<> */
2555 apic = APIC_COMMON(cpu->apic_state);
2556 apic->cpu = cpu;
2557 }
2558
2559 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2560 {
2561 if (cpu->apic_state == NULL) {
2562 return;
2563 }
2564
2565 if (qdev_init(cpu->apic_state)) {
2566 error_setg(errp, "APIC device '%s' could not be initialized",
2567 object_get_typename(OBJECT(cpu->apic_state)));
2568 return;
2569 }
2570 }
2571 #else
2572 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2573 {
2574 }
2575 #endif
2576
2577 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2578 {
2579 CPUState *cs = CPU(dev);
2580 X86CPU *cpu = X86_CPU(dev);
2581 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2582 CPUX86State *env = &cpu->env;
2583 Error *local_err = NULL;
2584
2585 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2586 env->cpuid_level = 7;
2587 }
2588
2589 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2590 * CPUID[1].EDX.
2591 */
2592 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2593 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2594 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2595 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2596 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2597 & CPUID_EXT2_AMD_ALIASES);
2598 }
2599
2600 if (!kvm_enabled()) {
2601 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2602 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2603 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2604 #ifdef TARGET_X86_64
2605 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2606 #endif
2607 );
2608 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2609 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2610 } else {
2611 if (check_cpuid && kvm_check_features_against_host(cpu)
2612 && enforce_cpuid) {
2613 error_setg(&local_err,
2614 "Host's CPU doesn't support requested features");
2615 goto out;
2616 }
2617 #ifdef CONFIG_KVM
2618 filter_features_for_kvm(cpu);
2619 #endif
2620 }
2621
2622 #ifndef CONFIG_USER_ONLY
2623 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2624
2625 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2626 x86_cpu_apic_create(cpu, &local_err);
2627 if (local_err != NULL) {
2628 goto out;
2629 }
2630 }
2631 #endif
2632
2633 mce_init(cpu);
2634 qemu_init_vcpu(cs);
2635
2636 x86_cpu_apic_realize(cpu, &local_err);
2637 if (local_err != NULL) {
2638 goto out;
2639 }
2640 cpu_reset(cs);
2641
2642 xcc->parent_realize(dev, &local_err);
2643 out:
2644 if (local_err != NULL) {
2645 error_propagate(errp, local_err);
2646 return;
2647 }
2648 }
2649
2650 /* Enables contiguous-apic-ID mode, for compatibility */
2651 static bool compat_apic_id_mode;
2652
2653 void enable_compat_apic_id_mode(void)
2654 {
2655 compat_apic_id_mode = true;
2656 }
2657
2658 /* Calculates initial APIC ID for a specific CPU index
2659 *
2660 * Currently we need to be able to calculate the APIC ID from the CPU index
2661 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2662 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2663 * all CPUs up to max_cpus.
2664 */
2665 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2666 {
2667 uint32_t correct_id;
2668 static bool warned;
2669
2670 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2671 if (compat_apic_id_mode) {
2672 if (cpu_index != correct_id && !warned) {
2673 error_report("APIC IDs set in compatibility mode, "
2674 "CPU topology won't match the configuration");
2675 warned = true;
2676 }
2677 return cpu_index;
2678 } else {
2679 return correct_id;
2680 }
2681 }
2682
2683 static void x86_cpu_initfn(Object *obj)
2684 {
2685 CPUState *cs = CPU(obj);
2686 X86CPU *cpu = X86_CPU(obj);
2687 CPUX86State *env = &cpu->env;
2688 static int inited;
2689
2690 cs->env_ptr = env;
2691 cpu_exec_init(env);
2692
2693 object_property_add(obj, "family", "int",
2694 x86_cpuid_version_get_family,
2695 x86_cpuid_version_set_family, NULL, NULL, NULL);
2696 object_property_add(obj, "model", "int",
2697 x86_cpuid_version_get_model,
2698 x86_cpuid_version_set_model, NULL, NULL, NULL);
2699 object_property_add(obj, "stepping", "int",
2700 x86_cpuid_version_get_stepping,
2701 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2702 object_property_add(obj, "level", "int",
2703 x86_cpuid_get_level,
2704 x86_cpuid_set_level, NULL, NULL, NULL);
2705 object_property_add(obj, "xlevel", "int",
2706 x86_cpuid_get_xlevel,
2707 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2708 object_property_add_str(obj, "vendor",
2709 x86_cpuid_get_vendor,
2710 x86_cpuid_set_vendor, NULL);
2711 object_property_add_str(obj, "model-id",
2712 x86_cpuid_get_model_id,
2713 x86_cpuid_set_model_id, NULL);
2714 object_property_add(obj, "tsc-frequency", "int",
2715 x86_cpuid_get_tsc_freq,
2716 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2717 object_property_add(obj, "apic-id", "int",
2718 x86_cpuid_get_apic_id,
2719 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2720 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2721 x86_cpu_get_feature_words,
2722 NULL, NULL, (void *)env->features, NULL);
2723 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2724 x86_cpu_get_feature_words,
2725 NULL, NULL, (void *)cpu->filtered_features, NULL);
2726
2727 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2728 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2729
2730 /* init various static tables used in TCG mode */
2731 if (tcg_enabled() && !inited) {
2732 inited = 1;
2733 optimize_flags_init();
2734 #ifndef CONFIG_USER_ONLY
2735 cpu_set_debug_excp_handler(breakpoint_handler);
2736 #endif
2737 }
2738 }
2739
2740 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2741 {
2742 X86CPU *cpu = X86_CPU(cs);
2743 CPUX86State *env = &cpu->env;
2744
2745 return env->cpuid_apic_id;
2746 }
2747
2748 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2749 {
2750 X86CPU *cpu = X86_CPU(cs);
2751
2752 return cpu->env.cr[0] & CR0_PG_MASK;
2753 }
2754
2755 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2756 {
2757 X86CPU *cpu = X86_CPU(cs);
2758
2759 cpu->env.eip = value;
2760 }
2761
2762 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2763 {
2764 X86CPU *cpu = X86_CPU(cs);
2765
2766 cpu->env.eip = tb->pc - tb->cs_base;
2767 }
2768
2769 static Property x86_cpu_properties[] = {
2770 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2771 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2772 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2773 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2774 DEFINE_PROP_END_OF_LIST()
2775 };
2776
2777 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2778 {
2779 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2780 CPUClass *cc = CPU_CLASS(oc);
2781 DeviceClass *dc = DEVICE_CLASS(oc);
2782
2783 xcc->parent_realize = dc->realize;
2784 dc->realize = x86_cpu_realizefn;
2785 dc->bus_type = TYPE_ICC_BUS;
2786 dc->props = x86_cpu_properties;
2787
2788 xcc->parent_reset = cc->reset;
2789 cc->reset = x86_cpu_reset;
2790 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2791
2792 cc->do_interrupt = x86_cpu_do_interrupt;
2793 cc->dump_state = x86_cpu_dump_state;
2794 cc->set_pc = x86_cpu_set_pc;
2795 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2796 cc->gdb_read_register = x86_cpu_gdb_read_register;
2797 cc->gdb_write_register = x86_cpu_gdb_write_register;
2798 cc->get_arch_id = x86_cpu_get_arch_id;
2799 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2800 #ifndef CONFIG_USER_ONLY
2801 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2802 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2803 cc->write_elf64_note = x86_cpu_write_elf64_note;
2804 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2805 cc->write_elf32_note = x86_cpu_write_elf32_note;
2806 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2807 cc->vmsd = &vmstate_x86_cpu;
2808 #endif
2809 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2810 }
2811
2812 static const TypeInfo x86_cpu_type_info = {
2813 .name = TYPE_X86_CPU,
2814 .parent = TYPE_CPU,
2815 .instance_size = sizeof(X86CPU),
2816 .instance_init = x86_cpu_initfn,
2817 .abstract = false,
2818 .class_size = sizeof(X86CPUClass),
2819 .class_init = x86_cpu_common_class_init,
2820 };
2821
2822 static void x86_cpu_register_types(void)
2823 {
2824 type_register_static(&x86_cpu_type_info);
2825 }
2826
2827 type_init(x86_cpu_register_types)
AR7 emulation for QEMU