target/avr: Add basic parameters of the new platform
[qemu/ar7.git] / hw / arm / nrf51_soc.c
blob45e6cc97d704642e945fea23e4f0fa7b880c0423
1 /*
2 * Nordic Semiconductor nRF51 SoC
3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
5 * Copyright 2018 Joel Stanley <joel@jms.id.au>
7 * This code is licensed under the GPL version 2 or later. See
8 * the COPYING file in the top-level directory.
9 */
11 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "hw/arm/boot.h"
14 #include "hw/sysbus.h"
15 #include "hw/misc/unimp.h"
16 #include "exec/address-spaces.h"
17 #include "qemu/log.h"
18 #include "cpu.h"
20 #include "hw/arm/nrf51.h"
21 #include "hw/arm/nrf51_soc.h"
24 * The size and base is for the NRF51822 part. If other parts
25 * are supported in the future, add a sub-class of NRF51SoC for
26 * the specific variants
28 #define NRF51822_FLASH_PAGES 256
29 #define NRF51822_SRAM_PAGES 16
30 #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
31 #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
33 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
35 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
37 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
38 __func__, addr, size);
39 return 1;
42 static void clock_write(void *opaque, hwaddr addr, uint64_t data,
43 unsigned int size)
45 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
46 __func__, addr, data, size);
49 static const MemoryRegionOps clock_ops = {
50 .read = clock_read,
51 .write = clock_write
55 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
57 NRF51State *s = NRF51_SOC(dev_soc);
58 MemoryRegion *mr;
59 Error *err = NULL;
60 uint8_t i = 0;
61 hwaddr base_addr = 0;
63 if (!s->board_memory) {
64 error_setg(errp, "memory property was not set");
65 return;
68 object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
69 &error_abort);
70 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
71 return;
74 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
76 memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
77 &err);
78 if (err) {
79 error_propagate(errp, err);
80 return;
82 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
84 /* UART */
85 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
86 return;
88 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
89 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
90 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
91 qdev_get_gpio_in(DEVICE(&s->cpu),
92 BASE_TO_IRQ(NRF51_UART_BASE)));
94 /* RNG */
95 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) {
96 return;
99 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
100 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
101 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
102 qdev_get_gpio_in(DEVICE(&s->cpu),
103 BASE_TO_IRQ(NRF51_RNG_BASE)));
105 /* UICR, FICR, NVMC, FLASH */
106 if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size",
107 s->flash_size, errp)) {
108 return;
111 if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) {
112 return;
115 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
116 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
117 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
118 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
119 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
120 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
121 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
122 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
124 /* GPIO */
125 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
126 return;
129 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
130 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
132 /* Pass all GPIOs to the SOC layer so they are available to the board */
133 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
135 /* TIMER */
136 for (i = 0; i < NRF51_NUM_TIMERS; i++) {
137 if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) {
138 return;
140 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
141 return;
144 base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
146 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
147 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
148 qdev_get_gpio_in(DEVICE(&s->cpu),
149 BASE_TO_IRQ(base_addr)));
152 /* STUB Peripherals */
153 memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
154 "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
155 memory_region_add_subregion_overlap(&s->container,
156 NRF51_IOMEM_BASE, &s->clock, -1);
158 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
159 NRF51_IOMEM_SIZE);
160 create_unimplemented_device("nrf51_soc.private",
161 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
164 static void nrf51_soc_init(Object *obj)
166 uint8_t i = 0;
168 NRF51State *s = NRF51_SOC(obj);
170 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
172 object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
173 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
174 ARM_CPU_TYPE_NAME("cortex-m0"));
175 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
177 object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
178 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
180 object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);
182 object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);
184 object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);
186 for (i = 0; i < NRF51_NUM_TIMERS; i++) {
187 object_initialize_child(obj, "timer[*]", &s->timer[i],
188 TYPE_NRF51_TIMER);
193 static Property nrf51_soc_properties[] = {
194 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
195 MemoryRegion *),
196 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
197 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
198 NRF51822_FLASH_SIZE),
199 DEFINE_PROP_END_OF_LIST(),
202 static void nrf51_soc_class_init(ObjectClass *klass, void *data)
204 DeviceClass *dc = DEVICE_CLASS(klass);
206 dc->realize = nrf51_soc_realize;
207 device_class_set_props(dc, nrf51_soc_properties);
210 static const TypeInfo nrf51_soc_info = {
211 .name = TYPE_NRF51_SOC,
212 .parent = TYPE_SYS_BUS_DEVICE,
213 .instance_size = sizeof(NRF51State),
214 .instance_init = nrf51_soc_init,
215 .class_init = nrf51_soc_class_init,
218 static void nrf51_soc_types(void)
220 type_register_static(&nrf51_soc_info);
222 type_init(nrf51_soc_types)