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target/avr: Add basic parameters of the new platform
[qemu/ar7.git] / hw / arm / aspeed.c
blob660dcb5414438f12828233b2fb90301bf3d00752
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "cpu.h"
15 #include "exec/address-spaces.h"
16 #include "hw/arm/boot.h"
17 #include "hw/arm/aspeed.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/boards.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/misc/pca9552.h"
22 #include "hw/misc/tmp105.h"
23 #include "hw/qdev-properties.h"
24 #include "qemu/log.h"
25 #include "sysemu/block-backend.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/loader.h"
28 #include "qemu/error-report.h"
29 #include "qemu/units.h"
30
31 static struct arm_boot_info aspeed_board_binfo = {
32 .board_id = -1, /* device-tree-only board */
33 };
34
35 struct AspeedMachineState {
36 /* Private */
37 MachineState parent_obj;
38 /* Public */
39
40 AspeedSoCState soc;
41 MemoryRegion ram_container;
42 MemoryRegion max_ram;
43 bool mmio_exec;
44 };
45
46 /* Palmetto hardware value: 0x120CE416 */
47 #define PALMETTO_BMC_HW_STRAP1 ( \
48 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
49 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
50 SCU_AST2400_HW_STRAP_ACPI_DIS | \
51 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
52 SCU_HW_STRAP_VGA_CLASS_CODE | \
53 SCU_HW_STRAP_LPC_RESET_PIN | \
54 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
55 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
56 SCU_HW_STRAP_SPI_WIDTH | \
57 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
58 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
59
60 /* AST2500 evb hardware value: 0xF100C2E6 */
61 #define AST2500_EVB_HW_STRAP1 (( \
62 AST2500_HW_STRAP1_DEFAULTS | \
63 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
64 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
65 SCU_AST2500_HW_STRAP_UART_DEBUG | \
66 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
67 SCU_HW_STRAP_MAC1_RGMII | \
68 SCU_HW_STRAP_MAC0_RGMII) & \
69 ~SCU_HW_STRAP_2ND_BOOT_WDT)
70
71 /* Romulus hardware value: 0xF10AD206 */
72 #define ROMULUS_BMC_HW_STRAP1 ( \
73 AST2500_HW_STRAP1_DEFAULTS | \
74 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
75 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
76 SCU_AST2500_HW_STRAP_UART_DEBUG | \
77 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
78 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
79 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
80
81 /* Sonorapass hardware value: 0xF100D216 */
82 #define SONORAPASS_BMC_HW_STRAP1 ( \
83 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
84 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
85 SCU_AST2500_HW_STRAP_UART_DEBUG | \
86 SCU_AST2500_HW_STRAP_RESERVED28 | \
87 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
88 SCU_HW_STRAP_VGA_CLASS_CODE | \
89 SCU_HW_STRAP_LPC_RESET_PIN | \
90 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
91 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
92 SCU_HW_STRAP_VGA_BIOS_ROM | \
93 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
94 SCU_AST2500_HW_STRAP_RESERVED1)
95
96 /* Swift hardware value: 0xF11AD206 */
97 #define SWIFT_BMC_HW_STRAP1 ( \
98 AST2500_HW_STRAP1_DEFAULTS | \
99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
101 SCU_AST2500_HW_STRAP_UART_DEBUG | \
102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
103 SCU_H_PLL_BYPASS_EN | \
104 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
106
107 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
108 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
109
110 /* AST2600 evb hardware value */
111 #define AST2600_EVB_HW_STRAP1 0x000000C0
112 #define AST2600_EVB_HW_STRAP2 0x00000003
113
114 /* Tacoma hardware value */
115 #define TACOMA_BMC_HW_STRAP1 0x00000000
116 #define TACOMA_BMC_HW_STRAP2 0x00000040
117
118 /*
119 * The max ram region is for firmwares that scan the address space
120 * with load/store to guess how much RAM the SoC has.
121 */
122 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
123 {
124 return 0;
125 }
126
127 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
128 unsigned size)
129 {
130 /* Discard writes */
131 }
132
133 static const MemoryRegionOps max_ram_ops = {
134 .read = max_ram_read,
135 .write = max_ram_write,
136 .endianness = DEVICE_NATIVE_ENDIAN,
137 };
138
139 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
140 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
141 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
142 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
143 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
144 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
145 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
146
147 static void aspeed_write_smpboot(ARMCPU *cpu,
148 const struct arm_boot_info *info)
149 {
150 static const uint32_t poll_mailbox_ready[] = {
151 /*
152 * r2 = per-cpu go sign value
153 * r1 = AST_SMP_MBOX_FIELD_ENTRY
154 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
155 */
156 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
157 0xe21000ff, /* ands r0, r0, #255 */
158 0xe59f201c, /* ldr r2, [pc, #28] */
159 0xe1822000, /* orr r2, r2, r0 */
160
161 0xe59f1018, /* ldr r1, [pc, #24] */
162 0xe59f0018, /* ldr r0, [pc, #24] */
163
164 0xe320f002, /* wfe */
165 0xe5904000, /* ldr r4, [r0] */
166 0xe1520004, /* cmp r2, r4 */
167 0x1afffffb, /* bne <wfe> */
168 0xe591f000, /* ldr pc, [r1] */
169 AST_SMP_MBOX_GOSIGN,
170 AST_SMP_MBOX_FIELD_ENTRY,
171 AST_SMP_MBOX_FIELD_GOSIGN,
172 };
173
174 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
175 sizeof(poll_mailbox_ready),
176 info->smp_loader_start);
177 }
178
179 static void aspeed_reset_secondary(ARMCPU *cpu,
180 const struct arm_boot_info *info)
181 {
182 AddressSpace *as = arm_boot_address_space(cpu, info);
183 CPUState *cs = CPU(cpu);
184
185 /* info->smp_bootreg_addr */
186 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
187 MEMTXATTRS_UNSPECIFIED, NULL);
188 cpu_set_pc(cs, info->smp_loader_start);
189 }
190
191 #define FIRMWARE_ADDR 0x0
192
193 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
194 Error **errp)
195 {
196 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
197 uint8_t *storage;
198 int64_t size;
199
200 /* The block backend size should have already been 'validated' by
201 * the creation of the m25p80 object.
202 */
203 size = blk_getlength(blk);
204 if (size <= 0) {
205 error_setg(errp, "failed to get flash size");
206 return;
207 }
208
209 if (rom_size > size) {
210 rom_size = size;
211 }
212
213 storage = g_new0(uint8_t, rom_size);
214 if (blk_pread(blk, 0, storage, rom_size) < 0) {
215 error_setg(errp, "failed to read the initial flash content");
216 return;
217 }
218
219 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
220 g_free(storage);
221 }
222
223 static void aspeed_board_init_flashes(AspeedSMCState *s,
224 const char *flashtype)
225 {
226 int i ;
227
228 for (i = 0; i < s->num_cs; ++i) {
229 AspeedSMCFlash *fl = &s->flashes[i];
230 DriveInfo *dinfo = drive_get_next(IF_MTD);
231 qemu_irq cs_line;
232
233 fl->flash = qdev_new(flashtype);
234 if (dinfo) {
235 qdev_prop_set_drive(fl->flash, "drive",
236 blk_by_legacy_dinfo(dinfo));
237 }
238 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
239
240 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
241 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
242 }
243 }
244
245 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
246 {
247 DeviceState *card;
248
249 card = qdev_new(TYPE_SD_CARD);
250 if (dinfo) {
251 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
252 &error_fatal);
253 }
254 qdev_realize_and_unref(card,
255 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
256 &error_fatal);
257 }
258
259 static void aspeed_machine_init(MachineState *machine)
260 {
261 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
262 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
263 AspeedSoCClass *sc;
264 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
265 ram_addr_t max_ram_size;
266 int i;
267 NICInfo *nd = &nd_table[0];
268
269 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
270 4 * GiB);
271 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
272
273 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
274
275 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
276
277 /*
278 * This will error out if isize is not supported by memory controller.
279 */
280 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", ram_size,
281 &error_fatal);
282
283 for (i = 0; i < sc->macs_num; i++) {
284 if ((amc->macs_mask & (1 << i)) && nd->used) {
285 qemu_check_nic_model(nd, TYPE_FTGMAC100);
286 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
287 nd++;
288 }
289 }
290
291 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
292 &error_abort);
293 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
294 &error_abort);
295 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
296 &error_abort);
297 object_property_set_link(OBJECT(&bmc->soc), "dram",
298 OBJECT(&bmc->ram_container), &error_abort);
299 if (machine->kernel_filename) {
300 /*
301 * When booting with a -kernel command line there is no u-boot
302 * that runs to unlock the SCU. In this case set the default to
303 * be unlocked as the kernel expects
304 */
305 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
306 ASPEED_SCU_PROT_KEY, &error_abort);
307 }
308 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
309
310 memory_region_add_subregion(get_system_memory(),
311 sc->memmap[ASPEED_SDRAM],
312 &bmc->ram_container);
313
314 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
315 &error_abort);
316 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
317 "max_ram", max_ram_size - ram_size);
318 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram);
319
320 aspeed_board_init_flashes(&bmc->soc.fmc, amc->fmc_model);
321 aspeed_board_init_flashes(&bmc->soc.spi[0], amc->spi_model);
322
323 /* Install first FMC flash content as a boot rom. */
324 if (drive0) {
325 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
326 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
327
328 /*
329 * create a ROM region using the default mapping window size of
330 * the flash module. The window size is 64MB for the AST2400
331 * SoC and 128MB for the AST2500 SoC, which is twice as big as
332 * needed by the flash modules of the Aspeed machines.
333 */
334 if (ASPEED_MACHINE(machine)->mmio_exec) {
335 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
336 &fl->mmio, 0, fl->size);
337 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
338 boot_rom);
339 } else {
340 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
341 fl->size, &error_abort);
342 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
343 boot_rom);
344 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
345 }
346 }
347
348 if (machine->kernel_filename && sc->num_cpus > 1) {
349 /* With no u-boot we must set up a boot stub for the secondary CPU */
350 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
351 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
352 0x80, &error_abort);
353 memory_region_add_subregion(get_system_memory(),
354 AST_SMP_MAILBOX_BASE, smpboot);
355
356 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
357 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
358 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
359 }
360
361 aspeed_board_binfo.ram_size = ram_size;
362 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
363 aspeed_board_binfo.nb_cpus = sc->num_cpus;
364
365 if (amc->i2c_init) {
366 amc->i2c_init(bmc);
367 }
368
369 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
370 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
371 }
372
373 if (bmc->soc.emmc.num_slots) {
374 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
375 }
376
377 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
378 }
379
380 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
381 {
382 AspeedSoCState *soc = &bmc->soc;
383 DeviceState *dev;
384 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
385
386 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
387 * enough to provide basic RTC features. Alarms will be missing */
388 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
389
390 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50,
391 eeprom_buf);
392
393 /* add a TMP423 temperature sensor */
394 dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
395 "tmp423", 0x4c);
396 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
397 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
398 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
399 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
400 }
401
402 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
403 {
404 AspeedSoCState *soc = &bmc->soc;
405 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
406
407 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50,
408 eeprom_buf);
409
410 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
411 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7),
412 TYPE_TMP105, 0x4d);
413
414 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
415 * plugged on the I2C bus header */
416 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
417 }
418
419 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
420 {
421 /* Start with some devices on our I2C busses */
422 ast2500_evb_i2c_init(bmc);
423 }
424
425 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
426 {
427 AspeedSoCState *soc = &bmc->soc;
428
429 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
430 * good enough */
431 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
432 }
433
434 static void swift_bmc_i2c_init(AspeedMachineState *bmc)
435 {
436 AspeedSoCState *soc = &bmc->soc;
437
438 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60);
439
440 /* The swift board expects a TMP275 but a TMP105 is compatible */
441 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48);
442 /* The swift board expects a pca9551 but a pca9552 is compatible */
443 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60);
444
445 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
446 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32);
447 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60);
448
449 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c);
450 /* The swift board expects a pca9539 but a pca9552 is compatible */
451 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74);
452
453 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c);
454 /* The swift board expects a pca9539 but a pca9552 is compatible */
455 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552",
456 0x74);
457
458 /* The swift board expects a TMP275 but a TMP105 is compatible */
459 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48);
460 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a);
461 }
462
463 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
464 {
465 AspeedSoCState *soc = &bmc->soc;
466
467 /* bus 2 : */
468 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), "tmp105", 0x48);
469 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), "tmp105", 0x49);
470 /* bus 2 : pca9546 @ 0x73 */
471
472 /* bus 3 : pca9548 @ 0x70 */
473
474 /* bus 4 : */
475 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
476 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), 0x54,
477 eeprom4_54);
478 /* PCA9539 @ 0x76, but PCA9552 is compatible */
479 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "pca9552", 0x76);
480 /* PCA9539 @ 0x77, but PCA9552 is compatible */
481 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "pca9552", 0x77);
482
483 /* bus 6 : */
484 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 6), "tmp105", 0x48);
485 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 6), "tmp105", 0x49);
486 /* bus 6 : pca9546 @ 0x73 */
487
488 /* bus 8 : */
489 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
490 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), 0x56,
491 eeprom8_56);
492 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60);
493 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x61);
494 /* bus 8 : adc128d818 @ 0x1d */
495 /* bus 8 : adc128d818 @ 0x1f */
496
497 /*
498 * bus 13 : pca9548 @ 0x71
499 * - channel 3:
500 * - tmm421 @ 0x4c
501 * - tmp421 @ 0x4e
502 * - tmp421 @ 0x4f
503 */
504
505 }
506
507 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
508 {
509 AspeedSoCState *soc = &bmc->soc;
510 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
511 DeviceState *dev;
512
513 /* Bus 3: TODO bmp280@77 */
514 /* Bus 3: TODO max31785@52 */
515 /* Bus 3: TODO dps310@76 */
516 dev = i2c_try_create_slave(TYPE_PCA9552, 0x60);
517 qdev_prop_set_string(dev, "description", "pca1");
518 i2c_realize_and_unref(dev, aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3),
519 &error_fatal);
520
521 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
522 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
523
524 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
525 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105,
526 0x4a);
527
528 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
529 * good enough */
530 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
531
532 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
533 eeprom_buf);
534 dev = i2c_try_create_slave(TYPE_PCA9552, 0x60);
535 qdev_prop_set_string(dev, "description", "pca0");
536 i2c_realize_and_unref(dev, aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11),
537 &error_fatal);
538 /* Bus 11: TODO ucd90160@64 */
539 }
540
541 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
542 {
543 return ASPEED_MACHINE(obj)->mmio_exec;
544 }
545
546 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
547 {
548 ASPEED_MACHINE(obj)->mmio_exec = value;
549 }
550
551 static void aspeed_machine_instance_init(Object *obj)
552 {
553 ASPEED_MACHINE(obj)->mmio_exec = false;
554 }
555
556 static void aspeed_machine_class_props_init(ObjectClass *oc)
557 {
558 object_class_property_add_bool(oc, "execute-in-place",
559 aspeed_get_mmio_exec,
560 aspeed_set_mmio_exec);
561 object_class_property_set_description(oc, "execute-in-place",
562 "boot directly from CE0 flash device");
563 }
564
565 static int aspeed_soc_num_cpus(const char *soc_name)
566 {
567 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
568 return sc->num_cpus;
569 }
570
571 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
572 {
573 MachineClass *mc = MACHINE_CLASS(oc);
574 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
575
576 mc->init = aspeed_machine_init;
577 mc->no_floppy = 1;
578 mc->no_cdrom = 1;
579 mc->no_parallel = 1;
580 mc->default_ram_id = "ram";
581 amc->macs_mask = ASPEED_MAC0_ON;
582
583 aspeed_machine_class_props_init(oc);
584 }
585
586 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
587 {
588 MachineClass *mc = MACHINE_CLASS(oc);
589 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
590
591 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
592 amc->soc_name = "ast2400-a1";
593 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
594 amc->fmc_model = "n25q256a";
595 amc->spi_model = "mx25l25635e";
596 amc->num_cs = 1;
597 amc->i2c_init = palmetto_bmc_i2c_init;
598 mc->default_ram_size = 256 * MiB;
599 mc->default_cpus = mc->min_cpus = mc->max_cpus =
600 aspeed_soc_num_cpus(amc->soc_name);
601 };
602
603 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
604 {
605 MachineClass *mc = MACHINE_CLASS(oc);
606 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
607
608 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
609 amc->soc_name = "ast2500-a1";
610 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
611 amc->fmc_model = "w25q256";
612 amc->spi_model = "mx25l25635e";
613 amc->num_cs = 1;
614 amc->i2c_init = ast2500_evb_i2c_init;
615 mc->default_ram_size = 512 * MiB;
616 mc->default_cpus = mc->min_cpus = mc->max_cpus =
617 aspeed_soc_num_cpus(amc->soc_name);
618 };
619
620 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
621 {
622 MachineClass *mc = MACHINE_CLASS(oc);
623 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
624
625 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
626 amc->soc_name = "ast2500-a1";
627 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
628 amc->fmc_model = "n25q256a";
629 amc->spi_model = "mx66l1g45g";
630 amc->num_cs = 2;
631 amc->i2c_init = romulus_bmc_i2c_init;
632 mc->default_ram_size = 512 * MiB;
633 mc->default_cpus = mc->min_cpus = mc->max_cpus =
634 aspeed_soc_num_cpus(amc->soc_name);
635 };
636
637 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
638 {
639 MachineClass *mc = MACHINE_CLASS(oc);
640 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
641
642 mc->desc = "OCP SonoraPass BMC (ARM1176)";
643 amc->soc_name = "ast2500-a1";
644 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
645 amc->fmc_model = "mx66l1g45g";
646 amc->spi_model = "mx66l1g45g";
647 amc->num_cs = 2;
648 amc->i2c_init = sonorapass_bmc_i2c_init;
649 mc->default_ram_size = 512 * MiB;
650 mc->default_cpus = mc->min_cpus = mc->max_cpus =
651 aspeed_soc_num_cpus(amc->soc_name);
652 };
653
654 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
655 {
656 MachineClass *mc = MACHINE_CLASS(oc);
657 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
658
659 mc->desc = "OpenPOWER Swift BMC (ARM1176)";
660 amc->soc_name = "ast2500-a1";
661 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
662 amc->fmc_model = "mx66l1g45g";
663 amc->spi_model = "mx66l1g45g";
664 amc->num_cs = 2;
665 amc->i2c_init = swift_bmc_i2c_init;
666 mc->default_ram_size = 512 * MiB;
667 mc->default_cpus = mc->min_cpus = mc->max_cpus =
668 aspeed_soc_num_cpus(amc->soc_name);
669 };
670
671 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
672 {
673 MachineClass *mc = MACHINE_CLASS(oc);
674 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
675
676 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
677 amc->soc_name = "ast2500-a1";
678 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
679 amc->fmc_model = "mx25l25635e";
680 amc->spi_model = "mx66l1g45g";
681 amc->num_cs = 2;
682 amc->i2c_init = witherspoon_bmc_i2c_init;
683 mc->default_ram_size = 512 * MiB;
684 mc->default_cpus = mc->min_cpus = mc->max_cpus =
685 aspeed_soc_num_cpus(amc->soc_name);
686 };
687
688 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
689 {
690 MachineClass *mc = MACHINE_CLASS(oc);
691 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
692
693 mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
694 amc->soc_name = "ast2600-a1";
695 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
696 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
697 amc->fmc_model = "w25q512jv";
698 amc->spi_model = "mx66u51235f";
699 amc->num_cs = 1;
700 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
701 amc->i2c_init = ast2600_evb_i2c_init;
702 mc->default_ram_size = 1 * GiB;
703 mc->default_cpus = mc->min_cpus = mc->max_cpus =
704 aspeed_soc_num_cpus(amc->soc_name);
705 };
706
707 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
708 {
709 MachineClass *mc = MACHINE_CLASS(oc);
710 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
711
712 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
713 amc->soc_name = "ast2600-a1";
714 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
715 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
716 amc->fmc_model = "mx66l1g45g";
717 amc->spi_model = "mx66l1g45g";
718 amc->num_cs = 2;
719 amc->macs_mask = ASPEED_MAC2_ON;
720 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
721 mc->default_ram_size = 1 * GiB;
722 mc->default_cpus = mc->min_cpus = mc->max_cpus =
723 aspeed_soc_num_cpus(amc->soc_name);
724 };
725
726 static const TypeInfo aspeed_machine_types[] = {
727 {
728 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
729 .parent = TYPE_ASPEED_MACHINE,
730 .class_init = aspeed_machine_palmetto_class_init,
731 }, {
732 .name = MACHINE_TYPE_NAME("ast2500-evb"),
733 .parent = TYPE_ASPEED_MACHINE,
734 .class_init = aspeed_machine_ast2500_evb_class_init,
735 }, {
736 .name = MACHINE_TYPE_NAME("romulus-bmc"),
737 .parent = TYPE_ASPEED_MACHINE,
738 .class_init = aspeed_machine_romulus_class_init,
739 }, {
740 .name = MACHINE_TYPE_NAME("swift-bmc"),
741 .parent = TYPE_ASPEED_MACHINE,
742 .class_init = aspeed_machine_swift_class_init,
743 }, {
744 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
745 .parent = TYPE_ASPEED_MACHINE,
746 .class_init = aspeed_machine_sonorapass_class_init,
747 }, {
748 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
749 .parent = TYPE_ASPEED_MACHINE,
750 .class_init = aspeed_machine_witherspoon_class_init,
751 }, {
752 .name = MACHINE_TYPE_NAME("ast2600-evb"),
753 .parent = TYPE_ASPEED_MACHINE,
754 .class_init = aspeed_machine_ast2600_evb_class_init,
755 }, {
756 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
757 .parent = TYPE_ASPEED_MACHINE,
758 .class_init = aspeed_machine_tacoma_class_init,
759 }, {
760 .name = TYPE_ASPEED_MACHINE,
761 .parent = TYPE_MACHINE,
762 .instance_size = sizeof(AspeedMachineState),
763 .instance_init = aspeed_machine_instance_init,
764 .class_size = sizeof(AspeedMachineClass),
765 .class_init = aspeed_machine_class_init,
766 .abstract = true,
767 }
768 };
769
770 DEFINE_TYPES(aspeed_machine_types)
AR7 emulation for QEMU