2 * QEMU 16450 / 16550 UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
26 #include "char/char.h"
27 #include "migration/register.h" /* register_savevm_live */
31 #define SERIAL_VERSION 2
35 //~ #define DEBUG_SERIAL
37 #if defined(DEBUG_SERIAL)
38 # define logout(fmt, ...) fprintf(stderr, "UART\t%-24s" fmt, __func__, ##__VA_ARGS__)
40 # define logout(fmt, ...) ((void)0)
43 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
45 //~ #define UART_IER_BIT7 0x80 /* FIFOs enabled */
46 //~ #define UART_IER_BIT6 0x40 /* FIFOs enabled */
47 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
48 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
49 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
50 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
52 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
53 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
55 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
56 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
57 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
58 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
59 #if defined(CONFIG_16550A)
60 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
62 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functioning */
63 #define UART_IIR_FE 0xC0 /* Fifo enabled */
67 * These are the definitions for the Modem Control Register
69 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
70 #define UART_MCR_OUT2 0x08 /* Out2 complement */
71 #define UART_MCR_OUT1 0x04 /* Out1 complement */
72 #define UART_MCR_RTS 0x02 /* RTS complement */
73 #define UART_MCR_DTR 0x01 /* DTR complement */
76 * These are the definitions for the Modem Status Register
78 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
79 #define UART_MSR_RI 0x40 /* Ring Indicator */
80 #define UART_MSR_DSR 0x20 /* Data Set Ready */
81 #define UART_MSR_CTS 0x10 /* Clear to Send */
82 #define UART_MSR_DDCD 0x08 /* Delta DCD */
83 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
84 #define UART_MSR_DDSR 0x02 /* Delta DSR */
85 #define UART_MSR_DCTS 0x01 /* Delta CTS */
86 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
88 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
89 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
90 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
91 #define UART_LSR_FE 0x08 /* Frame error indicator */
92 #define UART_LSR_PE 0x04 /* Parity error indicator */
93 #define UART_LSR_OE 0x02 /* Overrun error indicator */
94 #define UART_LSR_DR 0x01 /* Receiver data ready */
96 #if defined(CONFIG_16550A)
99 * These are the definitions for the Fifo Control Register
102 #define UART_FCR_ITL_MASQ 0xC0 /* Masq for Interrupt Trigger Level */
104 #define UART_FCR_ITL_1 0x00 /* 1 byte Interrupt Trigger Level */
105 #define UART_FCR_ITL_4 0x40 /* 4 bytes Interrupt Trigger Level */
106 #define UART_FCR_ITL_8 0x80 /* 8 bytes Interrupt Trigger Level */
107 #define UART_FCR_ITL_14 0xC0 /* 14 bytes Interrupt Trigger Level */
109 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
110 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
111 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
112 #define UART_FCR_FE 0x01 /* FIFO Enable */
114 #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
118 static int serial_instance
;
127 uint8_t rbr
; /* receive register */
129 uint8_t iir
; /* read only */
130 uint8_t fcr
; /* write only */
133 uint8_t lsr
; /* read only */
134 uint8_t msr
; /* read only */
136 /* NOTE: this hidden state is necessary for tx irq generation as
137 it can be reset while reading iir */
141 int last_break_enable
;
144 emulation_t emulation
;
146 uint8_t fifo
[UART_FIFO_LENGTH
];
149 static void serial_update_irq(SerialState
*s
)
151 if ((s
->lsr
& UART_LSR_DR
) && (s
->ier
& UART_IER_RDI
)) {
152 logout("rx interrupt\n");
153 s
->iir
= UART_IIR_RDI
;
154 qemu_irq_raise(s
->irq
);
155 } else if (s
->thr_ipending
&& (s
->ier
& UART_IER_THRI
)) {
156 logout("tx interrupt\n");
157 s
->iir
= UART_IIR_THRI
;
158 qemu_irq_raise(s
->irq
);
160 logout("no interrupt\n");
161 s
->iir
= UART_IIR_NO_INT
;
162 qemu_irq_lower(s
->irq
);
166 static void serial_update_parameters(SerialState
*s
)
168 int speed
, parity
, data_bits
, stop_bits
;
169 QEMUSerialSetParams ssp
;
183 data_bits
= (s
->lcr
& 0x03) + 5;
186 speed
= s
->frequency
/ s
->divider
;
189 ssp
.data_bits
= data_bits
;
190 ssp
.stop_bits
= stop_bits
;
191 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
194 "uart irq=%p divider=%d speed=%d parity=%c data=%d stop=%d (%s)\n",
195 s
->irq
, s
->divider
, speed
, parity
, data_bits
, stop_bits
,
200 void serial_write(void *opaque
, uint32_t addr
, uint32_t val
)
202 SerialState
*s
= opaque
;
207 logout("addr=0x%02x val=0x%02x\n", addr
, val
);
211 if (s
->lcr
& UART_LCR_DLAB
) {
212 s
->divider
= (s
->divider
& 0xff00) | val
;
213 serial_update_parameters(s
);
216 s
->lsr
&= ~UART_LSR_THRE
;
217 serial_update_irq(s
);
219 qemu_chr_fe_write(s
->chr
, &ch
, 1);
221 s
->lsr
|= UART_LSR_THRE
;
222 s
->lsr
|= UART_LSR_TEMT
;
223 serial_update_irq(s
);
227 if (s
->lcr
& UART_LCR_DLAB
) {
228 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
229 serial_update_parameters(s
);
232 if (s
->lsr
& UART_LSR_THRE
) {
235 serial_update_irq(s
);
239 /* fifo control register */
240 if (s
->emulation
== uart16550
) {
241 if (!(s
->fcr
& 0x01) && (val
& 0x01)) {
242 logout("enable fifo\n");
243 } else if ((s
->fcr
& 0x01) && !(val
& 0x01)) {
244 logout("disable fifo\n");
245 memset(s
->fifo
, 0, sizeof(s
->fifo
));
247 if (val
& UART_FCR_FE
) {
248 s
->iir
|= UART_IIR_FE
;
250 s
->iir
&= ~UART_IIR_FE
;
254 //~ s->lsr |= UART_LSR_THRE;
255 //~ s->lsr |= UART_LSR_TEMT;
256 serial_update_irq(s
);
263 serial_update_parameters(s
);
264 break_enable
= (val
>> 6) & 1;
265 if (break_enable
!= s
->last_break_enable
) {
266 s
->last_break_enable
= break_enable
;
267 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
285 uint32_t serial_read(void *opaque
, uint32_t addr
)
287 SerialState
*s
= opaque
;
295 if (s
->lcr
& UART_LCR_DLAB
) {
296 ret
= s
->divider
& 0xff;
299 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
300 serial_update_irq(s
);
304 if (s
->lcr
& UART_LCR_DLAB
) {
305 ret
= (s
->divider
>> 8) & 0xff;
312 /* reset THR pending bit */
313 if ((ret
& 0x7) == UART_IIR_THRI
)
315 serial_update_irq(s
);
327 if (s
->mcr
& UART_MCR_LOOP
) {
328 /* in loopback, the modem output pins are connected to the
330 ret
= (s
->mcr
& 0x0c) << 4;
331 ret
|= (s
->mcr
& 0x02) << 3;
332 ret
|= (s
->mcr
& 0x01) << 5;
341 logout("addr=0x%02x val=0x%02x\n", addr
, ret
);
345 static int serial_can_receive(SerialState
*s
)
347 return !(s
->lsr
& UART_LSR_DR
);
350 static void serial_receive_byte(SerialState
*s
, int ch
)
353 s
->lsr
|= UART_LSR_DR
;
354 serial_update_irq(s
);
357 static void serial_receive_break(SerialState
*s
)
360 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
361 serial_update_irq(s
);
364 static int serial_can_receive1(void *opaque
)
366 SerialState
*s
= opaque
;
367 return serial_can_receive(s
);
370 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
372 SerialState
*s
= opaque
;
373 serial_receive_byte(s
, buf
[0]);
376 static void serial_event(void *opaque
, int event
)
378 SerialState
*s
= opaque
;
379 if (event
== CHR_EVENT_BREAK
)
380 serial_receive_break(s
);
383 static void serial_save(QEMUFile
*f
, void *opaque
)
385 SerialState
*s
= opaque
;
387 qemu_put_be16s(f
,&s
->divider
);
388 qemu_put_8s(f
,&s
->rbr
);
389 qemu_put_8s(f
,&s
->ier
);
390 qemu_put_8s(f
,&s
->iir
);
391 qemu_put_8s(f
,&s
->lcr
);
392 qemu_put_8s(f
,&s
->mcr
);
393 qemu_put_8s(f
,&s
->lsr
);
394 qemu_put_8s(f
,&s
->msr
);
395 qemu_put_8s(f
,&s
->scr
);
398 static int serial_load(QEMUFile
*f
, void *opaque
, int version_id
)
400 SerialState
*s
= opaque
;
402 if(version_id
> SERIAL_VERSION
)
405 if(version_id
>= SERIAL_VERSION
)
406 qemu_get_be16s(f
,&s
->divider
);
408 s
->divider
= qemu_get_byte(f
);
409 qemu_get_8s(f
,&s
->rbr
);
410 qemu_get_8s(f
,&s
->ier
);
411 qemu_get_8s(f
,&s
->iir
);
412 qemu_get_8s(f
,&s
->lcr
);
413 qemu_get_8s(f
,&s
->mcr
);
414 qemu_get_8s(f
,&s
->lsr
);
415 qemu_get_8s(f
,&s
->msr
);
416 qemu_get_8s(f
,&s
->scr
);
421 static void serial_reset(void *opaque
)
423 SerialState
*s
= (SerialState
*)opaque
;
425 s
->iir
= UART_IIR_NO_INT
;
429 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
430 s
->msr
= UART_MSR_DCD
| UART_MSR_DSR
| UART_MSR_CTS
;
433 void serial_frequency(SerialState
*s
, uint32_t frequency
)
435 s
->frequency
= frequency
;
438 static SaveVMHandlers savevm_serial
= {
439 .save_state
= serial_save
,
440 .load_state
= serial_load
443 /* If fd is zero, it means that the serial device uses the console */
444 SerialState
*serial_16450_init(int base
, qemu_irq irq
, Chardev
*chr
)
448 fprintf(stderr
, "%s:%u\n", __FILE__
, __LINE__
);
450 s
= g_malloc0(sizeof(SerialState
));
455 s
->emulation
= uart16450
;
456 s
->frequency
= 115200;
459 register_savevm_live("serial", serial_instance
, SERIAL_VERSION
,
464 register_ioport_write(base
, 8, 1, serial_write
, s
);
465 register_ioport_read(base
, 8, 1, serial_read
, s
);
468 qemu_chr_fe_set_handlers(chr
, serial_can_receive1
, serial_receive1
,
469 serial_event
, s
, NULL
);
470 qemu_register_reset(serial_reset
, s
);
475 SerialState
*serial_16550_init(int base
, qemu_irq irq
, Chardev
*chr
)
478 s
= serial_16450_init(base
, irq
, chr
);
479 s
->emulation
= uart16550
;