2 * QEMU 16550A UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/char/serial.h"
28 #include "chardev/char-serial.h"
29 #include "qapi/error.h"
30 #include "qemu/timer.h"
31 #include "exec/address-spaces.h"
32 #include "qemu/error-report.h"
34 //#define DEBUG_SERIAL
36 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
38 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
39 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
40 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
41 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
43 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
44 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
46 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
47 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
48 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
49 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
50 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
52 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
53 #define UART_IIR_FE 0xC0 /* Fifo enabled */
56 * These are the definitions for the Modem Control Register
58 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
59 #define UART_MCR_OUT2 0x08 /* Out2 complement */
60 #define UART_MCR_OUT1 0x04 /* Out1 complement */
61 #define UART_MCR_RTS 0x02 /* RTS complement */
62 #define UART_MCR_DTR 0x01 /* DTR complement */
65 * These are the definitions for the Modem Status Register
67 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
68 #define UART_MSR_RI 0x40 /* Ring Indicator */
69 #define UART_MSR_DSR 0x20 /* Data Set Ready */
70 #define UART_MSR_CTS 0x10 /* Clear to Send */
71 #define UART_MSR_DDCD 0x08 /* Delta DCD */
72 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
73 #define UART_MSR_DDSR 0x02 /* Delta DSR */
74 #define UART_MSR_DCTS 0x01 /* Delta CTS */
75 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
77 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
78 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
79 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
80 #define UART_LSR_FE 0x08 /* Frame error indicator */
81 #define UART_LSR_PE 0x04 /* Parity error indicator */
82 #define UART_LSR_OE 0x02 /* Overrun error indicator */
83 #define UART_LSR_DR 0x01 /* Receiver data ready */
84 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
86 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
88 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
89 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
90 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
91 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
93 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
94 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
95 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
96 #define UART_FCR_FE 0x01 /* FIFO Enable */
98 #define MAX_XMIT_RETRY 4
101 #define DPRINTF(fmt, ...) \
102 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
104 #define DPRINTF(fmt, ...) \
108 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
);
109 static void serial_xmit(SerialState
*s
);
111 static inline void recv_fifo_put(SerialState
*s
, uint8_t chr
)
113 /* Receive overruns do not overwrite FIFO contents. */
114 if (!fifo8_is_full(&s
->recv_fifo
)) {
115 fifo8_push(&s
->recv_fifo
, chr
);
117 s
->lsr
|= UART_LSR_OE
;
121 static void serial_update_irq(SerialState
*s
)
123 uint8_t tmp_iir
= UART_IIR_NO_INT
;
125 if ((s
->ier
& UART_IER_RLSI
) && (s
->lsr
& UART_LSR_INT_ANY
)) {
126 tmp_iir
= UART_IIR_RLSI
;
127 } else if ((s
->ier
& UART_IER_RDI
) && s
->timeout_ipending
) {
128 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
129 * this is not in the specification but is observed on existing
131 tmp_iir
= UART_IIR_CTI
;
132 } else if ((s
->ier
& UART_IER_RDI
) && (s
->lsr
& UART_LSR_DR
) &&
133 (!(s
->fcr
& UART_FCR_FE
) ||
134 s
->recv_fifo
.num
>= s
->recv_fifo_itl
)) {
135 tmp_iir
= UART_IIR_RDI
;
136 } else if ((s
->ier
& UART_IER_THRI
) && s
->thr_ipending
) {
137 tmp_iir
= UART_IIR_THRI
;
138 } else if ((s
->ier
& UART_IER_MSI
) && (s
->msr
& UART_MSR_ANY_DELTA
)) {
139 tmp_iir
= UART_IIR_MSI
;
142 s
->iir
= tmp_iir
| (s
->iir
& 0xF0);
144 if (tmp_iir
!= UART_IIR_NO_INT
) {
145 qemu_irq_raise(s
->irq
);
147 qemu_irq_lower(s
->irq
);
151 static void serial_update_parameters(SerialState
*s
)
153 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
154 QEMUSerialSetParams ssp
;
156 if (s
->divider
== 0 || s
->divider
> s
->baudbase
) {
177 data_bits
= (s
->lcr
& 0x03) + 5;
178 frame_size
+= data_bits
+ stop_bits
;
179 speed
= s
->baudbase
/ s
->divider
;
182 ssp
.data_bits
= data_bits
;
183 ssp
.stop_bits
= stop_bits
;
184 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
185 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
187 DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
188 speed
, parity
, data_bits
, stop_bits
);
191 static void serial_update_msl(SerialState
*s
)
196 timer_del(s
->modem_status_poll
);
198 if (qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_GET_TIOCM
,
199 &flags
) == -ENOTSUP
) {
206 s
->msr
= (flags
& CHR_TIOCM_CTS
) ? s
->msr
| UART_MSR_CTS
: s
->msr
& ~UART_MSR_CTS
;
207 s
->msr
= (flags
& CHR_TIOCM_DSR
) ? s
->msr
| UART_MSR_DSR
: s
->msr
& ~UART_MSR_DSR
;
208 s
->msr
= (flags
& CHR_TIOCM_CAR
) ? s
->msr
| UART_MSR_DCD
: s
->msr
& ~UART_MSR_DCD
;
209 s
->msr
= (flags
& CHR_TIOCM_RI
) ? s
->msr
| UART_MSR_RI
: s
->msr
& ~UART_MSR_RI
;
211 if (s
->msr
!= omsr
) {
213 s
->msr
= s
->msr
| ((s
->msr
>> 4) ^ (omsr
>> 4));
214 /* UART_MSR_TERI only if change was from 1 -> 0 */
215 if ((s
->msr
& UART_MSR_TERI
) && !(omsr
& UART_MSR_RI
))
216 s
->msr
&= ~UART_MSR_TERI
;
217 serial_update_irq(s
);
220 /* The real 16550A apparently has a 250ns response latency to line status changes.
221 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
224 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
225 NANOSECONDS_PER_SECOND
/ 100);
229 static gboolean
serial_watch_cb(GIOChannel
*chan
, GIOCondition cond
,
232 SerialState
*s
= opaque
;
238 static void serial_xmit(SerialState
*s
)
241 assert(!(s
->lsr
& UART_LSR_TEMT
));
242 if (s
->tsr_retry
== 0) {
243 assert(!(s
->lsr
& UART_LSR_THRE
));
245 if (s
->fcr
& UART_FCR_FE
) {
246 assert(!fifo8_is_empty(&s
->xmit_fifo
));
247 s
->tsr
= fifo8_pop(&s
->xmit_fifo
);
248 if (!s
->xmit_fifo
.num
) {
249 s
->lsr
|= UART_LSR_THRE
;
253 s
->lsr
|= UART_LSR_THRE
;
255 if ((s
->lsr
& UART_LSR_THRE
) && !s
->thr_ipending
) {
257 serial_update_irq(s
);
261 if (s
->mcr
& UART_MCR_LOOP
) {
262 /* in loopback mode, say that we just received a char */
263 serial_receive1(s
, &s
->tsr
, 1);
264 } else if (qemu_chr_fe_write(&s
->chr
, &s
->tsr
, 1) != 1 &&
265 s
->tsr_retry
< MAX_XMIT_RETRY
) {
266 assert(s
->watch_tag
== 0);
268 qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
270 if (s
->watch_tag
> 0) {
277 /* Transmit another byte if it is already available. It is only
278 possible when FIFO is enabled and not empty. */
279 } while (!(s
->lsr
& UART_LSR_THRE
));
281 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
282 s
->lsr
|= UART_LSR_TEMT
;
286 is_load flag means, that value is set while loading VM state
287 and interrupt should not be invoked */
288 static void serial_write_fcr(SerialState
*s
, uint8_t val
)
290 /* Set fcr - val only has the bits that are supposed to "stick" */
293 if (val
& UART_FCR_FE
) {
294 s
->iir
|= UART_IIR_FE
;
295 /* Set recv_fifo trigger Level */
296 switch (val
& 0xC0) {
298 s
->recv_fifo_itl
= 1;
301 s
->recv_fifo_itl
= 4;
304 s
->recv_fifo_itl
= 8;
307 s
->recv_fifo_itl
= 14;
311 s
->iir
&= ~UART_IIR_FE
;
315 static void serial_update_tiocm(SerialState
*s
)
319 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_GET_TIOCM
, &flags
);
321 flags
&= ~(CHR_TIOCM_RTS
| CHR_TIOCM_DTR
);
323 if (s
->mcr
& UART_MCR_RTS
) {
324 flags
|= CHR_TIOCM_RTS
;
326 if (s
->mcr
& UART_MCR_DTR
) {
327 flags
|= CHR_TIOCM_DTR
;
330 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_TIOCM
, &flags
);
333 static void serial_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
336 SerialState
*s
= opaque
;
341 //~ fprintf(stderr, "%s(%p,0x%08x)\n", __func__, opaque, addr);
343 DPRINTF("write addr=0x%" HWADDR_PRIx
" val=0x%" PRIx64
"\n", addr
, val
);
347 if (s
->lcr
& UART_LCR_DLAB
) {
348 s
->divider
= (s
->divider
& 0xff00) | val
;
349 serial_update_parameters(s
);
351 s
->thr
= (uint8_t) val
;
352 if(s
->fcr
& UART_FCR_FE
) {
353 /* xmit overruns overwrite data, so make space if needed */
354 if (fifo8_is_full(&s
->xmit_fifo
)) {
355 fifo8_pop(&s
->xmit_fifo
);
357 fifo8_push(&s
->xmit_fifo
, s
->thr
);
360 s
->lsr
&= ~UART_LSR_THRE
;
361 s
->lsr
&= ~UART_LSR_TEMT
;
362 serial_update_irq(s
);
363 if (s
->tsr_retry
== 0) {
369 if (s
->lcr
& UART_LCR_DLAB
) {
370 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
371 serial_update_parameters(s
);
373 uint8_t changed
= (s
->ier
^ val
) & 0x0f;
375 /* If the backend device is a real serial port, turn polling of the modem
376 * status lines on physical port on or off depending on UART_IER_MSI state.
378 if ((changed
& UART_IER_MSI
) && s
->poll_msl
>= 0) {
379 if (s
->ier
& UART_IER_MSI
) {
381 serial_update_msl(s
);
383 timer_del(s
->modem_status_poll
);
388 /* Turning on the THRE interrupt on IER can trigger the interrupt
389 * if LSR.THRE=1, even if it had been masked before by reading IIR.
390 * This is not in the datasheet, but Windows relies on it. It is
391 * unclear if THRE has to be resampled every time THRI becomes
392 * 1, or only on the rising edge. Bochs does the latter, and Windows
393 * always toggles IER to all zeroes and back to all ones, so do the
396 * If IER.THRI is zero, thr_ipending is not used. Set it to zero
397 * so that the thr_ipending subsection is not migrated.
399 if (changed
& UART_IER_THRI
) {
400 if ((s
->ier
& UART_IER_THRI
) && (s
->lsr
& UART_LSR_THRE
)) {
408 serial_update_irq(s
);
413 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
414 if ((val
^ s
->fcr
) & UART_FCR_FE
) {
415 val
|= UART_FCR_XFR
| UART_FCR_RFR
;
420 if (val
& UART_FCR_RFR
) {
421 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
422 timer_del(s
->fifo_timeout_timer
);
423 s
->timeout_ipending
= 0;
424 fifo8_reset(&s
->recv_fifo
);
427 if (val
& UART_FCR_XFR
) {
428 s
->lsr
|= UART_LSR_THRE
;
430 fifo8_reset(&s
->xmit_fifo
);
433 serial_write_fcr(s
, val
& 0xC9);
434 serial_update_irq(s
);
440 serial_update_parameters(s
);
441 break_enable
= (val
>> 6) & 1;
442 if (break_enable
!= s
->last_break_enable
) {
443 s
->last_break_enable
= break_enable
;
444 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
451 int old_mcr
= s
->mcr
;
453 if (val
& UART_MCR_LOOP
)
456 if (s
->poll_msl
>= 0 && old_mcr
!= s
->mcr
) {
457 serial_update_tiocm(s
);
458 /* Update the modem status after a one-character-send wait-time, since there may be a response
459 from the device/computer at the other end of the serial line */
460 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
);
474 static uint64_t serial_ioport_read(void *opaque
, hwaddr addr
, unsigned size
)
476 SerialState
*s
= opaque
;
482 //~ fprintf(stderr, "%s(%p,0x%08x)\n", __func__, opaque, addr);
487 if (s
->lcr
& UART_LCR_DLAB
) {
488 ret
= s
->divider
& 0xff;
490 if(s
->fcr
& UART_FCR_FE
) {
491 ret
= fifo8_is_empty(&s
->recv_fifo
) ?
492 0 : fifo8_pop(&s
->recv_fifo
);
493 if (s
->recv_fifo
.num
== 0) {
494 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
496 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
498 s
->timeout_ipending
= 0;
501 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
503 serial_update_irq(s
);
504 if (!(s
->mcr
& UART_MCR_LOOP
)) {
505 /* in loopback mode, don't receive any data */
506 qemu_chr_fe_accept_input(&s
->chr
);
511 if (s
->lcr
& UART_LCR_DLAB
) {
512 ret
= (s
->divider
>> 8) & 0xff;
519 if ((ret
& UART_IIR_ID
) == UART_IIR_THRI
) {
521 serial_update_irq(s
);
532 /* Clear break and overrun interrupts */
533 if (s
->lsr
& (UART_LSR_BI
|UART_LSR_OE
)) {
534 s
->lsr
&= ~(UART_LSR_BI
|UART_LSR_OE
);
535 serial_update_irq(s
);
539 if (s
->mcr
& UART_MCR_LOOP
) {
540 /* in loopback, the modem output pins are connected to the
542 ret
= (s
->mcr
& 0x0c) << 4;
543 ret
|= (s
->mcr
& 0x02) << 3;
544 ret
|= (s
->mcr
& 0x01) << 5;
546 if (s
->poll_msl
>= 0)
547 serial_update_msl(s
);
549 /* Clear delta bits & msr int after read, if they were set */
550 if (s
->msr
& UART_MSR_ANY_DELTA
) {
552 serial_update_irq(s
);
560 DPRINTF("read addr=0x%" HWADDR_PRIx
" val=0x%02x\n", addr
, ret
);
564 static int serial_can_receive(SerialState
*s
)
566 //~ fprintf(stderr, "%s:%u\n", __FILE__, __LINE__);
567 if(s
->fcr
& UART_FCR_FE
) {
568 if (s
->recv_fifo
.num
< UART_FIFO_LENGTH
) {
570 * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
571 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
572 * effect will be to almost always fill the fifo completely before
573 * the guest has a chance to respond, effectively overriding the ITL
574 * that the guest has set.
576 return (s
->recv_fifo
.num
<= s
->recv_fifo_itl
) ?
577 s
->recv_fifo_itl
- s
->recv_fifo
.num
: 1;
582 return !(s
->lsr
& UART_LSR_DR
);
586 static void serial_receive_break(SerialState
*s
)
589 /* When the LSR_DR is set a null byte is pushed into the fifo */
590 recv_fifo_put(s
, '\0');
591 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
592 serial_update_irq(s
);
595 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
596 static void fifo_timeout_int (void *opaque
) {
597 SerialState
*s
= opaque
;
598 if (s
->recv_fifo
.num
) {
599 s
->timeout_ipending
= 1;
600 serial_update_irq(s
);
604 static int serial_can_receive1(void *opaque
)
606 SerialState
*s
= opaque
;
607 return serial_can_receive(s
);
610 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
612 SerialState
*s
= opaque
;
615 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER
);
617 if(s
->fcr
& UART_FCR_FE
) {
619 for (i
= 0; i
< size
; i
++) {
620 recv_fifo_put(s
, buf
[i
]);
622 s
->lsr
|= UART_LSR_DR
;
623 /* call the timeout receive callback in 4 char transmit time */
624 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
626 if (s
->lsr
& UART_LSR_DR
)
627 s
->lsr
|= UART_LSR_OE
;
629 s
->lsr
|= UART_LSR_DR
;
631 serial_update_irq(s
);
634 static void serial_event(void *opaque
, int event
)
636 SerialState
*s
= opaque
;
637 DPRINTF("event %x\n", event
);
638 if (event
== CHR_EVENT_BREAK
)
639 serial_receive_break(s
);
642 static int serial_pre_save(void *opaque
)
644 SerialState
*s
= opaque
;
645 s
->fcr_vmstate
= s
->fcr
;
650 static int serial_pre_load(void *opaque
)
652 SerialState
*s
= opaque
;
653 s
->thr_ipending
= -1;
658 static int serial_post_load(void *opaque
, int version_id
)
660 SerialState
*s
= opaque
;
662 if (version_id
< 3) {
665 if (s
->thr_ipending
== -1) {
666 s
->thr_ipending
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
669 if (s
->tsr_retry
> 0) {
670 /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */
671 if (s
->lsr
& UART_LSR_TEMT
) {
672 error_report("inconsistent state in serial device "
673 "(tsr empty, tsr_retry=%d", s
->tsr_retry
);
677 if (s
->tsr_retry
> MAX_XMIT_RETRY
) {
678 s
->tsr_retry
= MAX_XMIT_RETRY
;
681 assert(s
->watch_tag
== 0);
682 s
->watch_tag
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
685 /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */
686 if (!(s
->lsr
& UART_LSR_TEMT
)) {
687 error_report("inconsistent state in serial device "
688 "(tsr not empty, tsr_retry=0");
693 s
->last_break_enable
= (s
->lcr
>> 6) & 1;
694 /* Initialize fcr via setter to perform essential side-effects */
695 serial_write_fcr(s
, s
->fcr_vmstate
);
696 serial_update_parameters(s
);
700 static bool serial_thr_ipending_needed(void *opaque
)
702 SerialState
*s
= opaque
;
704 if (s
->ier
& UART_IER_THRI
) {
705 bool expected_value
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
706 return s
->thr_ipending
!= expected_value
;
708 /* LSR.THRE will be sampled again when the interrupt is
709 * enabled. thr_ipending is not used in this case, do
716 static const VMStateDescription vmstate_serial_thr_ipending
= {
717 .name
= "serial/thr_ipending",
719 .minimum_version_id
= 1,
720 .needed
= serial_thr_ipending_needed
,
721 .fields
= (VMStateField
[]) {
722 VMSTATE_INT32(thr_ipending
, SerialState
),
723 VMSTATE_END_OF_LIST()
727 static bool serial_tsr_needed(void *opaque
)
729 SerialState
*s
= (SerialState
*)opaque
;
730 return s
->tsr_retry
!= 0;
733 static const VMStateDescription vmstate_serial_tsr
= {
734 .name
= "serial/tsr",
736 .minimum_version_id
= 1,
737 .needed
= serial_tsr_needed
,
738 .fields
= (VMStateField
[]) {
739 VMSTATE_UINT32(tsr_retry
, SerialState
),
740 VMSTATE_UINT8(thr
, SerialState
),
741 VMSTATE_UINT8(tsr
, SerialState
),
742 VMSTATE_END_OF_LIST()
746 static bool serial_recv_fifo_needed(void *opaque
)
748 SerialState
*s
= (SerialState
*)opaque
;
749 return !fifo8_is_empty(&s
->recv_fifo
);
753 static const VMStateDescription vmstate_serial_recv_fifo
= {
754 .name
= "serial/recv_fifo",
756 .minimum_version_id
= 1,
757 .needed
= serial_recv_fifo_needed
,
758 .fields
= (VMStateField
[]) {
759 VMSTATE_STRUCT(recv_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
760 VMSTATE_END_OF_LIST()
764 static bool serial_xmit_fifo_needed(void *opaque
)
766 SerialState
*s
= (SerialState
*)opaque
;
767 return !fifo8_is_empty(&s
->xmit_fifo
);
770 static const VMStateDescription vmstate_serial_xmit_fifo
= {
771 .name
= "serial/xmit_fifo",
773 .minimum_version_id
= 1,
774 .needed
= serial_xmit_fifo_needed
,
775 .fields
= (VMStateField
[]) {
776 VMSTATE_STRUCT(xmit_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
777 VMSTATE_END_OF_LIST()
781 static bool serial_fifo_timeout_timer_needed(void *opaque
)
783 SerialState
*s
= (SerialState
*)opaque
;
784 return timer_pending(s
->fifo_timeout_timer
);
787 static const VMStateDescription vmstate_serial_fifo_timeout_timer
= {
788 .name
= "serial/fifo_timeout_timer",
790 .minimum_version_id
= 1,
791 .needed
= serial_fifo_timeout_timer_needed
,
792 .fields
= (VMStateField
[]) {
793 VMSTATE_TIMER_PTR(fifo_timeout_timer
, SerialState
),
794 VMSTATE_END_OF_LIST()
798 static bool serial_timeout_ipending_needed(void *opaque
)
800 SerialState
*s
= (SerialState
*)opaque
;
801 return s
->timeout_ipending
!= 0;
804 static const VMStateDescription vmstate_serial_timeout_ipending
= {
805 .name
= "serial/timeout_ipending",
807 .minimum_version_id
= 1,
808 .needed
= serial_timeout_ipending_needed
,
809 .fields
= (VMStateField
[]) {
810 VMSTATE_INT32(timeout_ipending
, SerialState
),
811 VMSTATE_END_OF_LIST()
815 static bool serial_poll_needed(void *opaque
)
817 SerialState
*s
= (SerialState
*)opaque
;
818 return s
->poll_msl
>= 0;
821 static const VMStateDescription vmstate_serial_poll
= {
822 .name
= "serial/poll",
824 .needed
= serial_poll_needed
,
825 .minimum_version_id
= 1,
826 .fields
= (VMStateField
[]) {
827 VMSTATE_INT32(poll_msl
, SerialState
),
828 VMSTATE_TIMER_PTR(modem_status_poll
, SerialState
),
829 VMSTATE_END_OF_LIST()
833 const VMStateDescription vmstate_serial
= {
836 .minimum_version_id
= 2,
837 .pre_save
= serial_pre_save
,
838 .pre_load
= serial_pre_load
,
839 .post_load
= serial_post_load
,
840 .fields
= (VMStateField
[]) {
841 VMSTATE_UINT16_V(divider
, SerialState
, 2),
842 VMSTATE_UINT8(rbr
, SerialState
),
843 VMSTATE_UINT8(ier
, SerialState
),
844 VMSTATE_UINT8(iir
, SerialState
),
845 VMSTATE_UINT8(lcr
, SerialState
),
846 VMSTATE_UINT8(mcr
, SerialState
),
847 VMSTATE_UINT8(lsr
, SerialState
),
848 VMSTATE_UINT8(msr
, SerialState
),
849 VMSTATE_UINT8(scr
, SerialState
),
850 VMSTATE_UINT8_V(fcr_vmstate
, SerialState
, 3),
851 VMSTATE_END_OF_LIST()
853 .subsections
= (const VMStateDescription
*[]) {
854 &vmstate_serial_thr_ipending
,
856 &vmstate_serial_recv_fifo
,
857 &vmstate_serial_xmit_fifo
,
858 &vmstate_serial_fifo_timeout_timer
,
859 &vmstate_serial_timeout_ipending
,
860 &vmstate_serial_poll
,
865 static void serial_reset(void *opaque
)
867 SerialState
*s
= opaque
;
869 if (s
->watch_tag
> 0) {
870 g_source_remove(s
->watch_tag
);
876 s
->iir
= UART_IIR_NO_INT
;
878 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
879 s
->msr
= UART_MSR_DCD
| UART_MSR_DSR
| UART_MSR_CTS
;
881 s
->mcr
= UART_MCR_OUT2
;
884 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ 9600) * 10;
886 serial_update_parameters(s
);
888 s
->timeout_ipending
= 0;
889 timer_del(s
->fifo_timeout_timer
);
890 timer_del(s
->modem_status_poll
);
892 fifo8_reset(&s
->recv_fifo
);
893 fifo8_reset(&s
->xmit_fifo
);
895 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
898 s
->last_break_enable
= 0;
899 qemu_irq_lower(s
->irq
);
901 serial_update_msl(s
);
902 s
->msr
&= ~UART_MSR_ANY_DELTA
;
905 static int serial_be_change(void *opaque
)
907 SerialState
*s
= opaque
;
909 qemu_chr_fe_set_handlers(&s
->chr
, serial_can_receive1
, serial_receive1
,
910 serial_event
, serial_be_change
, s
, NULL
, true);
912 serial_update_parameters(s
);
914 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
915 &s
->last_break_enable
);
917 s
->poll_msl
= (s
->ier
& UART_IER_MSI
) ? 1 : 0;
918 serial_update_msl(s
);
920 if (s
->poll_msl
>= 0 && !(s
->mcr
& UART_MCR_LOOP
)) {
921 serial_update_tiocm(s
);
924 if (s
->watch_tag
> 0) {
925 g_source_remove(s
->watch_tag
);
926 s
->watch_tag
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
933 void serial_realize_core(SerialState
*s
, Error
**errp
)
935 if (!qemu_chr_fe_backend_connected(&s
->chr
)) {
936 error_setg(errp
, "Can't create serial device, empty char device");
940 s
->modem_status_poll
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) serial_update_msl
, s
);
942 s
->fifo_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) fifo_timeout_int
, s
);
943 qemu_register_reset(serial_reset
, s
);
945 qemu_chr_fe_set_handlers(&s
->chr
, serial_can_receive1
, serial_receive1
,
946 serial_event
, serial_be_change
, s
, NULL
, true);
947 fifo8_create(&s
->recv_fifo
, UART_FIFO_LENGTH
);
948 fifo8_create(&s
->xmit_fifo
, UART_FIFO_LENGTH
);
952 void serial_exit_core(SerialState
*s
)
954 qemu_chr_fe_deinit(&s
->chr
, false);
956 timer_del(s
->modem_status_poll
);
957 timer_free(s
->modem_status_poll
);
959 timer_del(s
->fifo_timeout_timer
);
960 timer_free(s
->fifo_timeout_timer
);
962 fifo8_destroy(&s
->recv_fifo
);
963 fifo8_destroy(&s
->xmit_fifo
);
965 qemu_unregister_reset(serial_reset
, s
);
968 /* Change the main reference oscillator frequency. */
969 void serial_set_frequency(SerialState
*s
, uint32_t frequency
)
971 s
->baudbase
= frequency
;
972 serial_update_parameters(s
);
975 const MemoryRegionOps serial_io_ops
= {
976 .read
= serial_ioport_read
,
977 .write
= serial_ioport_write
,
979 .min_access_size
= 1,
980 .max_access_size
= 1,
982 .endianness
= DEVICE_LITTLE_ENDIAN
,
985 SerialState
*serial_init(int base
, qemu_irq irq
, int baudbase
,
986 Chardev
*chr
, MemoryRegion
*system_io
)
990 s
= g_malloc0(sizeof(SerialState
));
995 s
->baudbase
= baudbase
;
996 qemu_chr_fe_init(&s
->chr
, chr
, &error_abort
);
997 serial_realize_core(s
, &error_fatal
);
999 vmstate_register(NULL
, base
, &vmstate_serial
, s
);
1001 memory_region_init_io(&s
->io
, NULL
, &serial_io_ops
, s
, "serial", 8);
1002 memory_region_add_subregion(system_io
, base
, &s
->io
);
1007 /* Memory mapped interface */
1008 uint64_t serial_mm_read(void *opaque
, hwaddr addr
,
1011 SerialState
*s
= opaque
;
1012 return serial_ioport_read(s
, (addr
- s
->base
) >> s
->it_shift
, 1);
1015 void serial_mm_write(void *opaque
, hwaddr addr
,
1016 uint64_t value
, unsigned size
)
1018 SerialState
*s
= opaque
;
1019 value
&= ~0u >> (32 - (size
* 8));
1020 serial_ioport_write(s
, (addr
- s
->base
) >> s
->it_shift
, value
, 1);
1023 static const MemoryRegionOps serial_mm_ops
[3] = {
1024 [DEVICE_NATIVE_ENDIAN
] = {
1025 .read
= serial_mm_read
,
1026 .write
= serial_mm_write
,
1027 .endianness
= DEVICE_NATIVE_ENDIAN
,
1029 [DEVICE_LITTLE_ENDIAN
] = {
1030 .read
= serial_mm_read
,
1031 .write
= serial_mm_write
,
1032 .endianness
= DEVICE_LITTLE_ENDIAN
,
1034 [DEVICE_BIG_ENDIAN
] = {
1035 .read
= serial_mm_read
,
1036 .write
= serial_mm_write
,
1037 .endianness
= DEVICE_BIG_ENDIAN
,
1041 SerialState
*serial_mm_init(MemoryRegion
*address_space
,
1042 hwaddr base
, int it_shift
,
1043 qemu_irq irq
, int baudbase
,
1044 Chardev
*chr
, enum device_endian end
)
1048 s
= g_malloc0(sizeof(SerialState
));
1051 s
->it_shift
= it_shift
;
1053 s
->baudbase
= baudbase
;
1054 qemu_chr_fe_init(&s
->chr
, chr
, &error_abort
);
1056 serial_realize_core(s
, &error_fatal
);
1057 vmstate_register(NULL
, base
, &vmstate_serial
, s
);
1059 memory_region_init_io(&s
->io
, NULL
, &serial_mm_ops
[end
], s
,
1060 "serial", 8 << it_shift
);
1061 memory_region_add_subregion(address_space
, base
, &s
->io
);