hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "qemu/datadir.h"
  28 #include "cpu.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/arm/boot.h"
  31 #include "hw/arm/primecell.h"
  32 #include "hw/net/lan9118.h"
  33 #include "hw/i2c/i2c.h"
  34 #include "net/net.h"
  35 #include "sysemu/sysemu.h"
  36 #include "hw/boards.h"
  37 #include "hw/loader.h"
  38 #include "exec/address-spaces.h"
  39 #include "hw/block/flash.h"
  40 #include "sysemu/device_tree.h"
  41 #include "qemu/error-report.h"
  42 #include <libfdt.h>
  43 #include "hw/char/pl011.h"
  44 #include "hw/cpu/a9mpcore.h"
  45 #include "hw/cpu/a15mpcore.h"
  46 #include "hw/i2c/arm_sbcon_i2c.h"
  47 #include "hw/sd/sd.h"
  48 #include "qom/object.h"
  49
  50 #define VEXPRESS_BOARD_ID 0x8e0
  51 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  52 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  53
  54 /* Number of virtio transports to create (0..8; limited by
  55  * number of available IRQ lines).
  56  */
  57 #define NUM_VIRTIO_TRANSPORTS 4
  58
  59 /* Address maps for peripherals:
  60  * the Versatile Express motherboard has two possible maps,
  61  * the "legacy" one (used for A9) and the "Cortex-A Series"
  62  * map (used for newer cores).
  63  * Individual daughterboards can also have different maps for
  64  * their peripherals.
  65  */
  66
  67 enum {
  68     VE_SYSREGS,
  69     VE_SP810,
  70     VE_SERIALPCI,
  71     VE_PL041,
  72     VE_MMCI,
  73     VE_KMI0,
  74     VE_KMI1,
  75     VE_UART0,
  76     VE_UART1,
  77     VE_UART2,
  78     VE_UART3,
  79     VE_WDT,
  80     VE_TIMER01,
  81     VE_TIMER23,
  82     VE_SERIALDVI,
  83     VE_RTC,
  84     VE_COMPACTFLASH,
  85     VE_CLCD,
  86     VE_NORFLASH0,
  87     VE_NORFLASH1,
  88     VE_NORFLASHALIAS,
  89     VE_SRAM,
  90     VE_VIDEORAM,
  91     VE_ETHERNET,
  92     VE_USB,
  93     VE_DAPROM,
  94     VE_VIRTIO,
  95 };
  96
  97 static hwaddr motherboard_legacy_map[] = {
  98     [VE_NORFLASHALIAS] = 0,
  99     /* CS7: 0x10000000 .. 0x10020000 */
 100     [VE_SYSREGS] = 0x10000000,
 101     [VE_SP810] = 0x10001000,
 102     [VE_SERIALPCI] = 0x10002000,
 103     [VE_PL041] = 0x10004000,
 104     [VE_MMCI] = 0x10005000,
 105     [VE_KMI0] = 0x10006000,
 106     [VE_KMI1] = 0x10007000,
 107     [VE_UART0] = 0x10009000,
 108     [VE_UART1] = 0x1000a000,
 109     [VE_UART2] = 0x1000b000,
 110     [VE_UART3] = 0x1000c000,
 111     [VE_WDT] = 0x1000f000,
 112     [VE_TIMER01] = 0x10011000,
 113     [VE_TIMER23] = 0x10012000,
 114     [VE_VIRTIO] = 0x10013000,
 115     [VE_SERIALDVI] = 0x10016000,
 116     [VE_RTC] = 0x10017000,
 117     [VE_COMPACTFLASH] = 0x1001a000,
 118     [VE_CLCD] = 0x1001f000,
 119     /* CS0: 0x40000000 .. 0x44000000 */
 120     [VE_NORFLASH0] = 0x40000000,
 121     /* CS1: 0x44000000 .. 0x48000000 */
 122     [VE_NORFLASH1] = 0x44000000,
 123     /* CS2: 0x48000000 .. 0x4a000000 */
 124     [VE_SRAM] = 0x48000000,
 125     /* CS3: 0x4c000000 .. 0x50000000 */
 126     [VE_VIDEORAM] = 0x4c000000,
 127     [VE_ETHERNET] = 0x4e000000,
 128     [VE_USB] = 0x4f000000,
 129 };
 130
 131 static hwaddr motherboard_aseries_map[] = {
 132     [VE_NORFLASHALIAS] = 0,
 133     /* CS0: 0x08000000 .. 0x0c000000 */
 134     [VE_NORFLASH0] = 0x08000000,
 135     /* CS4: 0x0c000000 .. 0x10000000 */
 136     [VE_NORFLASH1] = 0x0c000000,
 137     /* CS5: 0x10000000 .. 0x14000000 */
 138     /* CS1: 0x14000000 .. 0x18000000 */
 139     [VE_SRAM] = 0x14000000,
 140     /* CS2: 0x18000000 .. 0x1c000000 */
 141     [VE_VIDEORAM] = 0x18000000,
 142     [VE_ETHERNET] = 0x1a000000,
 143     [VE_USB] = 0x1b000000,
 144     /* CS3: 0x1c000000 .. 0x20000000 */
 145     [VE_DAPROM] = 0x1c000000,
 146     [VE_SYSREGS] = 0x1c010000,
 147     [VE_SP810] = 0x1c020000,
 148     [VE_SERIALPCI] = 0x1c030000,
 149     [VE_PL041] = 0x1c040000,
 150     [VE_MMCI] = 0x1c050000,
 151     [VE_KMI0] = 0x1c060000,
 152     [VE_KMI1] = 0x1c070000,
 153     [VE_UART0] = 0x1c090000,
 154     [VE_UART1] = 0x1c0a0000,
 155     [VE_UART2] = 0x1c0b0000,
 156     [VE_UART3] = 0x1c0c0000,
 157     [VE_WDT] = 0x1c0f0000,
 158     [VE_TIMER01] = 0x1c110000,
 159     [VE_TIMER23] = 0x1c120000,
 160     [VE_VIRTIO] = 0x1c130000,
 161     [VE_SERIALDVI] = 0x1c160000,
 162     [VE_RTC] = 0x1c170000,
 163     [VE_COMPACTFLASH] = 0x1c1a0000,
 164     [VE_CLCD] = 0x1c1f0000,
 165 };
 166
 167 /* Structure defining the peculiarities of a specific daughterboard */
 168
 169 typedef struct VEDBoardInfo VEDBoardInfo;
 170
 171 struct VexpressMachineClass {
 172     MachineClass parent;
 173     VEDBoardInfo *daughterboard;
 174 };
 175
 176 struct VexpressMachineState {
 177     MachineState parent;
 178     bool secure;
 179     bool virt;
 180 };
 181
 182 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 183 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
 184 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
 185 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
 186
 187 typedef void DBoardInitFn(const VexpressMachineState *machine,
 188                           ram_addr_t ram_size,
 189                           const char *cpu_type,
 190                           qemu_irq *pic);
 191
 192 struct VEDBoardInfo {
 193     struct arm_boot_info bootinfo;
 194     const hwaddr *motherboard_map;
 195     hwaddr loader_start;
 196     const hwaddr gic_cpu_if_addr;
 197     uint32_t proc_id;
 198     uint32_t num_voltage_sensors;
 199     const uint32_t *voltages;
 200     uint32_t num_clocks;
 201     const uint32_t *clocks;
 202     DBoardInitFn *init;
 203 };
 204
 205 static void init_cpus(MachineState *ms, const char *cpu_type,
 206                       const char *privdev, hwaddr periphbase,
 207                       qemu_irq *pic, bool secure, bool virt)
 208 {
 209     DeviceState *dev;
 210     SysBusDevice *busdev;
 211     int n;
 212     unsigned int smp_cpus = ms->smp.cpus;
 213
 214     /* Create the actual CPUs */
 215     for (n = 0; n < smp_cpus; n++) {
 216         Object *cpuobj = object_new(cpu_type);
 217
 218         if (!secure) {
 219             object_property_set_bool(cpuobj, "has_el3", false, NULL);
 220         }
 221         if (!virt) {
 222             if (object_property_find(cpuobj, "has_el2")) {
 223                 object_property_set_bool(cpuobj, "has_el2", false, NULL);
 224             }
 225         }
 226
 227         if (object_property_find(cpuobj, "reset-cbar")) {
 228             object_property_set_int(cpuobj, "reset-cbar", periphbase,
 229                                     &error_abort);
 230         }
 231         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 232     }
 233
 234     /* Create the private peripheral devices (including the GIC);
 235      * this must happen after the CPUs are created because a15mpcore_priv
 236      * wires itself up to the CPU's generic_timer gpio out lines.
 237      */
 238     dev = qdev_new(privdev);
 239     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 240     busdev = SYS_BUS_DEVICE(dev);
 241     sysbus_realize_and_unref(busdev, &error_fatal);
 242     sysbus_mmio_map(busdev, 0, periphbase);
 243
 244     /* Interrupts [42:0] are from the motherboard;
 245      * [47:43] are reserved; [63:48] are daughterboard
 246      * peripherals. Note that some documentation numbers
 247      * external interrupts starting from 32 (because there
 248      * are internal interrupts 0..31).
 249      */
 250     for (n = 0; n < 64; n++) {
 251         pic[n] = qdev_get_gpio_in(dev, n);
 252     }
 253
 254     /* Connect the CPUs to the GIC */
 255     for (n = 0; n < smp_cpus; n++) {
 256         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 257
 258         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 259         sysbus_connect_irq(busdev, n + smp_cpus,
 260                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 261         sysbus_connect_irq(busdev, n + 2 * smp_cpus,
 262                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 263         sysbus_connect_irq(busdev, n + 3 * smp_cpus,
 264                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 265     }
 266 }
 267
 268 static void a9_daughterboard_init(const VexpressMachineState *vms,
 269                                   ram_addr_t ram_size,
 270                                   const char *cpu_type,
 271                                   qemu_irq *pic)
 272 {
 273     MachineState *machine = MACHINE(vms);
 274     MemoryRegion *sysmem = get_system_memory();
 275     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 276     ram_addr_t low_ram_size;
 277
 278     if (ram_size > 0x40000000) {
 279         /* 1GB is the maximum the address space permits */
 280         error_report("vexpress-a9: cannot model more than 1GB RAM");
 281         exit(1);
 282     }
 283
 284     low_ram_size = ram_size;
 285     if (low_ram_size > 0x4000000) {
 286         low_ram_size = 0x4000000;
 287     }
 288     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 289      * address space should in theory be remappable to various
 290      * things including ROM or RAM; we always map the RAM there.
 291      */
 292     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram,
 293                              0, low_ram_size);
 294     memory_region_add_subregion(sysmem, 0x0, lowram);
 295     memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
 296
 297     /* 0x1e000000 A9MPCore (SCU) private memory region */
 298     init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
 299               vms->secure, vms->virt);
 300
 301     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 302
 303     /* 0x10020000 PL111 CLCD (daughterboard) */
 304     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 305
 306     /* 0x10060000 AXI RAM */
 307     /* 0x100e0000 PL341 Dynamic Memory Controller */
 308     /* 0x100e1000 PL354 Static Memory Controller */
 309     /* 0x100e2000 System Configuration Controller */
 310
 311     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 312     /* 0x100e5000 SP805 Watchdog module */
 313     /* 0x100e6000 BP147 TrustZone Protection Controller */
 314     /* 0x100e9000 PL301 'Fast' AXI matrix */
 315     /* 0x100ea000 PL301 'Slow' AXI matrix */
 316     /* 0x100ec000 TrustZone Address Space Controller */
 317     /* 0x10200000 CoreSight debug APB */
 318     /* 0x1e00a000 PL310 L2 Cache Controller */
 319     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 320 }
 321
 322 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 323  * values are in microvolts.
 324  */
 325 static const uint32_t a9_voltages[] = {
 326     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 327     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 328     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 329     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 330     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 331     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 332 };
 333
 334 /* Reset values for daughterboard oscillators (in Hz) */
 335 static const uint32_t a9_clocks[] = {
 336     45000000, /* AMBA AXI ACLK: 45MHz */
 337     23750000, /* daughterboard CLCD clock: 23.75MHz */
 338     66670000, /* Test chip reference clock: 66.67MHz */
 339 };
 340
 341 static VEDBoardInfo a9_daughterboard = {
 342     .motherboard_map = motherboard_legacy_map,
 343     .loader_start = 0x60000000,
 344     .gic_cpu_if_addr = 0x1e000100,
 345     .proc_id = 0x0c000191,
 346     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 347     .voltages = a9_voltages,
 348     .num_clocks = ARRAY_SIZE(a9_clocks),
 349     .clocks = a9_clocks,
 350     .init = a9_daughterboard_init,
 351 };
 352
 353 static void a15_daughterboard_init(const VexpressMachineState *vms,
 354                                    ram_addr_t ram_size,
 355                                    const char *cpu_type,
 356                                    qemu_irq *pic)
 357 {
 358     MachineState *machine = MACHINE(vms);
 359     MemoryRegion *sysmem = get_system_memory();
 360     MemoryRegion *sram = g_new(MemoryRegion, 1);
 361
 362     {
 363         /* We have to use a separate 64 bit variable here to avoid the gcc
 364          * "comparison is always false due to limited range of data type"
 365          * warning if we are on a host where ram_addr_t is 32 bits.
 366          */
 367         uint64_t rsz = ram_size;
 368         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 369             error_report("vexpress-a15: cannot model more than 30GB RAM");
 370             exit(1);
 371         }
 372     }
 373
 374     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 375     memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
 376
 377     /* 0x2c000000 A15MPCore private memory region (GIC) */
 378     init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
 379               0x2c000000, pic, vms->secure, vms->virt);
 380
 381     /* A15 daughterboard peripherals: */
 382
 383     /* 0x20000000: CoreSight interfaces: not modelled */
 384     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 385     /* 0x2a420000: SCC: not modelled */
 386     /* 0x2a430000: system counter: not modelled */
 387     /* 0x2b000000: HDLCD controller: not modelled */
 388     /* 0x2b060000: SP805 watchdog: not modelled */
 389     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 390     /* 0x2e000000: system SRAM */
 391     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
 392                            &error_fatal);
 393     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 394
 395     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 396     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 397 }
 398
 399 static const uint32_t a15_voltages[] = {
 400     900000, /* Vcore: 0.9V : CPU core voltage */
 401 };
 402
 403 static const uint32_t a15_clocks[] = {
 404     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 405     0, /* OSCCLK1: reserved */
 406     0, /* OSCCLK2: reserved */
 407     0, /* OSCCLK3: reserved */
 408     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 409     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 410     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 411     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 412     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 413 };
 414
 415 static VEDBoardInfo a15_daughterboard = {
 416     .motherboard_map = motherboard_aseries_map,
 417     .loader_start = 0x80000000,
 418     .gic_cpu_if_addr = 0x2c002000,
 419     .proc_id = 0x14000237,
 420     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 421     .voltages = a15_voltages,
 422     .num_clocks = ARRAY_SIZE(a15_clocks),
 423     .clocks = a15_clocks,
 424     .init = a15_daughterboard_init,
 425 };
 426
 427 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 428                                 hwaddr addr, hwaddr size, uint32_t intc,
 429                                 int irq)
 430 {
 431     /* Add a virtio_mmio node to the device tree blob:
 432      *   virtio_mmio@ADDRESS {
 433      *       compatible = "virtio,mmio";
 434      *       reg = <ADDRESS, SIZE>;
 435      *       interrupt-parent = <&intc>;
 436      *       interrupts = <0, irq, 1>;
 437      *   }
 438      * (Note that the format of the interrupts property is dependent on the
 439      * interrupt controller that interrupt-parent points to; these are for
 440      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 441      */
 442     int rc;
 443     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 444
 445     rc = qemu_fdt_add_subnode(fdt, nodename);
 446     rc |= qemu_fdt_setprop_string(fdt, nodename,
 447                                   "compatible", "virtio,mmio");
 448     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 449                                        acells, addr, scells, size);
 450     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 451     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 452     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 453     g_free(nodename);
 454     if (rc) {
 455         return -1;
 456     }
 457     return 0;
 458 }
 459
 460 static uint32_t find_int_controller(void *fdt)
 461 {
 462     /* Find the FDT node corresponding to the interrupt controller
 463      * for virtio-mmio devices. We do this by scanning the fdt for
 464      * a node with the right compatibility, since we know there is
 465      * only one GIC on a vexpress board.
 466      * We return the phandle of the node, or 0 if none was found.
 467      */
 468     const char *compat = "arm,cortex-a9-gic";
 469     int offset;
 470
 471     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 472     if (offset >= 0) {
 473         return fdt_get_phandle(fdt, offset);
 474     }
 475     return 0;
 476 }
 477
 478 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 479 {
 480     uint32_t acells, scells, intc;
 481     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 482
 483     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
 484                                    NULL, &error_fatal);
 485     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
 486                                    NULL, &error_fatal);
 487     intc = find_int_controller(fdt);
 488     if (!intc) {
 489         /* Not fatal, we just won't provide virtio. This will
 490          * happen with older device tree blobs.
 491          */
 492         warn_report("couldn't find interrupt controller in "
 493                     "dtb; will not include virtio-mmio devices in the dtb");
 494     } else {
 495         int i;
 496         const hwaddr *map = daughterboard->motherboard_map;
 497
 498         /* We iterate backwards here because adding nodes
 499          * to the dtb puts them in last-first.
 500          */
 501         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 502             add_virtio_mmio_node(fdt, acells, scells,
 503                                  map[VE_VIRTIO] + 0x200 * i,
 504                                  0x200, intc, 40 + i);
 505         }
 506     }
 507 }
 508
 509
 510 /* Open code a private version of pflash registration since we
 511  * need to set non-default device width for VExpress platform.
 512  */
 513 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
 514                                              DriveInfo *di)
 515 {
 516     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
 517
 518     if (di) {
 519         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
 520     }
 521
 522     qdev_prop_set_uint32(dev, "num-blocks",
 523                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 524     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 525     qdev_prop_set_uint8(dev, "width", 4);
 526     qdev_prop_set_uint8(dev, "device-width", 2);
 527     qdev_prop_set_bit(dev, "big-endian", false);
 528     qdev_prop_set_uint16(dev, "id0", 0x89);
 529     qdev_prop_set_uint16(dev, "id1", 0x18);
 530     qdev_prop_set_uint16(dev, "id2", 0x00);
 531     qdev_prop_set_uint16(dev, "id3", 0x00);
 532     qdev_prop_set_string(dev, "name", name);
 533     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 534
 535     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 536     return PFLASH_CFI01(dev);
 537 }
 538
 539 static void vexpress_common_init(MachineState *machine)
 540 {
 541     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 542     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 543     VEDBoardInfo *daughterboard = vmc->daughterboard;
 544     DeviceState *dev, *sysctl, *pl041;
 545     qemu_irq pic[64];
 546     uint32_t sys_id;
 547     DriveInfo *dinfo;
 548     PFlashCFI01 *pflash0;
 549     I2CBus *i2c;
 550     ram_addr_t vram_size, sram_size;
 551     MemoryRegion *sysmem = get_system_memory();
 552     MemoryRegion *vram = g_new(MemoryRegion, 1);
 553     MemoryRegion *sram = g_new(MemoryRegion, 1);
 554     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 555     MemoryRegion *flash0mem;
 556     const hwaddr *map = daughterboard->motherboard_map;
 557     int i;
 558
 559     daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
 560
 561     /*
 562      * If a bios file was provided, attempt to map it into memory
 563      */
 564     if (machine->firmware) {
 565         char *fn;
 566         int image_size;
 567
 568         if (drive_get(IF_PFLASH, 0, 0)) {
 569             error_report("The contents of the first flash device may be "
 570                          "specified with -bios or with -drive if=pflash... "
 571                          "but you cannot use both options at once");
 572             exit(1);
 573         }
 574         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
 575         if (!fn) {
 576             error_report("Could not find ROM image '%s'", machine->firmware);
 577             exit(1);
 578         }
 579         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
 580                                          VEXPRESS_FLASH_SIZE);
 581         g_free(fn);
 582         if (image_size < 0) {
 583             error_report("Could not load ROM image '%s'", machine->firmware);
 584             exit(1);
 585         }
 586     }
 587
 588     /* Motherboard peripherals: the wiring is the same but the
 589      * addresses vary between the legacy and A-Series memory maps.
 590      */
 591
 592     sys_id = 0x1190f500;
 593
 594     sysctl = qdev_new("realview_sysctl");
 595     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 596     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 597     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 598                          daughterboard->num_voltage_sensors);
 599     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 600         char *propname = g_strdup_printf("db-voltage[%d]", i);
 601         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 602         g_free(propname);
 603     }
 604     qdev_prop_set_uint32(sysctl, "len-db-clock",
 605                          daughterboard->num_clocks);
 606     for (i = 0; i < daughterboard->num_clocks; i++) {
 607         char *propname = g_strdup_printf("db-clock[%d]", i);
 608         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 609         g_free(propname);
 610     }
 611     sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
 612     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 613
 614     /* VE_SP810: not modelled */
 615     /* VE_SERIALPCI: not modelled */
 616
 617     pl041 = qdev_new("pl041");
 618     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 619     sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
 620     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 621     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 622
 623     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 624     /* Wire up MMC card detect and read-only signals */
 625     qdev_connect_gpio_out_named(dev, "card-read-only", 0,
 626                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 627     qdev_connect_gpio_out_named(dev, "card-inserted", 0,
 628                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 629     dinfo = drive_get_next(IF_SD);
 630     if (dinfo) {
 631         DeviceState *card;
 632
 633         card = qdev_new(TYPE_SD_CARD);
 634         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 635                                 &error_fatal);
 636         qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
 637                                &error_fatal);
 638     }
 639
 640     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 641     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 642
 643     pl011_create(map[VE_UART0], pic[5], serial_hd(0));
 644     pl011_create(map[VE_UART1], pic[6], serial_hd(1));
 645     pl011_create(map[VE_UART2], pic[7], serial_hd(2));
 646     pl011_create(map[VE_UART3], pic[8], serial_hd(3));
 647
 648     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 649     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 650
 651     dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
 652     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 653     i2c_slave_create_simple(i2c, "sii9022", 0x39);
 654
 655     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 656
 657     /* VE_COMPACTFLASH: not modelled */
 658
 659     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 660
 661     dinfo = drive_get_next(IF_PFLASH);
 662     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 663                                        dinfo);
 664     if (!pflash0) {
 665         error_report("vexpress: error registering flash 0");
 666         exit(1);
 667     }
 668
 669     if (map[VE_NORFLASHALIAS] != -1) {
 670         /* Map flash 0 as an alias into low memory */
 671         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 672         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 673                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 674         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 675     }
 676
 677     dinfo = drive_get_next(IF_PFLASH);
 678     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 679                                   dinfo)) {
 680         error_report("vexpress: error registering flash 1");
 681         exit(1);
 682     }
 683
 684     sram_size = 0x2000000;
 685     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
 686                            &error_fatal);
 687     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 688
 689     vram_size = 0x800000;
 690     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
 691                            &error_fatal);
 692     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 693
 694     /* 0x4e000000 LAN9118 Ethernet */
 695     if (nd_table[0].used) {
 696         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 697     }
 698
 699     /* VE_USB: not modelled */
 700
 701     /* VE_DAPROM: not modelled */
 702
 703     /* Create mmio transports, so the user can create virtio backends
 704      * (which will be automatically plugged in to the transports). If
 705      * no backend is created the transport will just sit harmlessly idle.
 706      */
 707     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 708         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 709                              pic[40 + i]);
 710     }
 711
 712     daughterboard->bootinfo.ram_size = machine->ram_size;
 713     daughterboard->bootinfo.nb_cpus = machine->smp.cpus;
 714     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 715     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 716     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 717     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 718     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 719     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 720     /* When booting Linux we should be in secure state if the CPU has one. */
 721     daughterboard->bootinfo.secure_boot = vms->secure;
 722     arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
 723 }
 724
 725 static bool vexpress_get_secure(Object *obj, Error **errp)
 726 {
 727     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 728
 729     return vms->secure;
 730 }
 731
 732 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 733 {
 734     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 735
 736     vms->secure = value;
 737 }
 738
 739 static bool vexpress_get_virt(Object *obj, Error **errp)
 740 {
 741     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 742
 743     return vms->virt;
 744 }
 745
 746 static void vexpress_set_virt(Object *obj, bool value, Error **errp)
 747 {
 748     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 749
 750     vms->virt = value;
 751 }
 752
 753 static void vexpress_instance_init(Object *obj)
 754 {
 755     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 756
 757     /* EL3 is enabled by default on vexpress */
 758     vms->secure = true;
 759 }
 760
 761 static void vexpress_a15_instance_init(Object *obj)
 762 {
 763     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 764
 765     /*
 766      * For the vexpress-a15, EL2 is by default enabled if EL3 is,
 767      * but can also be specifically set to on or off.
 768      */
 769     vms->virt = true;
 770 }
 771
 772 static void vexpress_a9_instance_init(Object *obj)
 773 {
 774     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 775
 776     /* The A9 doesn't have the virt extensions */
 777     vms->virt = false;
 778 }
 779
 780 static void vexpress_class_init(ObjectClass *oc, void *data)
 781 {
 782     MachineClass *mc = MACHINE_CLASS(oc);
 783
 784     mc->desc = "ARM Versatile Express";
 785     mc->init = vexpress_common_init;
 786     mc->max_cpus = 4;
 787     mc->ignore_memory_transaction_failures = true;
 788     mc->default_ram_id = "vexpress.highmem";
 789
 790     object_class_property_add_bool(oc, "secure", vexpress_get_secure,
 791                                    vexpress_set_secure);
 792     object_class_property_set_description(oc, "secure",
 793                                           "Set on/off to enable/disable the ARM "
 794                                           "Security Extensions (TrustZone)");
 795 }
 796
 797 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 798 {
 799     MachineClass *mc = MACHINE_CLASS(oc);
 800     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 801
 802     mc->desc = "ARM Versatile Express for Cortex-A9";
 803     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 804
 805     vmc->daughterboard = &a9_daughterboard;
 806 }
 807
 808 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 809 {
 810     MachineClass *mc = MACHINE_CLASS(oc);
 811     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 812
 813     mc->desc = "ARM Versatile Express for Cortex-A15";
 814     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 815
 816     vmc->daughterboard = &a15_daughterboard;
 817
 818     object_class_property_add_bool(oc, "virtualization", vexpress_get_virt,
 819                                    vexpress_set_virt);
 820     object_class_property_set_description(oc, "virtualization",
 821                                           "Set on/off to enable/disable the ARM "
 822                                           "Virtualization Extensions "
 823                                           "(defaults to same as 'secure')");
 824
 825 }
 826
 827 static const TypeInfo vexpress_info = {
 828     .name = TYPE_VEXPRESS_MACHINE,
 829     .parent = TYPE_MACHINE,
 830     .abstract = true,
 831     .instance_size = sizeof(VexpressMachineState),
 832     .instance_init = vexpress_instance_init,
 833     .class_size = sizeof(VexpressMachineClass),
 834     .class_init = vexpress_class_init,
 835 };
 836
 837 static const TypeInfo vexpress_a9_info = {
 838     .name = TYPE_VEXPRESS_A9_MACHINE,
 839     .parent = TYPE_VEXPRESS_MACHINE,
 840     .class_init = vexpress_a9_class_init,
 841     .instance_init = vexpress_a9_instance_init,
 842 };
 843
 844 static const TypeInfo vexpress_a15_info = {
 845     .name = TYPE_VEXPRESS_A15_MACHINE,
 846     .parent = TYPE_VEXPRESS_MACHINE,
 847     .class_init = vexpress_a15_class_init,
 848     .instance_init = vexpress_a15_instance_init,
 849 };
 850
 851 static void vexpress_machine_init(void)
 852 {
 853     type_register_static(&vexpress_info);
 854     type_register_static(&vexpress_a9_info);
 855     type_register_static(&vexpress_a15_info);
 856 }
 857
 858 type_init(vexpress_machine_init);