hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/arm.h"
  24 #include "hw/loader.h"
  25 #include "net/net.h"
  26 #include "sysemu/kvm.h"
  27 #include "sysemu/sysemu.h"
  28 #include "hw/boards.h"
  29 #include "exec/address-spaces.h"
  30 #include "qemu/error-report.h"
  31 #include "hw/char/pl011.h"
  32 #include "hw/ide/ahci.h"
  33 #include "hw/cpu/a9mpcore.h"
  34 #include "hw/cpu/a15mpcore.h"
  35 #include "qemu/log.h"
  36
  37 #define SMP_BOOT_ADDR           0x100
  38 #define SMP_BOOT_REG            0x40
  39 #define MPCORE_PERIPHBASE       0xfff10000
  40
  41 #define MVBAR_ADDR              0x200
  42 #define BOARD_SETUP_ADDR        (MVBAR_ADDR + 8 * sizeof(uint32_t))
  43
  44 #define NIRQ_GIC                160
  45
  46 /* Board init.  */
  47
  48 static void hb_write_board_setup(ARMCPU *cpu,
  49                                  const struct arm_boot_info *info)
  50 {
  51     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
  52 }
  53
  54 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  55 {
  56     int n;
  57     uint32_t smpboot[] = {
  58         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  59         0xe210000f, /* ands r0, r0, #0x0f */
  60         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  61         0xe0830200, /* add r0, r3, r0, lsl #4 */
  62         0xe59f2024, /* ldr r2, privbase */
  63         0xe3a01001, /* mov r1, #1 */
  64         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  65         0xe3a010ff, /* mov r1, #0xff */
  66         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  67         0xf57ff04f, /* dsb */
  68         0xe320f003, /* wfi */
  69         0xe5901000, /* ldr     r1, [r0] */
  70         0xe1110001, /* tst     r1, r1 */
  71         0x0afffffb, /* beq     <wfi> */
  72         0xe12fff11, /* bx      r1 */
  73         MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
  74     };
  75     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  76         smpboot[n] = tswap32(smpboot[n]);
  77     }
  78     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  79 }
  80
  81 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  82 {
  83     CPUARMState *env = &cpu->env;
  84
  85     switch (info->nb_cpus) {
  86     case 4:
  87         address_space_stl_notdirty(&address_space_memory,
  88                                    SMP_BOOT_REG + 0x30, 0,
  89                                    MEMTXATTRS_UNSPECIFIED, NULL);
  90     case 3:
  91         address_space_stl_notdirty(&address_space_memory,
  92                                    SMP_BOOT_REG + 0x20, 0,
  93                                    MEMTXATTRS_UNSPECIFIED, NULL);
  94     case 2:
  95         address_space_stl_notdirty(&address_space_memory,
  96                                    SMP_BOOT_REG + 0x10, 0,
  97                                    MEMTXATTRS_UNSPECIFIED, NULL);
  98         env->regs[15] = SMP_BOOT_ADDR;
  99         break;
 100     default:
 101         break;
 102     }
 103 }
 104
 105 #define NUM_REGS      0x200
 106 static void hb_regs_write(void *opaque, hwaddr offset,
 107                           uint64_t value, unsigned size)
 108 {
 109     uint32_t *regs = opaque;
 110
 111     if (offset == 0xf00) {
 112         if (value == 1 || value == 2) {
 113             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 114         } else if (value == 3) {
 115             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 116         }
 117     }
 118
 119     if (offset / 4 >= NUM_REGS) {
 120         qemu_log_mask(LOG_GUEST_ERROR,
 121                   "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
 122         return;
 123     }
 124     regs[offset / 4] = value;
 125 }
 126
 127 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 128                              unsigned size)
 129 {
 130     uint32_t value;
 131     uint32_t *regs = opaque;
 132
 133     if (offset / 4 >= NUM_REGS) {
 134         qemu_log_mask(LOG_GUEST_ERROR,
 135                   "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
 136         return 0;
 137     }
 138     value = regs[offset / 4];
 139
 140     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 141         value |= 0x30000000;
 142     }
 143
 144     return value;
 145 }
 146
 147 static const MemoryRegionOps hb_mem_ops = {
 148     .read = hb_regs_read,
 149     .write = hb_regs_write,
 150     .endianness = DEVICE_NATIVE_ENDIAN,
 151 };
 152
 153 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
 154 #define HIGHBANK_REGISTERS(obj) \
 155     OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
 156
 157 typedef struct {
 158     /*< private >*/
 159     SysBusDevice parent_obj;
 160     /*< public >*/
 161
 162     MemoryRegion iomem;
 163     uint32_t regs[NUM_REGS];
 164 } HighbankRegsState;
 165
 166 static VMStateDescription vmstate_highbank_regs = {
 167     .name = "highbank-regs",
 168     .version_id = 0,
 169     .minimum_version_id = 0,
 170     .fields = (VMStateField[]) {
 171         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 172         VMSTATE_END_OF_LIST(),
 173     },
 174 };
 175
 176 static void highbank_regs_reset(DeviceState *dev)
 177 {
 178     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 179
 180     s->regs[0x40] = 0x05F20121;
 181     s->regs[0x41] = 0x2;
 182     s->regs[0x42] = 0x05F30121;
 183     s->regs[0x43] = 0x05F40121;
 184 }
 185
 186 static void highbank_regs_init(Object *obj)
 187 {
 188     HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
 189     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 190
 191     memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
 192                           "highbank_regs", 0x1000);
 193     sysbus_init_mmio(dev, &s->iomem);
 194 }
 195
 196 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 197 {
 198     DeviceClass *dc = DEVICE_CLASS(klass);
 199
 200     dc->desc = "Calxeda Highbank registers";
 201     dc->vmsd = &vmstate_highbank_regs;
 202     dc->reset = highbank_regs_reset;
 203 }
 204
 205 static const TypeInfo highbank_regs_info = {
 206     .name          = TYPE_HIGHBANK_REGISTERS,
 207     .parent        = TYPE_SYS_BUS_DEVICE,
 208     .instance_size = sizeof(HighbankRegsState),
 209     .instance_init = highbank_regs_init,
 210     .class_init    = highbank_regs_class_init,
 211 };
 212
 213 static void highbank_regs_register_types(void)
 214 {
 215     type_register_static(&highbank_regs_info);
 216 }
 217
 218 type_init(highbank_regs_register_types)
 219
 220 static struct arm_boot_info highbank_binfo;
 221
 222 enum cxmachines {
 223     CALXEDA_HIGHBANK,
 224     CALXEDA_MIDWAY,
 225 };
 226
 227 /* ram_size must be set to match the upper bound of memory in the
 228  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 229  * normally 0xff900000 or -m 4089. When running this board on a
 230  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 231  * device tree and pass -m 2047 to QEMU.
 232  */
 233 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 234 {
 235     ram_addr_t ram_size = machine->ram_size;
 236     const char *kernel_filename = machine->kernel_filename;
 237     const char *kernel_cmdline = machine->kernel_cmdline;
 238     const char *initrd_filename = machine->initrd_filename;
 239     DeviceState *dev = NULL;
 240     SysBusDevice *busdev;
 241     qemu_irq pic[128];
 242     int n;
 243     qemu_irq cpu_irq[4];
 244     qemu_irq cpu_fiq[4];
 245     qemu_irq cpu_virq[4];
 246     qemu_irq cpu_vfiq[4];
 247     MemoryRegion *sysram;
 248     MemoryRegion *dram;
 249     MemoryRegion *sysmem;
 250     char *sysboot_filename;
 251
 252     switch (machine_id) {
 253     case CALXEDA_HIGHBANK:
 254         machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 255         break;
 256     case CALXEDA_MIDWAY:
 257         machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 258         break;
 259     default:
 260         assert(0);
 261     }
 262
 263     for (n = 0; n < smp_cpus; n++) {
 264         Object *cpuobj;
 265         ARMCPU *cpu;
 266
 267         cpuobj = object_new(machine->cpu_type);
 268         cpu = ARM_CPU(cpuobj);
 269
 270         object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
 271                                 "psci-conduit", &error_abort);
 272
 273         if (n) {
 274             /* Secondary CPUs start in PSCI powered-down state */
 275             object_property_set_bool(cpuobj, true,
 276                                      "start-powered-off", &error_abort);
 277         }
 278
 279         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 280             object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
 281                                     "reset-cbar", &error_abort);
 282         }
 283         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 284         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
 285         cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
 286         cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
 287         cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
 288     }
 289
 290     sysmem = get_system_memory();
 291     dram = g_new(MemoryRegion, 1);
 292     memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
 293     /* SDRAM at address zero.  */
 294     memory_region_add_subregion(sysmem, 0, dram);
 295
 296     sysram = g_new(MemoryRegion, 1);
 297     memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
 298                            &error_fatal);
 299     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 300     if (bios_name != NULL) {
 301         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 302         if (sysboot_filename != NULL) {
 303             if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
 304                 error_report("Unable to load %s", bios_name);
 305                 exit(1);
 306             }
 307             g_free(sysboot_filename);
 308         } else {
 309             error_report("Unable to find %s", bios_name);
 310             exit(1);
 311         }
 312     }
 313
 314     switch (machine_id) {
 315     case CALXEDA_HIGHBANK:
 316         dev = qdev_create(NULL, "l2x0");
 317         qdev_init_nofail(dev);
 318         busdev = SYS_BUS_DEVICE(dev);
 319         sysbus_mmio_map(busdev, 0, 0xfff12000);
 320
 321         dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
 322         break;
 323     case CALXEDA_MIDWAY:
 324         dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
 325         break;
 326     }
 327     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 328     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 329     qdev_init_nofail(dev);
 330     busdev = SYS_BUS_DEVICE(dev);
 331     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 332     for (n = 0; n < smp_cpus; n++) {
 333         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 334         sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
 335         sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
 336         sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
 337     }
 338
 339     for (n = 0; n < 128; n++) {
 340         pic[n] = qdev_get_gpio_in(dev, n);
 341     }
 342
 343     dev = qdev_create(NULL, "sp804");
 344     qdev_prop_set_uint32(dev, "freq0", 150000000);
 345     qdev_prop_set_uint32(dev, "freq1", 150000000);
 346     qdev_init_nofail(dev);
 347     busdev = SYS_BUS_DEVICE(dev);
 348     sysbus_mmio_map(busdev, 0, 0xfff34000);
 349     sysbus_connect_irq(busdev, 0, pic[18]);
 350     pl011_create(0xfff36000, pic[20], serial_hd(0));
 351
 352     dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
 353     qdev_init_nofail(dev);
 354     busdev = SYS_BUS_DEVICE(dev);
 355     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 356
 357     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 358     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 359     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 360     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 361     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 362     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 363
 364     sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
 365
 366     if (nd_table[0].used) {
 367         qemu_check_nic_model(&nd_table[0], "xgmac");
 368         dev = qdev_create(NULL, "xgmac");
 369         qdev_set_nic_properties(dev, &nd_table[0]);
 370         qdev_init_nofail(dev);
 371         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 372         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 373         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 374         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 375
 376         qemu_check_nic_model(&nd_table[1], "xgmac");
 377         dev = qdev_create(NULL, "xgmac");
 378         qdev_set_nic_properties(dev, &nd_table[1]);
 379         qdev_init_nofail(dev);
 380         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 381         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 382         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 383         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 384     }
 385
 386     /* TODO create and connect IDE devices for ide_drive_get() */
 387
 388     highbank_binfo.ram_size = ram_size;
 389     highbank_binfo.kernel_filename = kernel_filename;
 390     highbank_binfo.kernel_cmdline = kernel_cmdline;
 391     highbank_binfo.initrd_filename = initrd_filename;
 392     /* highbank requires a dtb in order to boot, and the dtb will override
 393      * the board ID. The following value is ignored, so set it to -1 to be
 394      * clear that the value is meaningless.
 395      */
 396     highbank_binfo.board_id = -1;
 397     highbank_binfo.nb_cpus = smp_cpus;
 398     highbank_binfo.loader_start = 0;
 399     highbank_binfo.write_secondary_boot = hb_write_secondary;
 400     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 401     if (!kvm_enabled()) {
 402         highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 403         highbank_binfo.write_board_setup = hb_write_board_setup;
 404         highbank_binfo.secure_board_setup = true;
 405     } else {
 406         warn_report("cannot load built-in Monitor support "
 407                     "if KVM is enabled. Some guests (such as Linux) "
 408                     "may not boot.");
 409     }
 410
 411     arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
 412 }
 413
 414 static void highbank_init(MachineState *machine)
 415 {
 416     calxeda_init(machine, CALXEDA_HIGHBANK);
 417 }
 418
 419 static void midway_init(MachineState *machine)
 420 {
 421     calxeda_init(machine, CALXEDA_MIDWAY);
 422 }
 423
 424 static void highbank_class_init(ObjectClass *oc, void *data)
 425 {
 426     MachineClass *mc = MACHINE_CLASS(oc);
 427
 428     mc->desc = "Calxeda Highbank (ECX-1000)";
 429     mc->init = highbank_init;
 430     mc->block_default_type = IF_IDE;
 431     mc->units_per_default_bus = 1;
 432     mc->max_cpus = 4;
 433     mc->ignore_memory_transaction_failures = true;
 434 }
 435
 436 static const TypeInfo highbank_type = {
 437     .name = MACHINE_TYPE_NAME("highbank"),
 438     .parent = TYPE_MACHINE,
 439     .class_init = highbank_class_init,
 440 };
 441
 442 static void midway_class_init(ObjectClass *oc, void *data)
 443 {
 444     MachineClass *mc = MACHINE_CLASS(oc);
 445
 446     mc->desc = "Calxeda Midway (ECX-2000)";
 447     mc->init = midway_init;
 448     mc->block_default_type = IF_IDE;
 449     mc->units_per_default_bus = 1;
 450     mc->max_cpus = 4;
 451     mc->ignore_memory_transaction_failures = true;
 452 }
 453
 454 static const TypeInfo midway_type = {
 455     .name = MACHINE_TYPE_NAME("midway"),
 456     .parent = TYPE_MACHINE,
 457     .class_init = midway_class_init,
 458 };
 459
 460 static void calxeda_machines_init(void)
 461 {
 462     type_register_static(&highbank_type);
 463     type_register_static(&midway_type);
 464 }
 465
 466 type_init(calxeda_machines_init)