hw/timer/imx_gpt.c

   1 /*
   2  * IMX GPT Timer
   3  *
   4  * Copyright (c) 2008 OK Labs
   5  * Copyright (c) 2011 NICTA Pty Ltd
   6  * Originally written by Hans Jiang
   7  * Updated by Peter Chubb
   8  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   9  *
  10  * This code is licensed under GPL version 2 or later.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "hw/timer/imx_gpt.h"
  17 #include "qemu/main-loop.h"
  18 #include "qemu/module.h"
  19 #include "qemu/log.h"
  20
  21 #ifndef DEBUG_IMX_GPT
  22 #define DEBUG_IMX_GPT 0
  23 #endif
  24
  25 #define DPRINTF(fmt, args...) \
  26     do { \
  27         if (DEBUG_IMX_GPT) { \
  28             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
  29                                              __func__, ##args); \
  30         } \
  31     } while (0)
  32
  33 static const char *imx_gpt_reg_name(uint32_t reg)
  34 {
  35     switch (reg) {
  36     case 0:
  37         return "CR";
  38     case 1:
  39         return "PR";
  40     case 2:
  41         return "SR";
  42     case 3:
  43         return "IR";
  44     case 4:
  45         return "OCR1";
  46     case 5:
  47         return "OCR2";
  48     case 6:
  49         return "OCR3";
  50     case 7:
  51         return "ICR1";
  52     case 8:
  53         return "ICR2";
  54     case 9:
  55         return "CNT";
  56     default:
  57         return "[?]";
  58     }
  59 }
  60
  61 static const VMStateDescription vmstate_imx_timer_gpt = {
  62     .name = TYPE_IMX_GPT,
  63     .version_id = 3,
  64     .minimum_version_id = 3,
  65     .fields = (VMStateField[]) {
  66         VMSTATE_UINT32(cr, IMXGPTState),
  67         VMSTATE_UINT32(pr, IMXGPTState),
  68         VMSTATE_UINT32(sr, IMXGPTState),
  69         VMSTATE_UINT32(ir, IMXGPTState),
  70         VMSTATE_UINT32(ocr1, IMXGPTState),
  71         VMSTATE_UINT32(ocr2, IMXGPTState),
  72         VMSTATE_UINT32(ocr3, IMXGPTState),
  73         VMSTATE_UINT32(icr1, IMXGPTState),
  74         VMSTATE_UINT32(icr2, IMXGPTState),
  75         VMSTATE_UINT32(cnt, IMXGPTState),
  76         VMSTATE_UINT32(next_timeout, IMXGPTState),
  77         VMSTATE_UINT32(next_int, IMXGPTState),
  78         VMSTATE_UINT32(freq, IMXGPTState),
  79         VMSTATE_PTIMER(timer, IMXGPTState),
  80         VMSTATE_END_OF_LIST()
  81     }
  82 };
  83
  84 static const IMXClk imx25_gpt_clocks[] = {
  85     CLK_NONE,      /* 000 No clock source */
  86     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
  87     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
  88     CLK_NONE,      /* 011 not defined */
  89     CLK_32k,       /* 100 ipg_clk_32k */
  90     CLK_32k,       /* 101 ipg_clk_32k */
  91     CLK_32k,       /* 110 ipg_clk_32k */
  92     CLK_32k,       /* 111 ipg_clk_32k */
  93 };
  94
  95 static const IMXClk imx31_gpt_clocks[] = {
  96     CLK_NONE,      /* 000 No clock source */
  97     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
  98     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
  99     CLK_NONE,      /* 011 not defined */
 100     CLK_32k,       /* 100 ipg_clk_32k */
 101     CLK_NONE,      /* 101 not defined */
 102     CLK_NONE,      /* 110 not defined */
 103     CLK_NONE,      /* 111 not defined */
 104 };
 105
 106 static const IMXClk imx6_gpt_clocks[] = {
 107     CLK_NONE,      /* 000 No clock source */
 108     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
 109     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
 110     CLK_EXT,       /* 011 External clock */
 111     CLK_32k,       /* 100 ipg_clk_32k */
 112     CLK_HIGH_DIV,  /* 101 reference clock / 8 */
 113     CLK_NONE,      /* 110 not defined */
 114     CLK_HIGH,      /* 111 reference clock */
 115 };
 116
 117 static const IMXClk imx7_gpt_clocks[] = {
 118     CLK_NONE,      /* 000 No clock source */
 119     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
 120     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
 121     CLK_EXT,       /* 011 External clock */
 122     CLK_32k,       /* 100 ipg_clk_32k */
 123     CLK_HIGH,      /* 101 reference clock */
 124     CLK_NONE,      /* 110 not defined */
 125     CLK_NONE,      /* 111 not defined */
 126 };
 127
 128 static void imx_gpt_set_freq(IMXGPTState *s)
 129 {
 130     uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
 131
 132     s->freq = imx_ccm_get_clock_frequency(s->ccm,
 133                                           s->clocks[clksrc]) / (1 + s->pr);
 134
 135     DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);
 136
 137     if (s->freq) {
 138         ptimer_set_freq(s->timer, s->freq);
 139     }
 140 }
 141
 142 static void imx_gpt_update_int(IMXGPTState *s)
 143 {
 144     if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
 145         qemu_irq_raise(s->irq);
 146     } else {
 147         qemu_irq_lower(s->irq);
 148     }
 149 }
 150
 151 static uint32_t imx_gpt_update_count(IMXGPTState *s)
 152 {
 153     s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
 154
 155     return s->cnt;
 156 }
 157
 158 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
 159                                           uint32_t timeout)
 160 {
 161     if ((count < reg) && (timeout > reg)) {
 162         timeout = reg;
 163     }
 164
 165     return timeout;
 166 }
 167
 168 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
 169 {
 170     uint32_t timeout = GPT_TIMER_MAX;
 171     uint32_t count;
 172     long long limit;
 173
 174     if (!(s->cr & GPT_CR_EN)) {
 175         /* if not enabled just return */
 176         return;
 177     }
 178
 179     /* update the count */
 180     count = imx_gpt_update_count(s);
 181
 182     if (event) {
 183         /*
 184          * This is an event (the ptimer reached 0 and stopped), and the
 185          * timer counter is now equal to s->next_timeout.
 186          */
 187         if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) {
 188             /* We are in restart mode and we crossed the compare channel 1
 189              * value. We need to reset the counter to 0.
 190              */
 191             count = s->cnt = s->next_timeout = 0;
 192         } else if (count == GPT_TIMER_MAX) {
 193             /* We reached GPT_TIMER_MAX so we need to rollover */
 194             count = s->cnt = s->next_timeout = 0;
 195         }
 196     }
 197
 198     /* now, find the next timeout related to count */
 199
 200     if (s->ir & GPT_IR_OF1IE) {
 201         timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
 202     }
 203     if (s->ir & GPT_IR_OF2IE) {
 204         timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
 205     }
 206     if (s->ir & GPT_IR_OF3IE) {
 207         timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
 208     }
 209
 210     /* find the next set of interrupts to raise for next timer event */
 211
 212     s->next_int = 0;
 213     if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
 214         s->next_int |= GPT_SR_OF1;
 215     }
 216     if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
 217         s->next_int |= GPT_SR_OF2;
 218     }
 219     if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
 220         s->next_int |= GPT_SR_OF3;
 221     }
 222     if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) {
 223         s->next_int |= GPT_SR_ROV;
 224     }
 225
 226     /* the new range to count down from */
 227     limit = timeout - imx_gpt_update_count(s);
 228
 229     if (limit < 0) {
 230         /*
 231          * if we reach here, then QEMU is running too slow and we pass the
 232          * timeout limit while computing it. Let's deliver the interrupt
 233          * and compute a new limit.
 234          */
 235         s->sr |= s->next_int;
 236
 237         imx_gpt_compute_next_timeout(s, event);
 238
 239         imx_gpt_update_int(s);
 240     } else {
 241         /* New timeout value */
 242         s->next_timeout = timeout;
 243
 244         /* reset the limit to the computed range */
 245         ptimer_set_limit(s->timer, limit, 1);
 246     }
 247 }
 248
 249 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
 250 {
 251     IMXGPTState *s = IMX_GPT(opaque);
 252     uint32_t reg_value = 0;
 253
 254     switch (offset >> 2) {
 255     case 0: /* Control Register */
 256         reg_value = s->cr;
 257         break;
 258
 259     case 1: /* prescaler */
 260         reg_value = s->pr;
 261         break;
 262
 263     case 2: /* Status Register */
 264         reg_value = s->sr;
 265         break;
 266
 267     case 3: /* Interrupt Register */
 268         reg_value = s->ir;
 269         break;
 270
 271     case 4: /* Output Compare Register 1 */
 272         reg_value = s->ocr1;
 273         break;
 274
 275     case 5: /* Output Compare Register 2 */
 276         reg_value = s->ocr2;
 277         break;
 278
 279     case 6: /* Output Compare Register 3 */
 280         reg_value = s->ocr3;
 281         break;
 282
 283     case 7: /* input Capture Register 1 */
 284         qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
 285                       TYPE_IMX_GPT, __func__);
 286         reg_value = s->icr1;
 287         break;
 288
 289     case 8: /* input Capture Register 2 */
 290         qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
 291                       TYPE_IMX_GPT, __func__);
 292         reg_value = s->icr2;
 293         break;
 294
 295     case 9: /* cnt */
 296         imx_gpt_update_count(s);
 297         reg_value = s->cnt;
 298         break;
 299
 300     default:
 301         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 302                       HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
 303         break;
 304     }
 305
 306     DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);
 307
 308     return reg_value;
 309 }
 310
 311
 312 static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset)
 313 {
 314     /* stop timer */
 315     ptimer_stop(s->timer);
 316
 317     /* Soft reset and hard reset differ only in their handling of the CR
 318      * register -- soft reset preserves the values of some bits there.
 319      */
 320     if (is_soft_reset) {
 321         /* Clear all CR bits except those that are preserved by soft reset. */
 322         s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN |
 323             GPT_CR_WAITEN | GPT_CR_DBGEN |
 324             (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT);
 325     } else {
 326         s->cr = 0;
 327     }
 328     s->sr = 0;
 329     s->pr = 0;
 330     s->ir = 0;
 331     s->cnt = 0;
 332     s->ocr1 = GPT_TIMER_MAX;
 333     s->ocr2 = GPT_TIMER_MAX;
 334     s->ocr3 = GPT_TIMER_MAX;
 335     s->icr1 = 0;
 336     s->icr2 = 0;
 337
 338     s->next_timeout = GPT_TIMER_MAX;
 339     s->next_int = 0;
 340
 341     /* compute new freq */
 342     imx_gpt_set_freq(s);
 343
 344     /* reset the limit to GPT_TIMER_MAX */
 345     ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
 346
 347     /* if the timer is still enabled, restart it */
 348     if (s->freq && (s->cr & GPT_CR_EN)) {
 349         ptimer_run(s->timer, 1);
 350     }
 351 }
 352
 353 static void imx_gpt_soft_reset(DeviceState *dev)
 354 {
 355     IMXGPTState *s = IMX_GPT(dev);
 356     imx_gpt_reset_common(s, true);
 357 }
 358
 359 static void imx_gpt_reset(DeviceState *dev)
 360 {
 361     IMXGPTState *s = IMX_GPT(dev);
 362     imx_gpt_reset_common(s, false);
 363 }
 364
 365 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
 366                           unsigned size)
 367 {
 368     IMXGPTState *s = IMX_GPT(opaque);
 369     uint32_t oldreg;
 370
 371     DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),
 372             (uint32_t)value);
 373
 374     switch (offset >> 2) {
 375     case 0:
 376         oldreg = s->cr;
 377         s->cr = value & ~0x7c14;
 378         if (s->cr & GPT_CR_SWR) { /* force reset */
 379             /* handle the reset */
 380             imx_gpt_soft_reset(DEVICE(s));
 381         } else {
 382             /* set our freq, as the source might have changed */
 383             imx_gpt_set_freq(s);
 384
 385             if ((oldreg ^ s->cr) & GPT_CR_EN) {
 386                 if (s->cr & GPT_CR_EN) {
 387                     if (s->cr & GPT_CR_ENMOD) {
 388                         s->next_timeout = GPT_TIMER_MAX;
 389                         ptimer_set_count(s->timer, GPT_TIMER_MAX);
 390                         imx_gpt_compute_next_timeout(s, false);
 391                     }
 392                     ptimer_run(s->timer, 1);
 393                 } else {
 394                     /* stop timer */
 395                     ptimer_stop(s->timer);
 396                 }
 397             }
 398         }
 399         break;
 400
 401     case 1: /* Prescaler */
 402         s->pr = value & 0xfff;
 403         imx_gpt_set_freq(s);
 404         break;
 405
 406     case 2: /* SR */
 407         s->sr &= ~(value & 0x3f);
 408         imx_gpt_update_int(s);
 409         break;
 410
 411     case 3: /* IR -- interrupt register */
 412         s->ir = value & 0x3f;
 413         imx_gpt_update_int(s);
 414
 415         imx_gpt_compute_next_timeout(s, false);
 416
 417         break;
 418
 419     case 4: /* OCR1 -- output compare register */
 420         s->ocr1 = value;
 421
 422         /* In non-freerun mode, reset count when this register is written */
 423         if (!(s->cr & GPT_CR_FRR)) {
 424             s->next_timeout = GPT_TIMER_MAX;
 425             ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
 426         }
 427
 428         /* compute the new timeout */
 429         imx_gpt_compute_next_timeout(s, false);
 430
 431         break;
 432
 433     case 5: /* OCR2 -- output compare register */
 434         s->ocr2 = value;
 435
 436         /* compute the new timeout */
 437         imx_gpt_compute_next_timeout(s, false);
 438
 439         break;
 440
 441     case 6: /* OCR3 -- output compare register */
 442         s->ocr3 = value;
 443
 444         /* compute the new timeout */
 445         imx_gpt_compute_next_timeout(s, false);
 446
 447         break;
 448
 449     default:
 450         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 451                       HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
 452         break;
 453     }
 454 }
 455
 456 static void imx_gpt_timeout(void *opaque)
 457 {
 458     IMXGPTState *s = IMX_GPT(opaque);
 459
 460     DPRINTF("\n");
 461
 462     s->sr |= s->next_int;
 463     s->next_int = 0;
 464
 465     imx_gpt_compute_next_timeout(s, true);
 466
 467     imx_gpt_update_int(s);
 468
 469     if (s->freq && (s->cr & GPT_CR_EN)) {
 470         ptimer_run(s->timer, 1);
 471     }
 472 }
 473
 474 static const MemoryRegionOps imx_gpt_ops = {
 475     .read = imx_gpt_read,
 476     .write = imx_gpt_write,
 477     .endianness = DEVICE_NATIVE_ENDIAN,
 478 };
 479
 480
 481 static void imx_gpt_realize(DeviceState *dev, Error **errp)
 482 {
 483     IMXGPTState *s = IMX_GPT(dev);
 484     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 485     QEMUBH *bh;
 486
 487     sysbus_init_irq(sbd, &s->irq);
 488     memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
 489                           0x00001000);
 490     sysbus_init_mmio(sbd, &s->iomem);
 491
 492     bh = qemu_bh_new(imx_gpt_timeout, s);
 493     s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
 494 }
 495
 496 static void imx_gpt_class_init(ObjectClass *klass, void *data)
 497 {
 498     DeviceClass *dc = DEVICE_CLASS(klass);
 499
 500     dc->realize = imx_gpt_realize;
 501     dc->reset = imx_gpt_reset;
 502     dc->vmsd = &vmstate_imx_timer_gpt;
 503     dc->desc = "i.MX general timer";
 504 }
 505
 506 static void imx25_gpt_init(Object *obj)
 507 {
 508     IMXGPTState *s = IMX_GPT(obj);
 509
 510     s->clocks = imx25_gpt_clocks;
 511 }
 512
 513 static void imx31_gpt_init(Object *obj)
 514 {
 515     IMXGPTState *s = IMX_GPT(obj);
 516
 517     s->clocks = imx31_gpt_clocks;
 518 }
 519
 520 static void imx6_gpt_init(Object *obj)
 521 {
 522     IMXGPTState *s = IMX_GPT(obj);
 523
 524     s->clocks = imx6_gpt_clocks;
 525 }
 526
 527 static void imx7_gpt_init(Object *obj)
 528 {
 529     IMXGPTState *s = IMX_GPT(obj);
 530
 531     s->clocks = imx7_gpt_clocks;
 532 }
 533
 534 static const TypeInfo imx25_gpt_info = {
 535     .name = TYPE_IMX25_GPT,
 536     .parent = TYPE_SYS_BUS_DEVICE,
 537     .instance_size = sizeof(IMXGPTState),
 538     .instance_init = imx25_gpt_init,
 539     .class_init = imx_gpt_class_init,
 540 };
 541
 542 static const TypeInfo imx31_gpt_info = {
 543     .name = TYPE_IMX31_GPT,
 544     .parent = TYPE_IMX25_GPT,
 545     .instance_init = imx31_gpt_init,
 546 };
 547
 548 static const TypeInfo imx6_gpt_info = {
 549     .name = TYPE_IMX6_GPT,
 550     .parent = TYPE_IMX25_GPT,
 551     .instance_init = imx6_gpt_init,
 552 };
 553
 554 static const TypeInfo imx7_gpt_info = {
 555     .name = TYPE_IMX7_GPT,
 556     .parent = TYPE_IMX25_GPT,
 557     .instance_init = imx7_gpt_init,
 558 };
 559
 560 static void imx_gpt_register_types(void)
 561 {
 562     type_register_static(&imx25_gpt_info);
 563     type_register_static(&imx31_gpt_info);
 564     type_register_static(&imx6_gpt_info);
 565     type_register_static(&imx7_gpt_info);
 566 }
 567
 568 type_init(imx_gpt_register_types)