2 * QEMU PowerPC PowerNV LPC controller
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "sysemu/sysemu.h"
22 #include "target/ppc/cpu.h"
23 #include "qapi/error.h"
25 #include "qemu/module.h"
26 #include "hw/isa/isa.h"
28 #include "hw/ppc/pnv.h"
29 #include "hw/ppc/pnv_lpc.h"
30 #include "hw/ppc/pnv_xscom.h"
31 #include "hw/ppc/fdt.h"
42 /* OPB Master LS registers */
43 #define OPB_MASTER_LS_ROUTE0 0x8
44 #define OPB_MASTER_LS_ROUTE1 0xC
45 #define OPB_MASTER_LS_IRQ_STAT 0x50
46 #define OPB_MASTER_IRQ_LPC 0x00000800
47 #define OPB_MASTER_LS_IRQ_MASK 0x54
48 #define OPB_MASTER_LS_IRQ_POL 0x58
49 #define OPB_MASTER_LS_IRQ_INPUT 0x5c
51 /* LPC HC registers */
52 #define LPC_HC_FW_SEG_IDSEL 0x24
53 #define LPC_HC_FW_RD_ACC_SIZE 0x28
54 #define LPC_HC_FW_RD_1B 0x00000000
55 #define LPC_HC_FW_RD_2B 0x01000000
56 #define LPC_HC_FW_RD_4B 0x02000000
57 #define LPC_HC_FW_RD_16B 0x04000000
58 #define LPC_HC_FW_RD_128B 0x07000000
59 #define LPC_HC_IRQSER_CTRL 0x30
60 #define LPC_HC_IRQSER_EN 0x80000000
61 #define LPC_HC_IRQSER_QMODE 0x40000000
62 #define LPC_HC_IRQSER_START_MASK 0x03000000
63 #define LPC_HC_IRQSER_START_4CLK 0x00000000
64 #define LPC_HC_IRQSER_START_6CLK 0x01000000
65 #define LPC_HC_IRQSER_START_8CLK 0x02000000
66 #define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */
67 #define LPC_HC_IRQSTAT 0x38
68 #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
69 #define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
70 #define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000
71 #define LPC_HC_IRQ_LRESET 0x00000400
72 #define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080
73 #define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040
74 #define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020
75 #define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010
76 #define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008
77 #define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004
78 #define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002
79 #define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001
80 #define LPC_HC_ERROR_ADDRESS 0x40
82 #define LPC_OPB_SIZE 0x100000000ull
84 #define ISA_IO_SIZE 0x00010000
85 #define ISA_MEM_SIZE 0x10000000
86 #define ISA_FW_SIZE 0x10000000
87 #define LPC_IO_OPB_ADDR 0xd0010000
88 #define LPC_IO_OPB_SIZE 0x00010000
89 #define LPC_MEM_OPB_ADDR 0xe0010000
90 #define LPC_MEM_OPB_SIZE 0x10000000
91 #define LPC_FW_OPB_ADDR 0xf0000000
92 #define LPC_FW_OPB_SIZE 0x10000000
94 #define LPC_OPB_REGS_OPB_ADDR 0xc0010000
95 #define LPC_OPB_REGS_OPB_SIZE 0x00000060
96 #define LPC_OPB_REGS_OPBA_ADDR 0xc0011000
97 #define LPC_OPB_REGS_OPBA_SIZE 0x00000008
98 #define LPC_HC_REGS_OPB_ADDR 0xc0012000
99 #define LPC_HC_REGS_OPB_SIZE 0x00000100
101 static int pnv_lpc_dt_xscom(PnvXScomInterface
*dev
, void *fdt
, int xscom_offset
)
103 const char compat
[] = "ibm,power8-lpc\0ibm,lpc";
106 uint32_t lpc_pcba
= PNV_XSCOM_LPC_BASE
;
108 cpu_to_be32(lpc_pcba
),
109 cpu_to_be32(PNV_XSCOM_LPC_SIZE
)
112 name
= g_strdup_printf("isa@%x", lpc_pcba
);
113 offset
= fdt_add_subnode(fdt
, xscom_offset
, name
);
117 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, sizeof(reg
))));
118 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 2)));
119 _FDT((fdt_setprop_cell(fdt
, offset
, "#size-cells", 1)));
120 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
125 int pnv_dt_lpc(PnvChip
*chip
, void *fdt
, int root_offset
)
127 const char compat
[] = "ibm,power9-lpcm-opb\0simple-bus";
128 const char lpc_compat
[] = "ibm,power9-lpc\0ibm,lpc";
130 int offset
, lpcm_offset
;
131 uint64_t lpcm_addr
= PNV9_LPCM_BASE(chip
);
132 uint32_t opb_ranges
[8] = { 0,
133 cpu_to_be32(lpcm_addr
>> 32),
134 cpu_to_be32((uint32_t)lpcm_addr
),
135 cpu_to_be32(PNV9_LPCM_SIZE
/ 2),
136 cpu_to_be32(PNV9_LPCM_SIZE
/ 2),
137 cpu_to_be32(lpcm_addr
>> 32),
138 cpu_to_be32(PNV9_LPCM_SIZE
/ 2),
139 cpu_to_be32(PNV9_LPCM_SIZE
/ 2),
141 uint32_t opb_reg
[4] = { cpu_to_be32(lpcm_addr
>> 32),
142 cpu_to_be32((uint32_t)lpcm_addr
),
143 cpu_to_be32(PNV9_LPCM_SIZE
>> 32),
144 cpu_to_be32((uint32_t)PNV9_LPCM_SIZE
),
151 name
= g_strdup_printf("lpcm-opb@%"PRIx64
, lpcm_addr
);
152 lpcm_offset
= fdt_add_subnode(fdt
, root_offset
, name
);
156 _FDT((fdt_setprop(fdt
, lpcm_offset
, "reg", opb_reg
, sizeof(opb_reg
))));
157 _FDT((fdt_setprop_cell(fdt
, lpcm_offset
, "#address-cells", 1)));
158 _FDT((fdt_setprop_cell(fdt
, lpcm_offset
, "#size-cells", 1)));
159 _FDT((fdt_setprop(fdt
, lpcm_offset
, "compatible", compat
, sizeof(compat
))));
160 _FDT((fdt_setprop_cell(fdt
, lpcm_offset
, "ibm,chip-id", chip
->chip_id
)));
161 _FDT((fdt_setprop(fdt
, lpcm_offset
, "ranges", opb_ranges
,
162 sizeof(opb_ranges
))));
165 * OPB Master registers
167 name
= g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR
);
168 offset
= fdt_add_subnode(fdt
, lpcm_offset
, name
);
172 reg
[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR
);
173 reg
[1] = cpu_to_be32(LPC_OPB_REGS_OPB_SIZE
);
174 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, sizeof(reg
))));
175 _FDT((fdt_setprop_string(fdt
, offset
, "compatible",
176 "ibm,power9-lpcm-opb-master")));
179 * OPB arbitrer registers
181 name
= g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR
);
182 offset
= fdt_add_subnode(fdt
, lpcm_offset
, name
);
186 reg
[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR
);
187 reg
[1] = cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE
);
188 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, sizeof(reg
))));
189 _FDT((fdt_setprop_string(fdt
, offset
, "compatible",
190 "ibm,power9-lpcm-opb-arbiter")));
193 * LPC Host Controller registers
195 name
= g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR
);
196 offset
= fdt_add_subnode(fdt
, lpcm_offset
, name
);
200 reg
[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR
);
201 reg
[1] = cpu_to_be32(LPC_HC_REGS_OPB_SIZE
);
202 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, sizeof(reg
))));
203 _FDT((fdt_setprop_string(fdt
, offset
, "compatible",
204 "ibm,power9-lpc-controller")));
206 name
= g_strdup_printf("lpc@0");
207 offset
= fdt_add_subnode(fdt
, lpcm_offset
, name
);
210 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 2)));
211 _FDT((fdt_setprop_cell(fdt
, offset
, "#size-cells", 1)));
212 _FDT((fdt_setprop(fdt
, offset
, "compatible", lpc_compat
,
213 sizeof(lpc_compat
))));
219 * These read/write handlers of the OPB address space should be common
220 * with the P9 LPC Controller which uses direct MMIOs.
222 * TODO: rework to use address_space_stq() and address_space_ldq()
225 static bool opb_read(PnvLpcController
*lpc
, uint32_t addr
, uint8_t *data
,
228 /* XXX Handle access size limits and FW read caching here */
229 return !address_space_rw(&lpc
->opb_as
, addr
, MEMTXATTRS_UNSPECIFIED
,
233 static bool opb_write(PnvLpcController
*lpc
, uint32_t addr
, uint8_t *data
,
236 /* XXX Handle access size limits here */
237 return !address_space_rw(&lpc
->opb_as
, addr
, MEMTXATTRS_UNSPECIFIED
,
241 #define ECCB_CTL_READ PPC_BIT(15)
242 #define ECCB_CTL_SZ_LSH (63 - 7)
243 #define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7)
244 #define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63)
246 #define ECCB_STAT_OP_DONE PPC_BIT(52)
247 #define ECCB_STAT_OP_ERR PPC_BIT(52)
248 #define ECCB_STAT_RD_DATA_LSH (63 - 37)
249 #define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH)
251 static void pnv_lpc_do_eccb(PnvLpcController
*lpc
, uint64_t cmd
)
253 /* XXX Check for magic bits at the top, addr size etc... */
254 unsigned int sz
= (cmd
& ECCB_CTL_SZ_MASK
) >> ECCB_CTL_SZ_LSH
;
255 uint32_t opb_addr
= cmd
& ECCB_CTL_ADDR_MASK
;
259 if (sz
> sizeof(data
)) {
260 qemu_log_mask(LOG_GUEST_ERROR
,
261 "ECCB: invalid operation at @0x%08x size %d\n", opb_addr
, sz
);
265 if (cmd
& ECCB_CTL_READ
) {
266 success
= opb_read(lpc
, opb_addr
, data
, sz
);
268 lpc
->eccb_stat_reg
= ECCB_STAT_OP_DONE
|
269 (((uint64_t)data
[0]) << 24 |
270 ((uint64_t)data
[1]) << 16 |
271 ((uint64_t)data
[2]) << 8 |
272 ((uint64_t)data
[3])) << ECCB_STAT_RD_DATA_LSH
;
274 lpc
->eccb_stat_reg
= ECCB_STAT_OP_DONE
|
275 (0xffffffffull
<< ECCB_STAT_RD_DATA_LSH
);
278 data
[0] = lpc
->eccb_data_reg
>> 24;
279 data
[1] = lpc
->eccb_data_reg
>> 16;
280 data
[2] = lpc
->eccb_data_reg
>> 8;
281 data
[3] = lpc
->eccb_data_reg
;
283 success
= opb_write(lpc
, opb_addr
, data
, sz
);
284 lpc
->eccb_stat_reg
= ECCB_STAT_OP_DONE
;
286 /* XXX Which error bit (if any) to signal OPB error ? */
289 static uint64_t pnv_lpc_xscom_read(void *opaque
, hwaddr addr
, unsigned size
)
291 PnvLpcController
*lpc
= PNV_LPC(opaque
);
292 uint32_t offset
= addr
>> 3;
295 switch (offset
& 3) {
301 val
= lpc
->eccb_stat_reg
;
302 lpc
->eccb_stat_reg
= 0;
305 val
= ((uint64_t)lpc
->eccb_data_reg
) << 32;
311 static void pnv_lpc_xscom_write(void *opaque
, hwaddr addr
,
312 uint64_t val
, unsigned size
)
314 PnvLpcController
*lpc
= PNV_LPC(opaque
);
315 uint32_t offset
= addr
>> 3;
317 switch (offset
& 3) {
319 pnv_lpc_do_eccb(lpc
, val
);
327 lpc
->eccb_data_reg
= val
>> 32;
332 static const MemoryRegionOps pnv_lpc_xscom_ops
= {
333 .read
= pnv_lpc_xscom_read
,
334 .write
= pnv_lpc_xscom_write
,
335 .valid
.min_access_size
= 8,
336 .valid
.max_access_size
= 8,
337 .impl
.min_access_size
= 8,
338 .impl
.max_access_size
= 8,
339 .endianness
= DEVICE_BIG_ENDIAN
,
342 static uint64_t pnv_lpc_mmio_read(void *opaque
, hwaddr addr
, unsigned size
)
344 PnvLpcController
*lpc
= PNV_LPC(opaque
);
346 uint32_t opb_addr
= addr
& ECCB_CTL_ADDR_MASK
;
351 val
= address_space_ldl(&lpc
->opb_as
, opb_addr
, MEMTXATTRS_UNSPECIFIED
,
355 val
= address_space_ldub(&lpc
->opb_as
, opb_addr
, MEMTXATTRS_UNSPECIFIED
,
359 qemu_log_mask(LOG_GUEST_ERROR
, "OPB read failed at @0x%"
360 HWADDR_PRIx
" invalid size %d\n", addr
, size
);
364 if (result
!= MEMTX_OK
) {
365 qemu_log_mask(LOG_GUEST_ERROR
, "OPB read failed at @0x%"
366 HWADDR_PRIx
"\n", addr
);
372 static void pnv_lpc_mmio_write(void *opaque
, hwaddr addr
,
373 uint64_t val
, unsigned size
)
375 PnvLpcController
*lpc
= PNV_LPC(opaque
);
376 uint32_t opb_addr
= addr
& ECCB_CTL_ADDR_MASK
;
381 address_space_stl(&lpc
->opb_as
, opb_addr
, val
, MEMTXATTRS_UNSPECIFIED
,
385 address_space_stb(&lpc
->opb_as
, opb_addr
, val
, MEMTXATTRS_UNSPECIFIED
,
389 qemu_log_mask(LOG_GUEST_ERROR
, "OPB write failed at @0x%"
390 HWADDR_PRIx
" invalid size %d\n", addr
, size
);
394 if (result
!= MEMTX_OK
) {
395 qemu_log_mask(LOG_GUEST_ERROR
, "OPB write failed at @0x%"
396 HWADDR_PRIx
"\n", addr
);
400 static const MemoryRegionOps pnv_lpc_mmio_ops
= {
401 .read
= pnv_lpc_mmio_read
,
402 .write
= pnv_lpc_mmio_write
,
404 .min_access_size
= 1,
405 .max_access_size
= 4,
407 .endianness
= DEVICE_BIG_ENDIAN
,
410 static void pnv_lpc_eval_irqs(PnvLpcController
*lpc
)
412 bool lpc_to_opb_irq
= false;
413 PnvLpcClass
*plc
= PNV_LPC_GET_CLASS(lpc
);
415 /* Update LPC controller to OPB line */
416 if (lpc
->lpc_hc_irqser_ctrl
& LPC_HC_IRQSER_EN
) {
419 irqs
= lpc
->lpc_hc_irqstat
& lpc
->lpc_hc_irqmask
;
420 lpc_to_opb_irq
= (irqs
!= 0);
423 /* We don't honor the polarity register, it's pointless and unused
426 if (lpc_to_opb_irq
) {
427 lpc
->opb_irq_input
|= OPB_MASTER_IRQ_LPC
;
429 lpc
->opb_irq_input
&= ~OPB_MASTER_IRQ_LPC
;
432 /* Update OPB internal latch */
433 lpc
->opb_irq_stat
|= lpc
->opb_irq_input
& lpc
->opb_irq_mask
;
435 /* Reflect the interrupt */
436 pnv_psi_irq_set(lpc
->psi
, plc
->psi_irq
, lpc
->opb_irq_stat
!= 0);
439 static uint64_t lpc_hc_read(void *opaque
, hwaddr addr
, unsigned size
)
441 PnvLpcController
*lpc
= opaque
;
442 uint64_t val
= 0xfffffffffffffffful
;
445 case LPC_HC_FW_SEG_IDSEL
:
446 val
= lpc
->lpc_hc_fw_seg_idsel
;
448 case LPC_HC_FW_RD_ACC_SIZE
:
449 val
= lpc
->lpc_hc_fw_rd_acc_size
;
451 case LPC_HC_IRQSER_CTRL
:
452 val
= lpc
->lpc_hc_irqser_ctrl
;
455 val
= lpc
->lpc_hc_irqmask
;
458 val
= lpc
->lpc_hc_irqstat
;
460 case LPC_HC_ERROR_ADDRESS
:
461 val
= lpc
->lpc_hc_error_addr
;
464 qemu_log_mask(LOG_UNIMP
, "LPC HC Unimplemented register: 0x%"
465 HWADDR_PRIx
"\n", addr
);
470 static void lpc_hc_write(void *opaque
, hwaddr addr
, uint64_t val
,
473 PnvLpcController
*lpc
= opaque
;
475 /* XXX Filter out reserved bits */
478 case LPC_HC_FW_SEG_IDSEL
:
479 /* XXX Actually figure out how that works as this impact
480 * memory regions/aliases
482 lpc
->lpc_hc_fw_seg_idsel
= val
;
484 case LPC_HC_FW_RD_ACC_SIZE
:
485 lpc
->lpc_hc_fw_rd_acc_size
= val
;
487 case LPC_HC_IRQSER_CTRL
:
488 lpc
->lpc_hc_irqser_ctrl
= val
;
489 pnv_lpc_eval_irqs(lpc
);
492 lpc
->lpc_hc_irqmask
= val
;
493 pnv_lpc_eval_irqs(lpc
);
496 lpc
->lpc_hc_irqstat
&= ~val
;
497 pnv_lpc_eval_irqs(lpc
);
499 case LPC_HC_ERROR_ADDRESS
:
502 qemu_log_mask(LOG_UNIMP
, "LPC HC Unimplemented register: 0x%"
503 HWADDR_PRIx
"\n", addr
);
507 static const MemoryRegionOps lpc_hc_ops
= {
509 .write
= lpc_hc_write
,
510 .endianness
= DEVICE_BIG_ENDIAN
,
512 .min_access_size
= 4,
513 .max_access_size
= 4,
516 .min_access_size
= 4,
517 .max_access_size
= 4,
521 static uint64_t opb_master_read(void *opaque
, hwaddr addr
, unsigned size
)
523 PnvLpcController
*lpc
= opaque
;
524 uint64_t val
= 0xfffffffffffffffful
;
527 case OPB_MASTER_LS_ROUTE0
: /* TODO */
528 val
= lpc
->opb_irq_route0
;
530 case OPB_MASTER_LS_ROUTE1
: /* TODO */
531 val
= lpc
->opb_irq_route1
;
533 case OPB_MASTER_LS_IRQ_STAT
:
534 val
= lpc
->opb_irq_stat
;
536 case OPB_MASTER_LS_IRQ_MASK
:
537 val
= lpc
->opb_irq_mask
;
539 case OPB_MASTER_LS_IRQ_POL
:
540 val
= lpc
->opb_irq_pol
;
542 case OPB_MASTER_LS_IRQ_INPUT
:
543 val
= lpc
->opb_irq_input
;
546 qemu_log_mask(LOG_UNIMP
, "OPBM: read on unimplemented register: 0x%"
547 HWADDR_PRIx
"\n", addr
);
553 static void opb_master_write(void *opaque
, hwaddr addr
,
554 uint64_t val
, unsigned size
)
556 PnvLpcController
*lpc
= opaque
;
559 case OPB_MASTER_LS_ROUTE0
: /* TODO */
560 lpc
->opb_irq_route0
= val
;
562 case OPB_MASTER_LS_ROUTE1
: /* TODO */
563 lpc
->opb_irq_route1
= val
;
565 case OPB_MASTER_LS_IRQ_STAT
:
566 lpc
->opb_irq_stat
&= ~val
;
567 pnv_lpc_eval_irqs(lpc
);
569 case OPB_MASTER_LS_IRQ_MASK
:
570 lpc
->opb_irq_mask
= val
;
571 pnv_lpc_eval_irqs(lpc
);
573 case OPB_MASTER_LS_IRQ_POL
:
574 lpc
->opb_irq_pol
= val
;
575 pnv_lpc_eval_irqs(lpc
);
577 case OPB_MASTER_LS_IRQ_INPUT
:
581 qemu_log_mask(LOG_UNIMP
, "OPBM: write on unimplemented register: 0x%"
582 HWADDR_PRIx
" val=0x%08"PRIx64
"\n", addr
, val
);
586 static const MemoryRegionOps opb_master_ops
= {
587 .read
= opb_master_read
,
588 .write
= opb_master_write
,
589 .endianness
= DEVICE_BIG_ENDIAN
,
591 .min_access_size
= 4,
592 .max_access_size
= 4,
595 .min_access_size
= 4,
596 .max_access_size
= 4,
600 static void pnv_lpc_power8_realize(DeviceState
*dev
, Error
**errp
)
602 PnvLpcController
*lpc
= PNV_LPC(dev
);
603 PnvLpcClass
*plc
= PNV_LPC_GET_CLASS(dev
);
604 Error
*local_err
= NULL
;
606 plc
->parent_realize(dev
, &local_err
);
608 error_propagate(errp
, local_err
);
612 /* P8 uses a XSCOM region for LPC registers */
613 pnv_xscom_region_init(&lpc
->xscom_regs
, OBJECT(lpc
),
614 &pnv_lpc_xscom_ops
, lpc
, "xscom-lpc",
618 static void pnv_lpc_power8_class_init(ObjectClass
*klass
, void *data
)
620 DeviceClass
*dc
= DEVICE_CLASS(klass
);
621 PnvXScomInterfaceClass
*xdc
= PNV_XSCOM_INTERFACE_CLASS(klass
);
622 PnvLpcClass
*plc
= PNV_LPC_CLASS(klass
);
624 dc
->desc
= "PowerNV LPC Controller POWER8";
626 xdc
->dt_xscom
= pnv_lpc_dt_xscom
;
628 plc
->psi_irq
= PSIHB_IRQ_LPC_I2C
;
630 device_class_set_parent_realize(dc
, pnv_lpc_power8_realize
,
631 &plc
->parent_realize
);
634 static const TypeInfo pnv_lpc_power8_info
= {
635 .name
= TYPE_PNV8_LPC
,
636 .parent
= TYPE_PNV_LPC
,
637 .instance_size
= sizeof(PnvLpcController
),
638 .class_init
= pnv_lpc_power8_class_init
,
639 .interfaces
= (InterfaceInfo
[]) {
640 { TYPE_PNV_XSCOM_INTERFACE
},
645 static void pnv_lpc_power9_realize(DeviceState
*dev
, Error
**errp
)
647 PnvLpcController
*lpc
= PNV_LPC(dev
);
648 PnvLpcClass
*plc
= PNV_LPC_GET_CLASS(dev
);
649 Error
*local_err
= NULL
;
651 plc
->parent_realize(dev
, &local_err
);
653 error_propagate(errp
, local_err
);
657 /* P9 uses a MMIO region */
658 memory_region_init_io(&lpc
->xscom_regs
, OBJECT(lpc
), &pnv_lpc_mmio_ops
,
659 lpc
, "lpcm", PNV9_LPCM_SIZE
);
662 static void pnv_lpc_power9_class_init(ObjectClass
*klass
, void *data
)
664 DeviceClass
*dc
= DEVICE_CLASS(klass
);
665 PnvLpcClass
*plc
= PNV_LPC_CLASS(klass
);
667 dc
->desc
= "PowerNV LPC Controller POWER9";
669 plc
->psi_irq
= PSIHB9_IRQ_LPCHC
;
671 device_class_set_parent_realize(dc
, pnv_lpc_power9_realize
,
672 &plc
->parent_realize
);
675 static const TypeInfo pnv_lpc_power9_info
= {
676 .name
= TYPE_PNV9_LPC
,
677 .parent
= TYPE_PNV_LPC
,
678 .instance_size
= sizeof(PnvLpcController
),
679 .class_init
= pnv_lpc_power9_class_init
,
682 static void pnv_lpc_realize(DeviceState
*dev
, Error
**errp
)
684 PnvLpcController
*lpc
= PNV_LPC(dev
);
686 Error
*local_err
= NULL
;
688 obj
= object_property_get_link(OBJECT(dev
), "psi", &local_err
);
690 error_propagate(errp
, local_err
);
691 error_prepend(errp
, "required link 'psi' not found: ");
694 /* The LPC controller needs PSI to generate interrupts */
695 lpc
->psi
= PNV_PSI(obj
);
698 lpc
->lpc_hc_fw_rd_acc_size
= LPC_HC_FW_RD_4B
;
700 /* Create address space and backing MR for the OPB bus */
701 memory_region_init(&lpc
->opb_mr
, OBJECT(dev
), "lpc-opb", 0x100000000ull
);
702 address_space_init(&lpc
->opb_as
, &lpc
->opb_mr
, "lpc-opb");
704 /* Create ISA IO and Mem space regions which are the root of
705 * the ISA bus (ie, ISA address spaces). We don't create a
706 * separate one for FW which we alias to memory.
708 memory_region_init(&lpc
->isa_io
, OBJECT(dev
), "isa-io", ISA_IO_SIZE
);
709 memory_region_init(&lpc
->isa_mem
, OBJECT(dev
), "isa-mem", ISA_MEM_SIZE
);
710 memory_region_init(&lpc
->isa_fw
, OBJECT(dev
), "isa-fw", ISA_FW_SIZE
);
712 /* Create windows from the OPB space to the ISA space */
713 memory_region_init_alias(&lpc
->opb_isa_io
, OBJECT(dev
), "lpc-isa-io",
714 &lpc
->isa_io
, 0, LPC_IO_OPB_SIZE
);
715 memory_region_add_subregion(&lpc
->opb_mr
, LPC_IO_OPB_ADDR
,
717 memory_region_init_alias(&lpc
->opb_isa_mem
, OBJECT(dev
), "lpc-isa-mem",
718 &lpc
->isa_mem
, 0, LPC_MEM_OPB_SIZE
);
719 memory_region_add_subregion(&lpc
->opb_mr
, LPC_MEM_OPB_ADDR
,
721 memory_region_init_alias(&lpc
->opb_isa_fw
, OBJECT(dev
), "lpc-isa-fw",
722 &lpc
->isa_fw
, 0, LPC_FW_OPB_SIZE
);
723 memory_region_add_subregion(&lpc
->opb_mr
, LPC_FW_OPB_ADDR
,
726 /* Create MMIO regions for LPC HC and OPB registers */
727 memory_region_init_io(&lpc
->opb_master_regs
, OBJECT(dev
), &opb_master_ops
,
728 lpc
, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE
);
729 memory_region_add_subregion(&lpc
->opb_mr
, LPC_OPB_REGS_OPB_ADDR
,
730 &lpc
->opb_master_regs
);
731 memory_region_init_io(&lpc
->lpc_hc_regs
, OBJECT(dev
), &lpc_hc_ops
, lpc
,
732 "lpc-hc", LPC_HC_REGS_OPB_SIZE
);
733 memory_region_add_subregion(&lpc
->opb_mr
, LPC_HC_REGS_OPB_ADDR
,
737 static void pnv_lpc_class_init(ObjectClass
*klass
, void *data
)
739 DeviceClass
*dc
= DEVICE_CLASS(klass
);
741 dc
->realize
= pnv_lpc_realize
;
742 dc
->desc
= "PowerNV LPC Controller";
745 static const TypeInfo pnv_lpc_info
= {
746 .name
= TYPE_PNV_LPC
,
747 .parent
= TYPE_DEVICE
,
748 .class_init
= pnv_lpc_class_init
,
749 .class_size
= sizeof(PnvLpcClass
),
753 static void pnv_lpc_register_types(void)
755 type_register_static(&pnv_lpc_info
);
756 type_register_static(&pnv_lpc_power8_info
);
757 type_register_static(&pnv_lpc_power9_info
);
760 type_init(pnv_lpc_register_types
)
762 /* If we don't use the built-in LPC interrupt deserializer, we need
763 * to provide a set of qirqs for the ISA bus or things will go bad.
765 * Most machines using pre-Naples chips (without said deserializer)
766 * have a CPLD that will collect the SerIRQ and shoot them as a
767 * single level interrupt to the P8 chip. So let's setup a hook
768 * for doing just that.
770 static void pnv_lpc_isa_irq_handler_cpld(void *opaque
, int n
, int level
)
772 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
773 uint32_t old_state
= pnv
->cpld_irqstate
;
774 PnvLpcController
*lpc
= PNV_LPC(opaque
);
777 pnv
->cpld_irqstate
|= 1u << n
;
779 pnv
->cpld_irqstate
&= ~(1u << n
);
782 if (pnv
->cpld_irqstate
!= old_state
) {
783 pnv_psi_irq_set(lpc
->psi
, PSIHB_IRQ_EXTERNAL
, pnv
->cpld_irqstate
!= 0);
787 static void pnv_lpc_isa_irq_handler(void *opaque
, int n
, int level
)
789 PnvLpcController
*lpc
= PNV_LPC(opaque
);
791 /* The Naples HW latches the 1 levels, clearing is done by SW */
793 lpc
->lpc_hc_irqstat
|= LPC_HC_IRQ_SERIRQ0
>> n
;
794 pnv_lpc_eval_irqs(lpc
);
798 ISABus
*pnv_lpc_isa_create(PnvLpcController
*lpc
, bool use_cpld
, Error
**errp
)
800 Error
*local_err
= NULL
;
803 qemu_irq_handler handler
;
805 /* let isa_bus_new() create its own bridge on SysBus otherwise
806 * devices speficied on the command line won't find the bus and
807 * will fail to create.
809 isa_bus
= isa_bus_new(NULL
, &lpc
->isa_mem
, &lpc
->isa_io
, &local_err
);
811 error_propagate(errp
, local_err
);
815 /* Not all variants have a working serial irq decoder. If not,
816 * handling of LPC interrupts becomes a platform issue (some
817 * platforms have a CPLD to do it).
820 handler
= pnv_lpc_isa_irq_handler_cpld
;
822 handler
= pnv_lpc_isa_irq_handler
;
825 irqs
= qemu_allocate_irqs(handler
, lpc
, ISA_NUM_IRQS
);
827 isa_bus_irqs(isa_bus
, irqs
);