hw/gpio/imx_gpio.c

   1 /*
   2  * i.MX processors GPIO emulation.
   3  *
   4  * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/gpio/imx_gpio.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24
  25 #ifndef DEBUG_IMX_GPIO
  26 #define DEBUG_IMX_GPIO 0
  27 #endif
  28
  29 typedef enum IMXGPIOLevel {
  30     IMX_GPIO_LEVEL_LOW = 0,
  31     IMX_GPIO_LEVEL_HIGH = 1,
  32 } IMXGPIOLevel;
  33
  34 #define DPRINTF(fmt, args...) \
  35     do { \
  36         if (DEBUG_IMX_GPIO) { \
  37             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \
  38                                              __func__, ##args); \
  39         } \
  40     } while (0)
  41
  42 static const char *imx_gpio_reg_name(uint32_t reg)
  43 {
  44     switch (reg) {
  45     case DR_ADDR:
  46         return "DR";
  47     case GDIR_ADDR:
  48         return "GDIR";
  49     case PSR_ADDR:
  50         return "PSR";
  51     case ICR1_ADDR:
  52         return "ICR1";
  53     case ICR2_ADDR:
  54         return "ICR2";
  55     case IMR_ADDR:
  56         return "IMR";
  57     case ISR_ADDR:
  58         return "ISR";
  59     case EDGE_SEL_ADDR:
  60         return "EDGE_SEL";
  61     default:
  62         return "[?]";
  63     }
  64 }
  65
  66 static void imx_gpio_update_int(IMXGPIOState *s)
  67 {
  68     if (s->has_upper_pin_irq) {
  69         qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0);
  70         qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0);
  71     } else {
  72         qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0);
  73     }
  74 }
  75
  76 static void imx_gpio_set_int_line(IMXGPIOState *s, int line, IMXGPIOLevel level)
  77 {
  78     /* if this signal isn't configured as an input signal, nothing to do */
  79     if (!extract32(s->gdir, line, 1)) {
  80         return;
  81     }
  82
  83     /* When set, EDGE_SEL overrides the ICR config */
  84     if (extract32(s->edge_sel, line, 1)) {
  85         /* we detect interrupt on rising and falling edge */
  86         if (extract32(s->psr, line, 1) != level) {
  87             /* level changed */
  88             s->isr = deposit32(s->isr, line, 1, 1);
  89         }
  90     } else if (extract64(s->icr, 2*line + 1, 1)) {
  91         /* interrupt is edge sensitive */
  92         if (extract32(s->psr, line, 1) != level) {
  93             /* level changed */
  94             if (extract64(s->icr, 2*line, 1) != level) {
  95                 s->isr = deposit32(s->isr, line, 1, 1);
  96             }
  97         }
  98     } else {
  99         /* interrupt is level sensitive */
 100         if (extract64(s->icr, 2*line, 1) == level) {
 101             s->isr = deposit32(s->isr, line, 1, 1);
 102         }
 103     }
 104 }
 105
 106 static void imx_gpio_set(void *opaque, int line, int level)
 107 {
 108     IMXGPIOState *s = IMX_GPIO(opaque);
 109     IMXGPIOLevel imx_level = level ? IMX_GPIO_LEVEL_HIGH : IMX_GPIO_LEVEL_LOW;
 110
 111     imx_gpio_set_int_line(s, line, imx_level);
 112
 113     /* this is an input signal, so set PSR */
 114     s->psr = deposit32(s->psr, line, 1, imx_level);
 115
 116     imx_gpio_update_int(s);
 117 }
 118
 119 static void imx_gpio_set_all_int_lines(IMXGPIOState *s)
 120 {
 121     int i;
 122
 123     for (i = 0; i < IMX_GPIO_PIN_COUNT; i++) {
 124         IMXGPIOLevel imx_level = extract32(s->psr, i, 1);
 125         imx_gpio_set_int_line(s, i, imx_level);
 126     }
 127
 128     imx_gpio_update_int(s);
 129 }
 130
 131 static inline void imx_gpio_set_all_output_lines(IMXGPIOState *s)
 132 {
 133     int i;
 134
 135     for (i = 0; i < IMX_GPIO_PIN_COUNT; i++) {
 136         /*
 137          * if the line is set as output, then forward the line
 138          * level to its user.
 139          */
 140         if (extract32(s->gdir, i, 1) && s->output[i]) {
 141             qemu_set_irq(s->output[i], extract32(s->dr, i, 1));
 142         }
 143     }
 144 }
 145
 146 static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size)
 147 {
 148     IMXGPIOState *s = IMX_GPIO(opaque);
 149     uint32_t reg_value = 0;
 150
 151     switch (offset) {
 152     case DR_ADDR:
 153         /*
 154          * depending on the "line" configuration, the bit values
 155          * are coming either from DR or PSR
 156          */
 157         reg_value = (s->dr & s->gdir) | (s->psr & ~s->gdir);
 158         break;
 159
 160     case GDIR_ADDR:
 161         reg_value = s->gdir;
 162         break;
 163
 164     case PSR_ADDR:
 165         reg_value = s->psr & ~s->gdir;
 166         break;
 167
 168     case ICR1_ADDR:
 169         reg_value = extract64(s->icr, 0, 32);
 170         break;
 171
 172     case ICR2_ADDR:
 173         reg_value = extract64(s->icr, 32, 32);
 174         break;
 175
 176     case IMR_ADDR:
 177         reg_value = s->imr;
 178         break;
 179
 180     case ISR_ADDR:
 181         reg_value = s->isr;
 182         break;
 183
 184     case EDGE_SEL_ADDR:
 185         if (s->has_edge_sel) {
 186             reg_value = s->edge_sel;
 187         } else {
 188             qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
 189                           "present on this version of GPIO device\n",
 190                           TYPE_IMX_GPIO, __func__);
 191         }
 192         break;
 193
 194     default:
 195         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 196                       HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
 197         break;
 198     }
 199
 200     DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value);
 201
 202     return reg_value;
 203 }
 204
 205 static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
 206                            unsigned size)
 207 {
 208     IMXGPIOState *s = IMX_GPIO(opaque);
 209
 210     DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset),
 211             (uint32_t)value);
 212
 213     switch (offset) {
 214     case DR_ADDR:
 215         s->dr = value;
 216         imx_gpio_set_all_output_lines(s);
 217         break;
 218
 219     case GDIR_ADDR:
 220         s->gdir = value;
 221         imx_gpio_set_all_output_lines(s);
 222         imx_gpio_set_all_int_lines(s);
 223         break;
 224
 225     case ICR1_ADDR:
 226         s->icr = deposit64(s->icr, 0, 32, value);
 227         imx_gpio_set_all_int_lines(s);
 228         break;
 229
 230     case ICR2_ADDR:
 231         s->icr = deposit64(s->icr, 32, 32, value);
 232         imx_gpio_set_all_int_lines(s);
 233         break;
 234
 235     case IMR_ADDR:
 236         s->imr = value;
 237         imx_gpio_update_int(s);
 238         break;
 239
 240     case ISR_ADDR:
 241         s->isr &= ~value;
 242         imx_gpio_set_all_int_lines(s);
 243         break;
 244
 245     case EDGE_SEL_ADDR:
 246         if (s->has_edge_sel) {
 247             s->edge_sel = value;
 248             imx_gpio_set_all_int_lines(s);
 249         } else {
 250             qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
 251                           "present on this version of GPIO device\n",
 252                           TYPE_IMX_GPIO, __func__);
 253         }
 254         break;
 255
 256     default:
 257         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 258                       HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
 259         break;
 260     }
 261
 262     return;
 263 }
 264
 265 static const MemoryRegionOps imx_gpio_ops = {
 266     .read = imx_gpio_read,
 267     .write = imx_gpio_write,
 268     .valid.min_access_size = 4,
 269     .valid.max_access_size = 4,
 270     .endianness = DEVICE_NATIVE_ENDIAN,
 271 };
 272
 273 static const VMStateDescription vmstate_imx_gpio = {
 274     .name = TYPE_IMX_GPIO,
 275     .version_id = 1,
 276     .minimum_version_id = 1,
 277     .minimum_version_id_old = 1,
 278     .fields = (VMStateField[]) {
 279         VMSTATE_UINT32(dr, IMXGPIOState),
 280         VMSTATE_UINT32(gdir, IMXGPIOState),
 281         VMSTATE_UINT32(psr, IMXGPIOState),
 282         VMSTATE_UINT64(icr, IMXGPIOState),
 283         VMSTATE_UINT32(imr, IMXGPIOState),
 284         VMSTATE_UINT32(isr, IMXGPIOState),
 285         VMSTATE_BOOL(has_edge_sel, IMXGPIOState),
 286         VMSTATE_UINT32(edge_sel, IMXGPIOState),
 287         VMSTATE_END_OF_LIST()
 288     }
 289 };
 290
 291 static Property imx_gpio_properties[] = {
 292     DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true),
 293     DEFINE_PROP_BOOL("has-upper-pin-irq", IMXGPIOState, has_upper_pin_irq,
 294                      false),
 295     DEFINE_PROP_END_OF_LIST(),
 296 };
 297
 298 static void imx_gpio_reset(DeviceState *dev)
 299 {
 300     IMXGPIOState *s = IMX_GPIO(dev);
 301
 302     s->dr       = 0;
 303     s->gdir     = 0;
 304     s->psr      = 0;
 305     s->icr      = 0;
 306     s->imr      = 0;
 307     s->isr      = 0;
 308     s->edge_sel = 0;
 309
 310     imx_gpio_set_all_output_lines(s);
 311     imx_gpio_update_int(s);
 312 }
 313
 314 static void imx_gpio_realize(DeviceState *dev, Error **errp)
 315 {
 316     IMXGPIOState *s = IMX_GPIO(dev);
 317
 318     memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpio_ops, s,
 319                           TYPE_IMX_GPIO, IMX_GPIO_MEM_SIZE);
 320
 321     qdev_init_gpio_in(DEVICE(s), imx_gpio_set, IMX_GPIO_PIN_COUNT);
 322     qdev_init_gpio_out(DEVICE(s), s->output, IMX_GPIO_PIN_COUNT);
 323
 324     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[0]);
 325     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[1]);
 326     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 327 }
 328
 329 static void imx_gpio_class_init(ObjectClass *klass, void *data)
 330 {
 331     DeviceClass *dc = DEVICE_CLASS(klass);
 332
 333     dc->realize = imx_gpio_realize;
 334     dc->reset = imx_gpio_reset;
 335     dc->props = imx_gpio_properties;
 336     dc->vmsd = &vmstate_imx_gpio;
 337     dc->desc = "i.MX GPIO controller";
 338 }
 339
 340 static const TypeInfo imx_gpio_info = {
 341     .name = TYPE_IMX_GPIO,
 342     .parent = TYPE_SYS_BUS_DEVICE,
 343     .instance_size = sizeof(IMXGPIOState),
 344     .class_init = imx_gpio_class_init,
 345 };
 346
 347 static void imx_gpio_register_types(void)
 348 {
 349     type_register_static(&imx_gpio_info);
 350 }
 351
 352 type_init(imx_gpio_register_types)