target/ppc/helper_regs.h

   1 /*
   2  *  PowerPC emulation special registers manipulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HELPER_REGS_H
  21 #define HELPER_REGS_H
  22
  23 #include "qemu/main-loop.h"
  24 #include "exec/exec-all.h"
  25 #include "sysemu/kvm.h"
  26
  27 /* Swap temporary saved registers with GPRs */
  28 static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
  29 {
  30     target_ulong tmp;
  31
  32     tmp = env->gpr[0];
  33     env->gpr[0] = env->tgpr[0];
  34     env->tgpr[0] = tmp;
  35     tmp = env->gpr[1];
  36     env->gpr[1] = env->tgpr[1];
  37     env->tgpr[1] = tmp;
  38     tmp = env->gpr[2];
  39     env->gpr[2] = env->tgpr[2];
  40     env->tgpr[2] = tmp;
  41     tmp = env->gpr[3];
  42     env->gpr[3] = env->tgpr[3];
  43     env->tgpr[3] = tmp;
  44 }
  45
  46 static inline void hreg_compute_mem_idx(CPUPPCState *env)
  47 {
  48     /*
  49      * This is our encoding for server processors. The architecture
  50      * specifies that there is no such thing as userspace with
  51      * translation off, however it appears that MacOS does it and some
  52      * 32-bit CPUs support it. Weird...
  53      *
  54      *   0 = Guest User space virtual mode
  55      *   1 = Guest Kernel space virtual mode
  56      *   2 = Guest User space real mode
  57      *   3 = Guest Kernel space real mode
  58      *   4 = HV User space virtual mode
  59      *   5 = HV Kernel space virtual mode
  60      *   6 = HV User space real mode
  61      *   7 = HV Kernel space real mode
  62      *
  63      * For BookE, we need 8 MMU modes as follow:
  64      *
  65      *  0 = AS 0 HV User space
  66      *  1 = AS 0 HV Kernel space
  67      *  2 = AS 1 HV User space
  68      *  3 = AS 1 HV Kernel space
  69      *  4 = AS 0 Guest User space
  70      *  5 = AS 0 Guest Kernel space
  71      *  6 = AS 1 Guest User space
  72      *  7 = AS 1 Guest Kernel space
  73      */
  74     if (env->mmu_model & POWERPC_MMU_BOOKE) {
  75         env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  76         env->immu_idx += msr_is ? 2 : 0;
  77         env->dmmu_idx += msr_ds ? 2 : 0;
  78         env->immu_idx += msr_gs ? 4 : 0;
  79         env->dmmu_idx += msr_gs ? 4 : 0;
  80     } else {
  81         env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  82         env->immu_idx += msr_ir ? 0 : 2;
  83         env->dmmu_idx += msr_dr ? 0 : 2;
  84         env->immu_idx += msr_hv ? 4 : 0;
  85         env->dmmu_idx += msr_hv ? 4 : 0;
  86     }
  87 }
  88
  89 static inline void hreg_compute_hflags(CPUPPCState *env)
  90 {
  91     target_ulong hflags_mask;
  92
  93     /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
  94     hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
  95         (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
  96         (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
  97     hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
  98     hreg_compute_mem_idx(env);
  99     env->hflags = env->msr & hflags_mask;
 100     /* Merge with hflags coming from other registers */
 101     env->hflags |= env->hflags_nmsr;
 102 }
 103
 104 static inline void cpu_interrupt_exittb(CPUState *cs)
 105 {
 106     if (!kvm_enabled()) {
 107         return;
 108     }
 109
 110     if (!qemu_mutex_iothread_locked()) {
 111         qemu_mutex_lock_iothread();
 112         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 113         qemu_mutex_unlock_iothread();
 114     } else {
 115         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 116     }
 117 }
 118
 119 static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
 120                                  int alter_hv)
 121 {
 122     int excp;
 123 #if !defined(CONFIG_USER_ONLY)
 124     CPUState *cs = env_cpu(env);
 125 #endif
 126
 127     excp = 0;
 128     value &= env->msr_mask;
 129 #if !defined(CONFIG_USER_ONLY)
 130     /* Neither mtmsr nor guest state can alter HV */
 131     if (!alter_hv || !(env->msr & MSR_HVB)) {
 132         value &= ~MSR_HVB;
 133         value |= env->msr & MSR_HVB;
 134     }
 135     if (((value >> MSR_IR) & 1) != msr_ir ||
 136         ((value >> MSR_DR) & 1) != msr_dr) {
 137         cpu_interrupt_exittb(cs);
 138     }
 139     if ((env->mmu_model & POWERPC_MMU_BOOKE) &&
 140         ((value >> MSR_GS) & 1) != msr_gs) {
 141         cpu_interrupt_exittb(cs);
 142     }
 143     if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
 144                  ((value ^ env->msr) & (1 << MSR_TGPR)))) {
 145         /* Swap temporary saved registers with GPRs */
 146         hreg_swap_gpr_tgpr(env);
 147     }
 148     if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
 149         /* Change the exception prefix on PowerPC 601 */
 150         env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
 151     }
 152     /*
 153      * If PR=1 then EE, IR and DR must be 1
 154      *
 155      * Note: We only enforce this on 64-bit server processors.
 156      * It appears that:
 157      * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
 158      *   exploits it.
 159      * - 64-bit embedded implementations do not need any operation to be
 160      *   performed when PR is set.
 161      */
 162     if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
 163         value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
 164     }
 165 #endif
 166     env->msr = value;
 167     hreg_compute_hflags(env);
 168 #if !defined(CONFIG_USER_ONLY)
 169     if (unlikely(msr_pow == 1)) {
 170         if (!env->pending_interrupts && (*env->check_pow)(env)) {
 171             cs->halted = 1;
 172             excp = EXCP_HALTED;
 173         }
 174     }
 175 #endif
 176
 177     return excp;
 178 }
 179
 180 #if !defined(CONFIG_USER_ONLY)
 181 static inline void check_tlb_flush(CPUPPCState *env, bool global)
 182 {
 183     CPUState *cs = env_cpu(env);
 184
 185     /* Handle global flushes first */
 186     if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
 187         env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
 188         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 189         tlb_flush_all_cpus_synced(cs);
 190         return;
 191     }
 192
 193     /* Then handle local ones */
 194     if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
 195         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 196         tlb_flush(cs);
 197     }
 198 }
 199 #else
 200 static inline void check_tlb_flush(CPUPPCState *env, bool global) { }
 201 #endif
 202
 203 #endif /* HELPER_REGS_H */