4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
26 #include "hw/pci/msi.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
30 #include "qemu/error-report.h"
31 #include "sysemu/block-backend.h"
32 #include "sysemu/dma.h"
33 #include "hw/ide/internal.h"
34 #include "hw/ide/pci.h"
35 #include "hw/ide/ahci.h"
39 #define DPRINTF(port, fmt, ...) \
42 fprintf(stderr, "ahci: %s: [%d] ", __func__, port); \
43 fprintf(stderr, fmt, ## __VA_ARGS__); \
47 static void check_cmd(AHCIState
*s
, int port
);
48 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
);
49 static void ahci_reset_port(AHCIState
*s
, int port
);
50 static bool ahci_write_fis_d2h(AHCIDevice
*ad
);
51 static void ahci_init_d2h(AHCIDevice
*ad
);
52 static int ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
);
53 static bool ahci_map_clb_address(AHCIDevice
*ad
);
54 static bool ahci_map_fis_address(AHCIDevice
*ad
);
55 static void ahci_unmap_clb_address(AHCIDevice
*ad
);
56 static void ahci_unmap_fis_address(AHCIDevice
*ad
);
59 static uint32_t ahci_port_read(AHCIState
*s
, int port
, int offset
)
63 pr
= &s
->dev
[port
].port_regs
;
69 case PORT_LST_ADDR_HI
:
70 val
= pr
->lst_addr_hi
;
75 case PORT_FIS_ADDR_HI
:
76 val
= pr
->fis_addr_hi
;
94 if (s
->dev
[port
].port
.ifs
[0].blk
) {
95 val
= SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP
|
96 SATA_SCR_SSTATUS_SPD_GEN1
| SATA_SCR_SSTATUS_IPM_ACTIVE
;
98 val
= SATA_SCR_SSTATUS_DET_NODEV
;
117 DPRINTF(port
, "offset: 0x%x val: 0x%x\n", offset
, val
);
122 static void ahci_irq_raise(AHCIState
*s
, AHCIDevice
*dev
)
124 DeviceState
*dev_state
= s
->container
;
125 PCIDevice
*pci_dev
= (PCIDevice
*) object_dynamic_cast(OBJECT(dev_state
),
128 DPRINTF(0, "raise irq\n");
130 if (pci_dev
&& msi_enabled(pci_dev
)) {
131 msi_notify(pci_dev
, 0);
133 qemu_irq_raise(s
->irq
);
137 static void ahci_irq_lower(AHCIState
*s
, AHCIDevice
*dev
)
139 DeviceState
*dev_state
= s
->container
;
140 PCIDevice
*pci_dev
= (PCIDevice
*) object_dynamic_cast(OBJECT(dev_state
),
143 DPRINTF(0, "lower irq\n");
145 if (!pci_dev
|| !msi_enabled(pci_dev
)) {
146 qemu_irq_lower(s
->irq
);
150 static void ahci_check_irq(AHCIState
*s
)
154 DPRINTF(-1, "check irq %#x\n", s
->control_regs
.irqstatus
);
156 s
->control_regs
.irqstatus
= 0;
157 for (i
= 0; i
< s
->ports
; i
++) {
158 AHCIPortRegs
*pr
= &s
->dev
[i
].port_regs
;
159 if (pr
->irq_stat
& pr
->irq_mask
) {
160 s
->control_regs
.irqstatus
|= (1 << i
);
164 if (s
->control_regs
.irqstatus
&&
165 (s
->control_regs
.ghc
& HOST_CTL_IRQ_EN
)) {
166 ahci_irq_raise(s
, NULL
);
168 ahci_irq_lower(s
, NULL
);
172 static void ahci_trigger_irq(AHCIState
*s
, AHCIDevice
*d
,
175 DPRINTF(d
->port_no
, "trigger irq %#x -> %x\n",
176 irq_type
, d
->port_regs
.irq_mask
& irq_type
);
178 d
->port_regs
.irq_stat
|= irq_type
;
182 static void map_page(AddressSpace
*as
, uint8_t **ptr
, uint64_t addr
,
188 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
191 *ptr
= dma_memory_map(as
, addr
, &len
, DMA_DIRECTION_FROM_DEVICE
);
193 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
199 * Check the cmd register to see if we should start or stop
200 * the DMA or FIS RX engines.
202 * @ad: Device to dis/engage.
204 * @return 0 on success, -1 on error.
206 static int ahci_cond_start_engines(AHCIDevice
*ad
)
208 AHCIPortRegs
*pr
= &ad
->port_regs
;
209 bool cmd_start
= pr
->cmd
& PORT_CMD_START
;
210 bool cmd_on
= pr
->cmd
& PORT_CMD_LIST_ON
;
211 bool fis_start
= pr
->cmd
& PORT_CMD_FIS_RX
;
212 bool fis_on
= pr
->cmd
& PORT_CMD_FIS_ON
;
214 if (cmd_start
&& !cmd_on
) {
215 if (!ahci_map_clb_address(ad
)) {
216 pr
->cmd
&= ~PORT_CMD_START
;
217 error_report("AHCI: Failed to start DMA engine: "
218 "bad command list buffer address");
221 } else if (!cmd_start
&& cmd_on
) {
222 ahci_unmap_clb_address(ad
);
225 if (fis_start
&& !fis_on
) {
226 if (!ahci_map_fis_address(ad
)) {
227 pr
->cmd
&= ~PORT_CMD_FIS_RX
;
228 error_report("AHCI: Failed to start FIS receive engine: "
229 "bad FIS receive buffer address");
232 } else if (!fis_start
&& fis_on
) {
233 ahci_unmap_fis_address(ad
);
239 static void ahci_port_write(AHCIState
*s
, int port
, int offset
, uint32_t val
)
241 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
243 DPRINTF(port
, "offset: 0x%x val: 0x%x\n", offset
, val
);
248 case PORT_LST_ADDR_HI
:
249 pr
->lst_addr_hi
= val
;
254 case PORT_FIS_ADDR_HI
:
255 pr
->fis_addr_hi
= val
;
258 pr
->irq_stat
&= ~val
;
262 pr
->irq_mask
= val
& 0xfdc000ff;
266 /* Block any Read-only fields from being set;
267 * including LIST_ON and FIS_ON.
268 * The spec requires to set ICC bits to zero after the ICC change
269 * is done. We don't support ICC state changes, therefore always
270 * force the ICC bits to zero.
272 pr
->cmd
= (pr
->cmd
& PORT_CMD_RO_MASK
) |
273 (val
& ~(PORT_CMD_RO_MASK
|PORT_CMD_ICC_MASK
));
275 /* Check FIS RX and CLB engines */
276 ahci_cond_start_engines(&s
->dev
[port
]);
278 /* XXX usually the FIS would be pending on the bus here and
279 issuing deferred until the OS enables FIS receival.
280 Instead, we only submit it once - which works in most
281 cases, but is a hack. */
282 if ((pr
->cmd
& PORT_CMD_FIS_ON
) &&
283 !s
->dev
[port
].init_d2h_sent
) {
284 ahci_init_d2h(&s
->dev
[port
]);
299 if (((pr
->scr_ctl
& AHCI_SCR_SCTL_DET
) == 1) &&
300 ((val
& AHCI_SCR_SCTL_DET
) == 0)) {
301 ahci_reset_port(s
, port
);
313 pr
->cmd_issue
|= val
;
321 static uint64_t ahci_mem_read_32(void *opaque
, hwaddr addr
)
323 AHCIState
*s
= opaque
;
326 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
329 val
= s
->control_regs
.cap
;
332 val
= s
->control_regs
.ghc
;
335 val
= s
->control_regs
.irqstatus
;
337 case HOST_PORTS_IMPL
:
338 val
= s
->control_regs
.impl
;
341 val
= s
->control_regs
.version
;
345 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr
, val
);
346 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
347 (addr
< (AHCI_PORT_REGS_START_ADDR
+
348 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
349 val
= ahci_port_read(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
350 addr
& AHCI_PORT_ADDR_OFFSET_MASK
);
358 * AHCI 1.3 section 3 ("HBA Memory Registers")
359 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.
360 * Caller is responsible for masking unwanted higher order bytes.
362 static uint64_t ahci_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
364 hwaddr aligned
= addr
& ~0x3;
365 int ofst
= addr
- aligned
;
366 uint64_t lo
= ahci_mem_read_32(opaque
, aligned
);
370 /* if < 8 byte read does not cross 4 byte boundary */
371 if (ofst
+ size
<= 4) {
372 val
= lo
>> (ofst
* 8);
374 g_assert_cmpint(size
, >, 1);
376 /* If the 64bit read is unaligned, we will produce undefined
377 * results. AHCI does not support unaligned 64bit reads. */
378 hi
= ahci_mem_read_32(opaque
, aligned
+ 4);
379 val
= (hi
<< 32 | lo
) >> (ofst
* 8);
382 DPRINTF(-1, "addr=0x%" HWADDR_PRIx
" val=0x%" PRIx64
", size=%d\n",
388 static void ahci_mem_write(void *opaque
, hwaddr addr
,
389 uint64_t val
, unsigned size
)
391 AHCIState
*s
= opaque
;
393 DPRINTF(-1, "addr=0x%" HWADDR_PRIx
" val=0x%" PRIx64
", size=%d\n",
396 /* Only aligned reads are allowed on AHCI */
398 fprintf(stderr
, "ahci: Mis-aligned write to addr 0x"
399 TARGET_FMT_plx
"\n", addr
);
403 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
404 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64
"\n", (unsigned) addr
, val
);
407 case HOST_CAP
: /* R/WO, RO */
408 /* FIXME handle R/WO */
410 case HOST_CTL
: /* R/W */
411 if (val
& HOST_CTL_RESET
) {
412 DPRINTF(-1, "HBA Reset\n");
415 s
->control_regs
.ghc
= (val
& 0x3) | HOST_CTL_AHCI_EN
;
419 case HOST_IRQ_STAT
: /* R/WC, RO */
420 s
->control_regs
.irqstatus
&= ~val
;
423 case HOST_PORTS_IMPL
: /* R/WO, RO */
424 /* FIXME handle R/WO */
426 case HOST_VERSION
: /* RO */
427 /* FIXME report write? */
430 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr
);
432 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
433 (addr
< (AHCI_PORT_REGS_START_ADDR
+
434 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
435 ahci_port_write(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
436 addr
& AHCI_PORT_ADDR_OFFSET_MASK
, val
);
441 static const MemoryRegionOps ahci_mem_ops
= {
442 .read
= ahci_mem_read
,
443 .write
= ahci_mem_write
,
444 .endianness
= DEVICE_LITTLE_ENDIAN
,
447 static uint64_t ahci_idp_read(void *opaque
, hwaddr addr
,
450 AHCIState
*s
= opaque
;
452 if (addr
== s
->idp_offset
) {
455 } else if (addr
== s
->idp_offset
+ 4) {
456 /* data register - do memory read at location selected by index */
457 return ahci_mem_read(opaque
, s
->idp_index
, size
);
463 static void ahci_idp_write(void *opaque
, hwaddr addr
,
464 uint64_t val
, unsigned size
)
466 AHCIState
*s
= opaque
;
468 if (addr
== s
->idp_offset
) {
469 /* index register - mask off reserved bits */
470 s
->idp_index
= (uint32_t)val
& ((AHCI_MEM_BAR_SIZE
- 1) & ~3);
471 } else if (addr
== s
->idp_offset
+ 4) {
472 /* data register - do memory write at location selected by index */
473 ahci_mem_write(opaque
, s
->idp_index
, val
, size
);
477 static const MemoryRegionOps ahci_idp_ops
= {
478 .read
= ahci_idp_read
,
479 .write
= ahci_idp_write
,
480 .endianness
= DEVICE_LITTLE_ENDIAN
,
484 static void ahci_reg_init(AHCIState
*s
)
488 s
->control_regs
.cap
= (s
->ports
- 1) |
489 (AHCI_NUM_COMMAND_SLOTS
<< 8) |
490 (AHCI_SUPPORTED_SPEED_GEN1
<< AHCI_SUPPORTED_SPEED
) |
491 HOST_CAP_NCQ
| HOST_CAP_AHCI
| HOST_CAP_64
;
493 s
->control_regs
.impl
= (1 << s
->ports
) - 1;
495 s
->control_regs
.version
= AHCI_VERSION_1_0
;
497 for (i
= 0; i
< s
->ports
; i
++) {
498 s
->dev
[i
].port_state
= STATE_RUN
;
502 static void check_cmd(AHCIState
*s
, int port
)
504 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
507 if ((pr
->cmd
& PORT_CMD_START
) && pr
->cmd_issue
) {
508 for (slot
= 0; (slot
< 32) && pr
->cmd_issue
; slot
++) {
509 if ((pr
->cmd_issue
& (1U << slot
)) &&
510 !handle_cmd(s
, port
, slot
)) {
511 pr
->cmd_issue
&= ~(1U << slot
);
517 static void ahci_check_cmd_bh(void *opaque
)
519 AHCIDevice
*ad
= opaque
;
521 qemu_bh_delete(ad
->check_bh
);
524 if ((ad
->busy_slot
!= -1) &&
525 !(ad
->port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
))) {
527 ad
->port_regs
.cmd_issue
&= ~(1 << ad
->busy_slot
);
531 check_cmd(ad
->hba
, ad
->port_no
);
534 static void ahci_init_d2h(AHCIDevice
*ad
)
536 IDEState
*ide_state
= &ad
->port
.ifs
[0];
537 AHCIPortRegs
*pr
= &ad
->port_regs
;
539 if (ad
->init_d2h_sent
) {
543 if (ahci_write_fis_d2h(ad
)) {
544 ad
->init_d2h_sent
= true;
545 /* We're emulating receiving the first Reg H2D Fis from the device;
546 * Update the SIG register, but otherwise proceed as normal. */
547 pr
->sig
= ((uint32_t)ide_state
->hcyl
<< 24) |
548 (ide_state
->lcyl
<< 16) |
549 (ide_state
->sector
<< 8) |
550 (ide_state
->nsector
& 0xFF);
554 static void ahci_set_signature(AHCIDevice
*ad
, uint32_t sig
)
556 IDEState
*s
= &ad
->port
.ifs
[0];
557 s
->hcyl
= sig
>> 24 & 0xFF;
558 s
->lcyl
= sig
>> 16 & 0xFF;
559 s
->sector
= sig
>> 8 & 0xFF;
560 s
->nsector
= sig
& 0xFF;
562 DPRINTF(ad
->port_no
, "set hcyl:lcyl:sect:nsect = 0x%08x\n", sig
);
565 static void ahci_reset_port(AHCIState
*s
, int port
)
567 AHCIDevice
*d
= &s
->dev
[port
];
568 AHCIPortRegs
*pr
= &d
->port_regs
;
569 IDEState
*ide_state
= &d
->port
.ifs
[0];
572 DPRINTF(port
, "reset port\n");
574 ide_bus_reset(&d
->port
);
575 ide_state
->ncq_queues
= AHCI_MAX_CMDS
;
581 pr
->sig
= 0xFFFFFFFF;
583 d
->init_d2h_sent
= false;
585 ide_state
= &s
->dev
[port
].port
.ifs
[0];
586 if (!ide_state
->blk
) {
590 /* reset ncq queue */
591 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
592 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[i
];
593 ncq_tfs
->halt
= false;
594 if (!ncq_tfs
->used
) {
598 if (ncq_tfs
->aiocb
) {
599 blk_aio_cancel(ncq_tfs
->aiocb
);
600 ncq_tfs
->aiocb
= NULL
;
603 /* Maybe we just finished the request thanks to blk_aio_cancel() */
604 if (!ncq_tfs
->used
) {
608 qemu_sglist_destroy(&ncq_tfs
->sglist
);
612 s
->dev
[port
].port_state
= STATE_RUN
;
613 if (ide_state
->drive_kind
== IDE_CD
) {
614 ahci_set_signature(d
, SATA_SIGNATURE_CDROM
);\
615 ide_state
->status
= SEEK_STAT
| WRERR_STAT
| READY_STAT
;
617 ahci_set_signature(d
, SATA_SIGNATURE_DISK
);
618 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
621 ide_state
->error
= 1;
625 static void debug_print_fis(uint8_t *fis
, int cmd_len
)
630 fprintf(stderr
, "fis:");
631 for (i
= 0; i
< cmd_len
; i
++) {
632 if ((i
& 0xf) == 0) {
633 fprintf(stderr
, "\n%02x:",i
);
635 fprintf(stderr
, "%02x ",fis
[i
]);
637 fprintf(stderr
, "\n");
641 static bool ahci_map_fis_address(AHCIDevice
*ad
)
643 AHCIPortRegs
*pr
= &ad
->port_regs
;
644 map_page(ad
->hba
->as
, &ad
->res_fis
,
645 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
646 if (ad
->res_fis
!= NULL
) {
647 pr
->cmd
|= PORT_CMD_FIS_ON
;
651 pr
->cmd
&= ~PORT_CMD_FIS_ON
;
655 static void ahci_unmap_fis_address(AHCIDevice
*ad
)
657 if (ad
->res_fis
== NULL
) {
658 DPRINTF(ad
->port_no
, "Attempt to unmap NULL FIS address\n");
661 ad
->port_regs
.cmd
&= ~PORT_CMD_FIS_ON
;
662 dma_memory_unmap(ad
->hba
->as
, ad
->res_fis
, 256,
663 DMA_DIRECTION_FROM_DEVICE
, 256);
667 static bool ahci_map_clb_address(AHCIDevice
*ad
)
669 AHCIPortRegs
*pr
= &ad
->port_regs
;
671 map_page(ad
->hba
->as
, &ad
->lst
,
672 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
673 if (ad
->lst
!= NULL
) {
674 pr
->cmd
|= PORT_CMD_LIST_ON
;
678 pr
->cmd
&= ~PORT_CMD_LIST_ON
;
682 static void ahci_unmap_clb_address(AHCIDevice
*ad
)
684 if (ad
->lst
== NULL
) {
685 DPRINTF(ad
->port_no
, "Attempt to unmap NULL CLB address\n");
688 ad
->port_regs
.cmd
&= ~PORT_CMD_LIST_ON
;
689 dma_memory_unmap(ad
->hba
->as
, ad
->lst
, 1024,
690 DMA_DIRECTION_FROM_DEVICE
, 1024);
694 static void ahci_write_fis_sdb(AHCIState
*s
, NCQTransferState
*ncq_tfs
)
696 AHCIDevice
*ad
= ncq_tfs
->drive
;
697 AHCIPortRegs
*pr
= &ad
->port_regs
;
702 !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
706 sdb_fis
= (SDBFIS
*)&ad
->res_fis
[RES_FIS_SDBFIS
];
707 ide_state
= &ad
->port
.ifs
[0];
709 sdb_fis
->type
= SATA_FIS_TYPE_SDB
;
710 /* Interrupt pending & Notification bit */
711 sdb_fis
->flags
= 0x40; /* Interrupt bit, always 1 for NCQ */
712 sdb_fis
->status
= ide_state
->status
& 0x77;
713 sdb_fis
->error
= ide_state
->error
;
714 /* update SAct field in SDB_FIS */
715 sdb_fis
->payload
= cpu_to_le32(ad
->finished
);
717 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
718 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
719 (ad
->port
.ifs
[0].status
& 0x77) |
721 pr
->scr_act
&= ~ad
->finished
;
724 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */
725 if (sdb_fis
->flags
& 0x40) {
726 ahci_trigger_irq(s
, ad
, PORT_IRQ_SDB_FIS
);
730 static void ahci_write_fis_pio(AHCIDevice
*ad
, uint16_t len
)
732 AHCIPortRegs
*pr
= &ad
->port_regs
;
734 IDEState
*s
= &ad
->port
.ifs
[0];
736 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
740 pio_fis
= &ad
->res_fis
[RES_FIS_PSFIS
];
742 pio_fis
[0] = SATA_FIS_TYPE_PIO_SETUP
;
743 pio_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
744 pio_fis
[2] = s
->status
;
745 pio_fis
[3] = s
->error
;
747 pio_fis
[4] = s
->sector
;
748 pio_fis
[5] = s
->lcyl
;
749 pio_fis
[6] = s
->hcyl
;
750 pio_fis
[7] = s
->select
;
751 pio_fis
[8] = s
->hob_sector
;
752 pio_fis
[9] = s
->hob_lcyl
;
753 pio_fis
[10] = s
->hob_hcyl
;
755 pio_fis
[12] = s
->nsector
& 0xFF;
756 pio_fis
[13] = (s
->nsector
>> 8) & 0xFF;
758 pio_fis
[15] = s
->status
;
759 pio_fis
[16] = len
& 255;
760 pio_fis
[17] = len
>> 8;
764 /* Update shadow registers: */
765 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
766 ad
->port
.ifs
[0].status
;
768 if (pio_fis
[2] & ERR_STAT
) {
769 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_TF_ERR
);
772 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_PIOS_FIS
);
775 static bool ahci_write_fis_d2h(AHCIDevice
*ad
)
777 AHCIPortRegs
*pr
= &ad
->port_regs
;
780 IDEState
*s
= &ad
->port
.ifs
[0];
782 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
786 d2h_fis
= &ad
->res_fis
[RES_FIS_RFIS
];
788 d2h_fis
[0] = SATA_FIS_TYPE_REGISTER_D2H
;
789 d2h_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
790 d2h_fis
[2] = s
->status
;
791 d2h_fis
[3] = s
->error
;
793 d2h_fis
[4] = s
->sector
;
794 d2h_fis
[5] = s
->lcyl
;
795 d2h_fis
[6] = s
->hcyl
;
796 d2h_fis
[7] = s
->select
;
797 d2h_fis
[8] = s
->hob_sector
;
798 d2h_fis
[9] = s
->hob_lcyl
;
799 d2h_fis
[10] = s
->hob_hcyl
;
801 d2h_fis
[12] = s
->nsector
& 0xFF;
802 d2h_fis
[13] = (s
->nsector
>> 8) & 0xFF;
803 for (i
= 14; i
< 20; i
++) {
807 /* Update shadow registers: */
808 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
809 ad
->port
.ifs
[0].status
;
811 if (d2h_fis
[2] & ERR_STAT
) {
812 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_TF_ERR
);
815 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_D2H_REG_FIS
);
819 static int prdt_tbl_entry_size(const AHCI_SG
*tbl
)
821 /* flags_size is zero-based */
822 return (le32_to_cpu(tbl
->flags_size
) & AHCI_PRDT_SIZE_MASK
) + 1;
826 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.
827 * @ad: The AHCIDevice for whom we are building the SGList.
828 * @sglist: The SGList target to add PRD entries to.
829 * @cmd: The AHCI Command Header that describes where the PRDT is.
830 * @limit: The remaining size of the S/ATA transaction, in bytes.
831 * @offset: The number of bytes already transferred, in bytes.
833 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of
834 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop
835 * building the sglist from the PRDT as soon as we hit @limit bytes,
836 * which is <= INT32_MAX/2GiB.
838 static int ahci_populate_sglist(AHCIDevice
*ad
, QEMUSGList
*sglist
,
839 AHCICmdHdr
*cmd
, int64_t limit
, uint64_t offset
)
841 uint16_t opts
= le16_to_cpu(cmd
->opts
);
842 uint16_t prdtl
= le16_to_cpu(cmd
->prdtl
);
843 uint64_t cfis_addr
= le64_to_cpu(cmd
->tbl_addr
);
844 uint64_t prdt_addr
= cfis_addr
+ 0x80;
845 dma_addr_t prdt_len
= (prdtl
* sizeof(AHCI_SG
));
846 dma_addr_t real_prdt_len
= prdt_len
;
852 int64_t off_pos
= -1;
854 IDEBus
*bus
= &ad
->port
;
855 BusState
*qbus
= BUS(bus
);
858 DPRINTF(ad
->port_no
, "no sg list given by guest: 0x%08x\n", opts
);
863 if (!(prdt
= dma_memory_map(ad
->hba
->as
, prdt_addr
, &prdt_len
,
864 DMA_DIRECTION_TO_DEVICE
))){
865 DPRINTF(ad
->port_no
, "map failed\n");
869 if (prdt_len
< real_prdt_len
) {
870 DPRINTF(ad
->port_no
, "mapped less than expected\n");
875 /* Get entries in the PRDT, init a qemu sglist accordingly */
877 AHCI_SG
*tbl
= (AHCI_SG
*)prdt
;
879 for (i
= 0; i
< prdtl
; i
++) {
880 tbl_entry_size
= prdt_tbl_entry_size(&tbl
[i
]);
881 if (offset
< (sum
+ tbl_entry_size
)) {
883 off_pos
= offset
- sum
;
886 sum
+= tbl_entry_size
;
888 if ((off_idx
== -1) || (off_pos
< 0) || (off_pos
> tbl_entry_size
)) {
889 DPRINTF(ad
->port_no
, "%s: Incorrect offset! "
890 "off_idx: %d, off_pos: %"PRId64
"\n",
891 __func__
, off_idx
, off_pos
);
896 qemu_sglist_init(sglist
, qbus
->parent
, (prdtl
- off_idx
),
898 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[off_idx
].addr
) + off_pos
,
899 MIN(prdt_tbl_entry_size(&tbl
[off_idx
]) - off_pos
,
902 for (i
= off_idx
+ 1; i
< prdtl
&& sglist
->size
< limit
; i
++) {
903 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[i
].addr
),
904 MIN(prdt_tbl_entry_size(&tbl
[i
]),
905 limit
- sglist
->size
));
910 dma_memory_unmap(ad
->hba
->as
, prdt
, prdt_len
,
911 DMA_DIRECTION_TO_DEVICE
, prdt_len
);
915 static void ncq_err(NCQTransferState
*ncq_tfs
)
917 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
919 ide_state
->error
= ABRT_ERR
;
920 ide_state
->status
= READY_STAT
| ERR_STAT
;
921 ncq_tfs
->drive
->port_regs
.scr_err
|= (1 << ncq_tfs
->tag
);
922 qemu_sglist_destroy(&ncq_tfs
->sglist
);
926 static void ncq_finish(NCQTransferState
*ncq_tfs
)
928 /* If we didn't error out, set our finished bit. Errored commands
929 * do not get a bit set for the SDB FIS ACT register, nor do they
930 * clear the outstanding bit in scr_act (PxSACT). */
931 if (!(ncq_tfs
->drive
->port_regs
.scr_err
& (1 << ncq_tfs
->tag
))) {
932 ncq_tfs
->drive
->finished
|= (1 << ncq_tfs
->tag
);
935 ahci_write_fis_sdb(ncq_tfs
->drive
->hba
, ncq_tfs
);
937 DPRINTF(ncq_tfs
->drive
->port_no
, "NCQ transfer tag %d finished\n",
940 block_acct_done(blk_get_stats(ncq_tfs
->drive
->port
.ifs
[0].blk
),
942 qemu_sglist_destroy(&ncq_tfs
->sglist
);
946 static void ncq_cb(void *opaque
, int ret
)
948 NCQTransferState
*ncq_tfs
= (NCQTransferState
*)opaque
;
949 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
951 ncq_tfs
->aiocb
= NULL
;
952 if (ret
== -ECANCELED
) {
957 bool is_read
= ncq_tfs
->cmd
== READ_FPDMA_QUEUED
;
958 BlockErrorAction action
= blk_get_error_action(ide_state
->blk
,
960 if (action
== BLOCK_ERROR_ACTION_STOP
) {
961 ncq_tfs
->halt
= true;
962 ide_state
->bus
->error_status
= IDE_RETRY_HBA
;
963 } else if (action
== BLOCK_ERROR_ACTION_REPORT
) {
966 blk_error_action(ide_state
->blk
, action
, is_read
, -ret
);
968 ide_state
->status
= READY_STAT
| SEEK_STAT
;
971 if (!ncq_tfs
->halt
) {
976 static int is_ncq(uint8_t ata_cmd
)
978 /* Based on SATA 3.2 section 13.6.3.2 */
980 case READ_FPDMA_QUEUED
:
981 case WRITE_FPDMA_QUEUED
:
983 case RECEIVE_FPDMA_QUEUED
:
984 case SEND_FPDMA_QUEUED
:
991 static void execute_ncq_command(NCQTransferState
*ncq_tfs
)
993 AHCIDevice
*ad
= ncq_tfs
->drive
;
994 IDEState
*ide_state
= &ad
->port
.ifs
[0];
995 int port
= ad
->port_no
;
997 g_assert(is_ncq(ncq_tfs
->cmd
));
998 ncq_tfs
->halt
= false;
1000 switch (ncq_tfs
->cmd
) {
1001 case READ_FPDMA_QUEUED
:
1002 DPRINTF(port
, "NCQ reading %d sectors from LBA %"PRId64
", tag %d\n",
1003 ncq_tfs
->sector_count
, ncq_tfs
->lba
, ncq_tfs
->tag
);
1005 DPRINTF(port
, "tag %d aio read %"PRId64
"\n",
1006 ncq_tfs
->tag
, ncq_tfs
->lba
);
1008 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
1009 &ncq_tfs
->sglist
, BLOCK_ACCT_READ
);
1010 ncq_tfs
->aiocb
= dma_blk_read(ide_state
->blk
, &ncq_tfs
->sglist
,
1011 ncq_tfs
->lba
<< BDRV_SECTOR_BITS
,
1015 case WRITE_FPDMA_QUEUED
:
1016 DPRINTF(port
, "NCQ writing %d sectors to LBA %"PRId64
", tag %d\n",
1017 ncq_tfs
->sector_count
, ncq_tfs
->lba
, ncq_tfs
->tag
);
1019 DPRINTF(port
, "tag %d aio write %"PRId64
"\n",
1020 ncq_tfs
->tag
, ncq_tfs
->lba
);
1022 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
1023 &ncq_tfs
->sglist
, BLOCK_ACCT_WRITE
);
1024 ncq_tfs
->aiocb
= dma_blk_write(ide_state
->blk
, &ncq_tfs
->sglist
,
1025 ncq_tfs
->lba
<< BDRV_SECTOR_BITS
,
1030 DPRINTF(port
, "error: unsupported NCQ command (0x%02x) received\n",
1037 static void process_ncq_command(AHCIState
*s
, int port
, uint8_t *cmd_fis
,
1040 AHCIDevice
*ad
= &s
->dev
[port
];
1041 IDEState
*ide_state
= &ad
->port
.ifs
[0];
1042 NCQFrame
*ncq_fis
= (NCQFrame
*)cmd_fis
;
1043 uint8_t tag
= ncq_fis
->tag
>> 3;
1044 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[tag
];
1047 g_assert(is_ncq(ncq_fis
->command
));
1048 if (ncq_tfs
->used
) {
1049 /* error - already in use */
1050 fprintf(stderr
, "%s: tag %d already used\n", __FUNCTION__
, tag
);
1055 ncq_tfs
->drive
= ad
;
1056 ncq_tfs
->slot
= slot
;
1057 ncq_tfs
->cmdh
= &((AHCICmdHdr
*)ad
->lst
)[slot
];
1058 ncq_tfs
->cmd
= ncq_fis
->command
;
1059 ncq_tfs
->lba
= ((uint64_t)ncq_fis
->lba5
<< 40) |
1060 ((uint64_t)ncq_fis
->lba4
<< 32) |
1061 ((uint64_t)ncq_fis
->lba3
<< 24) |
1062 ((uint64_t)ncq_fis
->lba2
<< 16) |
1063 ((uint64_t)ncq_fis
->lba1
<< 8) |
1064 (uint64_t)ncq_fis
->lba0
;
1067 /* Sanity-check the NCQ packet */
1069 DPRINTF(port
, "Warn: NCQ slot (%d) did not match the given tag (%d)\n",
1073 if (ncq_fis
->aux0
|| ncq_fis
->aux1
|| ncq_fis
->aux2
|| ncq_fis
->aux3
) {
1074 DPRINTF(port
, "Warn: Attempt to use NCQ auxiliary fields.\n");
1076 if (ncq_fis
->prio
|| ncq_fis
->icc
) {
1077 DPRINTF(port
, "Warn: Unsupported attempt to use PRIO/ICC fields\n");
1079 if (ncq_fis
->fua
& NCQ_FIS_FUA_MASK
) {
1080 DPRINTF(port
, "Warn: Unsupported attempt to use Force Unit Access\n");
1082 if (ncq_fis
->tag
& NCQ_FIS_RARC_MASK
) {
1083 DPRINTF(port
, "Warn: Unsupported attempt to use Rebuild Assist\n");
1086 ncq_tfs
->sector_count
= ((ncq_fis
->sector_count_high
<< 8) |
1087 ncq_fis
->sector_count_low
);
1088 if (!ncq_tfs
->sector_count
) {
1089 ncq_tfs
->sector_count
= 0x10000;
1091 size
= ncq_tfs
->sector_count
* 512;
1092 ahci_populate_sglist(ad
, &ncq_tfs
->sglist
, ncq_tfs
->cmdh
, size
, 0);
1094 if (ncq_tfs
->sglist
.size
< size
) {
1095 error_report("ahci: PRDT length for NCQ command (0x%zx) "
1096 "is smaller than the requested size (0x%zx)",
1097 ncq_tfs
->sglist
.size
, size
);
1099 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_OVERFLOW
);
1101 } else if (ncq_tfs
->sglist
.size
!= size
) {
1102 DPRINTF(port
, "Warn: PRDTL (0x%zx)"
1103 " does not match requested size (0x%zx)",
1104 ncq_tfs
->sglist
.size
, size
);
1107 DPRINTF(port
, "NCQ transfer LBA from %"PRId64
" to %"PRId64
", "
1108 "drive max %"PRId64
"\n",
1109 ncq_tfs
->lba
, ncq_tfs
->lba
+ ncq_tfs
->sector_count
- 1,
1110 ide_state
->nb_sectors
- 1);
1112 execute_ncq_command(ncq_tfs
);
1115 static AHCICmdHdr
*get_cmd_header(AHCIState
*s
, uint8_t port
, uint8_t slot
)
1117 if (port
>= s
->ports
|| slot
>= AHCI_MAX_CMDS
) {
1121 return s
->dev
[port
].lst
? &((AHCICmdHdr
*)s
->dev
[port
].lst
)[slot
] : NULL
;
1124 static void handle_reg_h2d_fis(AHCIState
*s
, int port
,
1125 uint8_t slot
, uint8_t *cmd_fis
)
1127 IDEState
*ide_state
= &s
->dev
[port
].port
.ifs
[0];
1128 AHCICmdHdr
*cmd
= get_cmd_header(s
, port
, slot
);
1129 uint16_t opts
= le16_to_cpu(cmd
->opts
);
1131 if (cmd_fis
[1] & 0x0F) {
1132 DPRINTF(port
, "Port Multiplier not supported."
1133 " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
1134 cmd_fis
[0], cmd_fis
[1], cmd_fis
[2]);
1138 if (cmd_fis
[1] & 0x70) {
1139 DPRINTF(port
, "Reserved flags set in H2D Register FIS."
1140 " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
1141 cmd_fis
[0], cmd_fis
[1], cmd_fis
[2]);
1145 if (!(cmd_fis
[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
)) {
1146 switch (s
->dev
[port
].port_state
) {
1148 if (cmd_fis
[15] & ATA_SRST
) {
1149 s
->dev
[port
].port_state
= STATE_RESET
;
1153 if (!(cmd_fis
[15] & ATA_SRST
)) {
1154 ahci_reset_port(s
, port
);
1161 /* Check for NCQ command */
1162 if (is_ncq(cmd_fis
[2])) {
1163 process_ncq_command(s
, port
, cmd_fis
, slot
);
1167 /* Decompose the FIS:
1168 * AHCI does not interpret FIS packets, it only forwards them.
1169 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1170 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1172 * ATA4 describes sector number for LBA28/CHS commands.
1173 * ATA6 describes sector number for LBA48 commands.
1174 * ATA8 deprecates CHS fully, describing only LBA28/48.
1176 * We dutifully convert the FIS into IDE registers, and allow the
1177 * core layer to interpret them as needed. */
1178 ide_state
->feature
= cmd_fis
[3];
1179 ide_state
->sector
= cmd_fis
[4]; /* LBA 7:0 */
1180 ide_state
->lcyl
= cmd_fis
[5]; /* LBA 15:8 */
1181 ide_state
->hcyl
= cmd_fis
[6]; /* LBA 23:16 */
1182 ide_state
->select
= cmd_fis
[7]; /* LBA 27:24 (LBA28) */
1183 ide_state
->hob_sector
= cmd_fis
[8]; /* LBA 31:24 */
1184 ide_state
->hob_lcyl
= cmd_fis
[9]; /* LBA 39:32 */
1185 ide_state
->hob_hcyl
= cmd_fis
[10]; /* LBA 47:40 */
1186 ide_state
->hob_feature
= cmd_fis
[11];
1187 ide_state
->nsector
= (int64_t)((cmd_fis
[13] << 8) | cmd_fis
[12]);
1188 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1189 /* 15: Only valid when UPDATE_COMMAND not set. */
1191 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1192 * table to ide_state->io_buffer */
1193 if (opts
& AHCI_CMD_ATAPI
) {
1194 memcpy(ide_state
->io_buffer
, &cmd_fis
[AHCI_COMMAND_TABLE_ACMD
], 0x10);
1195 debug_print_fis(ide_state
->io_buffer
, 0x10);
1196 s
->dev
[port
].done_atapi_packet
= false;
1197 /* XXX send PIO setup FIS */
1200 ide_state
->error
= 0;
1202 /* Reset transferred byte counter */
1205 /* We're ready to process the command in FIS byte 2. */
1206 ide_exec_cmd(&s
->dev
[port
].port
, cmd_fis
[2]);
1209 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
)
1211 IDEState
*ide_state
;
1217 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1218 /* Engine currently busy, try again later */
1219 DPRINTF(port
, "engine busy\n");
1223 if (!s
->dev
[port
].lst
) {
1224 DPRINTF(port
, "error: lst not given but cmd handled");
1227 cmd
= get_cmd_header(s
, port
, slot
);
1228 /* remember current slot handle for later */
1229 s
->dev
[port
].cur_cmd
= cmd
;
1231 /* The device we are working for */
1232 ide_state
= &s
->dev
[port
].port
.ifs
[0];
1233 if (!ide_state
->blk
) {
1234 DPRINTF(port
, "error: guest accessed unused port");
1238 tbl_addr
= le64_to_cpu(cmd
->tbl_addr
);
1240 cmd_fis
= dma_memory_map(s
->as
, tbl_addr
, &cmd_len
,
1241 DMA_DIRECTION_FROM_DEVICE
);
1243 DPRINTF(port
, "error: guest passed us an invalid cmd fis\n");
1245 } else if (cmd_len
!= 0x80) {
1246 ahci_trigger_irq(s
, &s
->dev
[port
], PORT_IRQ_HBUS_ERR
);
1247 DPRINTF(port
, "error: dma_memory_map failed: "
1248 "(len(%02"PRIx64
") != 0x80)\n",
1252 debug_print_fis(cmd_fis
, 0x80);
1254 switch (cmd_fis
[0]) {
1255 case SATA_FIS_TYPE_REGISTER_H2D
:
1256 handle_reg_h2d_fis(s
, port
, slot
, cmd_fis
);
1259 DPRINTF(port
, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
1260 "cmd_fis[2]=%02x\n", cmd_fis
[0], cmd_fis
[1],
1266 dma_memory_unmap(s
->as
, cmd_fis
, cmd_len
, DMA_DIRECTION_FROM_DEVICE
,
1269 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1270 /* async command, complete later */
1271 s
->dev
[port
].busy_slot
= slot
;
1275 /* done handling the command */
1279 /* DMA dev <-> ram */
1280 static void ahci_start_transfer(IDEDMA
*dma
)
1282 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1283 IDEState
*s
= &ad
->port
.ifs
[0];
1284 uint32_t size
= (uint32_t)(s
->data_end
- s
->data_ptr
);
1285 /* write == ram -> device */
1286 uint16_t opts
= le16_to_cpu(ad
->cur_cmd
->opts
);
1287 int is_write
= opts
& AHCI_CMD_WRITE
;
1288 int is_atapi
= opts
& AHCI_CMD_ATAPI
;
1291 if (is_atapi
&& !ad
->done_atapi_packet
) {
1292 /* already prepopulated iobuffer */
1293 ad
->done_atapi_packet
= true;
1298 if (ahci_dma_prepare_buf(dma
, size
)) {
1302 DPRINTF(ad
->port_no
, "%sing %d bytes on %s w/%s sglist\n",
1303 is_write
? "writ" : "read", size
, is_atapi
? "atapi" : "ata",
1304 has_sglist
? "" : "o");
1306 if (has_sglist
&& size
) {
1308 dma_buf_write(s
->data_ptr
, size
, &s
->sg
);
1310 dma_buf_read(s
->data_ptr
, size
, &s
->sg
);
1315 /* declare that we processed everything */
1316 s
->data_ptr
= s
->data_end
;
1318 /* Update number of transferred bytes, destroy sglist */
1319 dma_buf_commit(s
, size
);
1321 s
->end_transfer_func(s
);
1323 if (!(s
->status
& DRQ_STAT
)) {
1324 /* done with PIO send/receive */
1325 ahci_write_fis_pio(ad
, le32_to_cpu(ad
->cur_cmd
->status
));
1329 static void ahci_start_dma(IDEDMA
*dma
, IDEState
*s
,
1330 BlockCompletionFunc
*dma_cb
)
1332 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1333 DPRINTF(ad
->port_no
, "\n");
1334 s
->io_buffer_offset
= 0;
1338 static void ahci_restart_dma(IDEDMA
*dma
)
1340 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
1344 * IDE/PIO restarts are handled by the core layer, but NCQ commands
1345 * need an extra kick from the AHCI HBA.
1347 static void ahci_restart(IDEDMA
*dma
)
1349 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1352 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
1353 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[i
];
1354 if (ncq_tfs
->halt
) {
1355 execute_ncq_command(ncq_tfs
);
1361 * Called in DMA and PIO R/W chains to read the PRDT.
1362 * Not shared with NCQ pathways.
1364 static int32_t ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
)
1366 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1367 IDEState
*s
= &ad
->port
.ifs
[0];
1369 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
,
1370 limit
, s
->io_buffer_offset
) == -1) {
1371 DPRINTF(ad
->port_no
, "ahci_dma_prepare_buf failed.\n");
1374 s
->io_buffer_size
= s
->sg
.size
;
1376 DPRINTF(ad
->port_no
, "len=%#x\n", s
->io_buffer_size
);
1377 return s
->io_buffer_size
;
1381 * Updates the command header with a bytes-read value.
1382 * Called via dma_buf_commit, for both DMA and PIO paths.
1383 * sglist destruction is handled within dma_buf_commit.
1385 static void ahci_commit_buf(IDEDMA
*dma
, uint32_t tx_bytes
)
1387 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1389 tx_bytes
+= le32_to_cpu(ad
->cur_cmd
->status
);
1390 ad
->cur_cmd
->status
= cpu_to_le32(tx_bytes
);
1393 static int ahci_dma_rw_buf(IDEDMA
*dma
, int is_write
)
1395 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1396 IDEState
*s
= &ad
->port
.ifs
[0];
1397 uint8_t *p
= s
->io_buffer
+ s
->io_buffer_index
;
1398 int l
= s
->io_buffer_size
- s
->io_buffer_index
;
1400 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
, l
, s
->io_buffer_offset
)) {
1405 dma_buf_read(p
, l
, &s
->sg
);
1407 dma_buf_write(p
, l
, &s
->sg
);
1410 /* free sglist, update byte count */
1411 dma_buf_commit(s
, l
);
1413 s
->io_buffer_index
+= l
;
1415 DPRINTF(ad
->port_no
, "len=%#x\n", l
);
1420 static void ahci_cmd_done(IDEDMA
*dma
)
1422 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1424 DPRINTF(ad
->port_no
, "cmd done\n");
1426 /* update d2h status */
1427 ahci_write_fis_d2h(ad
);
1429 if (!ad
->check_bh
) {
1430 /* maybe we still have something to process, check later */
1431 ad
->check_bh
= qemu_bh_new(ahci_check_cmd_bh
, ad
);
1432 qemu_bh_schedule(ad
->check_bh
);
1436 static void ahci_irq_set(void *opaque
, int n
, int level
)
1440 static const IDEDMAOps ahci_dma_ops
= {
1441 .start_dma
= ahci_start_dma
,
1442 .restart
= ahci_restart
,
1443 .restart_dma
= ahci_restart_dma
,
1444 .start_transfer
= ahci_start_transfer
,
1445 .prepare_buf
= ahci_dma_prepare_buf
,
1446 .commit_buf
= ahci_commit_buf
,
1447 .rw_buf
= ahci_dma_rw_buf
,
1448 .cmd_done
= ahci_cmd_done
,
1451 void ahci_init(AHCIState
*s
, DeviceState
*qdev
)
1453 s
->container
= qdev
;
1454 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1455 memory_region_init_io(&s
->mem
, OBJECT(qdev
), &ahci_mem_ops
, s
,
1456 "ahci", AHCI_MEM_BAR_SIZE
);
1457 memory_region_init_io(&s
->idp
, OBJECT(qdev
), &ahci_idp_ops
, s
,
1461 void ahci_realize(AHCIState
*s
, DeviceState
*qdev
, AddressSpace
*as
, int ports
)
1468 s
->dev
= g_new0(AHCIDevice
, ports
);
1470 irqs
= qemu_allocate_irqs(ahci_irq_set
, s
, s
->ports
);
1471 for (i
= 0; i
< s
->ports
; i
++) {
1472 AHCIDevice
*ad
= &s
->dev
[i
];
1474 ide_bus_new(&ad
->port
, sizeof(ad
->port
), qdev
, i
, 1);
1475 ide_init2(&ad
->port
, irqs
[i
]);
1479 ad
->port
.dma
= &ad
->dma
;
1480 ad
->port
.dma
->ops
= &ahci_dma_ops
;
1481 ide_register_restart_cb(&ad
->port
);
1486 void ahci_uninit(AHCIState
*s
)
1490 for (i
= 0; i
< s
->ports
; i
++) {
1491 AHCIDevice
*ad
= &s
->dev
[i
];
1493 for (j
= 0; j
< 2; j
++) {
1494 IDEState
*s
= &ad
->port
.ifs
[j
];
1503 void ahci_reset(AHCIState
*s
)
1508 s
->control_regs
.irqstatus
= 0;
1510 * The implementation of this bit is dependent upon the value of the
1511 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1512 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1513 * read-only and shall have a reset value of '1'.
1515 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1517 s
->control_regs
.ghc
= HOST_CTL_AHCI_EN
;
1519 for (i
= 0; i
< s
->ports
; i
++) {
1520 pr
= &s
->dev
[i
].port_regs
;
1524 pr
->cmd
= PORT_CMD_SPIN_UP
| PORT_CMD_POWER_ON
;
1525 ahci_reset_port(s
, i
);
1529 static const VMStateDescription vmstate_ncq_tfs
= {
1530 .name
= "ncq state",
1532 .fields
= (VMStateField
[]) {
1533 VMSTATE_UINT32(sector_count
, NCQTransferState
),
1534 VMSTATE_UINT64(lba
, NCQTransferState
),
1535 VMSTATE_UINT8(tag
, NCQTransferState
),
1536 VMSTATE_UINT8(cmd
, NCQTransferState
),
1537 VMSTATE_UINT8(slot
, NCQTransferState
),
1538 VMSTATE_BOOL(used
, NCQTransferState
),
1539 VMSTATE_BOOL(halt
, NCQTransferState
),
1540 VMSTATE_END_OF_LIST()
1544 static const VMStateDescription vmstate_ahci_device
= {
1545 .name
= "ahci port",
1547 .fields
= (VMStateField
[]) {
1548 VMSTATE_IDE_BUS(port
, AHCIDevice
),
1549 VMSTATE_IDE_DRIVE(port
.ifs
[0], AHCIDevice
),
1550 VMSTATE_UINT32(port_state
, AHCIDevice
),
1551 VMSTATE_UINT32(finished
, AHCIDevice
),
1552 VMSTATE_UINT32(port_regs
.lst_addr
, AHCIDevice
),
1553 VMSTATE_UINT32(port_regs
.lst_addr_hi
, AHCIDevice
),
1554 VMSTATE_UINT32(port_regs
.fis_addr
, AHCIDevice
),
1555 VMSTATE_UINT32(port_regs
.fis_addr_hi
, AHCIDevice
),
1556 VMSTATE_UINT32(port_regs
.irq_stat
, AHCIDevice
),
1557 VMSTATE_UINT32(port_regs
.irq_mask
, AHCIDevice
),
1558 VMSTATE_UINT32(port_regs
.cmd
, AHCIDevice
),
1559 VMSTATE_UINT32(port_regs
.tfdata
, AHCIDevice
),
1560 VMSTATE_UINT32(port_regs
.sig
, AHCIDevice
),
1561 VMSTATE_UINT32(port_regs
.scr_stat
, AHCIDevice
),
1562 VMSTATE_UINT32(port_regs
.scr_ctl
, AHCIDevice
),
1563 VMSTATE_UINT32(port_regs
.scr_err
, AHCIDevice
),
1564 VMSTATE_UINT32(port_regs
.scr_act
, AHCIDevice
),
1565 VMSTATE_UINT32(port_regs
.cmd_issue
, AHCIDevice
),
1566 VMSTATE_BOOL(done_atapi_packet
, AHCIDevice
),
1567 VMSTATE_INT32(busy_slot
, AHCIDevice
),
1568 VMSTATE_BOOL(init_d2h_sent
, AHCIDevice
),
1569 VMSTATE_STRUCT_ARRAY(ncq_tfs
, AHCIDevice
, AHCI_MAX_CMDS
,
1570 1, vmstate_ncq_tfs
, NCQTransferState
),
1571 VMSTATE_END_OF_LIST()
1575 static int ahci_state_post_load(void *opaque
, int version_id
)
1578 struct AHCIDevice
*ad
;
1579 NCQTransferState
*ncq_tfs
;
1581 AHCIState
*s
= opaque
;
1583 for (i
= 0; i
< s
->ports
; i
++) {
1585 pr
= &ad
->port_regs
;
1587 if (!(pr
->cmd
& PORT_CMD_START
) && (pr
->cmd
& PORT_CMD_LIST_ON
)) {
1588 error_report("AHCI: DMA engine should be off, but status bit "
1589 "indicates it is still running.");
1592 if (!(pr
->cmd
& PORT_CMD_FIS_RX
) && (pr
->cmd
& PORT_CMD_FIS_ON
)) {
1593 error_report("AHCI: FIS RX engine should be off, but status bit "
1594 "indicates it is still running.");
1598 /* After a migrate, the DMA/FIS engines are "off" and
1599 * need to be conditionally restarted */
1600 pr
->cmd
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
);
1601 if (ahci_cond_start_engines(ad
) != 0) {
1605 for (j
= 0; j
< AHCI_MAX_CMDS
; j
++) {
1606 ncq_tfs
= &ad
->ncq_tfs
[j
];
1607 ncq_tfs
->drive
= ad
;
1609 if (ncq_tfs
->used
!= ncq_tfs
->halt
) {
1612 if (!ncq_tfs
->halt
) {
1615 if (!is_ncq(ncq_tfs
->cmd
)) {
1618 if (ncq_tfs
->slot
!= ncq_tfs
->tag
) {
1621 /* If ncq_tfs->halt is justly set, the engine should be engaged,
1622 * and the command list buffer should be mapped. */
1623 ncq_tfs
->cmdh
= get_cmd_header(s
, i
, ncq_tfs
->slot
);
1624 if (!ncq_tfs
->cmdh
) {
1627 ahci_populate_sglist(ncq_tfs
->drive
, &ncq_tfs
->sglist
,
1628 ncq_tfs
->cmdh
, ncq_tfs
->sector_count
* 512,
1630 if (ncq_tfs
->sector_count
!= ncq_tfs
->sglist
.size
>> 9) {
1637 * If an error is present, ad->busy_slot will be valid and not -1.
1638 * In this case, an operation is waiting to resume and will re-check
1639 * for additional AHCI commands to execute upon completion.
1641 * In the case where no error was present, busy_slot will be -1,
1642 * and we should check to see if there are additional commands waiting.
1644 if (ad
->busy_slot
== -1) {
1647 /* We are in the middle of a command, and may need to access
1648 * the command header in guest memory again. */
1649 if (ad
->busy_slot
< 0 || ad
->busy_slot
>= AHCI_MAX_CMDS
) {
1652 ad
->cur_cmd
= get_cmd_header(s
, i
, ad
->busy_slot
);
1659 const VMStateDescription vmstate_ahci
= {
1662 .post_load
= ahci_state_post_load
,
1663 .fields
= (VMStateField
[]) {
1664 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev
, AHCIState
, ports
,
1665 vmstate_ahci_device
, AHCIDevice
),
1666 VMSTATE_UINT32(control_regs
.cap
, AHCIState
),
1667 VMSTATE_UINT32(control_regs
.ghc
, AHCIState
),
1668 VMSTATE_UINT32(control_regs
.irqstatus
, AHCIState
),
1669 VMSTATE_UINT32(control_regs
.impl
, AHCIState
),
1670 VMSTATE_UINT32(control_regs
.version
, AHCIState
),
1671 VMSTATE_UINT32(idp_index
, AHCIState
),
1672 VMSTATE_INT32_EQUAL(ports
, AHCIState
),
1673 VMSTATE_END_OF_LIST()
1677 static const VMStateDescription vmstate_sysbus_ahci
= {
1678 .name
= "sysbus-ahci",
1679 .fields
= (VMStateField
[]) {
1680 VMSTATE_AHCI(ahci
, SysbusAHCIState
),
1681 VMSTATE_END_OF_LIST()
1685 static void sysbus_ahci_reset(DeviceState
*dev
)
1687 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1689 ahci_reset(&s
->ahci
);
1692 static void sysbus_ahci_init(Object
*obj
)
1694 SysbusAHCIState
*s
= SYSBUS_AHCI(obj
);
1695 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1697 ahci_init(&s
->ahci
, DEVICE(obj
));
1699 sysbus_init_mmio(sbd
, &s
->ahci
.mem
);
1700 sysbus_init_irq(sbd
, &s
->ahci
.irq
);
1703 static void sysbus_ahci_realize(DeviceState
*dev
, Error
**errp
)
1705 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1707 ahci_realize(&s
->ahci
, dev
, &address_space_memory
, s
->num_ports
);
1710 static Property sysbus_ahci_properties
[] = {
1711 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState
, num_ports
, 1),
1712 DEFINE_PROP_END_OF_LIST(),
1715 static void sysbus_ahci_class_init(ObjectClass
*klass
, void *data
)
1717 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1719 dc
->realize
= sysbus_ahci_realize
;
1720 dc
->vmsd
= &vmstate_sysbus_ahci
;
1721 dc
->props
= sysbus_ahci_properties
;
1722 dc
->reset
= sysbus_ahci_reset
;
1723 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1726 static const TypeInfo sysbus_ahci_info
= {
1727 .name
= TYPE_SYSBUS_AHCI
,
1728 .parent
= TYPE_SYS_BUS_DEVICE
,
1729 .instance_size
= sizeof(SysbusAHCIState
),
1730 .instance_init
= sysbus_ahci_init
,
1731 .class_init
= sysbus_ahci_class_init
,
1734 #define ALLWINNER_AHCI_BISTAFR ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1735 #define ALLWINNER_AHCI_BISTCR ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1736 #define ALLWINNER_AHCI_BISTFCTR ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1737 #define ALLWINNER_AHCI_BISTSR ((0xac - ALLWINNER_AHCI_MMIO_OFF) / 4)
1738 #define ALLWINNER_AHCI_BISTDECR ((0xb0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1739 #define ALLWINNER_AHCI_DIAGNR0 ((0xb4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1740 #define ALLWINNER_AHCI_DIAGNR1 ((0xb8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1741 #define ALLWINNER_AHCI_OOBR ((0xbc - ALLWINNER_AHCI_MMIO_OFF) / 4)
1742 #define ALLWINNER_AHCI_PHYCS0R ((0xc0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1743 #define ALLWINNER_AHCI_PHYCS1R ((0xc4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1744 #define ALLWINNER_AHCI_PHYCS2R ((0xc8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1745 #define ALLWINNER_AHCI_TIMER1MS ((0xe0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1746 #define ALLWINNER_AHCI_GPARAM1R ((0xe8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1747 #define ALLWINNER_AHCI_GPARAM2R ((0xec - ALLWINNER_AHCI_MMIO_OFF) / 4)
1748 #define ALLWINNER_AHCI_PPARAMR ((0xf0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1749 #define ALLWINNER_AHCI_TESTR ((0xf4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1750 #define ALLWINNER_AHCI_VERSIONR ((0xf8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
1751 #define ALLWINNER_AHCI_IDR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
1752 #define ALLWINNER_AHCI_RWCR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
1754 static uint64_t allwinner_ahci_mem_read(void *opaque
, hwaddr addr
,
1757 AllwinnerAHCIState
*a
= opaque
;
1758 uint64_t val
= a
->regs
[addr
/4];
1761 case ALLWINNER_AHCI_PHYCS0R
:
1764 case ALLWINNER_AHCI_PHYCS2R
:
1765 val
&= ~(0x1 << 24);
1768 DPRINTF(-1, "addr=0x%" HWADDR_PRIx
" val=0x%" PRIx64
", size=%d\n",
1773 static void allwinner_ahci_mem_write(void *opaque
, hwaddr addr
,
1774 uint64_t val
, unsigned size
)
1776 AllwinnerAHCIState
*a
= opaque
;
1778 DPRINTF(-1, "addr=0x%" HWADDR_PRIx
" val=0x%" PRIx64
", size=%d\n",
1780 a
->regs
[addr
/4] = val
;
1783 static const MemoryRegionOps allwinner_ahci_mem_ops
= {
1784 .read
= allwinner_ahci_mem_read
,
1785 .write
= allwinner_ahci_mem_write
,
1786 .valid
.min_access_size
= 4,
1787 .valid
.max_access_size
= 4,
1788 .endianness
= DEVICE_LITTLE_ENDIAN
,
1791 static void allwinner_ahci_init(Object
*obj
)
1793 SysbusAHCIState
*s
= SYSBUS_AHCI(obj
);
1794 AllwinnerAHCIState
*a
= ALLWINNER_AHCI(obj
);
1796 memory_region_init_io(&a
->mmio
, OBJECT(obj
), &allwinner_ahci_mem_ops
, a
,
1797 "allwinner-ahci", ALLWINNER_AHCI_MMIO_SIZE
);
1798 memory_region_add_subregion(&s
->ahci
.mem
, ALLWINNER_AHCI_MMIO_OFF
,
1802 static const VMStateDescription vmstate_allwinner_ahci
= {
1803 .name
= "allwinner-ahci",
1805 .minimum_version_id
= 1,
1806 .fields
= (VMStateField
[]) {
1807 VMSTATE_UINT32_ARRAY(regs
, AllwinnerAHCIState
,
1808 ALLWINNER_AHCI_MMIO_SIZE
/4),
1809 VMSTATE_END_OF_LIST()
1813 static void allwinner_ahci_class_init(ObjectClass
*klass
, void *data
)
1815 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1817 dc
->vmsd
= &vmstate_allwinner_ahci
;
1820 static const TypeInfo allwinner_ahci_info
= {
1821 .name
= TYPE_ALLWINNER_AHCI
,
1822 .parent
= TYPE_SYSBUS_AHCI
,
1823 .instance_size
= sizeof(AllwinnerAHCIState
),
1824 .instance_init
= allwinner_ahci_init
,
1825 .class_init
= allwinner_ahci_class_init
,
1828 static void sysbus_ahci_register_types(void)
1830 type_register_static(&sysbus_ahci_info
);
1831 type_register_static(&allwinner_ahci_info
);
1834 type_init(sysbus_ahci_register_types
)
1836 void ahci_ide_create_devs(PCIDevice
*dev
, DriveInfo
**hd
)
1838 AHCIPCIState
*d
= ICH_AHCI(dev
);
1839 AHCIState
*ahci
= &d
->ahci
;
1842 for (i
= 0; i
< ahci
->ports
; i
++) {
1843 if (hd
[i
] == NULL
) {
1846 ide_create_drive(&ahci
->dev
[i
].port
, 0, hd
[i
]);