2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "tcg-be-ldst.h"
28 #if defined _CALL_DARWIN || defined __APPLE__
29 #define TCG_TARGET_CALL_DARWIN
32 # define TCG_TARGET_CALL_ALIGN_ARGS 1
35 /* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
40 # define TCG_REG_TMP1 TCG_REG_R2
42 # define TCG_REG_TMP1 TCG_REG_R12
45 /* For the 64-bit target, we don't like the 5 insn sequence needed to build
46 full 64-bit addresses. Better to have a base register to which we can
47 apply a 32-bit displacement.
49 There are generally three items of interest:
50 (1) helper functions in the main executable,
51 (2) TranslationBlock data structures,
52 (3) the return address in the epilogue.
54 For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer
55 will be inside the main executable, and thus near enough to make a
56 pointer to the epilogue be within 2GB of all helper functions.
58 For softmmu, we'll let the kernel choose the address of code_gen_buffer,
59 and odds are it'll be somewhere close to the main malloc arena, and so
60 a pointer to the epilogue will be within 2GB of the TranslationBlocks.
62 For --enable-pie, everything will be kinda near everything else,
63 somewhere in high memory.
65 Thus we choose to keep the return address in a call-saved register. */
66 #define TCG_REG_RA TCG_REG_R31
67 #define USE_REG_RA (TCG_TARGET_REG_BITS == 64)
69 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
70 #define SZP ((int)sizeof(void *))
72 /* Shorthand for size of a register. */
73 #define SZR (TCG_TARGET_REG_BITS / 8)
75 #define TCG_CT_CONST_S16 0x100
76 #define TCG_CT_CONST_U16 0x200
77 #define TCG_CT_CONST_S32 0x400
78 #define TCG_CT_CONST_U32 0x800
79 #define TCG_CT_CONST_ZERO 0x1000
80 #define TCG_CT_CONST_MONE 0x2000
82 static tcg_insn_unit
*tb_ret_addr
;
85 static bool have_isa_2_06
;
86 #define HAVE_ISA_2_06 have_isa_2_06
87 #define HAVE_ISEL have_isa_2_06
89 #ifndef CONFIG_SOFTMMU
90 #define TCG_GUEST_BASE_REG 30
94 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
130 static const int tcg_target_reg_alloc_order
[] = {
131 TCG_REG_R14
, /* call saved registers */
149 TCG_REG_R12
, /* call clobbered, non-arguments */
153 TCG_REG_R10
, /* call clobbered, arguments */
163 static const int tcg_target_call_iarg_regs
[] = {
174 static const int tcg_target_call_oarg_regs
[] = {
179 static const int tcg_target_callee_save_regs
[] = {
180 #ifdef TCG_TARGET_CALL_DARWIN
196 TCG_REG_R27
, /* currently used for the global env */
203 static inline bool in_range_b(tcg_target_long target
)
205 return target
== sextract64(target
, 0, 26);
208 static uint32_t reloc_pc24_val(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
210 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
211 assert(in_range_b(disp
));
212 return disp
& 0x3fffffc;
215 static void reloc_pc24(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
217 *pc
= (*pc
& ~0x3fffffc) | reloc_pc24_val(pc
, target
);
220 static uint16_t reloc_pc14_val(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
222 ptrdiff_t disp
= tcg_ptr_byte_diff(target
, pc
);
223 assert(disp
== (int16_t) disp
);
224 return disp
& 0xfffc;
227 static void reloc_pc14(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
229 *pc
= (*pc
& ~0xfffc) | reloc_pc14_val(pc
, target
);
232 static inline void tcg_out_b_noaddr(TCGContext
*s
, int insn
)
234 unsigned retrans
= *s
->code_ptr
& 0x3fffffc;
235 tcg_out32(s
, insn
| retrans
);
238 static inline void tcg_out_bc_noaddr(TCGContext
*s
, int insn
)
240 unsigned retrans
= *s
->code_ptr
& 0xfffc;
241 tcg_out32(s
, insn
| retrans
);
244 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
245 intptr_t value
, intptr_t addend
)
247 tcg_insn_unit
*target
= (tcg_insn_unit
*)value
;
252 reloc_pc14(code_ptr
, target
);
255 reloc_pc24(code_ptr
, target
);
262 /* parse target specific constraints */
263 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
269 case 'A': case 'B': case 'C': case 'D':
270 ct
->ct
|= TCG_CT_REG
;
271 tcg_regset_set_reg(ct
->u
.regs
, 3 + ct_str
[0] - 'A');
274 ct
->ct
|= TCG_CT_REG
;
275 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
277 case 'L': /* qemu_ld constraint */
278 ct
->ct
|= TCG_CT_REG
;
279 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
280 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
281 #ifdef CONFIG_SOFTMMU
282 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
283 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
286 case 'S': /* qemu_st constraint */
287 ct
->ct
|= TCG_CT_REG
;
288 tcg_regset_set32(ct
->u
.regs
, 0, 0xffffffff);
289 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
290 #ifdef CONFIG_SOFTMMU
291 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R4
);
292 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R5
);
293 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R6
);
297 ct
->ct
|= TCG_CT_CONST_S16
;
300 ct
->ct
|= TCG_CT_CONST_U16
;
303 ct
->ct
|= TCG_CT_CONST_MONE
;
306 ct
->ct
|= TCG_CT_CONST_S32
;
309 ct
->ct
|= TCG_CT_CONST_U32
;
312 ct
->ct
|= TCG_CT_CONST_ZERO
;
322 /* test if a constant matches the constraint */
323 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
324 const TCGArgConstraint
*arg_ct
)
327 if (ct
& TCG_CT_CONST
) {
331 /* The only 32-bit constraint we use aside from
332 TCG_CT_CONST is TCG_CT_CONST_S16. */
333 if (type
== TCG_TYPE_I32
) {
337 if ((ct
& TCG_CT_CONST_S16
) && val
== (int16_t)val
) {
339 } else if ((ct
& TCG_CT_CONST_U16
) && val
== (uint16_t)val
) {
341 } else if ((ct
& TCG_CT_CONST_S32
) && val
== (int32_t)val
) {
343 } else if ((ct
& TCG_CT_CONST_U32
) && val
== (uint32_t)val
) {
345 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
347 } else if ((ct
& TCG_CT_CONST_MONE
) && val
== -1) {
353 #define OPCD(opc) ((opc)<<26)
354 #define XO19(opc) (OPCD(19)|((opc)<<1))
355 #define MD30(opc) (OPCD(30)|((opc)<<2))
356 #define MDS30(opc) (OPCD(30)|((opc)<<1))
357 #define XO31(opc) (OPCD(31)|((opc)<<1))
358 #define XO58(opc) (OPCD(58)|(opc))
359 #define XO62(opc) (OPCD(62)|(opc))
363 #define LBZ OPCD( 34)
364 #define LHZ OPCD( 40)
365 #define LHA OPCD( 42)
366 #define LWZ OPCD( 32)
367 #define STB OPCD( 38)
368 #define STH OPCD( 44)
369 #define STW OPCD( 36)
372 #define STDU XO62( 1)
373 #define STDX XO31(149)
376 #define LDX XO31( 21)
379 #define LWAX XO31(341)
381 #define ADDIC OPCD( 12)
382 #define ADDI OPCD( 14)
383 #define ADDIS OPCD( 15)
384 #define ORI OPCD( 24)
385 #define ORIS OPCD( 25)
386 #define XORI OPCD( 26)
387 #define XORIS OPCD( 27)
388 #define ANDI OPCD( 28)
389 #define ANDIS OPCD( 29)
390 #define MULLI OPCD( 7)
391 #define CMPLI OPCD( 10)
392 #define CMPI OPCD( 11)
393 #define SUBFIC OPCD( 8)
395 #define LWZU OPCD( 33)
396 #define STWU OPCD( 37)
398 #define RLWIMI OPCD( 20)
399 #define RLWINM OPCD( 21)
400 #define RLWNM OPCD( 23)
402 #define RLDICL MD30( 0)
403 #define RLDICR MD30( 1)
404 #define RLDIMI MD30( 3)
405 #define RLDCL MDS30( 8)
407 #define BCLR XO19( 16)
408 #define BCCTR XO19(528)
409 #define CRAND XO19(257)
410 #define CRANDC XO19(129)
411 #define CRNAND XO19(225)
412 #define CROR XO19(449)
413 #define CRNOR XO19( 33)
415 #define EXTSB XO31(954)
416 #define EXTSH XO31(922)
417 #define EXTSW XO31(986)
418 #define ADD XO31(266)
419 #define ADDE XO31(138)
420 #define ADDME XO31(234)
421 #define ADDZE XO31(202)
422 #define ADDC XO31( 10)
423 #define AND XO31( 28)
424 #define SUBF XO31( 40)
425 #define SUBFC XO31( 8)
426 #define SUBFE XO31(136)
427 #define SUBFME XO31(232)
428 #define SUBFZE XO31(200)
430 #define XOR XO31(316)
431 #define MULLW XO31(235)
432 #define MULHW XO31( 75)
433 #define MULHWU XO31( 11)
434 #define DIVW XO31(491)
435 #define DIVWU XO31(459)
437 #define CMPL XO31( 32)
438 #define LHBRX XO31(790)
439 #define LWBRX XO31(534)
440 #define LDBRX XO31(532)
441 #define STHBRX XO31(918)
442 #define STWBRX XO31(662)
443 #define STDBRX XO31(660)
444 #define MFSPR XO31(339)
445 #define MTSPR XO31(467)
446 #define SRAWI XO31(824)
447 #define NEG XO31(104)
448 #define MFCR XO31( 19)
449 #define MFOCRF (MFCR | (1u << 20))
450 #define NOR XO31(124)
451 #define CNTLZW XO31( 26)
452 #define CNTLZD XO31( 58)
453 #define ANDC XO31( 60)
454 #define ORC XO31(412)
455 #define EQV XO31(284)
456 #define NAND XO31(476)
457 #define ISEL XO31( 15)
459 #define MULLD XO31(233)
460 #define MULHD XO31( 73)
461 #define MULHDU XO31( 9)
462 #define DIVD XO31(489)
463 #define DIVDU XO31(457)
465 #define LBZX XO31( 87)
466 #define LHZX XO31(279)
467 #define LHAX XO31(343)
468 #define LWZX XO31( 23)
469 #define STBX XO31(215)
470 #define STHX XO31(407)
471 #define STWX XO31(151)
473 #define SPR(a, b) ((((a)<<5)|(b))<<11)
475 #define CTR SPR(9, 0)
477 #define SLW XO31( 24)
478 #define SRW XO31(536)
479 #define SRAW XO31(792)
481 #define SLD XO31( 27)
482 #define SRD XO31(539)
483 #define SRAD XO31(794)
484 #define SRADI XO31(413<<1)
487 #define TRAP (TW | TO(31))
489 #define NOP ORI /* ori 0,0,0 */
491 #define RT(r) ((r)<<21)
492 #define RS(r) ((r)<<21)
493 #define RA(r) ((r)<<16)
494 #define RB(r) ((r)<<11)
495 #define TO(t) ((t)<<21)
496 #define SH(s) ((s)<<11)
497 #define MB(b) ((b)<<6)
498 #define ME(e) ((e)<<1)
499 #define BO(o) ((o)<<21)
500 #define MB64(b) ((b)<<5)
501 #define FXM(b) (1 << (19 - (b)))
505 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
506 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
507 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
508 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
510 #define BF(n) ((n)<<23)
511 #define BI(n, c) (((c)+((n)*4))<<16)
512 #define BT(n, c) (((c)+((n)*4))<<21)
513 #define BA(n, c) (((c)+((n)*4))<<16)
514 #define BB(n, c) (((c)+((n)*4))<<11)
515 #define BC_(n, c) (((c)+((n)*4))<<6)
517 #define BO_COND_TRUE BO(12)
518 #define BO_COND_FALSE BO( 4)
519 #define BO_ALWAYS BO(20)
528 static const uint32_t tcg_to_bc
[] = {
529 [TCG_COND_EQ
] = BC
| BI(7, CR_EQ
) | BO_COND_TRUE
,
530 [TCG_COND_NE
] = BC
| BI(7, CR_EQ
) | BO_COND_FALSE
,
531 [TCG_COND_LT
] = BC
| BI(7, CR_LT
) | BO_COND_TRUE
,
532 [TCG_COND_GE
] = BC
| BI(7, CR_LT
) | BO_COND_FALSE
,
533 [TCG_COND_LE
] = BC
| BI(7, CR_GT
) | BO_COND_FALSE
,
534 [TCG_COND_GT
] = BC
| BI(7, CR_GT
) | BO_COND_TRUE
,
535 [TCG_COND_LTU
] = BC
| BI(7, CR_LT
) | BO_COND_TRUE
,
536 [TCG_COND_GEU
] = BC
| BI(7, CR_LT
) | BO_COND_FALSE
,
537 [TCG_COND_LEU
] = BC
| BI(7, CR_GT
) | BO_COND_FALSE
,
538 [TCG_COND_GTU
] = BC
| BI(7, CR_GT
) | BO_COND_TRUE
,
541 /* The low bit here is set if the RA and RB fields must be inverted. */
542 static const uint32_t tcg_to_isel
[] = {
543 [TCG_COND_EQ
] = ISEL
| BC_(7, CR_EQ
),
544 [TCG_COND_NE
] = ISEL
| BC_(7, CR_EQ
) | 1,
545 [TCG_COND_LT
] = ISEL
| BC_(7, CR_LT
),
546 [TCG_COND_GE
] = ISEL
| BC_(7, CR_LT
) | 1,
547 [TCG_COND_LE
] = ISEL
| BC_(7, CR_GT
) | 1,
548 [TCG_COND_GT
] = ISEL
| BC_(7, CR_GT
),
549 [TCG_COND_LTU
] = ISEL
| BC_(7, CR_LT
),
550 [TCG_COND_GEU
] = ISEL
| BC_(7, CR_LT
) | 1,
551 [TCG_COND_LEU
] = ISEL
| BC_(7, CR_GT
) | 1,
552 [TCG_COND_GTU
] = ISEL
| BC_(7, CR_GT
),
555 static void tcg_out_mem_long(TCGContext
*s
, int opi
, int opx
, TCGReg rt
,
556 TCGReg base
, tcg_target_long offset
);
558 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
)
560 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
562 tcg_out32(s
, OR
| SAB(arg
, ret
, arg
));
566 static inline void tcg_out_rld(TCGContext
*s
, int op
, TCGReg ra
, TCGReg rs
,
569 assert(TCG_TARGET_REG_BITS
== 64);
570 sh
= SH(sh
& 0x1f) | (((sh
>> 5) & 1) << 1);
571 mb
= MB64((mb
>> 5) | ((mb
<< 1) & 0x3f));
572 tcg_out32(s
, op
| RA(ra
) | RS(rs
) | sh
| mb
);
575 static inline void tcg_out_rlw(TCGContext
*s
, int op
, TCGReg ra
, TCGReg rs
,
576 int sh
, int mb
, int me
)
578 tcg_out32(s
, op
| RA(ra
) | RS(rs
) | SH(sh
) | MB(mb
) | ME(me
));
581 static inline void tcg_out_ext32u(TCGContext
*s
, TCGReg dst
, TCGReg src
)
583 tcg_out_rld(s
, RLDICL
, dst
, src
, 0, 32);
586 static inline void tcg_out_shli32(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
588 tcg_out_rlw(s
, RLWINM
, dst
, src
, c
, 0, 31 - c
);
591 static inline void tcg_out_shli64(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
593 tcg_out_rld(s
, RLDICR
, dst
, src
, c
, 63 - c
);
596 static inline void tcg_out_shri32(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
598 tcg_out_rlw(s
, RLWINM
, dst
, src
, 32 - c
, c
, 31);
601 static inline void tcg_out_shri64(TCGContext
*s
, TCGReg dst
, TCGReg src
, int c
)
603 tcg_out_rld(s
, RLDICL
, dst
, src
, 64 - c
, c
);
606 static void tcg_out_movi32(TCGContext
*s
, TCGReg ret
, int32_t arg
)
608 if (arg
== (int16_t) arg
) {
609 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
611 tcg_out32(s
, ADDIS
| TAI(ret
, 0, arg
>> 16));
613 tcg_out32(s
, ORI
| SAI(ret
, ret
, arg
));
618 static void tcg_out_movi(TCGContext
*s
, TCGType type
, TCGReg ret
,
621 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
622 if (type
== TCG_TYPE_I32
|| arg
== (int32_t)arg
) {
623 tcg_out_movi32(s
, ret
, arg
);
624 } else if (arg
== (uint32_t)arg
&& !(arg
& 0x8000)) {
625 tcg_out32(s
, ADDI
| TAI(ret
, 0, arg
));
626 tcg_out32(s
, ORIS
| SAI(ret
, ret
, arg
>> 16));
631 intptr_t diff
= arg
- (intptr_t)tb_ret_addr
;
632 if (diff
== (int32_t)diff
) {
633 tcg_out_mem_long(s
, ADDI
, ADD
, ret
, TCG_REG_RA
, diff
);
638 high
= arg
>> 31 >> 1;
639 tcg_out_movi32(s
, ret
, high
);
641 tcg_out_shli64(s
, ret
, ret
, 32);
643 if (arg
& 0xffff0000) {
644 tcg_out32(s
, ORIS
| SAI(ret
, ret
, arg
>> 16));
647 tcg_out32(s
, ORI
| SAI(ret
, ret
, arg
));
652 static bool mask_operand(uint32_t c
, int *mb
, int *me
)
656 /* Accept a bit pattern like:
660 Keep track of the transitions. */
661 if (c
== 0 || c
== -1) {
667 if (test
& (test
- 1)) {
672 *mb
= test
? clz32(test
& -test
) + 1 : 0;
676 static bool mask64_operand(uint64_t c
, int *mb
, int *me
)
685 /* Accept 1..10..0. */
691 /* Accept 0..01..1. */
692 if (lsb
== 1 && (c
& (c
+ 1)) == 0) {
693 *mb
= clz64(c
+ 1) + 1;
700 static void tcg_out_andi32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
704 if (mask_operand(c
, &mb
, &me
)) {
705 tcg_out_rlw(s
, RLWINM
, dst
, src
, 0, mb
, me
);
706 } else if ((c
& 0xffff) == c
) {
707 tcg_out32(s
, ANDI
| SAI(src
, dst
, c
));
709 } else if ((c
& 0xffff0000) == c
) {
710 tcg_out32(s
, ANDIS
| SAI(src
, dst
, c
>> 16));
713 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_R0
, c
);
714 tcg_out32(s
, AND
| SAB(src
, dst
, TCG_REG_R0
));
718 static void tcg_out_andi64(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint64_t c
)
722 assert(TCG_TARGET_REG_BITS
== 64);
723 if (mask64_operand(c
, &mb
, &me
)) {
725 tcg_out_rld(s
, RLDICR
, dst
, src
, 0, me
);
727 tcg_out_rld(s
, RLDICL
, dst
, src
, 0, mb
);
729 } else if ((c
& 0xffff) == c
) {
730 tcg_out32(s
, ANDI
| SAI(src
, dst
, c
));
732 } else if ((c
& 0xffff0000) == c
) {
733 tcg_out32(s
, ANDIS
| SAI(src
, dst
, c
>> 16));
736 tcg_out_movi(s
, TCG_TYPE_I64
, TCG_REG_R0
, c
);
737 tcg_out32(s
, AND
| SAB(src
, dst
, TCG_REG_R0
));
741 static void tcg_out_zori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
,
742 int op_lo
, int op_hi
)
745 tcg_out32(s
, op_hi
| SAI(src
, dst
, c
>> 16));
749 tcg_out32(s
, op_lo
| SAI(src
, dst
, c
));
754 static void tcg_out_ori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
756 tcg_out_zori32(s
, dst
, src
, c
, ORI
, ORIS
);
759 static void tcg_out_xori32(TCGContext
*s
, TCGReg dst
, TCGReg src
, uint32_t c
)
761 tcg_out_zori32(s
, dst
, src
, c
, XORI
, XORIS
);
764 static void tcg_out_b(TCGContext
*s
, int mask
, tcg_insn_unit
*target
)
766 ptrdiff_t disp
= tcg_pcrel_diff(s
, target
);
767 if (in_range_b(disp
)) {
768 tcg_out32(s
, B
| (disp
& 0x3fffffc) | mask
);
770 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R0
, (uintptr_t)target
);
771 tcg_out32(s
, MTSPR
| RS(TCG_REG_R0
) | CTR
);
772 tcg_out32(s
, BCCTR
| BO_ALWAYS
| mask
);
776 static void tcg_out_mem_long(TCGContext
*s
, int opi
, int opx
, TCGReg rt
,
777 TCGReg base
, tcg_target_long offset
)
779 tcg_target_long orig
= offset
, l0
, l1
, extra
= 0, align
= 0;
780 bool is_store
= false;
781 TCGReg rs
= TCG_REG_TMP1
;
788 if (rt
!= TCG_REG_R0
) {
796 case STB
: case STH
: case STW
:
801 /* For unaligned, or very large offsets, use the indexed form. */
802 if (offset
& align
|| offset
!= (int32_t)offset
) {
806 tcg_debug_assert(!is_store
|| rs
!= rt
);
807 tcg_out_movi(s
, TCG_TYPE_PTR
, rs
, orig
);
808 tcg_out32(s
, opx
| TAB(rt
, base
, rs
));
812 l0
= (int16_t)offset
;
813 offset
= (offset
- l0
) >> 16;
814 l1
= (int16_t)offset
;
816 if (l1
< 0 && orig
>= 0) {
818 l1
= (int16_t)(offset
- 0x4000);
821 tcg_out32(s
, ADDIS
| TAI(rs
, base
, l1
));
825 tcg_out32(s
, ADDIS
| TAI(rs
, base
, extra
));
828 if (opi
!= ADDI
|| base
!= rt
|| l0
!= 0) {
829 tcg_out32(s
, opi
| TAI(rt
, base
, l0
));
833 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
,
834 TCGReg arg1
, intptr_t arg2
)
838 assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
839 if (type
== TCG_TYPE_I32
) {
840 opi
= LWZ
, opx
= LWZX
;
844 tcg_out_mem_long(s
, opi
, opx
, ret
, arg1
, arg2
);
847 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
848 TCGReg arg1
, intptr_t arg2
)
852 assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
853 if (type
== TCG_TYPE_I32
) {
854 opi
= STW
, opx
= STWX
;
856 opi
= STD
, opx
= STDX
;
858 tcg_out_mem_long(s
, opi
, opx
, arg
, arg1
, arg2
);
861 static void tcg_out_cmp(TCGContext
*s
, int cond
, TCGArg arg1
, TCGArg arg2
,
862 int const_arg2
, int cr
, TCGType type
)
867 tcg_debug_assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
869 /* Simplify the comparisons below wrt CMPI. */
870 if (type
== TCG_TYPE_I32
) {
871 arg2
= (int32_t)arg2
;
878 if ((int16_t) arg2
== arg2
) {
882 } else if ((uint16_t) arg2
== arg2
) {
897 if ((int16_t) arg2
== arg2
) {
912 if ((uint16_t) arg2
== arg2
) {
925 op
|= BF(cr
) | ((type
== TCG_TYPE_I64
) << 21);
928 tcg_out32(s
, op
| RA(arg1
) | (arg2
& 0xffff));
931 tcg_out_movi(s
, type
, TCG_REG_R0
, arg2
);
934 tcg_out32(s
, op
| RA(arg1
) | RB(arg2
));
938 static void tcg_out_setcond_eq0(TCGContext
*s
, TCGType type
,
939 TCGReg dst
, TCGReg src
)
941 if (type
== TCG_TYPE_I32
) {
942 tcg_out32(s
, CNTLZW
| RS(src
) | RA(dst
));
943 tcg_out_shri32(s
, dst
, dst
, 5);
945 tcg_out32(s
, CNTLZD
| RS(src
) | RA(dst
));
946 tcg_out_shri64(s
, dst
, dst
, 6);
950 static void tcg_out_setcond_ne0(TCGContext
*s
, TCGReg dst
, TCGReg src
)
952 /* X != 0 implies X + -1 generates a carry. Extra addition
953 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
955 tcg_out32(s
, ADDIC
| TAI(dst
, src
, -1));
956 tcg_out32(s
, SUBFE
| TAB(dst
, dst
, src
));
958 tcg_out32(s
, ADDIC
| TAI(TCG_REG_R0
, src
, -1));
959 tcg_out32(s
, SUBFE
| TAB(dst
, TCG_REG_R0
, src
));
963 static TCGReg
tcg_gen_setcond_xor(TCGContext
*s
, TCGReg arg1
, TCGArg arg2
,
967 if ((uint32_t)arg2
== arg2
) {
968 tcg_out_xori32(s
, TCG_REG_R0
, arg1
, arg2
);
970 tcg_out_movi(s
, TCG_TYPE_I64
, TCG_REG_R0
, arg2
);
971 tcg_out32(s
, XOR
| SAB(arg1
, TCG_REG_R0
, TCG_REG_R0
));
974 tcg_out32(s
, XOR
| SAB(arg1
, TCG_REG_R0
, arg2
));
979 static void tcg_out_setcond(TCGContext
*s
, TCGType type
, TCGCond cond
,
980 TCGArg arg0
, TCGArg arg1
, TCGArg arg2
,
985 assert(TCG_TARGET_REG_BITS
== 64 || type
== TCG_TYPE_I32
);
987 /* Ignore high bits of a potential constant arg2. */
988 if (type
== TCG_TYPE_I32
) {
989 arg2
= (uint32_t)arg2
;
992 /* Handle common and trivial cases before handling anything else. */
996 tcg_out_setcond_eq0(s
, type
, arg0
, arg1
);
999 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
1000 tcg_out_ext32u(s
, TCG_REG_R0
, arg1
);
1003 tcg_out_setcond_ne0(s
, arg0
, arg1
);
1006 tcg_out32(s
, NOR
| SAB(arg1
, arg0
, arg1
));
1010 /* Extract the sign bit. */
1011 if (type
== TCG_TYPE_I32
) {
1012 tcg_out_shri32(s
, arg0
, arg1
, 31);
1014 tcg_out_shri64(s
, arg0
, arg1
, 63);
1022 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1023 All other cases below are also at least 3 insns, so speed up the
1024 code generator by not considering them and always using ISEL. */
1028 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1030 isel
= tcg_to_isel
[cond
];
1032 tcg_out_movi(s
, type
, arg0
, 1);
1034 /* arg0 = (bc ? 0 : 1) */
1035 tab
= TAB(arg0
, 0, arg0
);
1038 /* arg0 = (bc ? 1 : 0) */
1039 tcg_out_movi(s
, type
, TCG_REG_R0
, 0);
1040 tab
= TAB(arg0
, arg0
, TCG_REG_R0
);
1042 tcg_out32(s
, isel
| tab
);
1048 arg1
= tcg_gen_setcond_xor(s
, arg1
, arg2
, const_arg2
);
1049 tcg_out_setcond_eq0(s
, type
, arg0
, arg1
);
1053 arg1
= tcg_gen_setcond_xor(s
, arg1
, arg2
, const_arg2
);
1054 /* Discard the high bits only once, rather than both inputs. */
1055 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
1056 tcg_out_ext32u(s
, TCG_REG_R0
, arg1
);
1059 tcg_out_setcond_ne0(s
, arg0
, arg1
);
1077 crop
= CRNOR
| BT(7, CR_EQ
) | BA(7, CR_LT
) | BB(7, CR_LT
);
1083 crop
= CRNOR
| BT(7, CR_EQ
) | BA(7, CR_GT
) | BB(7, CR_GT
);
1085 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1089 tcg_out32(s
, MFOCRF
| RT(TCG_REG_R0
) | FXM(7));
1090 tcg_out_rlw(s
, RLWINM
, arg0
, TCG_REG_R0
, sh
, 31, 31);
1098 static void tcg_out_bc(TCGContext
*s
, int bc
, TCGLabel
*l
)
1101 tcg_out32(s
, bc
| reloc_pc14_val(s
->code_ptr
, l
->u
.value_ptr
));
1103 tcg_out_reloc(s
, s
->code_ptr
, R_PPC_REL14
, l
, 0);
1104 tcg_out_bc_noaddr(s
, bc
);
1108 static void tcg_out_brcond(TCGContext
*s
, TCGCond cond
,
1109 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
1110 TCGLabel
*l
, TCGType type
)
1112 tcg_out_cmp(s
, cond
, arg1
, arg2
, const_arg2
, 7, type
);
1113 tcg_out_bc(s
, tcg_to_bc
[cond
], l
);
1116 static void tcg_out_movcond(TCGContext
*s
, TCGType type
, TCGCond cond
,
1117 TCGArg dest
, TCGArg c1
, TCGArg c2
, TCGArg v1
,
1118 TCGArg v2
, bool const_c2
)
1120 /* If for some reason both inputs are zero, don't produce bad code. */
1121 if (v1
== 0 && v2
== 0) {
1122 tcg_out_movi(s
, type
, dest
, 0);
1126 tcg_out_cmp(s
, cond
, c1
, c2
, const_c2
, 7, type
);
1129 int isel
= tcg_to_isel
[cond
];
1131 /* Swap the V operands if the operation indicates inversion. */
1138 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1140 tcg_out_movi(s
, type
, TCG_REG_R0
, 0);
1142 tcg_out32(s
, isel
| TAB(dest
, v1
, v2
));
1145 cond
= tcg_invert_cond(cond
);
1147 } else if (dest
!= v1
) {
1149 tcg_out_movi(s
, type
, dest
, 0);
1151 tcg_out_mov(s
, type
, dest
, v1
);
1154 /* Branch forward over one insn */
1155 tcg_out32(s
, tcg_to_bc
[cond
] | 8);
1157 tcg_out_movi(s
, type
, dest
, 0);
1159 tcg_out_mov(s
, type
, dest
, v2
);
1164 static void tcg_out_cmp2(TCGContext
*s
, const TCGArg
*args
,
1165 const int *const_args
)
1167 static const struct { uint8_t bit1
, bit2
; } bits
[] = {
1168 [TCG_COND_LT
] = { CR_LT
, CR_LT
},
1169 [TCG_COND_LE
] = { CR_LT
, CR_GT
},
1170 [TCG_COND_GT
] = { CR_GT
, CR_GT
},
1171 [TCG_COND_GE
] = { CR_GT
, CR_LT
},
1172 [TCG_COND_LTU
] = { CR_LT
, CR_LT
},
1173 [TCG_COND_LEU
] = { CR_LT
, CR_GT
},
1174 [TCG_COND_GTU
] = { CR_GT
, CR_GT
},
1175 [TCG_COND_GEU
] = { CR_GT
, CR_LT
},
1178 TCGCond cond
= args
[4], cond2
;
1179 TCGArg al
, ah
, bl
, bh
;
1180 int blconst
, bhconst
;
1187 blconst
= const_args
[2];
1188 bhconst
= const_args
[3];
1197 tcg_out_cmp(s
, cond
, al
, bl
, blconst
, 6, TCG_TYPE_I32
);
1198 tcg_out_cmp(s
, cond
, ah
, bh
, bhconst
, 7, TCG_TYPE_I32
);
1199 tcg_out32(s
, op
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, CR_EQ
));
1210 bit1
= bits
[cond
].bit1
;
1211 bit2
= bits
[cond
].bit2
;
1212 op
= (bit1
!= bit2
? CRANDC
: CRAND
);
1213 cond2
= tcg_unsigned_cond(cond
);
1215 tcg_out_cmp(s
, cond
, ah
, bh
, bhconst
, 6, TCG_TYPE_I32
);
1216 tcg_out_cmp(s
, cond2
, al
, bl
, blconst
, 7, TCG_TYPE_I32
);
1217 tcg_out32(s
, op
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, bit2
));
1218 tcg_out32(s
, CROR
| BT(7, CR_EQ
) | BA(6, bit1
) | BB(7, CR_EQ
));
1226 static void tcg_out_setcond2(TCGContext
*s
, const TCGArg
*args
,
1227 const int *const_args
)
1229 tcg_out_cmp2(s
, args
+ 1, const_args
+ 1);
1230 tcg_out32(s
, MFOCRF
| RT(TCG_REG_R0
) | FXM(7));
1231 tcg_out_rlw(s
, RLWINM
, args
[0], TCG_REG_R0
, 31, 31, 31);
1234 static void tcg_out_brcond2 (TCGContext
*s
, const TCGArg
*args
,
1235 const int *const_args
)
1237 tcg_out_cmp2(s
, args
, const_args
);
1238 tcg_out_bc(s
, BC
| BI(7, CR_EQ
) | BO_COND_TRUE
, arg_label(args
[5]));
1241 void ppc_tb_set_jmp_target(uintptr_t jmp_addr
, uintptr_t addr
)
1243 tcg_insn_unit i1
, i2
;
1245 intptr_t diff
= addr
- jmp_addr
;
1247 if (in_range_b(diff
)) {
1248 i1
= B
| (diff
& 0x3fffffc);
1250 } else if (USE_REG_RA
) {
1252 diff
= addr
- (uintptr_t)tb_ret_addr
;
1254 hi
= (int32_t)(diff
- lo
);
1255 assert(diff
== hi
+ lo
);
1256 i1
= ADDIS
| TAI(TCG_REG_TMP1
, TCG_REG_RA
, hi
>> 16);
1257 i2
= ADDI
| TAI(TCG_REG_TMP1
, TCG_REG_TMP1
, lo
);
1259 assert(TCG_TARGET_REG_BITS
== 32 || addr
== (int32_t)addr
);
1260 i1
= ADDIS
| TAI(TCG_REG_TMP1
, 0, addr
>> 16);
1261 i2
= ORI
| SAI(TCG_REG_TMP1
, TCG_REG_TMP1
, addr
);
1263 #ifdef HOST_WORDS_BIGENDIAN
1264 pair
= (uint64_t)i1
<< 32 | i2
;
1266 pair
= (uint64_t)i2
<< 32 | i1
;
1269 /* ??? __atomic_store_8, presuming there's some way to do that
1270 for 32-bit, otherwise this is good enough for 64-bit. */
1271 *(uint64_t *)jmp_addr
= pair
;
1272 flush_icache_range(jmp_addr
, jmp_addr
+ 8);
1275 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*target
)
1278 /* Look through the descriptor. If the branch is in range, and we
1279 don't have to spend too much effort on building the toc. */
1280 void *tgt
= ((void **)target
)[0];
1281 uintptr_t toc
= ((uintptr_t *)target
)[1];
1282 intptr_t diff
= tcg_pcrel_diff(s
, tgt
);
1284 if (in_range_b(diff
) && toc
== (uint32_t)toc
) {
1285 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP1
, toc
);
1286 tcg_out_b(s
, LK
, tgt
);
1288 /* Fold the low bits of the constant into the addresses below. */
1289 intptr_t arg
= (intptr_t)target
;
1290 int ofs
= (int16_t)arg
;
1292 if (ofs
+ 8 < 0x8000) {
1297 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP1
, arg
);
1298 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_TMP1
, ofs
);
1299 tcg_out32(s
, MTSPR
| RA(TCG_REG_R0
) | CTR
);
1300 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R2
, TCG_REG_TMP1
, ofs
+ SZP
);
1301 tcg_out32(s
, BCCTR
| BO_ALWAYS
| LK
);
1303 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1306 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1307 address, which the callee uses to compute its TOC address. */
1308 /* FIXME: when the branch is in range, we could avoid r12 load if we
1309 knew that the destination uses the same TOC, and what its local
1310 entry point offset is. */
1311 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R12
, (intptr_t)target
);
1313 diff
= tcg_pcrel_diff(s
, target
);
1314 if (in_range_b(diff
)) {
1315 tcg_out_b(s
, LK
, target
);
1317 tcg_out32(s
, MTSPR
| RS(TCG_REG_R12
) | CTR
);
1318 tcg_out32(s
, BCCTR
| BO_ALWAYS
| LK
);
1321 tcg_out_b(s
, LK
, target
);
1325 static const uint32_t qemu_ldx_opc
[16] = {
1332 [MO_BSWAP
| MO_UB
] = LBZX
,
1333 [MO_BSWAP
| MO_UW
] = LHBRX
,
1334 [MO_BSWAP
| MO_UL
] = LWBRX
,
1335 [MO_BSWAP
| MO_Q
] = LDBRX
,
1338 static const uint32_t qemu_stx_opc
[16] = {
1343 [MO_BSWAP
| MO_UB
] = STBX
,
1344 [MO_BSWAP
| MO_UW
] = STHBRX
,
1345 [MO_BSWAP
| MO_UL
] = STWBRX
,
1346 [MO_BSWAP
| MO_Q
] = STDBRX
,
1349 static const uint32_t qemu_exts_opc
[4] = {
1350 EXTSB
, EXTSH
, EXTSW
, 0
1353 #if defined (CONFIG_SOFTMMU)
1354 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1355 * int mmu_idx, uintptr_t ra)
1357 static void * const qemu_ld_helpers
[16] = {
1358 [MO_UB
] = helper_ret_ldub_mmu
,
1359 [MO_LEUW
] = helper_le_lduw_mmu
,
1360 [MO_LEUL
] = helper_le_ldul_mmu
,
1361 [MO_LEQ
] = helper_le_ldq_mmu
,
1362 [MO_BEUW
] = helper_be_lduw_mmu
,
1363 [MO_BEUL
] = helper_be_ldul_mmu
,
1364 [MO_BEQ
] = helper_be_ldq_mmu
,
1367 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1368 * uintxx_t val, int mmu_idx, uintptr_t ra)
1370 static void * const qemu_st_helpers
[16] = {
1371 [MO_UB
] = helper_ret_stb_mmu
,
1372 [MO_LEUW
] = helper_le_stw_mmu
,
1373 [MO_LEUL
] = helper_le_stl_mmu
,
1374 [MO_LEQ
] = helper_le_stq_mmu
,
1375 [MO_BEUW
] = helper_be_stw_mmu
,
1376 [MO_BEUL
] = helper_be_stl_mmu
,
1377 [MO_BEQ
] = helper_be_stq_mmu
,
1380 /* Perform the TLB load and compare. Places the result of the comparison
1381 in CR7, loads the addend of the TLB into R3, and returns the register
1382 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1384 static TCGReg
tcg_out_tlb_read(TCGContext
*s
, TCGMemOp opc
,
1385 TCGReg addrlo
, TCGReg addrhi
,
1386 int mem_index
, bool is_read
)
1390 ? offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_read
)
1391 : offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_write
));
1392 int add_off
= offsetof(CPUArchState
, tlb_table
[mem_index
][0].addend
);
1393 TCGReg base
= TCG_AREG0
;
1394 TCGMemOp s_bits
= opc
& MO_SIZE
;
1396 /* Extract the page index, shifted into place for tlb index. */
1397 if (TCG_TARGET_REG_BITS
== 64) {
1398 if (TARGET_LONG_BITS
== 32) {
1399 /* Zero-extend the address into a place helpful for further use. */
1400 tcg_out_ext32u(s
, TCG_REG_R4
, addrlo
);
1401 addrlo
= TCG_REG_R4
;
1403 tcg_out_rld(s
, RLDICL
, TCG_REG_R3
, addrlo
,
1404 64 - TARGET_PAGE_BITS
, 64 - CPU_TLB_BITS
);
1408 /* Compensate for very large offsets. */
1409 if (add_off
>= 0x8000) {
1410 /* Most target env are smaller than 32k; none are larger than 64k.
1411 Simplify the logic here merely to offset by 0x7ff0, giving us a
1412 range just shy of 64k. Check this assumption. */
1413 QEMU_BUILD_BUG_ON(offsetof(CPUArchState
,
1414 tlb_table
[NB_MMU_MODES
- 1][1])
1416 tcg_out32(s
, ADDI
| TAI(TCG_REG_TMP1
, base
, 0x7ff0));
1417 base
= TCG_REG_TMP1
;
1422 /* Extraction and shifting, part 2. */
1423 if (TCG_TARGET_REG_BITS
== 32 || TARGET_LONG_BITS
== 32) {
1424 tcg_out_rlw(s
, RLWINM
, TCG_REG_R3
, addrlo
,
1425 32 - (TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
),
1426 32 - (CPU_TLB_BITS
+ CPU_TLB_ENTRY_BITS
),
1427 31 - CPU_TLB_ENTRY_BITS
);
1429 tcg_out_shli64(s
, TCG_REG_R3
, TCG_REG_R3
, CPU_TLB_ENTRY_BITS
);
1432 tcg_out32(s
, ADD
| TAB(TCG_REG_R3
, TCG_REG_R3
, base
));
1434 /* Load the tlb comparator. */
1435 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1436 tcg_out_ld(s
, TCG_TYPE_I32
, TCG_REG_R4
, TCG_REG_R3
, cmp_off
);
1437 tcg_out_ld(s
, TCG_TYPE_I32
, TCG_REG_TMP1
, TCG_REG_R3
, cmp_off
+ 4);
1439 tcg_out_ld(s
, TCG_TYPE_TL
, TCG_REG_TMP1
, TCG_REG_R3
, cmp_off
);
1442 /* Load the TLB addend for use on the fast path. Do this asap
1443 to minimize any load use delay. */
1444 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R3
, TCG_REG_R3
, add_off
);
1446 /* Clear the non-page, non-alignment bits from the address */
1447 if (TCG_TARGET_REG_BITS
== 32 || TARGET_LONG_BITS
== 32) {
1448 /* We don't support unaligned accesses on 32-bits, preserve
1449 * the bottom bits and thus trigger a comparison failure on
1450 * unaligned accesses
1452 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, addrlo
, 0,
1453 (32 - s_bits
) & 31, 31 - TARGET_PAGE_BITS
);
1454 } else if (s_bits
) {
1455 /* > byte access, we need to handle alignment */
1456 if ((opc
& MO_AMASK
) == MO_ALIGN
) {
1457 /* Alignment required by the front-end, same as 32-bits */
1458 tcg_out_rld(s
, RLDICL
, TCG_REG_R0
, addrlo
,
1459 64 - TARGET_PAGE_BITS
, TARGET_PAGE_BITS
- s_bits
);
1460 tcg_out_rld(s
, RLDICL
, TCG_REG_R0
, TCG_REG_R0
, TARGET_PAGE_BITS
, 0);
1462 /* We support unaligned accesses, we need to make sure we fail
1463 * if we cross a page boundary. The trick is to add the
1464 * access_size-1 to the address before masking the low bits.
1465 * That will make the address overflow to the next page if we
1466 * cross a page boundary which will then force a mismatch of
1467 * the TLB compare since the next page cannot possibly be in
1468 * the same TLB index.
1470 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, (1 << s_bits
) - 1));
1471 tcg_out_rld(s
, RLDICR
, TCG_REG_R0
, TCG_REG_R0
,
1472 0, 63 - TARGET_PAGE_BITS
);
1475 /* Byte access, just chop off the bits below the page index */
1476 tcg_out_rld(s
, RLDICR
, TCG_REG_R0
, addrlo
, 0, 63 - TARGET_PAGE_BITS
);
1479 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1480 tcg_out_cmp(s
, TCG_COND_EQ
, TCG_REG_R0
, TCG_REG_TMP1
,
1481 0, 7, TCG_TYPE_I32
);
1482 tcg_out_cmp(s
, TCG_COND_EQ
, addrhi
, TCG_REG_R4
, 0, 6, TCG_TYPE_I32
);
1483 tcg_out32(s
, CRAND
| BT(7, CR_EQ
) | BA(6, CR_EQ
) | BB(7, CR_EQ
));
1485 tcg_out_cmp(s
, TCG_COND_EQ
, TCG_REG_R0
, TCG_REG_TMP1
,
1492 /* Record the context of a call to the out of line helper code for the slow
1493 path for a load or store, so that we can later generate the correct
1495 static void add_qemu_ldst_label(TCGContext
*s
, bool is_ld
, TCGMemOpIdx oi
,
1496 TCGReg datalo_reg
, TCGReg datahi_reg
,
1497 TCGReg addrlo_reg
, TCGReg addrhi_reg
,
1498 tcg_insn_unit
*raddr
, tcg_insn_unit
*lptr
)
1500 TCGLabelQemuLdst
*label
= new_ldst_label(s
);
1502 label
->is_ld
= is_ld
;
1504 label
->datalo_reg
= datalo_reg
;
1505 label
->datahi_reg
= datahi_reg
;
1506 label
->addrlo_reg
= addrlo_reg
;
1507 label
->addrhi_reg
= addrhi_reg
;
1508 label
->raddr
= raddr
;
1509 label
->label_ptr
[0] = lptr
;
1512 static void tcg_out_qemu_ld_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1514 TCGMemOpIdx oi
= lb
->oi
;
1515 TCGMemOp opc
= get_memop(oi
);
1516 TCGReg hi
, lo
, arg
= TCG_REG_R3
;
1518 reloc_pc14(lb
->label_ptr
[0], s
->code_ptr
);
1520 tcg_out_mov(s
, TCG_TYPE_PTR
, arg
++, TCG_AREG0
);
1522 lo
= lb
->addrlo_reg
;
1523 hi
= lb
->addrhi_reg
;
1524 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1525 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1528 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1529 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1531 /* If the address needed to be zero-extended, we'll have already
1532 placed it in R4. The only remaining case is 64-bit guest. */
1533 tcg_out_mov(s
, TCG_TYPE_TL
, arg
++, lo
);
1536 tcg_out_movi(s
, TCG_TYPE_I32
, arg
++, oi
);
1537 tcg_out32(s
, MFSPR
| RT(arg
) | LR
);
1539 tcg_out_call(s
, qemu_ld_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)]);
1541 lo
= lb
->datalo_reg
;
1542 hi
= lb
->datahi_reg
;
1543 if (TCG_TARGET_REG_BITS
== 32 && (opc
& MO_SIZE
) == MO_64
) {
1544 tcg_out_mov(s
, TCG_TYPE_I32
, lo
, TCG_REG_R4
);
1545 tcg_out_mov(s
, TCG_TYPE_I32
, hi
, TCG_REG_R3
);
1546 } else if (opc
& MO_SIGN
) {
1547 uint32_t insn
= qemu_exts_opc
[opc
& MO_SIZE
];
1548 tcg_out32(s
, insn
| RA(lo
) | RS(TCG_REG_R3
));
1550 tcg_out_mov(s
, TCG_TYPE_REG
, lo
, TCG_REG_R3
);
1553 tcg_out_b(s
, 0, lb
->raddr
);
1556 static void tcg_out_qemu_st_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1558 TCGMemOpIdx oi
= lb
->oi
;
1559 TCGMemOp opc
= get_memop(oi
);
1560 TCGMemOp s_bits
= opc
& MO_SIZE
;
1561 TCGReg hi
, lo
, arg
= TCG_REG_R3
;
1563 reloc_pc14(lb
->label_ptr
[0], s
->code_ptr
);
1565 tcg_out_mov(s
, TCG_TYPE_PTR
, arg
++, TCG_AREG0
);
1567 lo
= lb
->addrlo_reg
;
1568 hi
= lb
->addrhi_reg
;
1569 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1570 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1573 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1574 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1576 /* If the address needed to be zero-extended, we'll have already
1577 placed it in R4. The only remaining case is 64-bit guest. */
1578 tcg_out_mov(s
, TCG_TYPE_TL
, arg
++, lo
);
1581 lo
= lb
->datalo_reg
;
1582 hi
= lb
->datahi_reg
;
1583 if (TCG_TARGET_REG_BITS
== 32) {
1586 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1589 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, hi
);
1592 tcg_out_mov(s
, TCG_TYPE_I32
, arg
++, lo
);
1595 tcg_out_rlw(s
, RLWINM
, arg
++, lo
, 0, 32 - (8 << s_bits
), 31);
1599 if (s_bits
== MO_64
) {
1600 tcg_out_mov(s
, TCG_TYPE_I64
, arg
++, lo
);
1602 tcg_out_rld(s
, RLDICL
, arg
++, lo
, 0, 64 - (8 << s_bits
));
1606 tcg_out_movi(s
, TCG_TYPE_I32
, arg
++, oi
);
1607 tcg_out32(s
, MFSPR
| RT(arg
) | LR
);
1609 tcg_out_call(s
, qemu_st_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)]);
1611 tcg_out_b(s
, 0, lb
->raddr
);
1613 #endif /* SOFTMMU */
1615 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, bool is_64
)
1617 TCGReg datalo
, datahi
, addrlo
, rbase
;
1618 TCGReg addrhi
__attribute__((unused
));
1620 TCGMemOp opc
, s_bits
;
1621 #ifdef CONFIG_SOFTMMU
1623 tcg_insn_unit
*label_ptr
;
1627 datahi
= (TCG_TARGET_REG_BITS
== 32 && is_64
? *args
++ : 0);
1629 addrhi
= (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
? *args
++ : 0);
1631 opc
= get_memop(oi
);
1632 s_bits
= opc
& MO_SIZE
;
1634 #ifdef CONFIG_SOFTMMU
1635 mem_index
= get_mmuidx(oi
);
1636 addrlo
= tcg_out_tlb_read(s
, opc
, addrlo
, addrhi
, mem_index
, true);
1638 /* Load a pointer into the current opcode w/conditional branch-link. */
1639 label_ptr
= s
->code_ptr
;
1640 tcg_out_bc_noaddr(s
, BC
| BI(7, CR_EQ
) | BO_COND_FALSE
| LK
);
1643 #else /* !CONFIG_SOFTMMU */
1644 rbase
= guest_base
? TCG_GUEST_BASE_REG
: 0;
1645 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1646 tcg_out_ext32u(s
, TCG_REG_TMP1
, addrlo
);
1647 addrlo
= TCG_REG_TMP1
;
1651 if (TCG_TARGET_REG_BITS
== 32 && s_bits
== MO_64
) {
1652 if (opc
& MO_BSWAP
) {
1653 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1654 tcg_out32(s
, LWBRX
| TAB(datalo
, rbase
, addrlo
));
1655 tcg_out32(s
, LWBRX
| TAB(datahi
, rbase
, TCG_REG_R0
));
1656 } else if (rbase
!= 0) {
1657 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1658 tcg_out32(s
, LWZX
| TAB(datahi
, rbase
, addrlo
));
1659 tcg_out32(s
, LWZX
| TAB(datalo
, rbase
, TCG_REG_R0
));
1660 } else if (addrlo
== datahi
) {
1661 tcg_out32(s
, LWZ
| TAI(datalo
, addrlo
, 4));
1662 tcg_out32(s
, LWZ
| TAI(datahi
, addrlo
, 0));
1664 tcg_out32(s
, LWZ
| TAI(datahi
, addrlo
, 0));
1665 tcg_out32(s
, LWZ
| TAI(datalo
, addrlo
, 4));
1668 uint32_t insn
= qemu_ldx_opc
[opc
& (MO_BSWAP
| MO_SSIZE
)];
1669 if (!HAVE_ISA_2_06
&& insn
== LDBRX
) {
1670 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1671 tcg_out32(s
, LWBRX
| TAB(datalo
, rbase
, addrlo
));
1672 tcg_out32(s
, LWBRX
| TAB(TCG_REG_R0
, rbase
, TCG_REG_R0
));
1673 tcg_out_rld(s
, RLDIMI
, datalo
, TCG_REG_R0
, 32, 0);
1675 tcg_out32(s
, insn
| TAB(datalo
, rbase
, addrlo
));
1677 insn
= qemu_ldx_opc
[opc
& (MO_SIZE
| MO_BSWAP
)];
1678 tcg_out32(s
, insn
| TAB(datalo
, rbase
, addrlo
));
1679 insn
= qemu_exts_opc
[s_bits
];
1680 tcg_out32(s
, insn
| RA(datalo
) | RS(datalo
));
1684 #ifdef CONFIG_SOFTMMU
1685 add_qemu_ldst_label(s
, true, oi
, datalo
, datahi
, addrlo
, addrhi
,
1686 s
->code_ptr
, label_ptr
);
1690 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, bool is_64
)
1692 TCGReg datalo
, datahi
, addrlo
, rbase
;
1693 TCGReg addrhi
__attribute__((unused
));
1695 TCGMemOp opc
, s_bits
;
1696 #ifdef CONFIG_SOFTMMU
1698 tcg_insn_unit
*label_ptr
;
1702 datahi
= (TCG_TARGET_REG_BITS
== 32 && is_64
? *args
++ : 0);
1704 addrhi
= (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
? *args
++ : 0);
1706 opc
= get_memop(oi
);
1707 s_bits
= opc
& MO_SIZE
;
1709 #ifdef CONFIG_SOFTMMU
1710 mem_index
= get_mmuidx(oi
);
1711 addrlo
= tcg_out_tlb_read(s
, opc
, addrlo
, addrhi
, mem_index
, false);
1713 /* Load a pointer into the current opcode w/conditional branch-link. */
1714 label_ptr
= s
->code_ptr
;
1715 tcg_out_bc_noaddr(s
, BC
| BI(7, CR_EQ
) | BO_COND_FALSE
| LK
);
1718 #else /* !CONFIG_SOFTMMU */
1719 rbase
= guest_base
? TCG_GUEST_BASE_REG
: 0;
1720 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1721 tcg_out_ext32u(s
, TCG_REG_TMP1
, addrlo
);
1722 addrlo
= TCG_REG_TMP1
;
1726 if (TCG_TARGET_REG_BITS
== 32 && s_bits
== MO_64
) {
1727 if (opc
& MO_BSWAP
) {
1728 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1729 tcg_out32(s
, STWBRX
| SAB(datalo
, rbase
, addrlo
));
1730 tcg_out32(s
, STWBRX
| SAB(datahi
, rbase
, TCG_REG_R0
));
1731 } else if (rbase
!= 0) {
1732 tcg_out32(s
, ADDI
| TAI(TCG_REG_R0
, addrlo
, 4));
1733 tcg_out32(s
, STWX
| SAB(datahi
, rbase
, addrlo
));
1734 tcg_out32(s
, STWX
| SAB(datalo
, rbase
, TCG_REG_R0
));
1736 tcg_out32(s
, STW
| TAI(datahi
, addrlo
, 0));
1737 tcg_out32(s
, STW
| TAI(datalo
, addrlo
, 4));
1740 uint32_t insn
= qemu_stx_opc
[opc
& (MO_BSWAP
| MO_SIZE
)];
1741 if (!HAVE_ISA_2_06
&& insn
== STDBRX
) {
1742 tcg_out32(s
, STWBRX
| SAB(datalo
, rbase
, addrlo
));
1743 tcg_out32(s
, ADDI
| TAI(TCG_REG_TMP1
, addrlo
, 4));
1744 tcg_out_shri64(s
, TCG_REG_R0
, datalo
, 32);
1745 tcg_out32(s
, STWBRX
| SAB(TCG_REG_R0
, rbase
, TCG_REG_TMP1
));
1747 tcg_out32(s
, insn
| SAB(datalo
, rbase
, addrlo
));
1751 #ifdef CONFIG_SOFTMMU
1752 add_qemu_ldst_label(s
, false, oi
, datalo
, datahi
, addrlo
, addrhi
,
1753 s
->code_ptr
, label_ptr
);
1757 /* Parameters for function call generation, used in tcg.c. */
1758 #define TCG_TARGET_STACK_ALIGN 16
1759 #define TCG_TARGET_EXTEND_ARGS 1
1762 # define LINK_AREA_SIZE (6 * SZR)
1763 # define LR_OFFSET (1 * SZR)
1764 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1765 #elif defined(TCG_TARGET_CALL_DARWIN)
1766 # define LINK_AREA_SIZE (6 * SZR)
1767 # define LR_OFFSET (2 * SZR)
1768 #elif TCG_TARGET_REG_BITS == 64
1769 # if defined(_CALL_ELF) && _CALL_ELF == 2
1770 # define LINK_AREA_SIZE (4 * SZR)
1771 # define LR_OFFSET (1 * SZR)
1773 #else /* TCG_TARGET_REG_BITS == 32 */
1774 # if defined(_CALL_SYSV)
1775 # define LINK_AREA_SIZE (2 * SZR)
1776 # define LR_OFFSET (1 * SZR)
1780 # error "Unhandled abi"
1782 #ifndef TCG_TARGET_CALL_STACK_OFFSET
1783 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1786 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1787 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1789 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1790 + TCG_STATIC_CALL_ARGS_SIZE \
1791 + CPU_TEMP_BUF_SIZE \
1793 + TCG_TARGET_STACK_ALIGN - 1) \
1794 & -TCG_TARGET_STACK_ALIGN)
1796 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1798 static void tcg_target_qemu_prologue(TCGContext
*s
)
1803 void **desc
= (void **)s
->code_ptr
;
1804 desc
[0] = desc
+ 2; /* entry point */
1805 desc
[1] = 0; /* environment pointer */
1806 s
->code_ptr
= (void *)(desc
+ 2); /* skip over descriptor */
1809 tcg_set_frame(s
, TCG_REG_CALL_STACK
, REG_SAVE_BOT
- CPU_TEMP_BUF_SIZE
,
1813 tcg_out32(s
, MFSPR
| RT(TCG_REG_R0
) | LR
);
1814 tcg_out32(s
, (SZR
== 8 ? STDU
: STWU
)
1815 | SAI(TCG_REG_R1
, TCG_REG_R1
, -FRAME_SIZE
));
1817 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
) {
1818 tcg_out_st(s
, TCG_TYPE_REG
, tcg_target_callee_save_regs
[i
],
1819 TCG_REG_R1
, REG_SAVE_BOT
+ i
* SZR
);
1821 tcg_out_st(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_R1
, FRAME_SIZE
+LR_OFFSET
);
1823 #ifndef CONFIG_SOFTMMU
1825 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_GUEST_BASE_REG
, guest_base
);
1826 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
1830 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
1831 tcg_out32(s
, MTSPR
| RS(tcg_target_call_iarg_regs
[1]) | CTR
);
1835 /* Make the caller load the value as the TOC into R2. */
1836 tb_ret_addr
= s
->code_ptr
+ 2;
1837 desc
[1] = tb_ret_addr
;
1838 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_REG_RA
, TCG_REG_R2
);
1839 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
1840 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1841 /* Compute from the incoming R12 value. */
1842 tb_ret_addr
= s
->code_ptr
+ 2;
1843 tcg_out32(s
, ADDI
| TAI(TCG_REG_RA
, TCG_REG_R12
,
1844 tcg_ptr_byte_diff(tb_ret_addr
, s
->code_buf
)));
1845 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
1847 /* Reserve max 5 insns for the constant load. */
1848 tb_ret_addr
= s
->code_ptr
+ 6;
1849 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_RA
, (intptr_t)tb_ret_addr
);
1850 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
1851 while (s
->code_ptr
< tb_ret_addr
) {
1856 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
1857 tb_ret_addr
= s
->code_ptr
;
1861 assert(tb_ret_addr
== s
->code_ptr
);
1863 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_REG_R0
, TCG_REG_R1
, FRAME_SIZE
+LR_OFFSET
);
1864 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
) {
1865 tcg_out_ld(s
, TCG_TYPE_REG
, tcg_target_callee_save_regs
[i
],
1866 TCG_REG_R1
, REG_SAVE_BOT
+ i
* SZR
);
1868 tcg_out32(s
, MTSPR
| RS(TCG_REG_R0
) | LR
);
1869 tcg_out32(s
, ADDI
| TAI(TCG_REG_R1
, TCG_REG_R1
, FRAME_SIZE
));
1870 tcg_out32(s
, BCLR
| BO_ALWAYS
);
1873 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
1874 const int *const_args
)
1880 case INDEX_op_exit_tb
:
1882 ptrdiff_t disp
= tcg_pcrel_diff(s
, tb_ret_addr
);
1884 /* Use a direct branch if we can, otherwise use the value in RA.
1885 Note that the direct branch is always backward, thus we need
1886 to account for the possibility of 5 insns from the movi. */
1887 if (!in_range_b(disp
- 20)) {
1888 tcg_out32(s
, MTSPR
| RS(TCG_REG_RA
) | CTR
);
1889 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R3
, args
[0]);
1890 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
1894 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R3
, args
[0]);
1895 tcg_out_b(s
, 0, tb_ret_addr
);
1897 case INDEX_op_goto_tb
:
1898 tcg_debug_assert(s
->tb_jmp_offset
);
1899 /* Direct jump. Ensure the next insns are 8-byte aligned. */
1900 if ((uintptr_t)s
->code_ptr
& 7) {
1903 s
->tb_jmp_offset
[args
[0]] = tcg_current_code_size(s
);
1904 /* To be replaced by either a branch+nop or a load into TMP1. */
1906 tcg_out32(s
, MTSPR
| RS(TCG_REG_TMP1
) | CTR
);
1907 tcg_out32(s
, BCCTR
| BO_ALWAYS
);
1908 s
->tb_next_offset
[args
[0]] = tcg_current_code_size(s
);
1912 TCGLabel
*l
= arg_label(args
[0]);
1915 tcg_out_b(s
, 0, l
->u
.value_ptr
);
1917 tcg_out_reloc(s
, s
->code_ptr
, R_PPC_REL24
, l
, 0);
1918 tcg_out_b_noaddr(s
, B
);
1922 case INDEX_op_ld8u_i32
:
1923 case INDEX_op_ld8u_i64
:
1924 tcg_out_mem_long(s
, LBZ
, LBZX
, args
[0], args
[1], args
[2]);
1926 case INDEX_op_ld8s_i32
:
1927 case INDEX_op_ld8s_i64
:
1928 tcg_out_mem_long(s
, LBZ
, LBZX
, args
[0], args
[1], args
[2]);
1929 tcg_out32(s
, EXTSB
| RS(args
[0]) | RA(args
[0]));
1931 case INDEX_op_ld16u_i32
:
1932 case INDEX_op_ld16u_i64
:
1933 tcg_out_mem_long(s
, LHZ
, LHZX
, args
[0], args
[1], args
[2]);
1935 case INDEX_op_ld16s_i32
:
1936 case INDEX_op_ld16s_i64
:
1937 tcg_out_mem_long(s
, LHA
, LHAX
, args
[0], args
[1], args
[2]);
1939 case INDEX_op_ld_i32
:
1940 case INDEX_op_ld32u_i64
:
1941 tcg_out_mem_long(s
, LWZ
, LWZX
, args
[0], args
[1], args
[2]);
1943 case INDEX_op_ld32s_i64
:
1944 tcg_out_mem_long(s
, LWA
, LWAX
, args
[0], args
[1], args
[2]);
1946 case INDEX_op_ld_i64
:
1947 tcg_out_mem_long(s
, LD
, LDX
, args
[0], args
[1], args
[2]);
1949 case INDEX_op_st8_i32
:
1950 case INDEX_op_st8_i64
:
1951 tcg_out_mem_long(s
, STB
, STBX
, args
[0], args
[1], args
[2]);
1953 case INDEX_op_st16_i32
:
1954 case INDEX_op_st16_i64
:
1955 tcg_out_mem_long(s
, STH
, STHX
, args
[0], args
[1], args
[2]);
1957 case INDEX_op_st_i32
:
1958 case INDEX_op_st32_i64
:
1959 tcg_out_mem_long(s
, STW
, STWX
, args
[0], args
[1], args
[2]);
1961 case INDEX_op_st_i64
:
1962 tcg_out_mem_long(s
, STD
, STDX
, args
[0], args
[1], args
[2]);
1965 case INDEX_op_add_i32
:
1966 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1967 if (const_args
[2]) {
1969 tcg_out_mem_long(s
, ADDI
, ADD
, a0
, a1
, (int32_t)a2
);
1971 tcg_out32(s
, ADD
| TAB(a0
, a1
, a2
));
1974 case INDEX_op_sub_i32
:
1975 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1976 if (const_args
[1]) {
1977 if (const_args
[2]) {
1978 tcg_out_movi(s
, TCG_TYPE_I32
, a0
, a1
- a2
);
1980 tcg_out32(s
, SUBFIC
| TAI(a0
, a2
, a1
));
1982 } else if (const_args
[2]) {
1986 tcg_out32(s
, SUBF
| TAB(a0
, a2
, a1
));
1990 case INDEX_op_and_i32
:
1991 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1992 if (const_args
[2]) {
1993 tcg_out_andi32(s
, a0
, a1
, a2
);
1995 tcg_out32(s
, AND
| SAB(a1
, a0
, a2
));
1998 case INDEX_op_and_i64
:
1999 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2000 if (const_args
[2]) {
2001 tcg_out_andi64(s
, a0
, a1
, a2
);
2003 tcg_out32(s
, AND
| SAB(a1
, a0
, a2
));
2006 case INDEX_op_or_i64
:
2007 case INDEX_op_or_i32
:
2008 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2009 if (const_args
[2]) {
2010 tcg_out_ori32(s
, a0
, a1
, a2
);
2012 tcg_out32(s
, OR
| SAB(a1
, a0
, a2
));
2015 case INDEX_op_xor_i64
:
2016 case INDEX_op_xor_i32
:
2017 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2018 if (const_args
[2]) {
2019 tcg_out_xori32(s
, a0
, a1
, a2
);
2021 tcg_out32(s
, XOR
| SAB(a1
, a0
, a2
));
2024 case INDEX_op_andc_i32
:
2025 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2026 if (const_args
[2]) {
2027 tcg_out_andi32(s
, a0
, a1
, ~a2
);
2029 tcg_out32(s
, ANDC
| SAB(a1
, a0
, a2
));
2032 case INDEX_op_andc_i64
:
2033 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2034 if (const_args
[2]) {
2035 tcg_out_andi64(s
, a0
, a1
, ~a2
);
2037 tcg_out32(s
, ANDC
| SAB(a1
, a0
, a2
));
2040 case INDEX_op_orc_i32
:
2041 if (const_args
[2]) {
2042 tcg_out_ori32(s
, args
[0], args
[1], ~args
[2]);
2046 case INDEX_op_orc_i64
:
2047 tcg_out32(s
, ORC
| SAB(args
[1], args
[0], args
[2]));
2049 case INDEX_op_eqv_i32
:
2050 if (const_args
[2]) {
2051 tcg_out_xori32(s
, args
[0], args
[1], ~args
[2]);
2055 case INDEX_op_eqv_i64
:
2056 tcg_out32(s
, EQV
| SAB(args
[1], args
[0], args
[2]));
2058 case INDEX_op_nand_i32
:
2059 case INDEX_op_nand_i64
:
2060 tcg_out32(s
, NAND
| SAB(args
[1], args
[0], args
[2]));
2062 case INDEX_op_nor_i32
:
2063 case INDEX_op_nor_i64
:
2064 tcg_out32(s
, NOR
| SAB(args
[1], args
[0], args
[2]));
2067 case INDEX_op_mul_i32
:
2068 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2069 if (const_args
[2]) {
2070 tcg_out32(s
, MULLI
| TAI(a0
, a1
, a2
));
2072 tcg_out32(s
, MULLW
| TAB(a0
, a1
, a2
));
2076 case INDEX_op_div_i32
:
2077 tcg_out32(s
, DIVW
| TAB(args
[0], args
[1], args
[2]));
2080 case INDEX_op_divu_i32
:
2081 tcg_out32(s
, DIVWU
| TAB(args
[0], args
[1], args
[2]));
2084 case INDEX_op_shl_i32
:
2085 if (const_args
[2]) {
2086 tcg_out_shli32(s
, args
[0], args
[1], args
[2]);
2088 tcg_out32(s
, SLW
| SAB(args
[1], args
[0], args
[2]));
2091 case INDEX_op_shr_i32
:
2092 if (const_args
[2]) {
2093 tcg_out_shri32(s
, args
[0], args
[1], args
[2]);
2095 tcg_out32(s
, SRW
| SAB(args
[1], args
[0], args
[2]));
2098 case INDEX_op_sar_i32
:
2099 if (const_args
[2]) {
2100 tcg_out32(s
, SRAWI
| RS(args
[1]) | RA(args
[0]) | SH(args
[2]));
2102 tcg_out32(s
, SRAW
| SAB(args
[1], args
[0], args
[2]));
2105 case INDEX_op_rotl_i32
:
2106 if (const_args
[2]) {
2107 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], args
[2], 0, 31);
2109 tcg_out32(s
, RLWNM
| SAB(args
[1], args
[0], args
[2])
2113 case INDEX_op_rotr_i32
:
2114 if (const_args
[2]) {
2115 tcg_out_rlw(s
, RLWINM
, args
[0], args
[1], 32 - args
[2], 0, 31);
2117 tcg_out32(s
, SUBFIC
| TAI(TCG_REG_R0
, args
[2], 32));
2118 tcg_out32(s
, RLWNM
| SAB(args
[1], args
[0], TCG_REG_R0
)
2123 case INDEX_op_brcond_i32
:
2124 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
2125 arg_label(args
[3]), TCG_TYPE_I32
);
2127 case INDEX_op_brcond_i64
:
2128 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
2129 arg_label(args
[3]), TCG_TYPE_I64
);
2131 case INDEX_op_brcond2_i32
:
2132 tcg_out_brcond2(s
, args
, const_args
);
2135 case INDEX_op_neg_i32
:
2136 case INDEX_op_neg_i64
:
2137 tcg_out32(s
, NEG
| RT(args
[0]) | RA(args
[1]));
2140 case INDEX_op_not_i32
:
2141 case INDEX_op_not_i64
:
2142 tcg_out32(s
, NOR
| SAB(args
[1], args
[0], args
[1]));
2145 case INDEX_op_add_i64
:
2146 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2147 if (const_args
[2]) {
2149 tcg_out_mem_long(s
, ADDI
, ADD
, a0
, a1
, a2
);
2151 tcg_out32(s
, ADD
| TAB(a0
, a1
, a2
));
2154 case INDEX_op_sub_i64
:
2155 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2156 if (const_args
[1]) {
2157 if (const_args
[2]) {
2158 tcg_out_movi(s
, TCG_TYPE_I64
, a0
, a1
- a2
);
2160 tcg_out32(s
, SUBFIC
| TAI(a0
, a2
, a1
));
2162 } else if (const_args
[2]) {
2166 tcg_out32(s
, SUBF
| TAB(a0
, a2
, a1
));
2170 case INDEX_op_shl_i64
:
2171 if (const_args
[2]) {
2172 tcg_out_shli64(s
, args
[0], args
[1], args
[2]);
2174 tcg_out32(s
, SLD
| SAB(args
[1], args
[0], args
[2]));
2177 case INDEX_op_shr_i64
:
2178 if (const_args
[2]) {
2179 tcg_out_shri64(s
, args
[0], args
[1], args
[2]);
2181 tcg_out32(s
, SRD
| SAB(args
[1], args
[0], args
[2]));
2184 case INDEX_op_sar_i64
:
2185 if (const_args
[2]) {
2186 int sh
= SH(args
[2] & 0x1f) | (((args
[2] >> 5) & 1) << 1);
2187 tcg_out32(s
, SRADI
| RA(args
[0]) | RS(args
[1]) | sh
);
2189 tcg_out32(s
, SRAD
| SAB(args
[1], args
[0], args
[2]));
2192 case INDEX_op_rotl_i64
:
2193 if (const_args
[2]) {
2194 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], args
[2], 0);
2196 tcg_out32(s
, RLDCL
| SAB(args
[1], args
[0], args
[2]) | MB64(0));
2199 case INDEX_op_rotr_i64
:
2200 if (const_args
[2]) {
2201 tcg_out_rld(s
, RLDICL
, args
[0], args
[1], 64 - args
[2], 0);
2203 tcg_out32(s
, SUBFIC
| TAI(TCG_REG_R0
, args
[2], 64));
2204 tcg_out32(s
, RLDCL
| SAB(args
[1], args
[0], TCG_REG_R0
) | MB64(0));
2208 case INDEX_op_mul_i64
:
2209 a0
= args
[0], a1
= args
[1], a2
= args
[2];
2210 if (const_args
[2]) {
2211 tcg_out32(s
, MULLI
| TAI(a0
, a1
, a2
));
2213 tcg_out32(s
, MULLD
| TAB(a0
, a1
, a2
));
2216 case INDEX_op_div_i64
:
2217 tcg_out32(s
, DIVD
| TAB(args
[0], args
[1], args
[2]));
2219 case INDEX_op_divu_i64
:
2220 tcg_out32(s
, DIVDU
| TAB(args
[0], args
[1], args
[2]));
2223 case INDEX_op_qemu_ld_i32
:
2224 tcg_out_qemu_ld(s
, args
, false);
2226 case INDEX_op_qemu_ld_i64
:
2227 tcg_out_qemu_ld(s
, args
, true);
2229 case INDEX_op_qemu_st_i32
:
2230 tcg_out_qemu_st(s
, args
, false);
2232 case INDEX_op_qemu_st_i64
:
2233 tcg_out_qemu_st(s
, args
, true);
2236 case INDEX_op_ext8s_i32
:
2237 case INDEX_op_ext8s_i64
:
2240 case INDEX_op_ext16s_i32
:
2241 case INDEX_op_ext16s_i64
:
2244 case INDEX_op_ext_i32_i64
:
2245 case INDEX_op_ext32s_i64
:
2249 tcg_out32(s
, c
| RS(args
[1]) | RA(args
[0]));
2251 case INDEX_op_extu_i32_i64
:
2252 tcg_out_ext32u(s
, args
[0], args
[1]);
2255 case INDEX_op_setcond_i32
:
2256 tcg_out_setcond(s
, TCG_TYPE_I32
, args
[3], args
[0], args
[1], args
[2],
2259 case INDEX_op_setcond_i64
:
2260 tcg_out_setcond(s
, TCG_TYPE_I64
, args
[3], args
[0], args
[1], args
[2],
2263 case INDEX_op_setcond2_i32
:
2264 tcg_out_setcond2(s
, args
, const_args
);
2267 case INDEX_op_bswap16_i32
:
2268 case INDEX_op_bswap16_i64
:
2269 a0
= args
[0], a1
= args
[1];
2272 /* a0 = (a1 r<< 24) & 0xff # 000c */
2273 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 24, 24, 31);
2274 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2275 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 8, 16, 23);
2277 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2278 tcg_out_rlw(s
, RLWINM
, TCG_REG_R0
, a1
, 8, 16, 23);
2279 /* a0 = (a1 r<< 24) & 0xff # 000c */
2280 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 24, 24, 31);
2281 /* a0 = a0 | r0 # 00dc */
2282 tcg_out32(s
, OR
| SAB(TCG_REG_R0
, a0
, a0
));
2286 case INDEX_op_bswap32_i32
:
2287 case INDEX_op_bswap32_i64
:
2288 /* Stolen from gcc's builtin_bswap32 */
2290 a0
= args
[0] == a1
? TCG_REG_R0
: args
[0];
2292 /* a1 = args[1] # abcd */
2293 /* a0 = rotate_left (a1, 8) # bcda */
2294 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 8, 0, 31);
2295 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2296 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 0, 7);
2297 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2298 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 16, 23);
2300 if (a0
== TCG_REG_R0
) {
2301 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2305 case INDEX_op_bswap64_i64
:
2306 a0
= args
[0], a1
= args
[1], a2
= TCG_REG_R0
;
2312 /* a1 = # abcd efgh */
2313 /* a0 = rl32(a1, 8) # 0000 fghe */
2314 tcg_out_rlw(s
, RLWINM
, a0
, a1
, 8, 0, 31);
2315 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2316 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 0, 7);
2317 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2318 tcg_out_rlw(s
, RLWIMI
, a0
, a1
, 24, 16, 23);
2320 /* a0 = rl64(a0, 32) # hgfe 0000 */
2321 /* a2 = rl64(a1, 32) # efgh abcd */
2322 tcg_out_rld(s
, RLDICL
, a0
, a0
, 32, 0);
2323 tcg_out_rld(s
, RLDICL
, a2
, a1
, 32, 0);
2325 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2326 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 8, 0, 31);
2327 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2328 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 24, 0, 7);
2329 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2330 tcg_out_rlw(s
, RLWIMI
, a0
, a2
, 24, 16, 23);
2333 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2337 case INDEX_op_deposit_i32
:
2338 if (const_args
[2]) {
2339 uint32_t mask
= ((2u << (args
[4] - 1)) - 1) << args
[3];
2340 tcg_out_andi32(s
, args
[0], args
[0], ~mask
);
2342 tcg_out_rlw(s
, RLWIMI
, args
[0], args
[2], args
[3],
2343 32 - args
[3] - args
[4], 31 - args
[3]);
2346 case INDEX_op_deposit_i64
:
2347 if (const_args
[2]) {
2348 uint64_t mask
= ((2ull << (args
[4] - 1)) - 1) << args
[3];
2349 tcg_out_andi64(s
, args
[0], args
[0], ~mask
);
2351 tcg_out_rld(s
, RLDIMI
, args
[0], args
[2], args
[3],
2352 64 - args
[3] - args
[4]);
2356 case INDEX_op_movcond_i32
:
2357 tcg_out_movcond(s
, TCG_TYPE_I32
, args
[5], args
[0], args
[1], args
[2],
2358 args
[3], args
[4], const_args
[2]);
2360 case INDEX_op_movcond_i64
:
2361 tcg_out_movcond(s
, TCG_TYPE_I64
, args
[5], args
[0], args
[1], args
[2],
2362 args
[3], args
[4], const_args
[2]);
2365 #if TCG_TARGET_REG_BITS == 64
2366 case INDEX_op_add2_i64
:
2368 case INDEX_op_add2_i32
:
2370 /* Note that the CA bit is defined based on the word size of the
2371 environment. So in 64-bit mode it's always carry-out of bit 63.
2372 The fallback code using deposit works just as well for 32-bit. */
2373 a0
= args
[0], a1
= args
[1];
2374 if (a0
== args
[3] || (!const_args
[5] && a0
== args
[5])) {
2377 if (const_args
[4]) {
2378 tcg_out32(s
, ADDIC
| TAI(a0
, args
[2], args
[4]));
2380 tcg_out32(s
, ADDC
| TAB(a0
, args
[2], args
[4]));
2382 if (const_args
[5]) {
2383 tcg_out32(s
, (args
[5] ? ADDME
: ADDZE
) | RT(a1
) | RA(args
[3]));
2385 tcg_out32(s
, ADDE
| TAB(a1
, args
[3], args
[5]));
2387 if (a0
!= args
[0]) {
2388 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2392 #if TCG_TARGET_REG_BITS == 64
2393 case INDEX_op_sub2_i64
:
2395 case INDEX_op_sub2_i32
:
2397 a0
= args
[0], a1
= args
[1];
2398 if (a0
== args
[5] || (!const_args
[3] && a0
== args
[3])) {
2401 if (const_args
[2]) {
2402 tcg_out32(s
, SUBFIC
| TAI(a0
, args
[4], args
[2]));
2404 tcg_out32(s
, SUBFC
| TAB(a0
, args
[4], args
[2]));
2406 if (const_args
[3]) {
2407 tcg_out32(s
, (args
[3] ? SUBFME
: SUBFZE
) | RT(a1
) | RA(args
[5]));
2409 tcg_out32(s
, SUBFE
| TAB(a1
, args
[5], args
[3]));
2411 if (a0
!= args
[0]) {
2412 tcg_out_mov(s
, TCG_TYPE_REG
, args
[0], a0
);
2416 case INDEX_op_muluh_i32
:
2417 tcg_out32(s
, MULHWU
| TAB(args
[0], args
[1], args
[2]));
2419 case INDEX_op_mulsh_i32
:
2420 tcg_out32(s
, MULHW
| TAB(args
[0], args
[1], args
[2]));
2422 case INDEX_op_muluh_i64
:
2423 tcg_out32(s
, MULHDU
| TAB(args
[0], args
[1], args
[2]));
2425 case INDEX_op_mulsh_i64
:
2426 tcg_out32(s
, MULHD
| TAB(args
[0], args
[1], args
[2]));
2429 case INDEX_op_mov_i32
: /* Always emitted via tcg_out_mov. */
2430 case INDEX_op_mov_i64
:
2431 case INDEX_op_movi_i32
: /* Always emitted via tcg_out_movi. */
2432 case INDEX_op_movi_i64
:
2433 case INDEX_op_call
: /* Always emitted via tcg_out_call. */
2439 static const TCGTargetOpDef ppc_op_defs
[] = {
2440 { INDEX_op_exit_tb
, { } },
2441 { INDEX_op_goto_tb
, { } },
2442 { INDEX_op_br
, { } },
2444 { INDEX_op_ld8u_i32
, { "r", "r" } },
2445 { INDEX_op_ld8s_i32
, { "r", "r" } },
2446 { INDEX_op_ld16u_i32
, { "r", "r" } },
2447 { INDEX_op_ld16s_i32
, { "r", "r" } },
2448 { INDEX_op_ld_i32
, { "r", "r" } },
2450 { INDEX_op_st8_i32
, { "r", "r" } },
2451 { INDEX_op_st16_i32
, { "r", "r" } },
2452 { INDEX_op_st_i32
, { "r", "r" } },
2454 { INDEX_op_add_i32
, { "r", "r", "ri" } },
2455 { INDEX_op_mul_i32
, { "r", "r", "rI" } },
2456 { INDEX_op_div_i32
, { "r", "r", "r" } },
2457 { INDEX_op_divu_i32
, { "r", "r", "r" } },
2458 { INDEX_op_sub_i32
, { "r", "rI", "ri" } },
2459 { INDEX_op_and_i32
, { "r", "r", "ri" } },
2460 { INDEX_op_or_i32
, { "r", "r", "ri" } },
2461 { INDEX_op_xor_i32
, { "r", "r", "ri" } },
2462 { INDEX_op_andc_i32
, { "r", "r", "ri" } },
2463 { INDEX_op_orc_i32
, { "r", "r", "ri" } },
2464 { INDEX_op_eqv_i32
, { "r", "r", "ri" } },
2465 { INDEX_op_nand_i32
, { "r", "r", "r" } },
2466 { INDEX_op_nor_i32
, { "r", "r", "r" } },
2468 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
2469 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
2470 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
2471 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
2472 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
2474 { INDEX_op_neg_i32
, { "r", "r" } },
2475 { INDEX_op_not_i32
, { "r", "r" } },
2476 { INDEX_op_ext8s_i32
, { "r", "r" } },
2477 { INDEX_op_ext16s_i32
, { "r", "r" } },
2478 { INDEX_op_bswap16_i32
, { "r", "r" } },
2479 { INDEX_op_bswap32_i32
, { "r", "r" } },
2481 { INDEX_op_brcond_i32
, { "r", "ri" } },
2482 { INDEX_op_setcond_i32
, { "r", "r", "ri" } },
2483 { INDEX_op_movcond_i32
, { "r", "r", "ri", "rZ", "rZ" } },
2485 { INDEX_op_deposit_i32
, { "r", "0", "rZ" } },
2487 { INDEX_op_muluh_i32
, { "r", "r", "r" } },
2488 { INDEX_op_mulsh_i32
, { "r", "r", "r" } },
2490 #if TCG_TARGET_REG_BITS == 64
2491 { INDEX_op_ld8u_i64
, { "r", "r" } },
2492 { INDEX_op_ld8s_i64
, { "r", "r" } },
2493 { INDEX_op_ld16u_i64
, { "r", "r" } },
2494 { INDEX_op_ld16s_i64
, { "r", "r" } },
2495 { INDEX_op_ld32u_i64
, { "r", "r" } },
2496 { INDEX_op_ld32s_i64
, { "r", "r" } },
2497 { INDEX_op_ld_i64
, { "r", "r" } },
2499 { INDEX_op_st8_i64
, { "r", "r" } },
2500 { INDEX_op_st16_i64
, { "r", "r" } },
2501 { INDEX_op_st32_i64
, { "r", "r" } },
2502 { INDEX_op_st_i64
, { "r", "r" } },
2504 { INDEX_op_add_i64
, { "r", "r", "rT" } },
2505 { INDEX_op_sub_i64
, { "r", "rI", "rT" } },
2506 { INDEX_op_and_i64
, { "r", "r", "ri" } },
2507 { INDEX_op_or_i64
, { "r", "r", "rU" } },
2508 { INDEX_op_xor_i64
, { "r", "r", "rU" } },
2509 { INDEX_op_andc_i64
, { "r", "r", "ri" } },
2510 { INDEX_op_orc_i64
, { "r", "r", "r" } },
2511 { INDEX_op_eqv_i64
, { "r", "r", "r" } },
2512 { INDEX_op_nand_i64
, { "r", "r", "r" } },
2513 { INDEX_op_nor_i64
, { "r", "r", "r" } },
2515 { INDEX_op_shl_i64
, { "r", "r", "ri" } },
2516 { INDEX_op_shr_i64
, { "r", "r", "ri" } },
2517 { INDEX_op_sar_i64
, { "r", "r", "ri" } },
2518 { INDEX_op_rotl_i64
, { "r", "r", "ri" } },
2519 { INDEX_op_rotr_i64
, { "r", "r", "ri" } },
2521 { INDEX_op_mul_i64
, { "r", "r", "rI" } },
2522 { INDEX_op_div_i64
, { "r", "r", "r" } },
2523 { INDEX_op_divu_i64
, { "r", "r", "r" } },
2525 { INDEX_op_neg_i64
, { "r", "r" } },
2526 { INDEX_op_not_i64
, { "r", "r" } },
2527 { INDEX_op_ext8s_i64
, { "r", "r" } },
2528 { INDEX_op_ext16s_i64
, { "r", "r" } },
2529 { INDEX_op_ext32s_i64
, { "r", "r" } },
2530 { INDEX_op_ext_i32_i64
, { "r", "r" } },
2531 { INDEX_op_extu_i32_i64
, { "r", "r" } },
2532 { INDEX_op_bswap16_i64
, { "r", "r" } },
2533 { INDEX_op_bswap32_i64
, { "r", "r" } },
2534 { INDEX_op_bswap64_i64
, { "r", "r" } },
2536 { INDEX_op_brcond_i64
, { "r", "ri" } },
2537 { INDEX_op_setcond_i64
, { "r", "r", "ri" } },
2538 { INDEX_op_movcond_i64
, { "r", "r", "ri", "rZ", "rZ" } },
2540 { INDEX_op_deposit_i64
, { "r", "0", "rZ" } },
2542 { INDEX_op_mulsh_i64
, { "r", "r", "r" } },
2543 { INDEX_op_muluh_i64
, { "r", "r", "r" } },
2546 #if TCG_TARGET_REG_BITS == 32
2547 { INDEX_op_brcond2_i32
, { "r", "r", "ri", "ri" } },
2548 { INDEX_op_setcond2_i32
, { "r", "r", "r", "ri", "ri" } },
2551 #if TCG_TARGET_REG_BITS == 64
2552 { INDEX_op_add2_i64
, { "r", "r", "r", "r", "rI", "rZM" } },
2553 { INDEX_op_sub2_i64
, { "r", "r", "rI", "rZM", "r", "r" } },
2555 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "rI", "rZM" } },
2556 { INDEX_op_sub2_i32
, { "r", "r", "rI", "rZM", "r", "r" } },
2559 #if TCG_TARGET_REG_BITS == 64
2560 { INDEX_op_qemu_ld_i32
, { "r", "L" } },
2561 { INDEX_op_qemu_st_i32
, { "S", "S" } },
2562 { INDEX_op_qemu_ld_i64
, { "r", "L" } },
2563 { INDEX_op_qemu_st_i64
, { "S", "S" } },
2564 #elif TARGET_LONG_BITS == 32
2565 { INDEX_op_qemu_ld_i32
, { "r", "L" } },
2566 { INDEX_op_qemu_st_i32
, { "S", "S" } },
2567 { INDEX_op_qemu_ld_i64
, { "L", "L", "L" } },
2568 { INDEX_op_qemu_st_i64
, { "S", "S", "S" } },
2570 { INDEX_op_qemu_ld_i32
, { "r", "L", "L" } },
2571 { INDEX_op_qemu_st_i32
, { "S", "S", "S" } },
2572 { INDEX_op_qemu_ld_i64
, { "L", "L", "L", "L" } },
2573 { INDEX_op_qemu_st_i64
, { "S", "S", "S", "S" } },
2579 static void tcg_target_init(TCGContext
*s
)
2581 unsigned long hwcap
= qemu_getauxval(AT_HWCAP
);
2582 if (hwcap
& PPC_FEATURE_ARCH_2_06
) {
2583 have_isa_2_06
= true;
2586 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffffffff);
2587 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffffffff);
2588 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
2598 (1 << TCG_REG_R10
) |
2599 (1 << TCG_REG_R11
) |
2600 (1 << TCG_REG_R12
));
2602 tcg_regset_clear(s
->reserved_regs
);
2603 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
); /* tcg temp */
2604 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
); /* stack pointer */
2605 #if defined(_CALL_SYSV)
2606 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
); /* toc pointer */
2608 #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
2609 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R13
); /* thread pointer */
2611 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_TMP1
); /* mem temp */
2613 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_RA
); /* return addr */
2616 tcg_add_target_add_op_defs(ppc_op_defs
);
2622 DebugFrameFDEHeader fde
;
2623 uint8_t fde_def_cfa
[4];
2624 uint8_t fde_reg_ofs
[ARRAY_SIZE(tcg_target_callee_save_regs
) * 2 + 3];
2627 /* We're expecting a 2 byte uleb128 encoded value. */
2628 QEMU_BUILD_BUG_ON(FRAME_SIZE
>= (1 << 14));
2630 #if TCG_TARGET_REG_BITS == 64
2631 # define ELF_HOST_MACHINE EM_PPC64
2633 # define ELF_HOST_MACHINE EM_PPC
2636 static DebugFrame debug_frame
= {
2637 .cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
2640 .cie
.code_align
= 1,
2641 .cie
.data_align
= (-SZR
& 0x7f), /* sleb128 -SZR */
2642 .cie
.return_column
= 65,
2644 /* Total FDE size does not include the "len" member. */
2645 .fde
.len
= sizeof(DebugFrame
) - offsetof(DebugFrame
, fde
.cie_offset
),
2648 12, TCG_REG_R1
, /* DW_CFA_def_cfa r1, ... */
2649 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2653 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2654 0x11, 65, (LR_OFFSET
/ -SZR
) & 0x7f,
2658 void tcg_register_jit(void *buf
, size_t buf_size
)
2660 uint8_t *p
= &debug_frame
.fde_reg_ofs
[3];
2663 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); ++i
, p
+= 2) {
2664 p
[0] = 0x80 + tcg_target_callee_save_regs
[i
];
2665 p
[1] = (FRAME_SIZE
- (REG_SAVE_BOT
+ i
* SZR
)) / SZR
;
2668 debug_frame
.fde
.func_start
= (uintptr_t)buf
;
2669 debug_frame
.fde
.func_len
= buf_size
;
2671 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));
2673 #endif /* __ELF__ */
2675 static size_t dcache_bsize
= 16;
2676 static size_t icache_bsize
= 16;
2678 void flush_icache_range(uintptr_t start
, uintptr_t stop
)
2680 uintptr_t p
, start1
, stop1
;
2681 size_t dsize
= dcache_bsize
;
2682 size_t isize
= icache_bsize
;
2684 start1
= start
& ~(dsize
- 1);
2685 stop1
= (stop
+ dsize
- 1) & ~(dsize
- 1);
2686 for (p
= start1
; p
< stop1
; p
+= dsize
) {
2687 asm volatile ("dcbst 0,%0" : : "r"(p
) : "memory");
2689 asm volatile ("sync" : : : "memory");
2691 start
&= start
& ~(isize
- 1);
2692 stop1
= (stop
+ isize
- 1) & ~(isize
- 1);
2693 for (p
= start1
; p
< stop1
; p
+= isize
) {
2694 asm volatile ("icbi 0,%0" : : "r"(p
) : "memory");
2696 asm volatile ("sync" : : : "memory");
2697 asm volatile ("isync" : : : "memory");
2701 #include <sys/systemcfg.h>
2703 static void __attribute__((constructor
)) tcg_cache_init(void)
2705 icache_bsize
= _system_configuration
.icache_line
;
2706 dcache_bsize
= _system_configuration
.dcache_line
;
2709 #elif defined __linux__
2710 static void __attribute__((constructor
)) tcg_cache_init(void)
2712 unsigned long dsize
= qemu_getauxval(AT_DCACHEBSIZE
);
2713 unsigned long isize
= qemu_getauxval(AT_ICACHEBSIZE
);
2715 if (dsize
== 0 || isize
== 0) {
2717 fprintf(stderr
, "getauxval AT_DCACHEBSIZE failed\n");
2720 fprintf(stderr
, "getauxval AT_ICACHEBSIZE failed\n");
2724 dcache_bsize
= dsize
;
2725 icache_bsize
= isize
;
2728 #elif defined __APPLE__
2729 #include <sys/sysctl.h>
2731 static void __attribute__((constructor
)) tcg_cache_init(void)
2735 int name
[2] = { CTL_HW
, HW_CACHELINE
};
2737 len
= sizeof(cacheline
);
2738 if (sysctl(name
, 2, &cacheline
, &len
, NULL
, 0)) {
2739 perror("sysctl CTL_HW HW_CACHELINE failed");
2742 dcache_bsize
= cacheline
;
2743 icache_bsize
= cacheline
;
2746 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
2747 #include <sys/sysctl.h>
2749 static void __attribute__((constructor
)) tcg_cache_init(void)
2754 if (sysctlbyname ("machdep.cacheline_size", &cacheline
, &len
, NULL
, 0)) {
2755 fprintf(stderr
, "sysctlbyname machdep.cacheline_size failed: %s\n",
2759 dcache_bsize
= cacheline
;
2760 icache_bsize
= cacheline
;