tests/ahci-test.c

   1 /*
   2  * AHCI test cases
   3  *
   4  * Copyright (c) 2014 John Snow <jsnow@redhat.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <stdio.h>
  28 #include <getopt.h>
  29 #include <glib.h>
  30
  31 #include "libqtest.h"
  32 #include "libqos/libqos-pc.h"
  33 #include "libqos/ahci.h"
  34 #include "libqos/pci-pc.h"
  35
  36 #include "qemu-common.h"
  37 #include "qemu/host-utils.h"
  38
  39 #include "hw/pci/pci_ids.h"
  40 #include "hw/pci/pci_regs.h"
  41
  42 /* Test-specific defines. */
  43 #define TEST_IMAGE_SIZE    (64 * 1024 * 1024)
  44
  45 /*** Globals ***/
  46 static char tmp_path[] = "/tmp/qtest.XXXXXX";
  47 static bool ahci_pedantic;
  48
  49 /*** Function Declarations ***/
  50 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
  51 static void ahci_test_pci_spec(AHCIQState *ahci);
  52 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
  53                                uint8_t offset);
  54 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
  55 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
  56 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
  57
  58 /*** Utilities ***/
  59
  60 static void string_bswap16(uint16_t *s, size_t bytes)
  61 {
  62     g_assert_cmphex((bytes & 1), ==, 0);
  63     bytes /= 2;
  64
  65     while (bytes--) {
  66         *s = bswap16(*s);
  67         s++;
  68     }
  69 }
  70
  71 /*** Test Setup & Teardown ***/
  72
  73 /**
  74  * Start a Q35 machine and bookmark a handle to the AHCI device.
  75  */
  76 static AHCIQState *ahci_boot(void)
  77 {
  78     AHCIQState *s;
  79     const char *cli;
  80
  81     s = g_malloc0(sizeof(AHCIQState));
  82
  83     cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
  84         ",format=raw"
  85         " -M q35 "
  86         "-device ide-hd,drive=drive0 "
  87         "-global ide-hd.ver=%s";
  88     s->parent = qtest_pc_boot(cli, tmp_path, "testdisk", "version");
  89
  90     /* Verify that we have an AHCI device present. */
  91     s->dev = get_ahci_device(&s->fingerprint);
  92
  93     return s;
  94 }
  95
  96 /**
  97  * Clean up the PCI device, then terminate the QEMU instance.
  98  */
  99 static void ahci_shutdown(AHCIQState *ahci)
 100 {
 101     QOSState *qs = ahci->parent;
 102     free_ahci_device(ahci->dev);
 103     g_free(ahci);
 104     qtest_shutdown(qs);
 105 }
 106
 107 /*** Specification Adherence Tests ***/
 108
 109 /**
 110  * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
 111  */
 112 static void ahci_test_pci_spec(AHCIQState *ahci)
 113 {
 114     uint8_t datab;
 115     uint16_t data;
 116     uint32_t datal;
 117
 118     /* Most of these bits should start cleared until we turn them on. */
 119     data = qpci_config_readw(ahci->dev, PCI_COMMAND);
 120     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
 121     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
 122     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);     /* Reserved */
 123     ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
 124     ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
 125     ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);        /* Reserved */
 126     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
 127     ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
 128     ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
 129     ASSERT_BIT_CLEAR(data, 0xF800);                  /* Reserved */
 130
 131     data = qpci_config_readw(ahci->dev, PCI_STATUS);
 132     ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);     /* Reserved */
 133     ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
 134     ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);      /* must be set */
 135     ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);         /* Reserved */
 136     ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
 137     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
 138     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
 139     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
 140     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
 141     ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
 142
 143     /* RID occupies the low byte, CCs occupy the high three. */
 144     datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
 145     if (ahci_pedantic) {
 146         /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
 147          * Though in practice this is likely seldom true. */
 148         ASSERT_BIT_CLEAR(datal, 0xFF);
 149     }
 150
 151     /* BCC *must* equal 0x01. */
 152     g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
 153     if (PCI_SCC(datal) == 0x01) {
 154         /* IDE */
 155         ASSERT_BIT_SET(0x80000000, datal);
 156         ASSERT_BIT_CLEAR(0x60000000, datal);
 157     } else if (PCI_SCC(datal) == 0x04) {
 158         /* RAID */
 159         g_assert_cmphex(PCI_PI(datal), ==, 0);
 160     } else if (PCI_SCC(datal) == 0x06) {
 161         /* AHCI */
 162         g_assert_cmphex(PCI_PI(datal), ==, 0x01);
 163     } else {
 164         g_assert_not_reached();
 165     }
 166
 167     datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
 168     g_assert_cmphex(datab, ==, 0);
 169
 170     datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
 171     g_assert_cmphex(datab, ==, 0);
 172
 173     /* Only the bottom 7 bits must be off. */
 174     datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
 175     ASSERT_BIT_CLEAR(datab, 0x7F);
 176
 177     /* BIST is optional, but the low 7 bits must always start off regardless. */
 178     datab = qpci_config_readb(ahci->dev, PCI_BIST);
 179     ASSERT_BIT_CLEAR(datab, 0x7F);
 180
 181     /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
 182     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 183     g_assert_cmphex(datal, ==, 0);
 184
 185     qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
 186     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 187     /* ABAR must be 32-bit, memory mapped, non-prefetchable and
 188      * must be >= 512 bytes. To that end, bits 0-8 must be off. */
 189     ASSERT_BIT_CLEAR(datal, 0xFF);
 190
 191     /* Capability list MUST be present, */
 192     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
 193     /* But these bits are reserved. */
 194     ASSERT_BIT_CLEAR(datal, ~0xFF);
 195     g_assert_cmphex(datal, !=, 0);
 196
 197     /* Check specification adherence for capability extenstions. */
 198     data = qpci_config_readw(ahci->dev, datal);
 199
 200     switch (ahci->fingerprint) {
 201     case AHCI_INTEL_ICH9:
 202         /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
 203         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
 204         break;
 205     default:
 206         /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
 207         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
 208     }
 209
 210     ahci_test_pci_caps(ahci, data, (uint8_t)datal);
 211
 212     /* Reserved. */
 213     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
 214     g_assert_cmphex(datal, ==, 0);
 215
 216     /* IPIN might vary, but ILINE must be off. */
 217     datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
 218     g_assert_cmphex(datab, ==, 0);
 219 }
 220
 221 /**
 222  * Test PCI capabilities for AHCI specification adherence.
 223  */
 224 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
 225                                uint8_t offset)
 226 {
 227     uint8_t cid = header & 0xFF;
 228     uint8_t next = header >> 8;
 229
 230     g_test_message("CID: %02x; next: %02x", cid, next);
 231
 232     switch (cid) {
 233     case PCI_CAP_ID_PM:
 234         ahci_test_pmcap(ahci, offset);
 235         break;
 236     case PCI_CAP_ID_MSI:
 237         ahci_test_msicap(ahci, offset);
 238         break;
 239     case PCI_CAP_ID_SATA:
 240         ahci_test_satacap(ahci, offset);
 241         break;
 242
 243     default:
 244         g_test_message("Unknown CAP 0x%02x", cid);
 245     }
 246
 247     if (next) {
 248         ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
 249     }
 250 }
 251
 252 /**
 253  * Test SATA PCI capabilitity for AHCI specification adherence.
 254  */
 255 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
 256 {
 257     uint16_t dataw;
 258     uint32_t datal;
 259
 260     g_test_message("Verifying SATACAP");
 261
 262     /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
 263     dataw = qpci_config_readw(ahci->dev, offset + 2);
 264     g_assert_cmphex(dataw, ==, 0x10);
 265
 266     /* Grab the SATACR1 register. */
 267     datal = qpci_config_readw(ahci->dev, offset + 4);
 268
 269     switch (datal & 0x0F) {
 270     case 0x04: /* BAR0 */
 271     case 0x05: /* BAR1 */
 272     case 0x06:
 273     case 0x07:
 274     case 0x08:
 275     case 0x09: /* BAR5 */
 276     case 0x0F: /* Immediately following SATACR1 in PCI config space. */
 277         break;
 278     default:
 279         /* Invalid BARLOC for the Index Data Pair. */
 280         g_assert_not_reached();
 281     }
 282
 283     /* Reserved. */
 284     g_assert_cmphex((datal >> 24), ==, 0x00);
 285 }
 286
 287 /**
 288  * Test MSI PCI capability for AHCI specification adherence.
 289  */
 290 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
 291 {
 292     uint16_t dataw;
 293     uint32_t datal;
 294
 295     g_test_message("Verifying MSICAP");
 296
 297     dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
 298     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
 299     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
 300     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
 301
 302     datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
 303     g_assert_cmphex(datal, ==, 0);
 304
 305     if (dataw & PCI_MSI_FLAGS_64BIT) {
 306         g_test_message("MSICAP is 64bit");
 307         datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
 308         g_assert_cmphex(datal, ==, 0);
 309         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
 310         g_assert_cmphex(dataw, ==, 0);
 311     } else {
 312         g_test_message("MSICAP is 32bit");
 313         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
 314         g_assert_cmphex(dataw, ==, 0);
 315     }
 316 }
 317
 318 /**
 319  * Test Power Management PCI capability for AHCI specification adherence.
 320  */
 321 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
 322 {
 323     uint16_t dataw;
 324
 325     g_test_message("Verifying PMCAP");
 326
 327     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
 328     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
 329     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
 330     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
 331     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
 332
 333     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
 334     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
 335     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
 336     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
 337     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
 338 }
 339
 340 static void ahci_test_hba_spec(AHCIQState *ahci)
 341 {
 342     unsigned i;
 343     uint32_t reg;
 344     uint32_t ports;
 345     uint8_t nports_impl;
 346     uint8_t maxports;
 347
 348     g_assert(ahci != NULL);
 349
 350     /*
 351      * Note that the AHCI spec does expect the BIOS to set up a few things:
 352      * CAP.SSS    - Support for staggered spin-up            (t/f)
 353      * CAP.SMPS   - Support for mechanical presence switches (t/f)
 354      * PI         - Ports Implemented                        (1-32)
 355      * PxCMD.HPCP - Hot Plug Capable Port
 356      * PxCMD.MPSP - Mechanical Presence Switch Present
 357      * PxCMD.CPD  - Cold Presence Detection support
 358      *
 359      * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
 360      * Foreach Port Implemented:
 361      * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
 362      * -PxCLB/U and PxFB/U are set to valid regions in memory
 363      * -PxSUD is set to 1.
 364      * -PxSSTS.DET is polled for presence; if detected, we continue:
 365      * -PxSERR is cleared with 1's.
 366      * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
 367      *  the device is ready.
 368      */
 369
 370     /* 1 CAP - Capabilities Register */
 371     ahci->cap = ahci_rreg(ahci, AHCI_CAP);
 372     ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
 373
 374     /* 2 GHC - Global Host Control */
 375     reg = ahci_rreg(ahci, AHCI_GHC);
 376     ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
 377     ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
 378     ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
 379     if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
 380         g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
 381         ASSERT_BIT_SET(reg, AHCI_GHC_AE);
 382     } else {
 383         g_test_message("Supports AHCI/Legacy mix.");
 384         ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
 385     }
 386
 387     /* 3 IS - Interrupt Status */
 388     reg = ahci_rreg(ahci, AHCI_IS);
 389     g_assert_cmphex(reg, ==, 0);
 390
 391     /* 4 PI - Ports Implemented */
 392     ports = ahci_rreg(ahci, AHCI_PI);
 393     /* Ports Implemented must be non-zero. */
 394     g_assert_cmphex(ports, !=, 0);
 395     /* Ports Implemented must be <= Number of Ports. */
 396     nports_impl = ctpopl(ports);
 397     g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
 398
 399     /* Ports must be within the proper range. Given a mapping of SIZE,
 400      * 256 bytes are used for global HBA control, and the rest is used
 401      * for ports data, at 0x80 bytes each. */
 402     g_assert_cmphex(ahci->barsize, >, 0);
 403     maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
 404     /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
 405     g_assert_cmphex((reg >> maxports), ==, 0);
 406
 407     /* 5 AHCI Version */
 408     reg = ahci_rreg(ahci, AHCI_VS);
 409     switch (reg) {
 410     case AHCI_VERSION_0_95:
 411     case AHCI_VERSION_1_0:
 412     case AHCI_VERSION_1_1:
 413     case AHCI_VERSION_1_2:
 414     case AHCI_VERSION_1_3:
 415         break;
 416     default:
 417         g_assert_not_reached();
 418     }
 419
 420     /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
 421     reg = ahci_rreg(ahci, AHCI_CCCCTL);
 422     if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
 423         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
 424         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
 425         ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
 426         ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
 427     } else {
 428         g_assert_cmphex(reg, ==, 0);
 429     }
 430
 431     /* 7 CCC_PORTS */
 432     reg = ahci_rreg(ahci, AHCI_CCCPORTS);
 433     /* Must be zeroes initially regardless of CAP.CCCS */
 434     g_assert_cmphex(reg, ==, 0);
 435
 436     /* 8 EM_LOC */
 437     reg = ahci_rreg(ahci, AHCI_EMLOC);
 438     if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
 439         g_assert_cmphex(reg, ==, 0);
 440     }
 441
 442     /* 9 EM_CTL */
 443     reg = ahci_rreg(ahci, AHCI_EMCTL);
 444     if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
 445         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
 446         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
 447         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
 448         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
 449     } else {
 450         g_assert_cmphex(reg, ==, 0);
 451     }
 452
 453     /* 10 CAP2 -- Capabilities Extended */
 454     ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
 455     ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
 456
 457     /* 11 BOHC -- Bios/OS Handoff Control */
 458     reg = ahci_rreg(ahci, AHCI_BOHC);
 459     g_assert_cmphex(reg, ==, 0);
 460
 461     /* 12 -- 23: Reserved */
 462     g_test_message("Verifying HBA reserved area is empty.");
 463     for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
 464         reg = ahci_rreg(ahci, i);
 465         g_assert_cmphex(reg, ==, 0);
 466     }
 467
 468     /* 24 -- 39: NVMHCI */
 469     if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
 470         g_test_message("Verifying HBA/NVMHCI area is empty.");
 471         for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
 472             reg = ahci_rreg(ahci, i);
 473             g_assert_cmphex(reg, ==, 0);
 474         }
 475     }
 476
 477     /* 40 -- 63: Vendor */
 478     g_test_message("Verifying HBA/Vendor area is empty.");
 479     for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
 480         reg = ahci_rreg(ahci, i);
 481         g_assert_cmphex(reg, ==, 0);
 482     }
 483
 484     /* 64 -- XX: Port Space */
 485     for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
 486         if (BITSET(ports, 0x1)) {
 487             g_test_message("Testing port %u for spec", i);
 488             ahci_test_port_spec(ahci, i);
 489         } else {
 490             uint16_t j;
 491             uint16_t low = AHCI_PORTS + (32 * i);
 492             uint16_t high = AHCI_PORTS + (32 * (i + 1));
 493             g_test_message("Asserting unimplemented port %u "
 494                            "(reg [%u-%u]) is empty.",
 495                            i, low, high - 1);
 496             for (j = low; j < high; ++j) {
 497                 reg = ahci_rreg(ahci, j);
 498                 g_assert_cmphex(reg, ==, 0);
 499             }
 500         }
 501     }
 502 }
 503
 504 /**
 505  * Test the memory space for one port for specification adherence.
 506  */
 507 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
 508 {
 509     uint32_t reg;
 510     unsigned i;
 511
 512     /* (0) CLB */
 513     reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
 514     ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
 515
 516     /* (1) CLBU */
 517     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 518         reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
 519         g_assert_cmphex(reg, ==, 0);
 520     }
 521
 522     /* (2) FB */
 523     reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
 524     ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
 525
 526     /* (3) FBU */
 527     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 528         reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
 529         g_assert_cmphex(reg, ==, 0);
 530     }
 531
 532     /* (4) IS */
 533     reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
 534     g_assert_cmphex(reg, ==, 0);
 535
 536     /* (5) IE */
 537     reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
 538     g_assert_cmphex(reg, ==, 0);
 539
 540     /* (6) CMD */
 541     reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
 542     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
 543     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
 544     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
 545     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
 546     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
 547     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
 548     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
 549     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
 550     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
 551     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);  /* RW only if CAP.SALP */
 552     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);   /* RW only if CAP.SALP */
 553     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
 554     /* If CPDetect support does not exist, CPState must be off. */
 555     if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
 556         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
 557     }
 558     /* If MPSPresence is not set, MPSState must be off. */
 559     if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
 560         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 561     }
 562     /* If we do not support MPS, MPSS and MPSP must be off. */
 563     if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
 564         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 565         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
 566     }
 567     /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
 568     if (BITANY(reg, AHCI_PX_CMD_CPD || AHCI_PX_CMD_MPSP)) {
 569         ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
 570     }
 571     /* HPCP and ESP cannot both be active. */
 572     g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
 573     /* If CAP.FBSS is not set, FBSCP must not be set. */
 574     if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
 575         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
 576     }
 577
 578     /* (7) RESERVED */
 579     reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
 580     g_assert_cmphex(reg, ==, 0);
 581
 582     /* (8) TFD */
 583     reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
 584     /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
 585      * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
 586     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
 587     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
 588     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
 589     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
 590     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
 591     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
 592     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
 593
 594     /* (9) SIG */
 595     /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
 596      * Even when GHC.ST is zero, the AHCI HBA may receive the initial
 597      * D2H register FIS and update the signature asynchronously,
 598      * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
 599
 600     /* (10) SSTS / SCR0: SStatus */
 601     reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
 602     ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
 603     /* Even though the register should be 0 at boot, it is asynchronous and
 604      * prone to change, so we cannot test any well known value. */
 605
 606     /* (11) SCTL / SCR2: SControl */
 607     reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
 608     g_assert_cmphex(reg, ==, 0);
 609
 610     /* (12) SERR / SCR1: SError */
 611     reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
 612     g_assert_cmphex(reg, ==, 0);
 613
 614     /* (13) SACT / SCR3: SActive */
 615     reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
 616     g_assert_cmphex(reg, ==, 0);
 617
 618     /* (14) CI */
 619     reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
 620     g_assert_cmphex(reg, ==, 0);
 621
 622     /* (15) SNTF */
 623     reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
 624     g_assert_cmphex(reg, ==, 0);
 625
 626     /* (16) FBS */
 627     reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
 628     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
 629     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
 630     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
 631     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
 632     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
 633     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
 634     if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
 635         /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
 636         g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
 637     }
 638
 639     /* [17 -- 27] RESERVED */
 640     for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
 641         reg = ahci_px_rreg(ahci, port, i);
 642         g_assert_cmphex(reg, ==, 0);
 643     }
 644
 645     /* [28 -- 31] Vendor-Specific */
 646     for (i = AHCI_PX_VS; i < 32; ++i) {
 647         reg = ahci_px_rreg(ahci, port, i);
 648         if (reg) {
 649             g_test_message("INFO: Vendor register %u non-empty", i);
 650         }
 651     }
 652 }
 653
 654 /**
 655  * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
 656  * device we see, then read and check the response.
 657  */
 658 static void ahci_test_identify(AHCIQState *ahci)
 659 {
 660     RegD2HFIS *d2h = g_malloc0(0x20);
 661     RegD2HFIS *pio = g_malloc0(0x20);
 662     RegH2DFIS fis;
 663     AHCICommandHeader cmd;
 664     PRD prd;
 665     uint32_t reg, table, data_ptr;
 666     uint16_t buff[256];
 667     unsigned i;
 668     int rc;
 669
 670     g_assert(ahci != NULL);
 671
 672     /* We need to:
 673      * (1) Create a Command Table Buffer and update the Command List Slot #0
 674      *     to point to this buffer.
 675      * (2) Construct an FIS host-to-device command structure, and write it to
 676      *     the top of the command table buffer.
 677      * (3) Create a data buffer for the IDENTIFY response to be sent to
 678      * (4) Create a Physical Region Descriptor that points to the data buffer,
 679      *     and write it to the bottom (offset 0x80) of the command table.
 680      * (5) Now, PxCLB points to the command list, command 0 points to
 681      *     our table, and our table contains an FIS instruction and a
 682      *     PRD that points to our rx buffer.
 683      * (6) We inform the HBA via PxCI that there is a command ready in slot #0.
 684      */
 685
 686     /* Pick the first implemented and running port */
 687     i = ahci_port_select(ahci);
 688     g_test_message("Selected port %u for test", i);
 689
 690     /* Clear out the FIS Receive area and any pending interrupts. */
 691     ahci_port_clear(ahci, i);
 692
 693     /* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
 694     /* We need at least one PRD, so round up to the nearest 0x80 multiple.    */
 695     table = ahci_alloc(ahci, CMD_TBL_SIZ(1));
 696     g_assert(table);
 697     ASSERT_BIT_CLEAR(table, 0x7F);
 698
 699     /* Create a data buffer ... where we will dump the IDENTIFY data to. */
 700     data_ptr = ahci_alloc(ahci, 512);
 701     g_assert(data_ptr);
 702
 703     /* Copy the existing Command #0 structure from the CLB into local memory,
 704      * and build a new command #0. */
 705     memread(ahci->port[i].clb, &cmd, sizeof(cmd));
 706     cmd.flags = cpu_to_le16(5);      /* reg_h2d_fis is 5 double-words long */
 707     cmd.flags |= cpu_to_le16(0x400); /* clear PxTFD.STS.BSY when done */
 708     cmd.prdtl = cpu_to_le16(1);      /* One PRD table entry. */
 709     cmd.prdbc = 0;
 710     cmd.ctba = cpu_to_le32(table);
 711     cmd.ctbau = 0;
 712
 713     /* Construct our PRD, noting that DBC is 0-indexed. */
 714     prd.dba = cpu_to_le32(data_ptr);
 715     prd.dbau = 0;
 716     prd.res = 0;
 717     /* 511+1 bytes, request DPS interrupt */
 718     prd.dbc = cpu_to_le32(511 | 0x80000000);
 719
 720     /* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
 721     memset(&fis, 0x00, sizeof(fis));
 722     fis.fis_type = 0x27; /* Register Host-to-Device FIS */
 723     fis.command = 0xEC;  /* IDENTIFY */
 724     fis.device = 0;
 725     fis.flags = 0x80;    /* Indicate this is a command FIS */
 726
 727     /* We've committed nothing yet, no interrupts should be posted yet. */
 728     g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
 729
 730     /* Commit the Command FIS to the Command Table */
 731     memwrite(table, &fis, sizeof(fis));
 732
 733     /* Commit the PRD entry to the Command Table */
 734     memwrite(table + 0x80, &prd, sizeof(prd));
 735
 736     /* Commit Command #0, pointing to the Table, to the Command List Buffer. */
 737     memwrite(ahci->port[i].clb, &cmd, sizeof(cmd));
 738
 739     /* Everything is in place, but we haven't given the go-ahead yet. */
 740     g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
 741
 742     /* Issue Command #0 via PxCI */
 743     ahci_px_wreg(ahci, i, AHCI_PX_CI, (1 << 0));
 744     while (BITSET(ahci_px_rreg(ahci, i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) {
 745         usleep(50);
 746     }
 747
 748     /* Check for expected interrupts */
 749     reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
 750     ASSERT_BIT_SET(reg, AHCI_PX_IS_DHRS);
 751     ASSERT_BIT_SET(reg, AHCI_PX_IS_PSS);
 752     /* BUG: we expect AHCI_PX_IS_DPS to be set. */
 753     ASSERT_BIT_CLEAR(reg, AHCI_PX_IS_DPS);
 754
 755     /* Clear expected interrupts and assert all interrupts now cleared. */
 756     ahci_px_wreg(ahci, i, AHCI_PX_IS,
 757                  AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS);
 758     g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0);
 759
 760     /* Check for errors. */
 761     reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
 762     g_assert_cmphex(reg, ==, 0);
 763     reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
 764     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
 765     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
 766
 767     /* Investigate CMD #0, assert that we read 512 bytes */
 768     memread(ahci->port[i].clb, &cmd, sizeof(cmd));
 769     g_assert_cmphex(512, ==, le32_to_cpu(cmd.prdbc));
 770
 771     /* Investigate FIS responses */
 772     memread(ahci->port[i].fb + 0x20, pio, 0x20);
 773     memread(ahci->port[i].fb + 0x40, d2h, 0x20);
 774     g_assert_cmphex(pio->fis_type, ==, 0x5f);
 775     g_assert_cmphex(d2h->fis_type, ==, 0x34);
 776     g_assert_cmphex(pio->flags, ==, d2h->flags);
 777     g_assert_cmphex(pio->status, ==, d2h->status);
 778     g_assert_cmphex(pio->error, ==, d2h->error);
 779
 780     reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
 781     g_assert_cmphex((reg & AHCI_PX_TFD_ERR), ==, pio->error);
 782     g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, pio->status);
 783     /* The PIO Setup FIS contains a "bytes read" field, which is a
 784      * 16-bit value. The Physical Region Descriptor Byte Count is
 785      * 32-bit, but for small transfers using one PRD, it should match. */
 786     g_assert_cmphex(le16_to_cpu(pio->res4), ==, le32_to_cpu(cmd.prdbc));
 787
 788     /* Last, but not least: Investigate the IDENTIFY response data. */
 789     memread(data_ptr, &buff, 512);
 790
 791     /* Check serial number/version in the buffer */
 792     /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
 793      * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
 794      * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
 795      * as a consequence, only needs to unchunk the data on LE machines. */
 796     string_bswap16(&buff[10], 20);
 797     rc = memcmp(&buff[10], "testdisk            ", 20);
 798     g_assert_cmphex(rc, ==, 0);
 799
 800     string_bswap16(&buff[23], 8);
 801     rc = memcmp(&buff[23], "version ", 8);
 802     g_assert_cmphex(rc, ==, 0);
 803
 804     g_free(d2h);
 805     g_free(pio);
 806 }
 807
 808 /******************************************************************************/
 809 /* Test Interfaces                                                            */
 810 /******************************************************************************/
 811
 812 /**
 813  * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
 814  */
 815 static void test_sanity(void)
 816 {
 817     AHCIQState *ahci;
 818     ahci = ahci_boot();
 819     ahci_shutdown(ahci);
 820 }
 821
 822 /**
 823  * Ensure that the PCI configuration space for the AHCI device is in-line with
 824  * the AHCI 1.3 specification for initial values.
 825  */
 826 static void test_pci_spec(void)
 827 {
 828     AHCIQState *ahci;
 829     ahci = ahci_boot();
 830     ahci_test_pci_spec(ahci);
 831     ahci_shutdown(ahci);
 832 }
 833
 834 /**
 835  * Engage the PCI AHCI device and sanity check the response.
 836  * Perform additional PCI config space bringup for the HBA.
 837  */
 838 static void test_pci_enable(void)
 839 {
 840     AHCIQState *ahci;
 841
 842     ahci = ahci_boot();
 843     ahci_pci_enable(ahci);
 844     ahci_shutdown(ahci);
 845 }
 846
 847 /**
 848  * Investigate the memory mapped regions of the HBA,
 849  * and test them for AHCI specification adherence.
 850  */
 851 static void test_hba_spec(void)
 852 {
 853     AHCIQState *ahci;
 854
 855     ahci = ahci_boot();
 856     ahci_pci_enable(ahci);
 857     ahci_test_hba_spec(ahci);
 858     ahci_shutdown(ahci);
 859 }
 860
 861 /**
 862  * Engage the HBA functionality of the AHCI PCI device,
 863  * and bring it into a functional idle state.
 864  */
 865 static void test_hba_enable(void)
 866 {
 867     AHCIQState *ahci;
 868
 869     ahci = ahci_boot();
 870     ahci_pci_enable(ahci);
 871     ahci_hba_enable(ahci);
 872     ahci_shutdown(ahci);
 873 }
 874
 875 /**
 876  * Bring up the device and issue an IDENTIFY command.
 877  * Inspect the state of the HBA device and the data returned.
 878  */
 879 static void test_identify(void)
 880 {
 881     AHCIQState *ahci;
 882
 883     ahci = ahci_boot();
 884     ahci_pci_enable(ahci);
 885     ahci_hba_enable(ahci);
 886     ahci_test_identify(ahci);
 887     ahci_shutdown(ahci);
 888 }
 889
 890 /******************************************************************************/
 891
 892 int main(int argc, char **argv)
 893 {
 894     const char *arch;
 895     int fd;
 896     int ret;
 897     int c;
 898
 899     static struct option long_options[] = {
 900         {"pedantic", no_argument, 0, 'p' },
 901         {0, 0, 0, 0},
 902     };
 903
 904     /* Should be first to utilize g_test functionality, So we can see errors. */
 905     g_test_init(&argc, &argv, NULL);
 906
 907     while (1) {
 908         c = getopt_long(argc, argv, "", long_options, NULL);
 909         if (c == -1) {
 910             break;
 911         }
 912         switch (c) {
 913         case -1:
 914             break;
 915         case 'p':
 916             ahci_pedantic = 1;
 917             break;
 918         default:
 919             fprintf(stderr, "Unrecognized ahci_test option.\n");
 920             g_assert_not_reached();
 921         }
 922     }
 923
 924     /* Check architecture */
 925     arch = qtest_get_arch();
 926     if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
 927         g_test_message("Skipping test for non-x86");
 928         return 0;
 929     }
 930
 931     /* Create a temporary raw image */
 932     fd = mkstemp(tmp_path);
 933     g_assert(fd >= 0);
 934     ret = ftruncate(fd, TEST_IMAGE_SIZE);
 935     g_assert(ret == 0);
 936     close(fd);
 937
 938     /* Run the tests */
 939     qtest_add_func("/ahci/sanity",     test_sanity);
 940     qtest_add_func("/ahci/pci_spec",   test_pci_spec);
 941     qtest_add_func("/ahci/pci_enable", test_pci_enable);
 942     qtest_add_func("/ahci/hba_spec",   test_hba_spec);
 943     qtest_add_func("/ahci/hba_enable", test_hba_enable);
 944     qtest_add_func("/ahci/identify",   test_identify);
 945
 946     ret = g_test_run();
 947
 948     /* Cleanup */
 949     unlink(tmp_path);
 950
 951     return ret;
 952 }