target/loongarch/machine.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * QEMU LoongArch Machine State
   4  *
   5  * Copyright (c) 2021 Loongson Technology Corporation Limited
   6  */
   7
   8 #include "qemu/osdep.h"
   9 #include "cpu.h"
  10 #include "migration/cpu.h"
  11 #include "internals.h"
  12
  13 /* TLB state */
  14 const VMStateDescription vmstate_tlb = {
  15     .name = "cpu/tlb",
  16     .version_id = 0,
  17     .minimum_version_id = 0,
  18     .fields = (VMStateField[]) {
  19         VMSTATE_UINT64(tlb_misc, LoongArchTLB),
  20         VMSTATE_UINT64(tlb_entry0, LoongArchTLB),
  21         VMSTATE_UINT64(tlb_entry1, LoongArchTLB),
  22         VMSTATE_END_OF_LIST()
  23     }
  24 };
  25
  26 /* LoongArch CPU state */
  27
  28 const VMStateDescription vmstate_loongarch_cpu = {
  29     .name = "cpu",
  30     .version_id = 0,
  31     .minimum_version_id = 0,
  32     .fields = (VMStateField[]) {
  33
  34         VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
  35         VMSTATE_UINTTL(env.pc, LoongArchCPU),
  36         VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
  37         VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
  38         VMSTATE_BOOL_ARRAY(env.cf, LoongArchCPU, 8),
  39
  40         /* Remaining CSRs */
  41         VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
  42         VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
  43         VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
  44         VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
  45         VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
  46         VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
  47         VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
  48         VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
  49         VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
  50         VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
  51         VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
  52         VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
  53         VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
  54         VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
  55         VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
  56         VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
  57         VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
  58         VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
  59         VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
  60         VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
  61         VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
  62         VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
  63         VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
  64         VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
  65         VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
  66         VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
  67         VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
  68         VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
  69         VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
  70         VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
  71         VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
  72         VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
  73         VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
  74         VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
  75         VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
  76         VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
  77         VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
  78         VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
  79         VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
  80         VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
  81         VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
  82         VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
  83         VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
  84         VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
  85         VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
  86         VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
  87         VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
  88         VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
  89         VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
  90         VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
  91
  92         /* Debug CSRs */
  93         VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
  94         VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
  95         VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
  96         /* TLB */
  97         VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX,
  98                              0, vmstate_tlb, LoongArchTLB),
  99
 100         VMSTATE_END_OF_LIST()
 101     },
 102 };