linux-user/aarch64/cpu_loop.c

   1 /*
   2  *  qemu user cpu loop
   3  *
   4  *  Copyright (c) 2003-2008 Fabrice Bellard
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu.h"
  22 #include "user-internals.h"
  23 #include "cpu_loop-common.h"
  24 #include "signal-common.h"
  25 #include "qemu/guest-random.h"
  26 #include "semihosting/common-semi.h"
  27 #include "target/arm/syndrome.h"
  28
  29 #define get_user_code_u32(x, gaddr, env)                \
  30     ({ abi_long __r = get_user_u32((x), (gaddr));       \
  31         if (!__r && bswap_code(arm_sctlr_b(env))) {     \
  32             (x) = bswap32(x);                           \
  33         }                                               \
  34         __r;                                            \
  35     })
  36
  37 #define get_user_code_u16(x, gaddr, env)                \
  38     ({ abi_long __r = get_user_u16((x), (gaddr));       \
  39         if (!__r && bswap_code(arm_sctlr_b(env))) {     \
  40             (x) = bswap16(x);                           \
  41         }                                               \
  42         __r;                                            \
  43     })
  44
  45 #define get_user_data_u32(x, gaddr, env)                \
  46     ({ abi_long __r = get_user_u32((x), (gaddr));       \
  47         if (!__r && arm_cpu_bswap_data(env)) {          \
  48             (x) = bswap32(x);                           \
  49         }                                               \
  50         __r;                                            \
  51     })
  52
  53 #define get_user_data_u16(x, gaddr, env)                \
  54     ({ abi_long __r = get_user_u16((x), (gaddr));       \
  55         if (!__r && arm_cpu_bswap_data(env)) {          \
  56             (x) = bswap16(x);                           \
  57         }                                               \
  58         __r;                                            \
  59     })
  60
  61 #define put_user_data_u32(x, gaddr, env)                \
  62     ({ typeof(x) __x = (x);                             \
  63         if (arm_cpu_bswap_data(env)) {                  \
  64             __x = bswap32(__x);                         \
  65         }                                               \
  66         put_user_u32(__x, (gaddr));                     \
  67     })
  68
  69 #define put_user_data_u16(x, gaddr, env)                \
  70     ({ typeof(x) __x = (x);                             \
  71         if (arm_cpu_bswap_data(env)) {                  \
  72             __x = bswap16(__x);                         \
  73         }                                               \
  74         put_user_u16(__x, (gaddr));                     \
  75     })
  76
  77 /* AArch64 main loop */
  78 void cpu_loop(CPUARMState *env)
  79 {
  80     CPUState *cs = env_cpu(env);
  81     int trapnr, ec, fsc, si_code, si_signo;
  82     abi_long ret;
  83
  84     for (;;) {
  85         cpu_exec_start(cs);
  86         trapnr = cpu_exec(cs);
  87         cpu_exec_end(cs);
  88         process_queued_cpu_work(cs);
  89
  90         switch (trapnr) {
  91         case EXCP_SWI:
  92             /*
  93              * On syscall, PSTATE.ZA is preserved, along with the ZA matrix.
  94              * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState.
  95              */
  96             if (FIELD_EX64(env->svcr, SVCR, SM)) {
  97                 env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0);
  98                 arm_rebuild_hflags(env);
  99                 arm_reset_sve_state(env);
 100             }
 101             ret = do_syscall(env,
 102                              env->xregs[8],
 103                              env->xregs[0],
 104                              env->xregs[1],
 105                              env->xregs[2],
 106                              env->xregs[3],
 107                              env->xregs[4],
 108                              env->xregs[5],
 109                              0, 0);
 110             if (ret == -QEMU_ERESTARTSYS) {
 111                 env->pc -= 4;
 112             } else if (ret != -QEMU_ESIGRETURN) {
 113                 env->xregs[0] = ret;
 114             }
 115             break;
 116         case EXCP_INTERRUPT:
 117             /* just indicate that signals should be handled asap */
 118             break;
 119         case EXCP_UDEF:
 120             force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
 121             break;
 122         case EXCP_PREFETCH_ABORT:
 123         case EXCP_DATA_ABORT:
 124             ec = syn_get_ec(env->exception.syndrome);
 125             switch (ec) {
 126             case EC_DATAABORT:
 127             case EC_INSNABORT:
 128                 /* Both EC have the same format for FSC, or close enough. */
 129                 fsc = extract32(env->exception.syndrome, 0, 6);
 130                 switch (fsc) {
 131                 case 0x04 ... 0x07: /* Translation fault, level {0-3} */
 132                     si_signo = TARGET_SIGSEGV;
 133                     si_code = TARGET_SEGV_MAPERR;
 134                     break;
 135                 case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
 136                 case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
 137                     si_signo = TARGET_SIGSEGV;
 138                     si_code = TARGET_SEGV_ACCERR;
 139                     break;
 140                 case 0x11: /* Synchronous Tag Check Fault */
 141                     si_signo = TARGET_SIGSEGV;
 142                     si_code = TARGET_SEGV_MTESERR;
 143                     break;
 144                 case 0x21: /* Alignment fault */
 145                     si_signo = TARGET_SIGBUS;
 146                     si_code = TARGET_BUS_ADRALN;
 147                     break;
 148                 default:
 149                     g_assert_not_reached();
 150                 }
 151                 break;
 152             case EC_PCALIGNMENT:
 153                 si_signo = TARGET_SIGBUS;
 154                 si_code = TARGET_BUS_ADRALN;
 155                 break;
 156             default:
 157                 g_assert_not_reached();
 158             }
 159             force_sig_fault(si_signo, si_code, env->exception.vaddress);
 160             break;
 161         case EXCP_DEBUG:
 162         case EXCP_BKPT:
 163             force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
 164             break;
 165         case EXCP_SEMIHOST:
 166             do_common_semihosting(cs);
 167             env->pc += 4;
 168             break;
 169         case EXCP_YIELD:
 170             /* nothing to do here for user-mode, just resume guest code */
 171             break;
 172         case EXCP_ATOMIC:
 173             cpu_exec_step_atomic(cs);
 174             break;
 175         default:
 176             EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
 177             abort();
 178         }
 179
 180         /* Check for MTE asynchronous faults */
 181         if (unlikely(env->cp15.tfsr_el[0])) {
 182             env->cp15.tfsr_el[0] = 0;
 183             force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0);
 184         }
 185
 186         process_pending_signals(env);
 187         /* Exception return on AArch64 always clears the exclusive monitor,
 188          * so any return to running guest code implies this.
 189          */
 190         env->exclusive_addr = -1;
 191     }
 192 }
 193
 194 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
 195 {
 196     ARMCPU *cpu = env_archcpu(env);
 197     CPUState *cs = env_cpu(env);
 198     TaskState *ts = cs->opaque;
 199     struct image_info *info = ts->info;
 200     int i;
 201
 202     if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
 203         fprintf(stderr,
 204                 "The selected ARM CPU does not support 64 bit mode\n");
 205         exit(EXIT_FAILURE);
 206     }
 207
 208     for (i = 0; i < 31; i++) {
 209         env->xregs[i] = regs->regs[i];
 210     }
 211     env->pc = regs->pc;
 212     env->xregs[31] = regs->sp;
 213 #if TARGET_BIG_ENDIAN
 214     env->cp15.sctlr_el[1] |= SCTLR_E0E;
 215     for (i = 1; i < 4; ++i) {
 216         env->cp15.sctlr_el[i] |= SCTLR_EE;
 217     }
 218     arm_rebuild_hflags(env);
 219 #endif
 220
 221     if (cpu_isar_feature(aa64_pauth, cpu)) {
 222         qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
 223     }
 224
 225     ts->stack_base = info->start_stack;
 226     ts->heap_base = info->brk;
 227     /* This will be filled in on the first SYS_HEAPINFO call.  */
 228     ts->heap_limit = 0;
 229 }