2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/timer.h"
24 #include "qemu/module.h"
25 #include "qemu/queue.h"
26 #include "migration/vmstate.h"
27 #include "hw/qdev-properties.h"
29 #include "qapi/error.h"
37 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
39 #define DPRINTF(...) do {} while (0)
41 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
42 __func__, __LINE__, _msg); abort(); } while (0)
44 #define TRB_LINK_LIMIT 32
45 #define COMMAND_LIMIT 256
46 #define TRANSFER_LIMIT 256
49 #define LEN_OPER (0x400 + 0x10 * XHCI_MAXPORTS)
50 #define LEN_RUNTIME ((XHCI_MAXINTRS + 1) * 0x20)
51 #define LEN_DOORBELL ((XHCI_MAXSLOTS + 1) * 0x20)
53 #define OFF_OPER LEN_CAP
54 #define OFF_RUNTIME 0x1000
55 #define OFF_DOORBELL 0x2000
57 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
58 #error Increase OFF_RUNTIME
60 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
61 #error Increase OFF_DOORBELL
63 #if (OFF_DOORBELL + LEN_DOORBELL) > XHCI_LEN_REGS
64 # error Increase XHCI_LEN_REGS
68 #define USBCMD_RS (1<<0)
69 #define USBCMD_HCRST (1<<1)
70 #define USBCMD_INTE (1<<2)
71 #define USBCMD_HSEE (1<<3)
72 #define USBCMD_LHCRST (1<<7)
73 #define USBCMD_CSS (1<<8)
74 #define USBCMD_CRS (1<<9)
75 #define USBCMD_EWE (1<<10)
76 #define USBCMD_EU3S (1<<11)
78 #define USBSTS_HCH (1<<0)
79 #define USBSTS_HSE (1<<2)
80 #define USBSTS_EINT (1<<3)
81 #define USBSTS_PCD (1<<4)
82 #define USBSTS_SSS (1<<8)
83 #define USBSTS_RSS (1<<9)
84 #define USBSTS_SRE (1<<10)
85 #define USBSTS_CNR (1<<11)
86 #define USBSTS_HCE (1<<12)
89 #define PORTSC_CCS (1<<0)
90 #define PORTSC_PED (1<<1)
91 #define PORTSC_OCA (1<<3)
92 #define PORTSC_PR (1<<4)
93 #define PORTSC_PLS_SHIFT 5
94 #define PORTSC_PLS_MASK 0xf
95 #define PORTSC_PP (1<<9)
96 #define PORTSC_SPEED_SHIFT 10
97 #define PORTSC_SPEED_MASK 0xf
98 #define PORTSC_SPEED_FULL (1<<10)
99 #define PORTSC_SPEED_LOW (2<<10)
100 #define PORTSC_SPEED_HIGH (3<<10)
101 #define PORTSC_SPEED_SUPER (4<<10)
102 #define PORTSC_PIC_SHIFT 14
103 #define PORTSC_PIC_MASK 0x3
104 #define PORTSC_LWS (1<<16)
105 #define PORTSC_CSC (1<<17)
106 #define PORTSC_PEC (1<<18)
107 #define PORTSC_WRC (1<<19)
108 #define PORTSC_OCC (1<<20)
109 #define PORTSC_PRC (1<<21)
110 #define PORTSC_PLC (1<<22)
111 #define PORTSC_CEC (1<<23)
112 #define PORTSC_CAS (1<<24)
113 #define PORTSC_WCE (1<<25)
114 #define PORTSC_WDE (1<<26)
115 #define PORTSC_WOE (1<<27)
116 #define PORTSC_DR (1<<30)
117 #define PORTSC_WPR (1<<31)
119 #define CRCR_RCS (1<<0)
120 #define CRCR_CS (1<<1)
121 #define CRCR_CA (1<<2)
122 #define CRCR_CRR (1<<3)
124 #define IMAN_IP (1<<0)
125 #define IMAN_IE (1<<1)
127 #define ERDP_EHB (1<<3)
130 typedef struct XHCITRB
{
149 PLS_COMPILANCE_MODE
= 10,
154 #define CR_LINK TR_LINK
157 #define TRB_TYPE_SHIFT 10
158 #define TRB_TYPE_MASK 0x3f
159 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
161 #define TRB_EV_ED (1<<2)
163 #define TRB_TR_ENT (1<<1)
164 #define TRB_TR_ISP (1<<2)
165 #define TRB_TR_NS (1<<3)
166 #define TRB_TR_CH (1<<4)
167 #define TRB_TR_IOC (1<<5)
168 #define TRB_TR_IDT (1<<6)
169 #define TRB_TR_TBC_SHIFT 7
170 #define TRB_TR_TBC_MASK 0x3
171 #define TRB_TR_BEI (1<<9)
172 #define TRB_TR_TLBPC_SHIFT 16
173 #define TRB_TR_TLBPC_MASK 0xf
174 #define TRB_TR_FRAMEID_SHIFT 20
175 #define TRB_TR_FRAMEID_MASK 0x7ff
176 #define TRB_TR_SIA (1<<31)
178 #define TRB_TR_DIR (1<<16)
180 #define TRB_CR_SLOTID_SHIFT 24
181 #define TRB_CR_SLOTID_MASK 0xff
182 #define TRB_CR_EPID_SHIFT 16
183 #define TRB_CR_EPID_MASK 0x1f
185 #define TRB_CR_BSR (1<<9)
186 #define TRB_CR_DC (1<<9)
188 #define TRB_LK_TC (1<<1)
190 #define TRB_INTR_SHIFT 22
191 #define TRB_INTR_MASK 0x3ff
192 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
194 #define EP_TYPE_MASK 0x7
195 #define EP_TYPE_SHIFT 3
197 #define EP_STATE_MASK 0x7
198 #define EP_DISABLED (0<<0)
199 #define EP_RUNNING (1<<0)
200 #define EP_HALTED (2<<0)
201 #define EP_STOPPED (3<<0)
202 #define EP_ERROR (4<<0)
204 #define SLOT_STATE_MASK 0x1f
205 #define SLOT_STATE_SHIFT 27
206 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
207 #define SLOT_ENABLED 0
208 #define SLOT_DEFAULT 1
209 #define SLOT_ADDRESSED 2
210 #define SLOT_CONFIGURED 3
212 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
213 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
215 #define get_field(data, field) \
216 (((data) >> field##_SHIFT) & field##_MASK)
218 #define set_field(data, newval, field) do { \
219 uint32_t val = *data; \
220 val &= ~(field##_MASK << field##_SHIFT); \
221 val |= ((newval) & field##_MASK) << field##_SHIFT; \
225 typedef enum EPType
{
236 typedef struct XHCITransfer
{
237 XHCIEPContext
*epctx
;
244 unsigned int iso_pkts
;
245 unsigned int streamid
;
250 unsigned int trb_count
;
256 unsigned int pktsize
;
257 unsigned int cur_pkt
;
259 uint64_t mfindex_kick
;
261 QTAILQ_ENTRY(XHCITransfer
) next
;
264 struct XHCIStreamContext
{
270 struct XHCIEPContext
{
277 QTAILQ_HEAD(, XHCITransfer
) transfers
;
281 unsigned int max_psize
;
283 uint32_t kick_active
;
286 unsigned int max_pstreams
;
288 unsigned int nr_pstreams
;
289 XHCIStreamContext
*pstreams
;
291 /* iso xfer scheduling */
292 unsigned int interval
;
293 int64_t mfindex_last
;
294 QEMUTimer
*kick_timer
;
297 typedef struct XHCIEvRingSeg
{
304 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
305 unsigned int epid
, unsigned int streamid
);
306 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
);
307 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
309 static void xhci_xfer_report(XHCITransfer
*xfer
);
310 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
311 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
312 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
);
314 static const char *TRBType_names
[] = {
315 [TRB_RESERVED
] = "TRB_RESERVED",
316 [TR_NORMAL
] = "TR_NORMAL",
317 [TR_SETUP
] = "TR_SETUP",
318 [TR_DATA
] = "TR_DATA",
319 [TR_STATUS
] = "TR_STATUS",
320 [TR_ISOCH
] = "TR_ISOCH",
321 [TR_LINK
] = "TR_LINK",
322 [TR_EVDATA
] = "TR_EVDATA",
323 [TR_NOOP
] = "TR_NOOP",
324 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
325 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
326 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
327 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
328 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
329 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
330 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
331 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
332 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
333 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
334 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
335 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
336 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
337 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
338 [CR_NOOP
] = "CR_NOOP",
339 [ER_TRANSFER
] = "ER_TRANSFER",
340 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
341 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
342 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
343 [ER_DOORBELL
] = "ER_DOORBELL",
344 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
345 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
346 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
347 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
348 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
351 static const char *TRBCCode_names
[] = {
352 [CC_INVALID
] = "CC_INVALID",
353 [CC_SUCCESS
] = "CC_SUCCESS",
354 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
355 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
356 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
357 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
358 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
359 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
360 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
361 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
362 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
363 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
364 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
365 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
366 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
367 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
368 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
369 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
370 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
371 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
372 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
373 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
374 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
375 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
376 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
377 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
378 [CC_STOPPED
] = "CC_STOPPED",
379 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
380 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
381 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
382 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
383 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
384 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
385 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
386 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
387 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
390 static const char *ep_state_names
[] = {
391 [EP_DISABLED
] = "disabled",
392 [EP_RUNNING
] = "running",
393 [EP_HALTED
] = "halted",
394 [EP_STOPPED
] = "stopped",
395 [EP_ERROR
] = "error",
398 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
400 if (index
>= llen
|| list
[index
] == NULL
) {
406 static const char *trb_name(XHCITRB
*trb
)
408 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
409 ARRAY_SIZE(TRBType_names
));
412 static const char *event_name(XHCIEvent
*event
)
414 return lookup_name(event
->ccode
, TRBCCode_names
,
415 ARRAY_SIZE(TRBCCode_names
));
418 static const char *ep_state_name(uint32_t state
)
420 return lookup_name(state
, ep_state_names
,
421 ARRAY_SIZE(ep_state_names
));
424 bool xhci_get_flag(XHCIState
*xhci
, enum xhci_flags bit
)
426 return xhci
->flags
& (1 << bit
);
429 void xhci_set_flag(XHCIState
*xhci
, enum xhci_flags bit
)
431 xhci
->flags
|= (1 << bit
);
434 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
436 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
437 return (now
- xhci
->mfindex_start
) / 125000;
440 static void xhci_mfwrap_update(XHCIState
*xhci
)
442 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
443 uint32_t mfindex
, left
;
446 if ((xhci
->usbcmd
& bits
) == bits
) {
447 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
448 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
449 left
= 0x4000 - mfindex
;
450 timer_mod(xhci
->mfwrap_timer
, now
+ left
* 125000);
452 timer_del(xhci
->mfwrap_timer
);
456 static void xhci_mfwrap_timer(void *opaque
)
458 XHCIState
*xhci
= opaque
;
459 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
461 xhci_event(xhci
, &wrap
, 0);
462 xhci_mfwrap_update(xhci
);
465 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
467 if (sizeof(dma_addr_t
) == 4) {
470 return low
| (((dma_addr_t
)high
<< 16) << 16);
474 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
476 if (sizeof(dma_addr_t
) == 4) {
477 return addr
& 0xffffffff;
483 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
484 uint32_t *buf
, size_t len
)
488 assert((len
% sizeof(uint32_t)) == 0);
490 dma_memory_read(xhci
->as
, addr
, buf
, len
, MEMTXATTRS_UNSPECIFIED
);
492 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
493 buf
[i
] = le32_to_cpu(buf
[i
]);
497 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
498 uint32_t *buf
, size_t len
)
502 uint32_t n
= len
/ sizeof(uint32_t);
504 assert((len
% sizeof(uint32_t)) == 0);
505 assert(n
<= ARRAY_SIZE(tmp
));
507 for (i
= 0; i
< n
; i
++) {
508 tmp
[i
] = cpu_to_le32(buf
[i
]);
510 dma_memory_write(xhci
->as
, addr
, tmp
, len
, MEMTXATTRS_UNSPECIFIED
);
513 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
520 switch (uport
->dev
->speed
) {
524 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
525 index
= uport
->index
+ xhci
->numports_3
;
527 index
= uport
->index
;
530 case USB_SPEED_SUPER
:
531 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
532 index
= uport
->index
;
534 index
= uport
->index
+ xhci
->numports_2
;
540 return &xhci
->ports
[index
];
543 static void xhci_intr_update(XHCIState
*xhci
, int v
)
548 if (xhci
->intr
[0].iman
& IMAN_IP
&&
549 xhci
->intr
[0].iman
& IMAN_IE
&&
550 xhci
->usbcmd
& USBCMD_INTE
) {
553 if (xhci
->intr_raise
) {
554 if (xhci
->intr_raise(xhci
, 0, level
)) {
555 xhci
->intr
[0].iman
&= ~IMAN_IP
;
559 if (xhci
->intr_update
) {
560 xhci
->intr_update(xhci
, v
,
561 xhci
->intr
[v
].iman
& IMAN_IE
);
565 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
567 bool pending
= (xhci
->intr
[v
].erdp_low
& ERDP_EHB
);
569 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
570 xhci
->intr
[v
].iman
|= IMAN_IP
;
571 xhci
->usbsts
|= USBSTS_EINT
;
576 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
580 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
583 if (xhci
->intr_raise
) {
584 if (xhci
->intr_raise(xhci
, v
, true)) {
585 xhci
->intr
[v
].iman
&= ~IMAN_IP
;
590 static inline int xhci_running(XHCIState
*xhci
)
592 return !(xhci
->usbsts
& USBSTS_HCH
);
595 static void xhci_die(XHCIState
*xhci
)
597 xhci
->usbsts
|= USBSTS_HCE
;
598 DPRINTF("xhci: asserted controller error\n");
601 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
603 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
607 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
608 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
609 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
610 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
612 ev_trb
.control
|= TRB_C
;
614 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
616 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
617 event_name(event
), ev_trb
.parameter
,
618 ev_trb
.status
, ev_trb
.control
);
620 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
621 dma_memory_write(xhci
->as
, addr
, &ev_trb
, TRB_SIZE
, MEMTXATTRS_UNSPECIFIED
);
624 if (intr
->er_ep_idx
>= intr
->er_size
) {
626 intr
->er_pcs
= !intr
->er_pcs
;
630 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
632 XHCIInterrupter
*intr
;
636 if (v
>= xhci
->numintrs
) {
637 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
640 intr
= &xhci
->intr
[v
];
642 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
643 if (erdp
< intr
->er_start
||
644 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
645 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
646 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
647 v
, intr
->er_start
, intr
->er_size
);
652 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
653 assert(dp_idx
< intr
->er_size
);
655 if ((intr
->er_ep_idx
+ 2) % intr
->er_size
== dp_idx
) {
656 DPRINTF("xhci: ER %d full, send ring full error\n", v
);
657 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
658 xhci_write_event(xhci
, &full
, v
);
659 } else if ((intr
->er_ep_idx
+ 1) % intr
->er_size
== dp_idx
) {
660 DPRINTF("xhci: ER %d full, drop event\n", v
);
662 xhci_write_event(xhci
, event
, v
);
665 xhci_intr_raise(xhci
, v
);
668 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
671 ring
->dequeue
= base
;
675 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
678 uint32_t link_cnt
= 0;
682 dma_memory_read(xhci
->as
, ring
->dequeue
, trb
, TRB_SIZE
,
683 MEMTXATTRS_UNSPECIFIED
);
684 trb
->addr
= ring
->dequeue
;
685 trb
->ccs
= ring
->ccs
;
686 le64_to_cpus(&trb
->parameter
);
687 le32_to_cpus(&trb
->status
);
688 le32_to_cpus(&trb
->control
);
690 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
691 trb
->parameter
, trb
->status
, trb
->control
);
693 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
697 type
= TRB_TYPE(*trb
);
699 if (type
!= TR_LINK
) {
701 *addr
= ring
->dequeue
;
703 ring
->dequeue
+= TRB_SIZE
;
706 if (++link_cnt
> TRB_LINK_LIMIT
) {
707 trace_usb_xhci_enforced_limit("trb-link");
710 ring
->dequeue
= xhci_mask64(trb
->parameter
);
711 if (trb
->control
& TRB_LK_TC
) {
712 ring
->ccs
= !ring
->ccs
;
718 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
722 dma_addr_t dequeue
= ring
->dequeue
;
723 bool ccs
= ring
->ccs
;
724 /* hack to bundle together the two/three TDs that make a setup transfer */
725 bool control_td_set
= 0;
726 uint32_t link_cnt
= 0;
730 dma_memory_read(xhci
->as
, dequeue
, &trb
, TRB_SIZE
,
731 MEMTXATTRS_UNSPECIFIED
);
732 le64_to_cpus(&trb
.parameter
);
733 le32_to_cpus(&trb
.status
);
734 le32_to_cpus(&trb
.control
);
736 if ((trb
.control
& TRB_C
) != ccs
) {
740 type
= TRB_TYPE(trb
);
742 if (type
== TR_LINK
) {
743 if (++link_cnt
> TRB_LINK_LIMIT
) {
746 dequeue
= xhci_mask64(trb
.parameter
);
747 if (trb
.control
& TRB_LK_TC
) {
756 if (type
== TR_SETUP
) {
758 } else if (type
== TR_STATUS
) {
762 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
768 static void xhci_er_reset(XHCIState
*xhci
, int v
)
770 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
772 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
774 if (intr
->erstsz
== 0 || erstba
== 0) {
780 /* cache the (sole) event ring segment location */
781 if (intr
->erstsz
!= 1) {
782 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
786 dma_memory_read(xhci
->as
, erstba
, &seg
, sizeof(seg
),
787 MEMTXATTRS_UNSPECIFIED
);
788 le32_to_cpus(&seg
.addr_low
);
789 le32_to_cpus(&seg
.addr_high
);
790 le32_to_cpus(&seg
.size
);
791 if (seg
.size
< 16 || seg
.size
> 4096) {
792 DPRINTF("xhci: invalid value for segment size: %d\n", seg
.size
);
796 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
797 intr
->er_size
= seg
.size
;
802 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
803 v
, intr
->er_start
, intr
->er_size
);
806 static void xhci_run(XHCIState
*xhci
)
808 trace_usb_xhci_run();
809 xhci
->usbsts
&= ~USBSTS_HCH
;
810 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
813 static void xhci_stop(XHCIState
*xhci
)
815 trace_usb_xhci_stop();
816 xhci
->usbsts
|= USBSTS_HCH
;
817 xhci
->crcr_low
&= ~CRCR_CRR
;
820 static XHCIStreamContext
*xhci_alloc_stream_contexts(unsigned count
,
823 XHCIStreamContext
*stctx
;
826 stctx
= g_new0(XHCIStreamContext
, count
);
827 for (i
= 0; i
< count
; i
++) {
828 stctx
[i
].pctx
= base
+ i
* 16;
834 static void xhci_reset_streams(XHCIEPContext
*epctx
)
838 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
839 epctx
->pstreams
[i
].sct
= -1;
843 static void xhci_alloc_streams(XHCIEPContext
*epctx
, dma_addr_t base
)
845 assert(epctx
->pstreams
== NULL
);
846 epctx
->nr_pstreams
= 2 << epctx
->max_pstreams
;
847 epctx
->pstreams
= xhci_alloc_stream_contexts(epctx
->nr_pstreams
, base
);
850 static void xhci_free_streams(XHCIEPContext
*epctx
)
852 assert(epctx
->pstreams
!= NULL
);
854 g_free(epctx
->pstreams
);
855 epctx
->pstreams
= NULL
;
856 epctx
->nr_pstreams
= 0;
859 static int xhci_epmask_to_eps_with_streams(XHCIState
*xhci
,
862 XHCIEPContext
**epctxs
,
866 XHCIEPContext
*epctx
;
870 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
872 slot
= &xhci
->slots
[slotid
- 1];
874 for (i
= 2, j
= 0; i
<= 31; i
++) {
875 if (!(epmask
& (1u << i
))) {
879 epctx
= slot
->eps
[i
- 1];
880 ep
= xhci_epid_to_usbep(epctx
);
881 if (!epctx
|| !epctx
->nr_pstreams
|| !ep
) {
893 static void xhci_free_device_streams(XHCIState
*xhci
, unsigned int slotid
,
896 USBEndpoint
*eps
[30];
899 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, NULL
, eps
);
901 usb_device_free_streams(eps
[0]->dev
, eps
, nr_eps
);
905 static TRBCCode
xhci_alloc_device_streams(XHCIState
*xhci
, unsigned int slotid
,
908 XHCIEPContext
*epctxs
[30];
909 USBEndpoint
*eps
[30];
910 int i
, r
, nr_eps
, req_nr_streams
, dev_max_streams
;
912 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, epctxs
,
918 req_nr_streams
= epctxs
[0]->nr_pstreams
;
919 dev_max_streams
= eps
[0]->max_streams
;
921 for (i
= 1; i
< nr_eps
; i
++) {
923 * HdG: I don't expect these to ever trigger, but if they do we need
924 * to come up with another solution, ie group identical endpoints
925 * together and make an usb_device_alloc_streams call per group.
927 if (epctxs
[i
]->nr_pstreams
!= req_nr_streams
) {
928 FIXME("guest streams config not identical for all eps");
929 return CC_RESOURCE_ERROR
;
931 if (eps
[i
]->max_streams
!= dev_max_streams
) {
932 FIXME("device streams config not identical for all eps");
933 return CC_RESOURCE_ERROR
;
938 * max-streams in both the device descriptor and in the controller is a
939 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
940 * streams the guest will ask for 5 rounded up to the next power of 2 which
941 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
943 * For redirected devices however this is an issue, as there we must ask
944 * the real xhci controller to alloc streams, and the host driver for the
945 * real xhci controller will likely disallow allocating more streams then
946 * the device can handle.
948 * So we limit the requested nr_streams to the maximum number the device
951 if (req_nr_streams
> dev_max_streams
) {
952 req_nr_streams
= dev_max_streams
;
955 r
= usb_device_alloc_streams(eps
[0]->dev
, eps
, nr_eps
, req_nr_streams
);
957 DPRINTF("xhci: alloc streams failed\n");
958 return CC_RESOURCE_ERROR
;
964 static XHCIStreamContext
*xhci_find_stream(XHCIEPContext
*epctx
,
965 unsigned int streamid
,
968 XHCIStreamContext
*sctx
;
970 uint32_t ctx
[2], sct
;
972 assert(streamid
!= 0);
974 if (streamid
>= epctx
->nr_pstreams
) {
975 *cc_error
= CC_INVALID_STREAM_ID_ERROR
;
978 sctx
= epctx
->pstreams
+ streamid
;
980 FIXME("secondary streams not implemented yet");
983 if (sctx
->sct
== -1) {
984 xhci_dma_read_u32s(epctx
->xhci
, sctx
->pctx
, ctx
, sizeof(ctx
));
985 sct
= (ctx
[0] >> 1) & 0x07;
986 if (epctx
->lsa
&& sct
!= 1) {
987 *cc_error
= CC_INVALID_STREAM_TYPE_ERROR
;
991 base
= xhci_addr64(ctx
[0] & ~0xf, ctx
[1]);
992 xhci_ring_init(epctx
->xhci
, &sctx
->ring
, base
);
997 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
998 XHCIStreamContext
*sctx
, uint32_t state
)
1000 XHCIRing
*ring
= NULL
;
1004 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1005 ctx
[0] &= ~EP_STATE_MASK
;
1008 /* update ring dequeue ptr */
1009 if (epctx
->nr_pstreams
) {
1012 xhci_dma_read_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1014 ctx2
[0] |= sctx
->ring
.dequeue
| sctx
->ring
.ccs
;
1015 ctx2
[1] = (sctx
->ring
.dequeue
>> 16) >> 16;
1016 xhci_dma_write_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1019 ring
= &epctx
->ring
;
1022 ctx
[2] = ring
->dequeue
| ring
->ccs
;
1023 ctx
[3] = (ring
->dequeue
>> 16) >> 16;
1025 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1026 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1029 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1030 if (epctx
->state
!= state
) {
1031 trace_usb_xhci_ep_state(epctx
->slotid
, epctx
->epid
,
1032 ep_state_name(epctx
->state
),
1033 ep_state_name(state
));
1035 epctx
->state
= state
;
1038 static void xhci_ep_kick_timer(void *opaque
)
1040 XHCIEPContext
*epctx
= opaque
;
1041 xhci_kick_epctx(epctx
, 0);
1044 static XHCIEPContext
*xhci_alloc_epctx(XHCIState
*xhci
,
1045 unsigned int slotid
,
1048 XHCIEPContext
*epctx
;
1050 epctx
= g_new0(XHCIEPContext
, 1);
1052 epctx
->slotid
= slotid
;
1055 QTAILQ_INIT(&epctx
->transfers
);
1056 epctx
->kick_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_ep_kick_timer
, epctx
);
1061 static void xhci_init_epctx(XHCIEPContext
*epctx
,
1062 dma_addr_t pctx
, uint32_t *ctx
)
1066 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1068 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1070 epctx
->max_psize
= ctx
[1]>>16;
1071 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1072 epctx
->max_pstreams
= (ctx
[0] >> 10) & epctx
->xhci
->max_pstreams_mask
;
1073 epctx
->lsa
= (ctx
[0] >> 15) & 1;
1074 if (epctx
->max_pstreams
) {
1075 xhci_alloc_streams(epctx
, dequeue
);
1077 xhci_ring_init(epctx
->xhci
, &epctx
->ring
, dequeue
);
1078 epctx
->ring
.ccs
= ctx
[2] & 1;
1081 epctx
->interval
= 1 << ((ctx
[0] >> 16) & 0xff);
1084 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1085 unsigned int epid
, dma_addr_t pctx
,
1089 XHCIEPContext
*epctx
;
1091 trace_usb_xhci_ep_enable(slotid
, epid
);
1092 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1093 assert(epid
>= 1 && epid
<= 31);
1095 slot
= &xhci
->slots
[slotid
-1];
1096 if (slot
->eps
[epid
-1]) {
1097 xhci_disable_ep(xhci
, slotid
, epid
);
1100 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
1101 slot
->eps
[epid
-1] = epctx
;
1102 xhci_init_epctx(epctx
, pctx
, ctx
);
1104 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1105 "size is %d\n", epid
/2, epid
%2, epctx
->type
, epctx
->max_psize
);
1107 epctx
->mfindex_last
= 0;
1109 epctx
->state
= EP_RUNNING
;
1110 ctx
[0] &= ~EP_STATE_MASK
;
1111 ctx
[0] |= EP_RUNNING
;
1116 static XHCITransfer
*xhci_ep_alloc_xfer(XHCIEPContext
*epctx
,
1119 uint32_t limit
= epctx
->nr_pstreams
+ 16;
1122 if (epctx
->xfer_count
>= limit
) {
1126 xfer
= g_new0(XHCITransfer
, 1);
1127 xfer
->epctx
= epctx
;
1128 xfer
->trbs
= g_new(XHCITRB
, length
);
1129 xfer
->trb_count
= length
;
1130 usb_packet_init(&xfer
->packet
);
1132 QTAILQ_INSERT_TAIL(&epctx
->transfers
, xfer
, next
);
1133 epctx
->xfer_count
++;
1138 static void xhci_ep_free_xfer(XHCITransfer
*xfer
)
1140 QTAILQ_REMOVE(&xfer
->epctx
->transfers
, xfer
, next
);
1141 xfer
->epctx
->xfer_count
--;
1143 usb_packet_cleanup(&xfer
->packet
);
1148 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
, TRBCCode report
)
1152 if (report
&& (t
->running_async
|| t
->running_retry
)) {
1154 xhci_xfer_report(t
);
1157 if (t
->running_async
) {
1158 usb_cancel_packet(&t
->packet
);
1159 t
->running_async
= 0;
1162 if (t
->running_retry
) {
1164 t
->epctx
->retry
= NULL
;
1165 timer_del(t
->epctx
->kick_timer
);
1167 t
->running_retry
= 0;
1178 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1179 unsigned int epid
, TRBCCode report
)
1182 XHCIEPContext
*epctx
;
1185 USBEndpoint
*ep
= NULL
;
1186 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1187 assert(epid
>= 1 && epid
<= 31);
1189 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1191 slot
= &xhci
->slots
[slotid
-1];
1193 if (!slot
->eps
[epid
-1]) {
1197 epctx
= slot
->eps
[epid
-1];
1200 xfer
= QTAILQ_FIRST(&epctx
->transfers
);
1204 killed
+= xhci_ep_nuke_one_xfer(xfer
, report
);
1206 report
= 0; /* Only report once */
1208 xhci_ep_free_xfer(xfer
);
1211 ep
= xhci_epid_to_usbep(epctx
);
1213 usb_device_ep_stopped(ep
->dev
, ep
);
1218 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1222 XHCIEPContext
*epctx
;
1224 trace_usb_xhci_ep_disable(slotid
, epid
);
1225 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1226 assert(epid
>= 1 && epid
<= 31);
1228 slot
= &xhci
->slots
[slotid
-1];
1230 if (!slot
->eps
[epid
-1]) {
1231 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1235 xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0);
1237 epctx
= slot
->eps
[epid
-1];
1239 if (epctx
->nr_pstreams
) {
1240 xhci_free_streams(epctx
);
1243 /* only touch guest RAM if we're not resetting the HC */
1244 if (xhci
->dcbaap_low
|| xhci
->dcbaap_high
) {
1245 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_DISABLED
);
1248 timer_free(epctx
->kick_timer
);
1250 slot
->eps
[epid
-1] = NULL
;
1255 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1259 XHCIEPContext
*epctx
;
1261 trace_usb_xhci_ep_stop(slotid
, epid
);
1262 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1264 if (epid
< 1 || epid
> 31) {
1265 DPRINTF("xhci: bad ep %d\n", epid
);
1266 return CC_TRB_ERROR
;
1269 slot
= &xhci
->slots
[slotid
-1];
1271 if (!slot
->eps
[epid
-1]) {
1272 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1273 return CC_EP_NOT_ENABLED_ERROR
;
1276 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, CC_STOPPED
) > 0) {
1277 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1278 "data might be lost\n");
1281 epctx
= slot
->eps
[epid
-1];
1283 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1285 if (epctx
->nr_pstreams
) {
1286 xhci_reset_streams(epctx
);
1292 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1296 XHCIEPContext
*epctx
;
1298 trace_usb_xhci_ep_reset(slotid
, epid
);
1299 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1301 if (epid
< 1 || epid
> 31) {
1302 DPRINTF("xhci: bad ep %d\n", epid
);
1303 return CC_TRB_ERROR
;
1306 slot
= &xhci
->slots
[slotid
-1];
1308 if (!slot
->eps
[epid
-1]) {
1309 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1310 return CC_EP_NOT_ENABLED_ERROR
;
1313 epctx
= slot
->eps
[epid
-1];
1315 if (epctx
->state
!= EP_HALTED
) {
1316 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1317 epid
, epctx
->state
);
1318 return CC_CONTEXT_STATE_ERROR
;
1321 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0) > 0) {
1322 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1323 "data might be lost\n");
1326 if (!xhci
->slots
[slotid
-1].uport
||
1327 !xhci
->slots
[slotid
-1].uport
->dev
||
1328 !xhci
->slots
[slotid
-1].uport
->dev
->attached
) {
1329 return CC_USB_TRANSACTION_ERROR
;
1332 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1334 if (epctx
->nr_pstreams
) {
1335 xhci_reset_streams(epctx
);
1341 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1342 unsigned int epid
, unsigned int streamid
,
1346 XHCIEPContext
*epctx
;
1347 XHCIStreamContext
*sctx
;
1350 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1352 if (epid
< 1 || epid
> 31) {
1353 DPRINTF("xhci: bad ep %d\n", epid
);
1354 return CC_TRB_ERROR
;
1357 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, streamid
, pdequeue
);
1358 dequeue
= xhci_mask64(pdequeue
);
1360 slot
= &xhci
->slots
[slotid
-1];
1362 if (!slot
->eps
[epid
-1]) {
1363 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1364 return CC_EP_NOT_ENABLED_ERROR
;
1367 epctx
= slot
->eps
[epid
-1];
1369 if (epctx
->state
!= EP_STOPPED
) {
1370 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1371 return CC_CONTEXT_STATE_ERROR
;
1374 if (epctx
->nr_pstreams
) {
1376 sctx
= xhci_find_stream(epctx
, streamid
, &err
);
1380 xhci_ring_init(xhci
, &sctx
->ring
, dequeue
& ~0xf);
1381 sctx
->ring
.ccs
= dequeue
& 1;
1384 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1385 epctx
->ring
.ccs
= dequeue
& 1;
1388 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_STOPPED
);
1393 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1395 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1398 xfer
->int_req
= false;
1399 qemu_sglist_init(&xfer
->sgl
, DEVICE(xhci
), xfer
->trb_count
, xhci
->as
);
1400 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1401 XHCITRB
*trb
= &xfer
->trbs
[i
];
1403 unsigned int chunk
= 0;
1405 if (trb
->control
& TRB_TR_IOC
) {
1406 xfer
->int_req
= true;
1409 switch (TRB_TYPE(*trb
)) {
1411 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1412 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1418 addr
= xhci_mask64(trb
->parameter
);
1419 chunk
= trb
->status
& 0x1ffff;
1420 if (trb
->control
& TRB_TR_IDT
) {
1421 if (chunk
> 8 || in_xfer
) {
1422 DPRINTF("xhci: invalid immediate data TRB\n");
1425 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1427 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1436 qemu_sglist_destroy(&xfer
->sgl
);
1441 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1443 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1444 qemu_sglist_destroy(&xfer
->sgl
);
1447 static void xhci_xfer_report(XHCITransfer
*xfer
)
1453 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1454 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1457 left
= xfer
->packet
.actual_length
;
1459 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1460 XHCITRB
*trb
= &xfer
->trbs
[i
];
1461 unsigned int chunk
= 0;
1463 switch (TRB_TYPE(*trb
)) {
1465 chunk
= trb
->status
& 0x1ffff;
1473 chunk
= trb
->status
& 0x1ffff;
1476 if (xfer
->status
== CC_SUCCESS
) {
1489 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1490 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1491 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1492 event
.slotid
= xfer
->epctx
->slotid
;
1493 event
.epid
= xfer
->epctx
->epid
;
1494 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1496 event
.ptr
= trb
->addr
;
1497 if (xfer
->status
== CC_SUCCESS
) {
1498 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1500 event
.ccode
= xfer
->status
;
1502 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1503 event
.ptr
= trb
->parameter
;
1504 event
.flags
|= TRB_EV_ED
;
1505 event
.length
= edtla
& 0xffffff;
1506 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1509 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1511 if (xfer
->status
!= CC_SUCCESS
) {
1516 switch (TRB_TYPE(*trb
)) {
1526 static void xhci_stall_ep(XHCITransfer
*xfer
)
1528 XHCIEPContext
*epctx
= xfer
->epctx
;
1529 XHCIState
*xhci
= epctx
->xhci
;
1531 XHCIStreamContext
*sctx
;
1533 if (epctx
->type
== ET_ISO_IN
|| epctx
->type
== ET_ISO_OUT
) {
1534 /* never halt isoch endpoints, 4.10.2 */
1538 if (epctx
->nr_pstreams
) {
1539 sctx
= xhci_find_stream(epctx
, xfer
->streamid
, &err
);
1543 sctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1544 sctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1545 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_HALTED
);
1547 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1548 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1549 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_HALTED
);
1553 static int xhci_setup_packet(XHCITransfer
*xfer
)
1558 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1560 if (xfer
->packet
.ep
) {
1561 ep
= xfer
->packet
.ep
;
1563 ep
= xhci_epid_to_usbep(xfer
->epctx
);
1565 DPRINTF("xhci: slot %d has no device\n",
1566 xfer
->epctx
->slotid
);
1571 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1572 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->streamid
,
1573 xfer
->trbs
[0].addr
, false, xfer
->int_req
);
1574 if (usb_packet_map(&xfer
->packet
, &xfer
->sgl
)) {
1575 qemu_sglist_destroy(&xfer
->sgl
);
1578 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1579 xfer
->packet
.pid
, ep
->dev
->addr
, ep
->nr
);
1583 static int xhci_try_complete_packet(XHCITransfer
*xfer
)
1585 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1586 trace_usb_xhci_xfer_async(xfer
);
1587 xfer
->running_async
= 1;
1588 xfer
->running_retry
= 0;
1591 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1592 trace_usb_xhci_xfer_nak(xfer
);
1593 xfer
->running_async
= 0;
1594 xfer
->running_retry
= 1;
1598 xfer
->running_async
= 0;
1599 xfer
->running_retry
= 0;
1601 xhci_xfer_unmap(xfer
);
1604 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1605 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1606 xfer
->status
= CC_SUCCESS
;
1607 xhci_xfer_report(xfer
);
1612 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1613 switch (xfer
->packet
.status
) {
1615 case USB_RET_IOERROR
:
1616 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1617 xhci_xfer_report(xfer
);
1618 xhci_stall_ep(xfer
);
1621 xfer
->status
= CC_STALL_ERROR
;
1622 xhci_xfer_report(xfer
);
1623 xhci_stall_ep(xfer
);
1625 case USB_RET_BABBLE
:
1626 xfer
->status
= CC_BABBLE_DETECTED
;
1627 xhci_xfer_report(xfer
);
1628 xhci_stall_ep(xfer
);
1631 DPRINTF("%s: FIXME: status = %d\n", __func__
,
1632 xfer
->packet
.status
);
1633 FIXME("unhandled USB_RET_*");
1638 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1640 XHCITRB
*trb_setup
, *trb_status
;
1641 uint8_t bmRequestType
;
1643 trb_setup
= &xfer
->trbs
[0];
1644 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1646 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1647 xfer
->epctx
->epid
, xfer
->streamid
);
1649 /* at most one Event Data TRB allowed after STATUS */
1650 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1654 /* do some sanity checks */
1655 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1656 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1657 TRB_TYPE(*trb_setup
));
1660 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1661 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1662 TRB_TYPE(*trb_status
));
1665 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1666 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1669 if ((trb_setup
->status
& 0x1ffff) != 8) {
1670 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1671 (trb_setup
->status
& 0x1ffff));
1675 bmRequestType
= trb_setup
->parameter
;
1677 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1678 xfer
->iso_xfer
= false;
1679 xfer
->timed_xfer
= false;
1681 if (xhci_setup_packet(xfer
) < 0) {
1684 xfer
->packet
.parameter
= trb_setup
->parameter
;
1686 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1687 xhci_try_complete_packet(xfer
);
1691 static void xhci_calc_intr_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1692 XHCIEPContext
*epctx
, uint64_t mfindex
)
1694 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1695 ~(epctx
->interval
-1));
1696 uint64_t kick
= epctx
->mfindex_last
+ epctx
->interval
;
1698 assert(epctx
->interval
!= 0);
1699 xfer
->mfindex_kick
= MAX(asap
, kick
);
1702 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1703 XHCIEPContext
*epctx
, uint64_t mfindex
)
1705 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1706 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1707 ~(epctx
->interval
-1));
1708 if (asap
>= epctx
->mfindex_last
&&
1709 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1710 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1712 xfer
->mfindex_kick
= asap
;
1715 xfer
->mfindex_kick
= ((xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1716 & TRB_TR_FRAMEID_MASK
) << 3;
1717 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1718 if (xfer
->mfindex_kick
+ 0x100 < mfindex
) {
1719 xfer
->mfindex_kick
+= 0x4000;
1724 static void xhci_check_intr_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1725 XHCIEPContext
*epctx
, uint64_t mfindex
)
1727 if (xfer
->mfindex_kick
> mfindex
) {
1728 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1729 (xfer
->mfindex_kick
- mfindex
) * 125000);
1730 xfer
->running_retry
= 1;
1732 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1733 timer_del(epctx
->kick_timer
);
1734 xfer
->running_retry
= 0;
1739 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1743 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx
->slotid
, epctx
->epid
);
1745 xfer
->in_xfer
= epctx
->type
>>2;
1747 switch(epctx
->type
) {
1751 xfer
->iso_xfer
= false;
1752 xfer
->timed_xfer
= true;
1753 mfindex
= xhci_mfindex_get(xhci
);
1754 xhci_calc_intr_kick(xhci
, xfer
, epctx
, mfindex
);
1755 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1756 if (xfer
->running_retry
) {
1763 xfer
->iso_xfer
= false;
1764 xfer
->timed_xfer
= false;
1769 xfer
->iso_xfer
= true;
1770 xfer
->timed_xfer
= true;
1771 mfindex
= xhci_mfindex_get(xhci
);
1772 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1773 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1774 if (xfer
->running_retry
) {
1779 trace_usb_xhci_unimplemented("endpoint type", epctx
->type
);
1783 if (xhci_setup_packet(xfer
) < 0) {
1786 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1787 xhci_try_complete_packet(xfer
);
1791 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1793 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1794 xfer
->epctx
->epid
, xfer
->streamid
);
1795 return xhci_submit(xhci
, xfer
, epctx
);
1798 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
1799 unsigned int epid
, unsigned int streamid
)
1801 XHCIEPContext
*epctx
;
1803 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1804 assert(epid
>= 1 && epid
<= 31);
1806 if (!xhci
->slots
[slotid
-1].enabled
) {
1807 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1810 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1812 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1817 if (epctx
->kick_active
) {
1820 xhci_kick_epctx(epctx
, streamid
);
1823 static bool xhci_slot_ok(XHCIState
*xhci
, int slotid
)
1825 return (xhci
->slots
[slotid
- 1].uport
&&
1826 xhci
->slots
[slotid
- 1].uport
->dev
&&
1827 xhci
->slots
[slotid
- 1].uport
->dev
->attached
);
1830 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
)
1832 XHCIState
*xhci
= epctx
->xhci
;
1833 XHCIStreamContext
*stctx
= NULL
;
1836 USBEndpoint
*ep
= NULL
;
1838 unsigned int count
= 0;
1842 trace_usb_xhci_ep_kick(epctx
->slotid
, epctx
->epid
, streamid
);
1843 assert(!epctx
->kick_active
);
1845 /* If the device has been detached, but the guest has not noticed this
1846 yet the 2 above checks will succeed, but we must NOT continue */
1847 if (!xhci_slot_ok(xhci
, epctx
->slotid
)) {
1852 XHCITransfer
*xfer
= epctx
->retry
;
1854 trace_usb_xhci_xfer_retry(xfer
);
1855 assert(xfer
->running_retry
);
1856 if (xfer
->timed_xfer
) {
1857 /* time to kick the transfer? */
1858 mfindex
= xhci_mfindex_get(xhci
);
1859 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1860 if (xfer
->running_retry
) {
1863 xfer
->timed_xfer
= 0;
1864 xfer
->running_retry
= 1;
1866 if (xfer
->iso_xfer
) {
1867 /* retry iso transfer */
1868 if (xhci_setup_packet(xfer
) < 0) {
1871 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1872 assert(xfer
->packet
.status
!= USB_RET_NAK
);
1873 xhci_try_complete_packet(xfer
);
1875 /* retry nak'ed transfer */
1876 if (xhci_setup_packet(xfer
) < 0) {
1879 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1880 if (xfer
->packet
.status
== USB_RET_NAK
) {
1881 xhci_xfer_unmap(xfer
);
1884 xhci_try_complete_packet(xfer
);
1886 assert(!xfer
->running_retry
);
1887 if (xfer
->complete
) {
1888 /* update ring dequeue ptr */
1889 xhci_set_ep_state(xhci
, epctx
, stctx
, epctx
->state
);
1890 xhci_ep_free_xfer(epctx
->retry
);
1892 epctx
->retry
= NULL
;
1895 if (epctx
->state
== EP_HALTED
) {
1896 DPRINTF("xhci: ep halted, not running schedule\n");
1901 if (epctx
->nr_pstreams
) {
1903 stctx
= xhci_find_stream(epctx
, streamid
, &err
);
1904 if (stctx
== NULL
) {
1907 ring
= &stctx
->ring
;
1908 xhci_set_ep_state(xhci
, epctx
, stctx
, EP_RUNNING
);
1910 ring
= &epctx
->ring
;
1912 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_RUNNING
);
1914 if (!ring
->dequeue
) {
1918 epctx
->kick_active
++;
1920 length
= xhci_ring_chain_length(xhci
, ring
);
1922 if (epctx
->type
== ET_ISO_OUT
|| epctx
->type
== ET_ISO_IN
) {
1924 XHCIEvent ev
= { ER_TRANSFER
};
1925 ev
.ccode
= epctx
->type
== ET_ISO_IN
?
1926 CC_RING_OVERRUN
: CC_RING_UNDERRUN
;
1927 ev
.slotid
= epctx
->slotid
;
1928 ev
.epid
= epctx
->epid
;
1929 ev
.ptr
= epctx
->ring
.dequeue
;
1930 xhci_event(xhci
, &ev
, xhci
->slots
[epctx
->slotid
-1].intr
);
1934 xfer
= xhci_ep_alloc_xfer(epctx
, length
);
1939 for (i
= 0; i
< length
; i
++) {
1941 type
= xhci_ring_fetch(xhci
, ring
, &xfer
->trbs
[i
], NULL
);
1944 xhci_ep_free_xfer(xfer
);
1945 epctx
->kick_active
--;
1949 xfer
->streamid
= streamid
;
1951 if (epctx
->epid
== 1) {
1952 xhci_fire_ctl_transfer(xhci
, xfer
);
1954 xhci_fire_transfer(xhci
, xfer
, epctx
);
1956 if (!xhci_slot_ok(xhci
, epctx
->slotid
)) {
1957 /* surprise removal -> stop processing */
1960 if (xfer
->complete
) {
1961 /* update ring dequeue ptr */
1962 xhci_set_ep_state(xhci
, epctx
, stctx
, epctx
->state
);
1963 xhci_ep_free_xfer(xfer
);
1967 if (epctx
->state
== EP_HALTED
) {
1970 if (xfer
!= NULL
&& xfer
->running_retry
) {
1971 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1972 epctx
->retry
= xfer
;
1973 xhci_xfer_unmap(xfer
);
1976 if (count
++ > TRANSFER_LIMIT
) {
1977 trace_usb_xhci_enforced_limit("transfers");
1981 epctx
->kick_active
--;
1983 ep
= xhci_epid_to_usbep(epctx
);
1985 usb_device_flush_ep_queue(ep
->dev
, ep
);
1989 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
1991 trace_usb_xhci_slot_enable(slotid
);
1992 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1993 xhci
->slots
[slotid
-1].enabled
= 1;
1994 xhci
->slots
[slotid
-1].uport
= NULL
;
1995 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
2000 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
2004 trace_usb_xhci_slot_disable(slotid
);
2005 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2007 for (i
= 1; i
<= 31; i
++) {
2008 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2009 xhci_disable_ep(xhci
, slotid
, i
);
2013 xhci
->slots
[slotid
-1].enabled
= 0;
2014 xhci
->slots
[slotid
-1].addressed
= 0;
2015 xhci
->slots
[slotid
-1].uport
= NULL
;
2016 xhci
->slots
[slotid
-1].intr
= 0;
2020 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
2026 port
= (slot_ctx
[1]>>16) & 0xFF;
2027 if (port
< 1 || port
> xhci
->numports
) {
2030 port
= xhci
->ports
[port
-1].uport
->index
+1;
2031 pos
= snprintf(path
, sizeof(path
), "%d", port
);
2032 for (i
= 0; i
< 5; i
++) {
2033 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
2037 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
2040 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
2041 if (strcmp(uport
->path
, path
) == 0) {
2048 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
2049 uint64_t pictx
, bool bsr
)
2054 dma_addr_t ictx
, octx
, dcbaap
;
2056 uint32_t ictl_ctx
[2];
2057 uint32_t slot_ctx
[4];
2058 uint32_t ep0_ctx
[5];
2062 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2064 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
2065 ldq_le_dma(xhci
->as
, dcbaap
+ 8 * slotid
, &poctx
, MEMTXATTRS_UNSPECIFIED
);
2066 ictx
= xhci_mask64(pictx
);
2067 octx
= xhci_mask64(poctx
);
2069 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2070 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2072 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2074 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
2075 DPRINTF("xhci: invalid input context control %08x %08x\n",
2076 ictl_ctx
[0], ictl_ctx
[1]);
2077 return CC_TRB_ERROR
;
2080 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
2081 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
2083 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2084 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2086 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2087 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2089 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
2090 if (uport
== NULL
) {
2091 DPRINTF("xhci: port not found\n");
2092 return CC_TRB_ERROR
;
2094 trace_usb_xhci_slot_address(slotid
, uport
->path
);
2097 if (!dev
|| !dev
->attached
) {
2098 DPRINTF("xhci: port %s not connected\n", uport
->path
);
2099 return CC_USB_TRANSACTION_ERROR
;
2102 for (i
= 0; i
< xhci
->numslots
; i
++) {
2103 if (i
== slotid
-1) {
2106 if (xhci
->slots
[i
].uport
== uport
) {
2107 DPRINTF("xhci: port %s already assigned to slot %d\n",
2109 return CC_TRB_ERROR
;
2113 slot
= &xhci
->slots
[slotid
-1];
2114 slot
->uport
= uport
;
2116 slot
->intr
= get_field(slot_ctx
[2], TRB_INTR
);
2118 /* Make sure device is in USB_STATE_DEFAULT state */
2119 usb_device_reset(dev
);
2121 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2126 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slotid
;
2127 memset(&p
, 0, sizeof(p
));
2128 usb_packet_addbuf(&p
, buf
, sizeof(buf
));
2129 usb_packet_setup(&p
, USB_TOKEN_OUT
,
2130 usb_ep_get(dev
, USB_TOKEN_OUT
, 0), 0,
2132 usb_device_handle_control(dev
, &p
,
2133 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
2134 slotid
, 0, 0, NULL
);
2135 assert(p
.status
!= USB_RET_ASYNC
);
2136 usb_packet_cleanup(&p
);
2139 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
2141 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2142 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2143 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2144 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2146 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2147 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2149 xhci
->slots
[slotid
-1].addressed
= 1;
2154 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2155 uint64_t pictx
, bool dc
)
2157 dma_addr_t ictx
, octx
;
2158 uint32_t ictl_ctx
[2];
2159 uint32_t slot_ctx
[4];
2160 uint32_t islot_ctx
[4];
2165 trace_usb_xhci_slot_configure(slotid
);
2166 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2168 ictx
= xhci_mask64(pictx
);
2169 octx
= xhci
->slots
[slotid
-1].ctx
;
2171 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2172 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2175 for (i
= 2; i
<= 31; i
++) {
2176 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2177 xhci_disable_ep(xhci
, slotid
, i
);
2181 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2182 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2183 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2184 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2185 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2186 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2191 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2193 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2194 DPRINTF("xhci: invalid input context control %08x %08x\n",
2195 ictl_ctx
[0], ictl_ctx
[1]);
2196 return CC_TRB_ERROR
;
2199 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2200 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2202 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2203 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx
[3]);
2204 return CC_CONTEXT_STATE_ERROR
;
2207 xhci_free_device_streams(xhci
, slotid
, ictl_ctx
[0] | ictl_ctx
[1]);
2209 for (i
= 2; i
<= 31; i
++) {
2210 if (ictl_ctx
[0] & (1<<i
)) {
2211 xhci_disable_ep(xhci
, slotid
, i
);
2213 if (ictl_ctx
[1] & (1<<i
)) {
2214 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2215 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2216 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2217 ep_ctx
[3], ep_ctx
[4]);
2218 xhci_disable_ep(xhci
, slotid
, i
);
2219 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2220 if (res
!= CC_SUCCESS
) {
2223 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2224 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2225 ep_ctx
[3], ep_ctx
[4]);
2226 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2230 res
= xhci_alloc_device_streams(xhci
, slotid
, ictl_ctx
[1]);
2231 if (res
!= CC_SUCCESS
) {
2232 for (i
= 2; i
<= 31; i
++) {
2233 if (ictl_ctx
[1] & (1u << i
)) {
2234 xhci_disable_ep(xhci
, slotid
, i
);
2240 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2241 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2242 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2243 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2244 SLOT_CONTEXT_ENTRIES_SHIFT
);
2245 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2246 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2248 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2254 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2257 dma_addr_t ictx
, octx
;
2258 uint32_t ictl_ctx
[2];
2259 uint32_t iep0_ctx
[5];
2260 uint32_t ep0_ctx
[5];
2261 uint32_t islot_ctx
[4];
2262 uint32_t slot_ctx
[4];
2264 trace_usb_xhci_slot_evaluate(slotid
);
2265 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2267 ictx
= xhci_mask64(pictx
);
2268 octx
= xhci
->slots
[slotid
-1].ctx
;
2270 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2271 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2273 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2275 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2276 DPRINTF("xhci: invalid input context control %08x %08x\n",
2277 ictl_ctx
[0], ictl_ctx
[1]);
2278 return CC_TRB_ERROR
;
2281 if (ictl_ctx
[1] & 0x1) {
2282 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2284 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2285 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2287 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2289 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2290 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2291 /* update interrupter target field */
2292 xhci
->slots
[slotid
-1].intr
= get_field(islot_ctx
[2], TRB_INTR
);
2293 set_field(&slot_ctx
[2], xhci
->slots
[slotid
-1].intr
, TRB_INTR
);
2295 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2296 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2298 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2301 if (ictl_ctx
[1] & 0x2) {
2302 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2304 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2305 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2306 iep0_ctx
[3], iep0_ctx
[4]);
2308 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2310 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2311 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2313 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2314 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2316 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2322 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2324 uint32_t slot_ctx
[4];
2328 trace_usb_xhci_slot_reset(slotid
);
2329 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2331 octx
= xhci
->slots
[slotid
-1].ctx
;
2333 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2335 for (i
= 2; i
<= 31; i
++) {
2336 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2337 xhci_disable_ep(xhci
, slotid
, i
);
2341 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2342 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2343 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2344 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2345 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2346 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2351 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2353 unsigned int slotid
;
2354 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2355 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2356 DPRINTF("xhci: bad slot id %d\n", slotid
);
2357 event
->ccode
= CC_TRB_ERROR
;
2359 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2360 DPRINTF("xhci: slot id %d not enabled\n", slotid
);
2361 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2367 /* cleanup slot state on usb device detach */
2368 static void xhci_detach_slot(XHCIState
*xhci
, USBPort
*uport
)
2372 for (slot
= 0; slot
< xhci
->numslots
; slot
++) {
2373 if (xhci
->slots
[slot
].uport
== uport
) {
2377 if (slot
== xhci
->numslots
) {
2381 for (ep
= 0; ep
< 31; ep
++) {
2382 if (xhci
->slots
[slot
].eps
[ep
]) {
2383 xhci_ep_nuke_xfers(xhci
, slot
+ 1, ep
+ 1, 0);
2386 xhci
->slots
[slot
].uport
= NULL
;
2389 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2392 uint8_t bw_ctx
[xhci
->numports
+1];
2394 DPRINTF("xhci_get_port_bandwidth()\n");
2396 ctx
= xhci_mask64(pctx
);
2398 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2400 /* TODO: actually implement real values here */
2402 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2403 dma_memory_write(xhci
->as
, ctx
, bw_ctx
, sizeof(bw_ctx
),
2404 MEMTXATTRS_UNSPECIFIED
);
2409 static uint32_t rotl(uint32_t v
, unsigned count
)
2412 return (v
<< count
) | (v
>> (32 - count
));
2416 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2419 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2420 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2421 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2425 static void xhci_process_commands(XHCIState
*xhci
)
2429 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2431 unsigned int i
, slotid
= 0, count
= 0;
2433 DPRINTF("xhci_process_commands()\n");
2434 if (!xhci_running(xhci
)) {
2435 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2439 xhci
->crcr_low
|= CRCR_CRR
;
2441 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2444 case CR_ENABLE_SLOT
:
2445 for (i
= 0; i
< xhci
->numslots
; i
++) {
2446 if (!xhci
->slots
[i
].enabled
) {
2450 if (i
>= xhci
->numslots
) {
2451 DPRINTF("xhci: no device slots available\n");
2452 event
.ccode
= CC_NO_SLOTS_ERROR
;
2455 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2458 case CR_DISABLE_SLOT
:
2459 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2461 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2464 case CR_ADDRESS_DEVICE
:
2465 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2467 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2468 trb
.control
& TRB_CR_BSR
);
2471 case CR_CONFIGURE_ENDPOINT
:
2472 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2474 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2475 trb
.control
& TRB_CR_DC
);
2478 case CR_EVALUATE_CONTEXT
:
2479 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2481 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2484 case CR_STOP_ENDPOINT
:
2485 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2487 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2489 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2492 case CR_RESET_ENDPOINT
:
2493 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2495 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2497 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2500 case CR_SET_TR_DEQUEUE
:
2501 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2503 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2505 unsigned int streamid
= (trb
.status
>> 16) & 0xffff;
2506 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
,
2511 case CR_RESET_DEVICE
:
2512 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2514 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2517 case CR_GET_PORT_BANDWIDTH
:
2518 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2521 event
.ccode
= CC_SUCCESS
;
2523 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2524 if (xhci
->nec_quirks
) {
2525 event
.type
= 48; /* NEC reply */
2526 event
.length
= 0x3034;
2528 event
.ccode
= CC_TRB_ERROR
;
2531 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2532 if (xhci
->nec_quirks
) {
2533 uint32_t chi
= trb
.parameter
>> 32;
2534 uint32_t clo
= trb
.parameter
;
2535 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2536 event
.length
= val
& 0xFFFF;
2537 event
.epid
= val
>> 16;
2539 event
.type
= 48; /* NEC reply */
2541 event
.ccode
= CC_TRB_ERROR
;
2545 trace_usb_xhci_unimplemented("command", type
);
2546 event
.ccode
= CC_TRB_ERROR
;
2549 event
.slotid
= slotid
;
2550 xhci_event(xhci
, &event
, 0);
2552 if (count
++ > COMMAND_LIMIT
) {
2553 trace_usb_xhci_enforced_limit("commands");
2559 static bool xhci_port_have_device(XHCIPort
*port
)
2561 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2562 return false; /* no device present */
2564 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2565 return false; /* speed mismatch */
2570 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2572 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2573 port
->portnr
<< 24 };
2575 if ((port
->portsc
& bits
) == bits
) {
2578 trace_usb_xhci_port_notify(port
->portnr
, bits
);
2579 port
->portsc
|= bits
;
2580 if (!xhci_running(port
->xhci
)) {
2583 xhci_event(port
->xhci
, &ev
, 0);
2586 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2588 uint32_t pls
= PLS_RX_DETECT
;
2591 port
->portsc
= PORTSC_PP
;
2592 if (!is_detach
&& xhci_port_have_device(port
)) {
2593 port
->portsc
|= PORTSC_CCS
;
2594 switch (port
->uport
->dev
->speed
) {
2596 port
->portsc
|= PORTSC_SPEED_LOW
;
2599 case USB_SPEED_FULL
:
2600 port
->portsc
|= PORTSC_SPEED_FULL
;
2603 case USB_SPEED_HIGH
:
2604 port
->portsc
|= PORTSC_SPEED_HIGH
;
2607 case USB_SPEED_SUPER
:
2608 port
->portsc
|= PORTSC_SPEED_SUPER
;
2609 port
->portsc
|= PORTSC_PED
;
2614 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2615 trace_usb_xhci_port_link(port
->portnr
, pls
);
2616 xhci_port_notify(port
, PORTSC_CSC
);
2619 static void xhci_port_reset(XHCIPort
*port
, bool warm_reset
)
2621 trace_usb_xhci_port_reset(port
->portnr
, warm_reset
);
2623 if (!xhci_port_have_device(port
)) {
2627 usb_device_reset(port
->uport
->dev
);
2629 switch (port
->uport
->dev
->speed
) {
2630 case USB_SPEED_SUPER
:
2632 port
->portsc
|= PORTSC_WRC
;
2636 case USB_SPEED_FULL
:
2637 case USB_SPEED_HIGH
:
2638 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2639 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2640 port
->portsc
|= PORTSC_PED
;
2644 port
->portsc
&= ~PORTSC_PR
;
2645 xhci_port_notify(port
, PORTSC_PRC
);
2648 static void xhci_reset(DeviceState
*dev
)
2650 XHCIState
*xhci
= XHCI(dev
);
2653 trace_usb_xhci_reset();
2654 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2655 DPRINTF("xhci: reset while running!\n");
2659 xhci
->usbsts
= USBSTS_HCH
;
2662 xhci
->crcr_high
= 0;
2663 xhci
->dcbaap_low
= 0;
2664 xhci
->dcbaap_high
= 0;
2667 for (i
= 0; i
< xhci
->numslots
; i
++) {
2668 xhci_disable_slot(xhci
, i
+1);
2671 for (i
= 0; i
< xhci
->numports
; i
++) {
2672 xhci_port_update(xhci
->ports
+ i
, 0);
2675 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2676 xhci
->intr
[i
].iman
= 0;
2677 xhci
->intr
[i
].imod
= 0;
2678 xhci
->intr
[i
].erstsz
= 0;
2679 xhci
->intr
[i
].erstba_low
= 0;
2680 xhci
->intr
[i
].erstba_high
= 0;
2681 xhci
->intr
[i
].erdp_low
= 0;
2682 xhci
->intr
[i
].erdp_high
= 0;
2684 xhci
->intr
[i
].er_ep_idx
= 0;
2685 xhci
->intr
[i
].er_pcs
= 1;
2686 xhci
->intr
[i
].ev_buffer_put
= 0;
2687 xhci
->intr
[i
].ev_buffer_get
= 0;
2690 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
2691 xhci_mfwrap_update(xhci
);
2694 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2696 XHCIState
*xhci
= ptr
;
2700 case 0x00: /* HCIVERSION, CAPLENGTH */
2701 ret
= 0x01000000 | LEN_CAP
;
2703 case 0x04: /* HCSPARAMS 1 */
2704 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2705 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2707 case 0x08: /* HCSPARAMS 2 */
2710 case 0x0c: /* HCSPARAMS 3 */
2713 case 0x10: /* HCCPARAMS */
2714 if (sizeof(dma_addr_t
) == 4) {
2715 ret
= 0x00080000 | (xhci
->max_pstreams_mask
<< 12);
2717 ret
= 0x00080001 | (xhci
->max_pstreams_mask
<< 12);
2720 case 0x14: /* DBOFF */
2723 case 0x18: /* RTSOFF */
2727 /* extended capabilities */
2728 case 0x20: /* Supported Protocol:00 */
2729 ret
= 0x02000402; /* USB 2.0 */
2731 case 0x24: /* Supported Protocol:04 */
2732 ret
= 0x20425355; /* "USB " */
2734 case 0x28: /* Supported Protocol:08 */
2735 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2736 ret
= (xhci
->numports_2
<<8) | (xhci
->numports_3
+1);
2738 ret
= (xhci
->numports_2
<<8) | 1;
2741 case 0x2c: /* Supported Protocol:0c */
2742 ret
= 0x00000000; /* reserved */
2744 case 0x30: /* Supported Protocol:00 */
2745 ret
= 0x03000002; /* USB 3.0 */
2747 case 0x34: /* Supported Protocol:04 */
2748 ret
= 0x20425355; /* "USB " */
2750 case 0x38: /* Supported Protocol:08 */
2751 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2752 ret
= (xhci
->numports_3
<<8) | 1;
2754 ret
= (xhci
->numports_3
<<8) | (xhci
->numports_2
+1);
2757 case 0x3c: /* Supported Protocol:0c */
2758 ret
= 0x00000000; /* reserved */
2761 trace_usb_xhci_unimplemented("cap read", reg
);
2765 trace_usb_xhci_cap_read(reg
, ret
);
2769 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2771 XHCIPort
*port
= ptr
;
2775 case 0x00: /* PORTSC */
2778 case 0x04: /* PORTPMSC */
2779 case 0x08: /* PORTLI */
2782 case 0x0c: /* reserved */
2784 trace_usb_xhci_unimplemented("port read", reg
);
2788 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2792 static void xhci_port_write(void *ptr
, hwaddr reg
,
2793 uint64_t val
, unsigned size
)
2795 XHCIPort
*port
= ptr
;
2796 uint32_t portsc
, notify
;
2798 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2801 case 0x00: /* PORTSC */
2802 /* write-1-to-start bits */
2803 if (val
& PORTSC_WPR
) {
2804 xhci_port_reset(port
, true);
2807 if (val
& PORTSC_PR
) {
2808 xhci_port_reset(port
, false);
2812 portsc
= port
->portsc
;
2814 /* write-1-to-clear bits*/
2815 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2816 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2817 if (val
& PORTSC_LWS
) {
2818 /* overwrite PLS only when LWS=1 */
2819 uint32_t old_pls
= get_field(port
->portsc
, PORTSC_PLS
);
2820 uint32_t new_pls
= get_field(val
, PORTSC_PLS
);
2823 if (old_pls
!= PLS_U0
) {
2824 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2825 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2826 notify
= PORTSC_PLC
;
2830 if (old_pls
< PLS_U3
) {
2831 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2832 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2836 /* windows does this for some reason, don't spam stderr */
2839 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
2840 __func__
, old_pls
, new_pls
);
2844 /* read/write bits */
2845 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2846 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2847 port
->portsc
= portsc
;
2849 xhci_port_notify(port
, notify
);
2852 case 0x04: /* PORTPMSC */
2853 case 0x08: /* PORTLI */
2855 trace_usb_xhci_unimplemented("port write", reg
);
2859 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
2861 XHCIState
*xhci
= ptr
;
2865 case 0x00: /* USBCMD */
2868 case 0x04: /* USBSTS */
2871 case 0x08: /* PAGESIZE */
2874 case 0x14: /* DNCTRL */
2877 case 0x18: /* CRCR low */
2878 ret
= xhci
->crcr_low
& ~0xe;
2880 case 0x1c: /* CRCR high */
2881 ret
= xhci
->crcr_high
;
2883 case 0x30: /* DCBAAP low */
2884 ret
= xhci
->dcbaap_low
;
2886 case 0x34: /* DCBAAP high */
2887 ret
= xhci
->dcbaap_high
;
2889 case 0x38: /* CONFIG */
2893 trace_usb_xhci_unimplemented("oper read", reg
);
2897 trace_usb_xhci_oper_read(reg
, ret
);
2901 static void xhci_oper_write(void *ptr
, hwaddr reg
,
2902 uint64_t val
, unsigned size
)
2904 XHCIState
*xhci
= XHCI(ptr
);
2906 trace_usb_xhci_oper_write(reg
, val
);
2909 case 0x00: /* USBCMD */
2910 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2912 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2915 if (val
& USBCMD_CSS
) {
2917 xhci
->usbsts
&= ~USBSTS_SRE
;
2919 if (val
& USBCMD_CRS
) {
2921 xhci
->usbsts
|= USBSTS_SRE
;
2923 xhci
->usbcmd
= val
& 0xc0f;
2924 xhci_mfwrap_update(xhci
);
2925 if (val
& USBCMD_HCRST
) {
2926 xhci_reset(DEVICE(xhci
));
2928 xhci_intr_update(xhci
, 0);
2931 case 0x04: /* USBSTS */
2932 /* these bits are write-1-to-clear */
2933 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2934 xhci_intr_update(xhci
, 0);
2937 case 0x14: /* DNCTRL */
2938 xhci
->dnctrl
= val
& 0xffff;
2940 case 0x18: /* CRCR low */
2941 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2943 case 0x1c: /* CRCR high */
2944 xhci
->crcr_high
= val
;
2945 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2946 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2947 xhci
->crcr_low
&= ~CRCR_CRR
;
2948 xhci_event(xhci
, &event
, 0);
2949 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2951 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2952 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2954 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2956 case 0x30: /* DCBAAP low */
2957 xhci
->dcbaap_low
= val
& 0xffffffc0;
2959 case 0x34: /* DCBAAP high */
2960 xhci
->dcbaap_high
= val
;
2962 case 0x38: /* CONFIG */
2963 xhci
->config
= val
& 0xff;
2966 trace_usb_xhci_unimplemented("oper write", reg
);
2970 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
2973 XHCIState
*xhci
= ptr
;
2978 case 0x00: /* MFINDEX */
2979 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
2982 trace_usb_xhci_unimplemented("runtime read", reg
);
2986 int v
= (reg
- 0x20) / 0x20;
2987 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
2988 switch (reg
& 0x1f) {
2989 case 0x00: /* IMAN */
2992 case 0x04: /* IMOD */
2995 case 0x08: /* ERSTSZ */
2998 case 0x10: /* ERSTBA low */
2999 ret
= intr
->erstba_low
;
3001 case 0x14: /* ERSTBA high */
3002 ret
= intr
->erstba_high
;
3004 case 0x18: /* ERDP low */
3005 ret
= intr
->erdp_low
;
3007 case 0x1c: /* ERDP high */
3008 ret
= intr
->erdp_high
;
3013 trace_usb_xhci_runtime_read(reg
, ret
);
3017 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
3018 uint64_t val
, unsigned size
)
3020 XHCIState
*xhci
= ptr
;
3021 XHCIInterrupter
*intr
;
3024 trace_usb_xhci_runtime_write(reg
, val
);
3027 trace_usb_xhci_unimplemented("runtime write", reg
);
3030 v
= (reg
- 0x20) / 0x20;
3031 intr
= &xhci
->intr
[v
];
3033 switch (reg
& 0x1f) {
3034 case 0x00: /* IMAN */
3035 if (val
& IMAN_IP
) {
3036 intr
->iman
&= ~IMAN_IP
;
3038 intr
->iman
&= ~IMAN_IE
;
3039 intr
->iman
|= val
& IMAN_IE
;
3040 xhci_intr_update(xhci
, v
);
3042 case 0x04: /* IMOD */
3045 case 0x08: /* ERSTSZ */
3046 intr
->erstsz
= val
& 0xffff;
3048 case 0x10: /* ERSTBA low */
3049 if (xhci
->nec_quirks
) {
3050 /* NEC driver bug: it doesn't align this to 64 bytes */
3051 intr
->erstba_low
= val
& 0xfffffff0;
3053 intr
->erstba_low
= val
& 0xffffffc0;
3056 case 0x14: /* ERSTBA high */
3057 intr
->erstba_high
= val
;
3058 xhci_er_reset(xhci
, v
);
3060 case 0x18: /* ERDP low */
3061 if (val
& ERDP_EHB
) {
3062 intr
->erdp_low
&= ~ERDP_EHB
;
3064 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
3065 if (val
& ERDP_EHB
) {
3066 dma_addr_t erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
3067 unsigned int dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
3068 if (erdp
>= intr
->er_start
&&
3069 erdp
< (intr
->er_start
+ TRB_SIZE
* intr
->er_size
) &&
3070 dp_idx
!= intr
->er_ep_idx
) {
3071 xhci_intr_raise(xhci
, v
);
3075 case 0x1c: /* ERDP high */
3076 intr
->erdp_high
= val
;
3079 trace_usb_xhci_unimplemented("oper write", reg
);
3083 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
3086 /* doorbells always read as 0 */
3087 trace_usb_xhci_doorbell_read(reg
, 0);
3091 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
3092 uint64_t val
, unsigned size
)
3094 XHCIState
*xhci
= ptr
;
3095 unsigned int epid
, streamid
;
3097 trace_usb_xhci_doorbell_write(reg
, val
);
3099 if (!xhci_running(xhci
)) {
3100 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3108 xhci_process_commands(xhci
);
3110 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3115 streamid
= (val
>> 16) & 0xffff;
3116 if (reg
> xhci
->numslots
) {
3117 DPRINTF("xhci: bad doorbell %d\n", (int)reg
);
3118 } else if (epid
== 0 || epid
> 31) {
3119 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3120 (int)reg
, (uint32_t)val
);
3122 xhci_kick_ep(xhci
, reg
, epid
, streamid
);
3127 static void xhci_cap_write(void *opaque
, hwaddr addr
, uint64_t val
,
3133 static const MemoryRegionOps xhci_cap_ops
= {
3134 .read
= xhci_cap_read
,
3135 .write
= xhci_cap_write
,
3136 .valid
.min_access_size
= 1,
3137 .valid
.max_access_size
= 4,
3138 .impl
.min_access_size
= 4,
3139 .impl
.max_access_size
= 4,
3140 .endianness
= DEVICE_LITTLE_ENDIAN
,
3143 static const MemoryRegionOps xhci_oper_ops
= {
3144 .read
= xhci_oper_read
,
3145 .write
= xhci_oper_write
,
3146 .valid
.min_access_size
= 4,
3147 .valid
.max_access_size
= sizeof(dma_addr_t
),
3148 .endianness
= DEVICE_LITTLE_ENDIAN
,
3151 static const MemoryRegionOps xhci_port_ops
= {
3152 .read
= xhci_port_read
,
3153 .write
= xhci_port_write
,
3154 .valid
.min_access_size
= 4,
3155 .valid
.max_access_size
= 4,
3156 .endianness
= DEVICE_LITTLE_ENDIAN
,
3159 static const MemoryRegionOps xhci_runtime_ops
= {
3160 .read
= xhci_runtime_read
,
3161 .write
= xhci_runtime_write
,
3162 .valid
.min_access_size
= 4,
3163 .valid
.max_access_size
= sizeof(dma_addr_t
),
3164 .endianness
= DEVICE_LITTLE_ENDIAN
,
3167 static const MemoryRegionOps xhci_doorbell_ops
= {
3168 .read
= xhci_doorbell_read
,
3169 .write
= xhci_doorbell_write
,
3170 .valid
.min_access_size
= 4,
3171 .valid
.max_access_size
= 4,
3172 .endianness
= DEVICE_LITTLE_ENDIAN
,
3175 static void xhci_attach(USBPort
*usbport
)
3177 XHCIState
*xhci
= usbport
->opaque
;
3178 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3180 xhci_port_update(port
, 0);
3183 static void xhci_detach(USBPort
*usbport
)
3185 XHCIState
*xhci
= usbport
->opaque
;
3186 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3188 xhci_detach_slot(xhci
, usbport
);
3189 xhci_port_update(port
, 1);
3192 static void xhci_wakeup(USBPort
*usbport
)
3194 XHCIState
*xhci
= usbport
->opaque
;
3195 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3198 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
3201 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
3202 xhci_port_notify(port
, PORTSC_PLC
);
3205 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
3207 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
3209 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
3210 xhci_ep_nuke_one_xfer(xfer
, 0);
3213 xhci_try_complete_packet(xfer
);
3214 xhci_kick_epctx(xfer
->epctx
, xfer
->streamid
);
3215 if (xfer
->complete
) {
3216 xhci_ep_free_xfer(xfer
);
3220 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
3222 USBBus
*bus
= usb_bus_from_device(child
);
3223 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3225 xhci_detach_slot(xhci
, child
->port
);
3228 static USBPortOps xhci_uport_ops
= {
3229 .attach
= xhci_attach
,
3230 .detach
= xhci_detach
,
3231 .wakeup
= xhci_wakeup
,
3232 .complete
= xhci_complete
,
3233 .child_detach
= xhci_child_detach
,
3236 static int xhci_find_epid(USBEndpoint
*ep
)
3241 if (ep
->pid
== USB_TOKEN_IN
) {
3242 return ep
->nr
* 2 + 1;
3248 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
)
3256 uport
= epctx
->xhci
->slots
[epctx
->slotid
- 1].uport
;
3257 if (!uport
|| !uport
->dev
) {
3260 token
= (epctx
->epid
& 1) ? USB_TOKEN_IN
: USB_TOKEN_OUT
;
3261 return usb_ep_get(uport
->dev
, token
, epctx
->epid
>> 1);
3264 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
3265 unsigned int stream
)
3267 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3270 DPRINTF("%s\n", __func__
);
3271 slotid
= ep
->dev
->addr
;
3272 if (slotid
== 0 || slotid
> xhci
->numslots
||
3273 !xhci
->slots
[slotid
- 1].enabled
) {
3274 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
3277 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
), stream
);
3280 static USBBusOps xhci_bus_ops
= {
3281 .wakeup_endpoint
= xhci_wakeup_endpoint
,
3284 static void usb_xhci_init(XHCIState
*xhci
)
3287 unsigned int i
, usbports
, speedmask
;
3289 xhci
->usbsts
= USBSTS_HCH
;
3291 if (xhci
->numports_2
> XHCI_MAXPORTS_2
) {
3292 xhci
->numports_2
= XHCI_MAXPORTS_2
;
3294 if (xhci
->numports_3
> XHCI_MAXPORTS_3
) {
3295 xhci
->numports_3
= XHCI_MAXPORTS_3
;
3297 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3298 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3300 usb_bus_new(&xhci
->bus
, sizeof(xhci
->bus
), &xhci_bus_ops
, xhci
->hostOpaque
);
3302 for (i
= 0; i
< usbports
; i
++) {
3304 if (i
< xhci
->numports_2
) {
3305 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3306 port
= &xhci
->ports
[i
+ xhci
->numports_3
];
3307 port
->portnr
= i
+ 1 + xhci
->numports_3
;
3309 port
= &xhci
->ports
[i
];
3310 port
->portnr
= i
+ 1;
3312 port
->uport
= &xhci
->uports
[i
];
3314 USB_SPEED_MASK_LOW
|
3315 USB_SPEED_MASK_FULL
|
3316 USB_SPEED_MASK_HIGH
;
3317 assert(i
< XHCI_MAXPORTS
);
3318 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3319 speedmask
|= port
->speedmask
;
3321 if (i
< xhci
->numports_3
) {
3322 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3323 port
= &xhci
->ports
[i
];
3324 port
->portnr
= i
+ 1;
3326 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3327 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3329 port
->uport
= &xhci
->uports
[i
];
3330 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3331 assert(i
< XHCI_MAXPORTS
);
3332 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3333 speedmask
|= port
->speedmask
;
3335 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3336 &xhci_uport_ops
, speedmask
);
3340 static void usb_xhci_realize(DeviceState
*dev
, Error
**errp
)
3344 XHCIState
*xhci
= XHCI(dev
);
3346 if (xhci
->numintrs
> XHCI_MAXINTRS
) {
3347 xhci
->numintrs
= XHCI_MAXINTRS
;
3349 while (xhci
->numintrs
& (xhci
->numintrs
- 1)) { /* ! power of 2 */
3352 if (xhci
->numintrs
< 1) {
3355 if (xhci
->numslots
> XHCI_MAXSLOTS
) {
3356 xhci
->numslots
= XHCI_MAXSLOTS
;
3358 if (xhci
->numslots
< 1) {
3361 if (xhci_get_flag(xhci
, XHCI_FLAG_ENABLE_STREAMS
)) {
3362 xhci
->max_pstreams_mask
= 7; /* == 256 primary streams */
3364 xhci
->max_pstreams_mask
= 0;
3367 usb_xhci_init(xhci
);
3368 xhci
->mfwrap_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_mfwrap_timer
, xhci
);
3370 memory_region_init(&xhci
->mem
, OBJECT(dev
), "xhci", XHCI_LEN_REGS
);
3371 memory_region_init_io(&xhci
->mem_cap
, OBJECT(dev
), &xhci_cap_ops
, xhci
,
3372 "capabilities", LEN_CAP
);
3373 memory_region_init_io(&xhci
->mem_oper
, OBJECT(dev
), &xhci_oper_ops
, xhci
,
3374 "operational", 0x400);
3375 memory_region_init_io(&xhci
->mem_runtime
, OBJECT(dev
), &xhci_runtime_ops
,
3376 xhci
, "runtime", LEN_RUNTIME
);
3377 memory_region_init_io(&xhci
->mem_doorbell
, OBJECT(dev
), &xhci_doorbell_ops
,
3378 xhci
, "doorbell", LEN_DOORBELL
);
3380 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3381 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3382 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3383 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3385 for (i
= 0; i
< xhci
->numports
; i
++) {
3386 XHCIPort
*port
= &xhci
->ports
[i
];
3387 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3389 memory_region_init_io(&port
->mem
, OBJECT(dev
), &xhci_port_ops
, port
,
3391 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3395 static void usb_xhci_unrealize(DeviceState
*dev
)
3398 XHCIState
*xhci
= XHCI(dev
);
3400 trace_usb_xhci_exit();
3402 for (i
= 0; i
< xhci
->numslots
; i
++) {
3403 xhci_disable_slot(xhci
, i
+ 1);
3406 if (xhci
->mfwrap_timer
) {
3407 timer_free(xhci
->mfwrap_timer
);
3408 xhci
->mfwrap_timer
= NULL
;
3411 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_cap
);
3412 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_oper
);
3413 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_runtime
);
3414 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_doorbell
);
3416 for (i
= 0; i
< xhci
->numports
; i
++) {
3417 XHCIPort
*port
= &xhci
->ports
[i
];
3418 memory_region_del_subregion(&xhci
->mem
, &port
->mem
);
3421 usb_bus_release(&xhci
->bus
);
3424 static int usb_xhci_post_load(void *opaque
, int version_id
)
3426 XHCIState
*xhci
= opaque
;
3428 XHCIEPContext
*epctx
;
3429 dma_addr_t dcbaap
, pctx
;
3430 uint32_t slot_ctx
[4];
3432 int slotid
, epid
, state
;
3435 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
3437 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
3438 slot
= &xhci
->slots
[slotid
-1];
3439 if (!slot
->addressed
) {
3442 ldq_le_dma(xhci
->as
, dcbaap
+ 8 * slotid
, &addr
, MEMTXATTRS_UNSPECIFIED
);
3443 slot
->ctx
= xhci_mask64(addr
);
3445 xhci_dma_read_u32s(xhci
, slot
->ctx
, slot_ctx
, sizeof(slot_ctx
));
3446 slot
->uport
= xhci_lookup_uport(xhci
, slot_ctx
);
3448 /* should not happen, but may trigger on guest bugs */
3450 slot
->addressed
= 0;
3453 assert(slot
->uport
&& slot
->uport
->dev
);
3455 for (epid
= 1; epid
<= 31; epid
++) {
3456 pctx
= slot
->ctx
+ 32 * epid
;
3457 xhci_dma_read_u32s(xhci
, pctx
, ep_ctx
, sizeof(ep_ctx
));
3458 state
= ep_ctx
[0] & EP_STATE_MASK
;
3459 if (state
== EP_DISABLED
) {
3462 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
3463 slot
->eps
[epid
-1] = epctx
;
3464 xhci_init_epctx(epctx
, pctx
, ep_ctx
);
3465 epctx
->state
= state
;
3466 if (state
== EP_RUNNING
) {
3467 /* kick endpoint after vmload is finished */
3468 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
3475 static const VMStateDescription vmstate_xhci_ring
= {
3476 .name
= "xhci-ring",
3478 .fields
= (VMStateField
[]) {
3479 VMSTATE_UINT64(dequeue
, XHCIRing
),
3480 VMSTATE_BOOL(ccs
, XHCIRing
),
3481 VMSTATE_END_OF_LIST()
3485 static const VMStateDescription vmstate_xhci_port
= {
3486 .name
= "xhci-port",
3488 .fields
= (VMStateField
[]) {
3489 VMSTATE_UINT32(portsc
, XHCIPort
),
3490 VMSTATE_END_OF_LIST()
3494 static const VMStateDescription vmstate_xhci_slot
= {
3495 .name
= "xhci-slot",
3497 .fields
= (VMStateField
[]) {
3498 VMSTATE_BOOL(enabled
, XHCISlot
),
3499 VMSTATE_BOOL(addressed
, XHCISlot
),
3500 VMSTATE_END_OF_LIST()
3504 static const VMStateDescription vmstate_xhci_event
= {
3505 .name
= "xhci-event",
3507 .fields
= (VMStateField
[]) {
3508 VMSTATE_UINT32(type
, XHCIEvent
),
3509 VMSTATE_UINT32(ccode
, XHCIEvent
),
3510 VMSTATE_UINT64(ptr
, XHCIEvent
),
3511 VMSTATE_UINT32(length
, XHCIEvent
),
3512 VMSTATE_UINT32(flags
, XHCIEvent
),
3513 VMSTATE_UINT8(slotid
, XHCIEvent
),
3514 VMSTATE_UINT8(epid
, XHCIEvent
),
3515 VMSTATE_END_OF_LIST()
3519 static bool xhci_er_full(void *opaque
, int version_id
)
3524 static const VMStateDescription vmstate_xhci_intr
= {
3525 .name
= "xhci-intr",
3527 .fields
= (VMStateField
[]) {
3529 VMSTATE_UINT32(iman
, XHCIInterrupter
),
3530 VMSTATE_UINT32(imod
, XHCIInterrupter
),
3531 VMSTATE_UINT32(erstsz
, XHCIInterrupter
),
3532 VMSTATE_UINT32(erstba_low
, XHCIInterrupter
),
3533 VMSTATE_UINT32(erstba_high
, XHCIInterrupter
),
3534 VMSTATE_UINT32(erdp_low
, XHCIInterrupter
),
3535 VMSTATE_UINT32(erdp_high
, XHCIInterrupter
),
3538 VMSTATE_BOOL(msix_used
, XHCIInterrupter
),
3539 VMSTATE_BOOL(er_pcs
, XHCIInterrupter
),
3540 VMSTATE_UINT64(er_start
, XHCIInterrupter
),
3541 VMSTATE_UINT32(er_size
, XHCIInterrupter
),
3542 VMSTATE_UINT32(er_ep_idx
, XHCIInterrupter
),
3544 /* event queue (used if ring is full) */
3545 VMSTATE_BOOL(er_full_unused
, XHCIInterrupter
),
3546 VMSTATE_UINT32_TEST(ev_buffer_put
, XHCIInterrupter
, xhci_er_full
),
3547 VMSTATE_UINT32_TEST(ev_buffer_get
, XHCIInterrupter
, xhci_er_full
),
3548 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer
, XHCIInterrupter
, EV_QUEUE
,
3550 vmstate_xhci_event
, XHCIEvent
),
3552 VMSTATE_END_OF_LIST()
3556 const VMStateDescription vmstate_xhci
= {
3557 .name
= "xhci-core",
3559 .post_load
= usb_xhci_post_load
,
3560 .fields
= (VMStateField
[]) {
3561 VMSTATE_STRUCT_VARRAY_UINT32(ports
, XHCIState
, numports
, 1,
3562 vmstate_xhci_port
, XHCIPort
),
3563 VMSTATE_STRUCT_VARRAY_UINT32(slots
, XHCIState
, numslots
, 1,
3564 vmstate_xhci_slot
, XHCISlot
),
3565 VMSTATE_STRUCT_VARRAY_UINT32(intr
, XHCIState
, numintrs
, 1,
3566 vmstate_xhci_intr
, XHCIInterrupter
),
3568 /* Operational Registers */
3569 VMSTATE_UINT32(usbcmd
, XHCIState
),
3570 VMSTATE_UINT32(usbsts
, XHCIState
),
3571 VMSTATE_UINT32(dnctrl
, XHCIState
),
3572 VMSTATE_UINT32(crcr_low
, XHCIState
),
3573 VMSTATE_UINT32(crcr_high
, XHCIState
),
3574 VMSTATE_UINT32(dcbaap_low
, XHCIState
),
3575 VMSTATE_UINT32(dcbaap_high
, XHCIState
),
3576 VMSTATE_UINT32(config
, XHCIState
),
3578 /* Runtime Registers & state */
3579 VMSTATE_INT64(mfindex_start
, XHCIState
),
3580 VMSTATE_TIMER_PTR(mfwrap_timer
, XHCIState
),
3581 VMSTATE_STRUCT(cmd_ring
, XHCIState
, 1, vmstate_xhci_ring
, XHCIRing
),
3583 VMSTATE_END_OF_LIST()
3587 static Property xhci_properties
[] = {
3588 DEFINE_PROP_BIT("streams", XHCIState
, flags
,
3589 XHCI_FLAG_ENABLE_STREAMS
, true),
3590 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3591 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3592 DEFINE_PROP_LINK("host", XHCIState
, hostOpaque
, TYPE_DEVICE
,
3594 DEFINE_PROP_END_OF_LIST(),
3597 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3599 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3601 dc
->realize
= usb_xhci_realize
;
3602 dc
->unrealize
= usb_xhci_unrealize
;
3603 dc
->reset
= xhci_reset
;
3604 device_class_set_props(dc
, xhci_properties
);
3605 dc
->user_creatable
= false;
3608 static const TypeInfo xhci_info
= {
3610 .parent
= TYPE_DEVICE
,
3611 .instance_size
= sizeof(XHCIState
),
3612 .class_init
= xhci_class_init
,
3615 static void xhci_register_types(void)
3617 type_register_static(&xhci_info
);
3620 type_init(xhci_register_types
)