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icount: Take iothread lock when running QEMU timers
[qemu/ar7.git] / hw / riscv / virt.c
blobbc424dd2f523dd2ba10e96d4f6200691cb18983d
1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/sysbus.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/char/serial.h"
30 #include "target/riscv/cpu.h"
31 #include "hw/core/sysbus-fdt.h"
32 #include "hw/riscv/riscv_hart.h"
33 #include "hw/riscv/virt.h"
34 #include "hw/riscv/boot.h"
35 #include "hw/riscv/numa.h"
36 #include "hw/intc/riscv_aclint.h"
37 #include "hw/intc/riscv_aplic.h"
38 #include "hw/intc/riscv_imsic.h"
39 #include "hw/intc/sifive_plic.h"
40 #include "hw/misc/sifive_test.h"
41 #include "hw/platform-bus.h"
42 #include "chardev/char.h"
43 #include "sysemu/device_tree.h"
44 #include "sysemu/sysemu.h"
45 #include "sysemu/kvm.h"
46 #include "sysemu/tpm.h"
47 #include "hw/pci/pci.h"
48 #include "hw/pci-host/gpex.h"
49 #include "hw/display/ramfb.h"
50
51 /*
52 * The virt machine physical address space used by some of the devices
53 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
54 * number of CPUs, and number of IMSIC guest files.
55 *
56 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
57 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
58 * of virt machine physical address space.
59 */
60
61 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
62 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
63 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
64 #error "Can't accomodate single IMSIC group in address space"
65 #endif
66
67 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
68 VIRT_IMSIC_GROUP_MAX_SIZE)
69 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE
70 #error "Can't accomodate all IMSIC groups in address space"
71 #endif
72
73 static const MemMapEntry virt_memmap[] = {
74 [VIRT_DEBUG] = { 0x0, 0x100 },
75 [VIRT_MROM] = { 0x1000, 0xf000 },
76 [VIRT_TEST] = { 0x100000, 0x1000 },
77 [VIRT_RTC] = { 0x101000, 0x1000 },
78 [VIRT_CLINT] = { 0x2000000, 0x10000 },
79 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
80 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
81 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
82 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
83 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
84 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
85 [VIRT_UART0] = { 0x10000000, 0x100 },
86 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
87 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
88 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
89 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
90 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
91 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
92 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
93 [VIRT_DRAM] = { 0x80000000, 0x0 },
94 };
95
96 /* PCIe high mmio is fixed for RV32 */
97 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
98 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
99
100 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
101 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
102
103 static MemMapEntry virt_high_pcie_memmap;
104
105 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
106
107 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
108 const char *name,
109 const char *alias_prop_name)
110 {
111 /*
112 * Create a single flash device. We use the same parameters as
113 * the flash devices on the ARM virt board.
114 */
115 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
116
117 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
118 qdev_prop_set_uint8(dev, "width", 4);
119 qdev_prop_set_uint8(dev, "device-width", 2);
120 qdev_prop_set_bit(dev, "big-endian", false);
121 qdev_prop_set_uint16(dev, "id0", 0x89);
122 qdev_prop_set_uint16(dev, "id1", 0x18);
123 qdev_prop_set_uint16(dev, "id2", 0x00);
124 qdev_prop_set_uint16(dev, "id3", 0x00);
125 qdev_prop_set_string(dev, "name", name);
126
127 object_property_add_child(OBJECT(s), name, OBJECT(dev));
128 object_property_add_alias(OBJECT(s), alias_prop_name,
129 OBJECT(dev), "drive");
130
131 return PFLASH_CFI01(dev);
132 }
133
134 static void virt_flash_create(RISCVVirtState *s)
135 {
136 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
137 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
138 }
139
140 static void virt_flash_map1(PFlashCFI01 *flash,
141 hwaddr base, hwaddr size,
142 MemoryRegion *sysmem)
143 {
144 DeviceState *dev = DEVICE(flash);
145
146 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
147 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
148 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
149 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
150
151 memory_region_add_subregion(sysmem, base,
152 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
153 0));
154 }
155
156 static void virt_flash_map(RISCVVirtState *s,
157 MemoryRegion *sysmem)
158 {
159 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
160 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
161
162 virt_flash_map1(s->flash[0], flashbase, flashsize,
163 sysmem);
164 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
165 sysmem);
166 }
167
168 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
169 uint32_t irqchip_phandle)
170 {
171 int pin, dev;
172 uint32_t irq_map_stride = 0;
173 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS *
174 FDT_MAX_INT_MAP_WIDTH] = {};
175 uint32_t *irq_map = full_irq_map;
176
177 /* This code creates a standard swizzle of interrupts such that
178 * each device's first interrupt is based on it's PCI_SLOT number.
179 * (See pci_swizzle_map_irq_fn())
180 *
181 * We only need one entry per interrupt in the table (not one per
182 * possible slot) seeing the interrupt-map-mask will allow the table
183 * to wrap to any number of devices.
184 */
185 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
186 int devfn = dev * 0x8;
187
188 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
189 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
190 int i = 0;
191
192 /* Fill PCI address cells */
193 irq_map[i] = cpu_to_be32(devfn << 8);
194 i += FDT_PCI_ADDR_CELLS;
195
196 /* Fill PCI Interrupt cells */
197 irq_map[i] = cpu_to_be32(pin + 1);
198 i += FDT_PCI_INT_CELLS;
199
200 /* Fill interrupt controller phandle and cells */
201 irq_map[i++] = cpu_to_be32(irqchip_phandle);
202 irq_map[i++] = cpu_to_be32(irq_nr);
203 if (s->aia_type != VIRT_AIA_TYPE_NONE) {
204 irq_map[i++] = cpu_to_be32(0x4);
205 }
206
207 if (!irq_map_stride) {
208 irq_map_stride = i;
209 }
210 irq_map += irq_map_stride;
211 }
212 }
213
214 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
215 GPEX_NUM_IRQS * GPEX_NUM_IRQS *
216 irq_map_stride * sizeof(uint32_t));
217
218 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
219 0x1800, 0, 0, 0x7);
220 }
221
222 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
223 char *clust_name, uint32_t *phandle,
224 bool is_32_bit, uint32_t *intc_phandles)
225 {
226 int cpu;
227 uint32_t cpu_phandle;
228 MachineState *mc = MACHINE(s);
229 char *name, *cpu_name, *core_name, *intc_name;
230
231 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
232 cpu_phandle = (*phandle)++;
233
234 cpu_name = g_strdup_printf("/cpus/cpu@%d",
235 s->soc[socket].hartid_base + cpu);
236 qemu_fdt_add_subnode(mc->fdt, cpu_name);
237 if (riscv_feature(&s->soc[socket].harts[cpu].env,
238 RISCV_FEATURE_MMU)) {
239 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
240 (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
241 } else {
242 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
243 "riscv,none");
244 }
245 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
246 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
247 g_free(name);
248 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
249 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
250 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
251 s->soc[socket].hartid_base + cpu);
252 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
253 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
254 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
255
256 intc_phandles[cpu] = (*phandle)++;
257
258 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
259 qemu_fdt_add_subnode(mc->fdt, intc_name);
260 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
261 intc_phandles[cpu]);
262 if (riscv_feature(&s->soc[socket].harts[cpu].env,
263 RISCV_FEATURE_AIA)) {
264 static const char * const compat[2] = {
265 "riscv,cpu-intc-aia", "riscv,cpu-intc"
266 };
267 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
268 (char **)&compat, ARRAY_SIZE(compat));
269 } else {
270 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
271 "riscv,cpu-intc");
272 }
273 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
274 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
275
276 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
277 qemu_fdt_add_subnode(mc->fdt, core_name);
278 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
279
280 g_free(core_name);
281 g_free(intc_name);
282 g_free(cpu_name);
283 }
284 }
285
286 static void create_fdt_socket_memory(RISCVVirtState *s,
287 const MemMapEntry *memmap, int socket)
288 {
289 char *mem_name;
290 uint64_t addr, size;
291 MachineState *mc = MACHINE(s);
292
293 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
294 size = riscv_socket_mem_size(mc, socket);
295 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
296 qemu_fdt_add_subnode(mc->fdt, mem_name);
297 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
298 addr >> 32, addr, size >> 32, size);
299 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
300 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
301 g_free(mem_name);
302 }
303
304 static void create_fdt_socket_clint(RISCVVirtState *s,
305 const MemMapEntry *memmap, int socket,
306 uint32_t *intc_phandles)
307 {
308 int cpu;
309 char *clint_name;
310 uint32_t *clint_cells;
311 unsigned long clint_addr;
312 MachineState *mc = MACHINE(s);
313 static const char * const clint_compat[2] = {
314 "sifive,clint0", "riscv,clint0"
315 };
316
317 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
318
319 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
320 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
321 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
322 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
323 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
324 }
325
326 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
327 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
328 qemu_fdt_add_subnode(mc->fdt, clint_name);
329 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
330 (char **)&clint_compat,
331 ARRAY_SIZE(clint_compat));
332 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
333 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
334 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
335 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
336 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
337 g_free(clint_name);
338
339 g_free(clint_cells);
340 }
341
342 static void create_fdt_socket_aclint(RISCVVirtState *s,
343 const MemMapEntry *memmap, int socket,
344 uint32_t *intc_phandles)
345 {
346 int cpu;
347 char *name;
348 unsigned long addr, size;
349 uint32_t aclint_cells_size;
350 uint32_t *aclint_mswi_cells;
351 uint32_t *aclint_sswi_cells;
352 uint32_t *aclint_mtimer_cells;
353 MachineState *mc = MACHINE(s);
354
355 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
356 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
357 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
358
359 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
360 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
361 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
362 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
363 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
364 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
365 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
366 }
367 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
368
369 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
370 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
371 name = g_strdup_printf("/soc/mswi@%lx", addr);
372 qemu_fdt_add_subnode(mc->fdt, name);
373 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
374 "riscv,aclint-mswi");
375 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
376 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
377 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
378 aclint_mswi_cells, aclint_cells_size);
379 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
380 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
381 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
382 g_free(name);
383 }
384
385 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
386 addr = memmap[VIRT_CLINT].base +
387 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
388 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
389 } else {
390 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
391 (memmap[VIRT_CLINT].size * socket);
392 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
393 }
394 name = g_strdup_printf("/soc/mtimer@%lx", addr);
395 qemu_fdt_add_subnode(mc->fdt, name);
396 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
397 "riscv,aclint-mtimer");
398 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
399 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
400 0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
401 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
402 0x0, RISCV_ACLINT_DEFAULT_MTIME);
403 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
404 aclint_mtimer_cells, aclint_cells_size);
405 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
406 g_free(name);
407
408 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
409 addr = memmap[VIRT_ACLINT_SSWI].base +
410 (memmap[VIRT_ACLINT_SSWI].size * socket);
411 name = g_strdup_printf("/soc/sswi@%lx", addr);
412 qemu_fdt_add_subnode(mc->fdt, name);
413 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
414 "riscv,aclint-sswi");
415 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
416 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
417 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
418 aclint_sswi_cells, aclint_cells_size);
419 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
420 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
421 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
422 g_free(name);
423 }
424
425 g_free(aclint_mswi_cells);
426 g_free(aclint_mtimer_cells);
427 g_free(aclint_sswi_cells);
428 }
429
430 static void create_fdt_socket_plic(RISCVVirtState *s,
431 const MemMapEntry *memmap, int socket,
432 uint32_t *phandle, uint32_t *intc_phandles,
433 uint32_t *plic_phandles)
434 {
435 int cpu;
436 char *plic_name;
437 uint32_t *plic_cells;
438 unsigned long plic_addr;
439 MachineState *mc = MACHINE(s);
440 static const char * const plic_compat[2] = {
441 "sifive,plic-1.0.0", "riscv,plic0"
442 };
443
444 if (kvm_enabled()) {
445 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
446 } else {
447 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
448 }
449
450 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
451 if (kvm_enabled()) {
452 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
453 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
454 } else {
455 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
456 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
457 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
458 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
459 }
460 }
461
462 plic_phandles[socket] = (*phandle)++;
463 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
464 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
465 qemu_fdt_add_subnode(mc->fdt, plic_name);
466 qemu_fdt_setprop_cell(mc->fdt, plic_name,
467 "#interrupt-cells", FDT_PLIC_INT_CELLS);
468 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
469 (char **)&plic_compat,
470 ARRAY_SIZE(plic_compat));
471 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
472 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
473 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
474 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
475 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
476 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
477 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
478 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
479 plic_phandles[socket]);
480
481 if (!socket) {
482 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
483 memmap[VIRT_PLATFORM_BUS].base,
484 memmap[VIRT_PLATFORM_BUS].size,
485 VIRT_PLATFORM_BUS_IRQ);
486 }
487
488 g_free(plic_name);
489
490 g_free(plic_cells);
491 }
492
493 static uint32_t imsic_num_bits(uint32_t count)
494 {
495 uint32_t ret = 0;
496
497 while (BIT(ret) < count) {
498 ret++;
499 }
500
501 return ret;
502 }
503
504 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
505 uint32_t *phandle, uint32_t *intc_phandles,
506 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
507 {
508 int cpu, socket;
509 char *imsic_name;
510 MachineState *mc = MACHINE(s);
511 uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
512 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
513
514 *msi_m_phandle = (*phandle)++;
515 *msi_s_phandle = (*phandle)++;
516 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
517 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
518
519 /* M-level IMSIC node */
520 for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
521 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
522 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
523 }
524 imsic_max_hart_per_socket = 0;
525 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
526 imsic_addr = memmap[VIRT_IMSIC_M].base +
527 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
528 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
529 imsic_regs[socket * 4 + 0] = 0;
530 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
531 imsic_regs[socket * 4 + 2] = 0;
532 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
533 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
534 imsic_max_hart_per_socket = s->soc[socket].num_harts;
535 }
536 }
537 imsic_name = g_strdup_printf("/soc/imsics@%lx",
538 (unsigned long)memmap[VIRT_IMSIC_M].base);
539 qemu_fdt_add_subnode(mc->fdt, imsic_name);
540 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
541 "riscv,imsics");
542 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
543 FDT_IMSIC_INT_CELLS);
544 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
545 NULL, 0);
546 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
547 NULL, 0);
548 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
549 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
550 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
551 riscv_socket_count(mc) * sizeof(uint32_t) * 4);
552 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
553 VIRT_IRQCHIP_NUM_MSIS);
554 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
555 VIRT_IRQCHIP_IPI_MSI);
556 if (riscv_socket_count(mc) > 1) {
557 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
558 imsic_num_bits(imsic_max_hart_per_socket));
559 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
560 imsic_num_bits(riscv_socket_count(mc)));
561 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
562 IMSIC_MMIO_GROUP_MIN_SHIFT);
563 }
564 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
565
566 g_free(imsic_name);
567
568 /* S-level IMSIC node */
569 for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
570 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
571 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
572 }
573 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
574 imsic_max_hart_per_socket = 0;
575 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
576 imsic_addr = memmap[VIRT_IMSIC_S].base +
577 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
578 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
579 s->soc[socket].num_harts;
580 imsic_regs[socket * 4 + 0] = 0;
581 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
582 imsic_regs[socket * 4 + 2] = 0;
583 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
584 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
585 imsic_max_hart_per_socket = s->soc[socket].num_harts;
586 }
587 }
588 imsic_name = g_strdup_printf("/soc/imsics@%lx",
589 (unsigned long)memmap[VIRT_IMSIC_S].base);
590 qemu_fdt_add_subnode(mc->fdt, imsic_name);
591 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
592 "riscv,imsics");
593 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
594 FDT_IMSIC_INT_CELLS);
595 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
596 NULL, 0);
597 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
598 NULL, 0);
599 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
600 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
601 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
602 riscv_socket_count(mc) * sizeof(uint32_t) * 4);
603 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
604 VIRT_IRQCHIP_NUM_MSIS);
605 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
606 VIRT_IRQCHIP_IPI_MSI);
607 if (imsic_guest_bits) {
608 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
609 imsic_guest_bits);
610 }
611 if (riscv_socket_count(mc) > 1) {
612 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
613 imsic_num_bits(imsic_max_hart_per_socket));
614 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
615 imsic_num_bits(riscv_socket_count(mc)));
616 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
617 IMSIC_MMIO_GROUP_MIN_SHIFT);
618 }
619 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
620 g_free(imsic_name);
621
622 g_free(imsic_regs);
623 g_free(imsic_cells);
624 }
625
626 static void create_fdt_socket_aplic(RISCVVirtState *s,
627 const MemMapEntry *memmap, int socket,
628 uint32_t msi_m_phandle,
629 uint32_t msi_s_phandle,
630 uint32_t *phandle,
631 uint32_t *intc_phandles,
632 uint32_t *aplic_phandles)
633 {
634 int cpu;
635 char *aplic_name;
636 uint32_t *aplic_cells;
637 unsigned long aplic_addr;
638 MachineState *mc = MACHINE(s);
639 uint32_t aplic_m_phandle, aplic_s_phandle;
640
641 aplic_m_phandle = (*phandle)++;
642 aplic_s_phandle = (*phandle)++;
643 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
644
645 /* M-level APLIC node */
646 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
647 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
648 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
649 }
650 aplic_addr = memmap[VIRT_APLIC_M].base +
651 (memmap[VIRT_APLIC_M].size * socket);
652 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
653 qemu_fdt_add_subnode(mc->fdt, aplic_name);
654 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
655 qemu_fdt_setprop_cell(mc->fdt, aplic_name,
656 "#interrupt-cells", FDT_APLIC_INT_CELLS);
657 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
658 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
659 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
660 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
661 } else {
662 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
663 msi_m_phandle);
664 }
665 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
666 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
667 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
668 VIRT_IRQCHIP_NUM_SOURCES);
669 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
670 aplic_s_phandle);
671 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
672 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
673 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
674 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
675 g_free(aplic_name);
676
677 /* S-level APLIC node */
678 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
679 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
680 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
681 }
682 aplic_addr = memmap[VIRT_APLIC_S].base +
683 (memmap[VIRT_APLIC_S].size * socket);
684 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
685 qemu_fdt_add_subnode(mc->fdt, aplic_name);
686 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
687 qemu_fdt_setprop_cell(mc->fdt, aplic_name,
688 "#interrupt-cells", FDT_APLIC_INT_CELLS);
689 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
690 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
691 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
692 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
693 } else {
694 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
695 msi_s_phandle);
696 }
697 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
698 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
699 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
700 VIRT_IRQCHIP_NUM_SOURCES);
701 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
702 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
703
704 if (!socket) {
705 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
706 memmap[VIRT_PLATFORM_BUS].base,
707 memmap[VIRT_PLATFORM_BUS].size,
708 VIRT_PLATFORM_BUS_IRQ);
709 }
710
711 g_free(aplic_name);
712
713 g_free(aplic_cells);
714 aplic_phandles[socket] = aplic_s_phandle;
715 }
716
717 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
718 bool is_32_bit, uint32_t *phandle,
719 uint32_t *irq_mmio_phandle,
720 uint32_t *irq_pcie_phandle,
721 uint32_t *irq_virtio_phandle,
722 uint32_t *msi_pcie_phandle)
723 {
724 char *clust_name;
725 int socket, phandle_pos;
726 MachineState *mc = MACHINE(s);
727 uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
728 uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
729
730 qemu_fdt_add_subnode(mc->fdt, "/cpus");
731 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
732 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
733 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
734 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
735 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
736
737 intc_phandles = g_new0(uint32_t, mc->smp.cpus);
738
739 phandle_pos = mc->smp.cpus;
740 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
741 phandle_pos -= s->soc[socket].num_harts;
742
743 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
744 qemu_fdt_add_subnode(mc->fdt, clust_name);
745
746 create_fdt_socket_cpus(s, socket, clust_name, phandle,
747 is_32_bit, &intc_phandles[phandle_pos]);
748
749 create_fdt_socket_memory(s, memmap, socket);
750
751 g_free(clust_name);
752
753 if (!kvm_enabled()) {
754 if (s->have_aclint) {
755 create_fdt_socket_aclint(s, memmap, socket,
756 &intc_phandles[phandle_pos]);
757 } else {
758 create_fdt_socket_clint(s, memmap, socket,
759 &intc_phandles[phandle_pos]);
760 }
761 }
762 }
763
764 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
765 create_fdt_imsic(s, memmap, phandle, intc_phandles,
766 &msi_m_phandle, &msi_s_phandle);
767 *msi_pcie_phandle = msi_s_phandle;
768 }
769
770 phandle_pos = mc->smp.cpus;
771 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
772 phandle_pos -= s->soc[socket].num_harts;
773
774 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
775 create_fdt_socket_plic(s, memmap, socket, phandle,
776 &intc_phandles[phandle_pos], xplic_phandles);
777 } else {
778 create_fdt_socket_aplic(s, memmap, socket,
779 msi_m_phandle, msi_s_phandle, phandle,
780 &intc_phandles[phandle_pos], xplic_phandles);
781 }
782 }
783
784 g_free(intc_phandles);
785
786 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
787 if (socket == 0) {
788 *irq_mmio_phandle = xplic_phandles[socket];
789 *irq_virtio_phandle = xplic_phandles[socket];
790 *irq_pcie_phandle = xplic_phandles[socket];
791 }
792 if (socket == 1) {
793 *irq_virtio_phandle = xplic_phandles[socket];
794 *irq_pcie_phandle = xplic_phandles[socket];
795 }
796 if (socket == 2) {
797 *irq_pcie_phandle = xplic_phandles[socket];
798 }
799 }
800
801 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
802 }
803
804 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
805 uint32_t irq_virtio_phandle)
806 {
807 int i;
808 char *name;
809 MachineState *mc = MACHINE(s);
810
811 for (i = 0; i < VIRTIO_COUNT; i++) {
812 name = g_strdup_printf("/soc/virtio_mmio@%lx",
813 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
814 qemu_fdt_add_subnode(mc->fdt, name);
815 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
816 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
817 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
818 0x0, memmap[VIRT_VIRTIO].size);
819 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
820 irq_virtio_phandle);
821 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
822 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
823 VIRTIO_IRQ + i);
824 } else {
825 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
826 VIRTIO_IRQ + i, 0x4);
827 }
828 g_free(name);
829 }
830 }
831
832 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
833 uint32_t irq_pcie_phandle,
834 uint32_t msi_pcie_phandle)
835 {
836 char *name;
837 MachineState *mc = MACHINE(s);
838
839 name = g_strdup_printf("/soc/pci@%lx",
840 (long) memmap[VIRT_PCIE_ECAM].base);
841 qemu_fdt_add_subnode(mc->fdt, name);
842 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
843 FDT_PCI_ADDR_CELLS);
844 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
845 FDT_PCI_INT_CELLS);
846 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
847 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
848 "pci-host-ecam-generic");
849 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
850 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
851 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
852 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
853 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
854 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
855 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
856 }
857 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
858 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
859 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
860 1, FDT_PCI_RANGE_IOPORT, 2, 0,
861 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
862 1, FDT_PCI_RANGE_MMIO,
863 2, memmap[VIRT_PCIE_MMIO].base,
864 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
865 1, FDT_PCI_RANGE_MMIO_64BIT,
866 2, virt_high_pcie_memmap.base,
867 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
868
869 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
870 g_free(name);
871 }
872
873 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
874 uint32_t *phandle)
875 {
876 char *name;
877 uint32_t test_phandle;
878 MachineState *mc = MACHINE(s);
879
880 test_phandle = (*phandle)++;
881 name = g_strdup_printf("/soc/test@%lx",
882 (long)memmap[VIRT_TEST].base);
883 qemu_fdt_add_subnode(mc->fdt, name);
884 {
885 static const char * const compat[3] = {
886 "sifive,test1", "sifive,test0", "syscon"
887 };
888 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
889 (char **)&compat, ARRAY_SIZE(compat));
890 }
891 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
892 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
893 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
894 test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
895 g_free(name);
896
897 name = g_strdup_printf("/soc/reboot");
898 qemu_fdt_add_subnode(mc->fdt, name);
899 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
900 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
901 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
902 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
903 g_free(name);
904
905 name = g_strdup_printf("/soc/poweroff");
906 qemu_fdt_add_subnode(mc->fdt, name);
907 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
908 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
909 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
910 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
911 g_free(name);
912 }
913
914 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
915 uint32_t irq_mmio_phandle)
916 {
917 char *name;
918 MachineState *mc = MACHINE(s);
919
920 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
921 qemu_fdt_add_subnode(mc->fdt, name);
922 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
923 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
924 0x0, memmap[VIRT_UART0].base,
925 0x0, memmap[VIRT_UART0].size);
926 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
927 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
928 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
929 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
930 } else {
931 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
932 }
933
934 qemu_fdt_add_subnode(mc->fdt, "/chosen");
935 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
936 g_free(name);
937 }
938
939 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
940 uint32_t irq_mmio_phandle)
941 {
942 char *name;
943 MachineState *mc = MACHINE(s);
944
945 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
946 qemu_fdt_add_subnode(mc->fdt, name);
947 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
948 "google,goldfish-rtc");
949 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
950 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
951 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
952 irq_mmio_phandle);
953 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
954 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
955 } else {
956 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
957 }
958 g_free(name);
959 }
960
961 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
962 {
963 char *name;
964 MachineState *mc = MACHINE(s);
965 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
966 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
967
968 name = g_strdup_printf("/flash@%" PRIx64, flashbase);
969 qemu_fdt_add_subnode(mc->fdt, name);
970 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
971 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
972 2, flashbase, 2, flashsize,
973 2, flashbase + flashsize, 2, flashsize);
974 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
975 g_free(name);
976 }
977
978 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
979 {
980 char *nodename;
981 MachineState *mc = MACHINE(s);
982 hwaddr base = memmap[VIRT_FW_CFG].base;
983 hwaddr size = memmap[VIRT_FW_CFG].size;
984
985 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
986 qemu_fdt_add_subnode(mc->fdt, nodename);
987 qemu_fdt_setprop_string(mc->fdt, nodename,
988 "compatible", "qemu,fw-cfg-mmio");
989 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
990 2, base, 2, size);
991 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
992 g_free(nodename);
993 }
994
995 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
996 uint64_t mem_size, const char *cmdline, bool is_32_bit)
997 {
998 MachineState *mc = MACHINE(s);
999 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
1000 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
1001
1002 if (mc->dtb) {
1003 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
1004 if (!mc->fdt) {
1005 error_report("load_device_tree() failed");
1006 exit(1);
1007 }
1008 goto update_bootargs;
1009 } else {
1010 mc->fdt = create_device_tree(&s->fdt_size);
1011 if (!mc->fdt) {
1012 error_report("create_device_tree() failed");
1013 exit(1);
1014 }
1015 }
1016
1017 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
1018 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
1019 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
1020 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
1021
1022 qemu_fdt_add_subnode(mc->fdt, "/soc");
1023 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
1024 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
1025 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
1026 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
1027
1028 create_fdt_sockets(s, memmap, is_32_bit, &phandle,
1029 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
1030 &msi_pcie_phandle);
1031
1032 create_fdt_virtio(s, memmap, irq_virtio_phandle);
1033
1034 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle);
1035
1036 create_fdt_reset(s, memmap, &phandle);
1037
1038 create_fdt_uart(s, memmap, irq_mmio_phandle);
1039
1040 create_fdt_rtc(s, memmap, irq_mmio_phandle);
1041
1042 create_fdt_flash(s, memmap);
1043 create_fdt_fw_cfg(s, memmap);
1044
1045 update_bootargs:
1046 if (cmdline && *cmdline) {
1047 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
1048 }
1049 }
1050
1051 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
1052 hwaddr ecam_base, hwaddr ecam_size,
1053 hwaddr mmio_base, hwaddr mmio_size,
1054 hwaddr high_mmio_base,
1055 hwaddr high_mmio_size,
1056 hwaddr pio_base,
1057 DeviceState *irqchip)
1058 {
1059 DeviceState *dev;
1060 MemoryRegion *ecam_alias, *ecam_reg;
1061 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
1062 qemu_irq irq;
1063 int i;
1064
1065 dev = qdev_new(TYPE_GPEX_HOST);
1066
1067 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1068
1069 ecam_alias = g_new0(MemoryRegion, 1);
1070 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1071 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1072 ecam_reg, 0, ecam_size);
1073 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
1074
1075 mmio_alias = g_new0(MemoryRegion, 1);
1076 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1077 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1078 mmio_reg, mmio_base, mmio_size);
1079 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
1080
1081 /* Map high MMIO space */
1082 high_mmio_alias = g_new0(MemoryRegion, 1);
1083 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1084 mmio_reg, high_mmio_base, high_mmio_size);
1085 memory_region_add_subregion(get_system_memory(), high_mmio_base,
1086 high_mmio_alias);
1087
1088 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
1089
1090 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1091 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
1092
1093 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
1094 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
1095 }
1096
1097 return dev;
1098 }
1099
1100 static FWCfgState *create_fw_cfg(const MachineState *mc)
1101 {
1102 hwaddr base = virt_memmap[VIRT_FW_CFG].base;
1103 FWCfgState *fw_cfg;
1104
1105 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
1106 &address_space_memory);
1107 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
1108
1109 return fw_cfg;
1110 }
1111
1112 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
1113 int base_hartid, int hart_count)
1114 {
1115 DeviceState *ret;
1116 char *plic_hart_config;
1117
1118 /* Per-socket PLIC hart topology configuration string */
1119 plic_hart_config = riscv_plic_hart_config_string(hart_count);
1120
1121 /* Per-socket PLIC */
1122 ret = sifive_plic_create(
1123 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
1124 plic_hart_config, hart_count, base_hartid,
1125 VIRT_IRQCHIP_NUM_SOURCES,
1126 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
1127 VIRT_PLIC_PRIORITY_BASE,
1128 VIRT_PLIC_PENDING_BASE,
1129 VIRT_PLIC_ENABLE_BASE,
1130 VIRT_PLIC_ENABLE_STRIDE,
1131 VIRT_PLIC_CONTEXT_BASE,
1132 VIRT_PLIC_CONTEXT_STRIDE,
1133 memmap[VIRT_PLIC].size);
1134
1135 g_free(plic_hart_config);
1136
1137 return ret;
1138 }
1139
1140 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
1141 const MemMapEntry *memmap, int socket,
1142 int base_hartid, int hart_count)
1143 {
1144 int i;
1145 hwaddr addr;
1146 uint32_t guest_bits;
1147 DeviceState *aplic_m;
1148 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
1149
1150 if (msimode) {
1151 /* Per-socket M-level IMSICs */
1152 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1153 for (i = 0; i < hart_count; i++) {
1154 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
1155 base_hartid + i, true, 1,
1156 VIRT_IRQCHIP_NUM_MSIS);
1157 }
1158
1159 /* Per-socket S-level IMSICs */
1160 guest_bits = imsic_num_bits(aia_guests + 1);
1161 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1162 for (i = 0; i < hart_count; i++) {
1163 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
1164 base_hartid + i, false, 1 + aia_guests,
1165 VIRT_IRQCHIP_NUM_MSIS);
1166 }
1167 }
1168
1169 /* Per-socket M-level APLIC */
1170 aplic_m = riscv_aplic_create(
1171 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
1172 memmap[VIRT_APLIC_M].size,
1173 (msimode) ? 0 : base_hartid,
1174 (msimode) ? 0 : hart_count,
1175 VIRT_IRQCHIP_NUM_SOURCES,
1176 VIRT_IRQCHIP_NUM_PRIO_BITS,
1177 msimode, true, NULL);
1178
1179 if (aplic_m) {
1180 /* Per-socket S-level APLIC */
1181 riscv_aplic_create(
1182 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
1183 memmap[VIRT_APLIC_S].size,
1184 (msimode) ? 0 : base_hartid,
1185 (msimode) ? 0 : hart_count,
1186 VIRT_IRQCHIP_NUM_SOURCES,
1187 VIRT_IRQCHIP_NUM_PRIO_BITS,
1188 msimode, false, aplic_m);
1189 }
1190
1191 return aplic_m;
1192 }
1193
1194 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
1195 {
1196 DeviceState *dev;
1197 SysBusDevice *sysbus;
1198 const MemMapEntry *memmap = virt_memmap;
1199 int i;
1200 MemoryRegion *sysmem = get_system_memory();
1201
1202 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1203 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1204 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
1205 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size);
1206 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1207 s->platform_bus_dev = dev;
1208
1209 sysbus = SYS_BUS_DEVICE(dev);
1210 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
1211 int irq = VIRT_PLATFORM_BUS_IRQ + i;
1212 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
1213 }
1214
1215 memory_region_add_subregion(sysmem,
1216 memmap[VIRT_PLATFORM_BUS].base,
1217 sysbus_mmio_get_region(sysbus, 0));
1218 }
1219
1220 static void virt_machine_done(Notifier *notifier, void *data)
1221 {
1222 RISCVVirtState *s = container_of(notifier, RISCVVirtState,
1223 machine_done);
1224 const MemMapEntry *memmap = virt_memmap;
1225 MachineState *machine = MACHINE(s);
1226 target_ulong start_addr = memmap[VIRT_DRAM].base;
1227 target_ulong firmware_end_addr, kernel_start_addr;
1228 uint32_t fdt_load_addr;
1229 uint64_t kernel_entry;
1230
1231 /*
1232 * Only direct boot kernel is currently supported for KVM VM,
1233 * so the "-bios" parameter is not supported when KVM is enabled.
1234 */
1235 if (kvm_enabled()) {
1236 if (machine->firmware) {
1237 if (strcmp(machine->firmware, "none")) {
1238 error_report("Machine mode firmware is not supported in "
1239 "combination with KVM.");
1240 exit(1);
1241 }
1242 } else {
1243 machine->firmware = g_strdup("none");
1244 }
1245 }
1246
1247 if (riscv_is_32bit(&s->soc[0])) {
1248 firmware_end_addr = riscv_find_and_load_firmware(machine,
1249 RISCV32_BIOS_BIN, start_addr, NULL);
1250 } else {
1251 firmware_end_addr = riscv_find_and_load_firmware(machine,
1252 RISCV64_BIOS_BIN, start_addr, NULL);
1253 }
1254
1255 if (machine->kernel_filename) {
1256 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
1257 firmware_end_addr);
1258
1259 kernel_entry = riscv_load_kernel(machine->kernel_filename,
1260 kernel_start_addr, NULL);
1261
1262 if (machine->initrd_filename) {
1263 hwaddr start;
1264 hwaddr end = riscv_load_initrd(machine->initrd_filename,
1265 machine->ram_size, kernel_entry,
1266 &start);
1267 qemu_fdt_setprop_cell(machine->fdt, "/chosen",
1268 "linux,initrd-start", start);
1269 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
1270 end);
1271 }
1272 } else {
1273 /*
1274 * If dynamic firmware is used, it doesn't know where is the next mode
1275 * if kernel argument is not set.
1276 */
1277 kernel_entry = 0;
1278 }
1279
1280 if (drive_get(IF_PFLASH, 0, 0)) {
1281 /*
1282 * Pflash was supplied, let's overwrite the address we jump to after
1283 * reset to the base of the flash.
1284 */
1285 start_addr = virt_memmap[VIRT_FLASH].base;
1286 }
1287
1288 /*
1289 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
1290 * tree cannot be altered and we get FDT_ERR_NOSPACE.
1291 */
1292 s->fw_cfg = create_fw_cfg(machine);
1293 rom_set_fw(s->fw_cfg);
1294
1295 /* Compute the fdt load address in dram */
1296 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
1297 machine->ram_size, machine->fdt);
1298 /* load the reset vector */
1299 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
1300 virt_memmap[VIRT_MROM].base,
1301 virt_memmap[VIRT_MROM].size, kernel_entry,
1302 fdt_load_addr, machine->fdt);
1303
1304 /*
1305 * Only direct boot kernel is currently supported for KVM VM,
1306 * So here setup kernel start address and fdt address.
1307 * TODO:Support firmware loading and integrate to TCG start
1308 */
1309 if (kvm_enabled()) {
1310 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
1311 }
1312 }
1313
1314 static void virt_machine_init(MachineState *machine)
1315 {
1316 const MemMapEntry *memmap = virt_memmap;
1317 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1318 MemoryRegion *system_memory = get_system_memory();
1319 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
1320 char *soc_name;
1321 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
1322 int i, base_hartid, hart_count;
1323
1324 /* Check socket count limit */
1325 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
1326 error_report("number of sockets/nodes should be less than %d",
1327 VIRT_SOCKETS_MAX);
1328 exit(1);
1329 }
1330
1331 /* Initialize sockets */
1332 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
1333 for (i = 0; i < riscv_socket_count(machine); i++) {
1334 if (!riscv_socket_check_hartids(machine, i)) {
1335 error_report("discontinuous hartids in socket%d", i);
1336 exit(1);
1337 }
1338
1339 base_hartid = riscv_socket_first_hartid(machine, i);
1340 if (base_hartid < 0) {
1341 error_report("can't find hartid base for socket%d", i);
1342 exit(1);
1343 }
1344
1345 hart_count = riscv_socket_hart_count(machine, i);
1346 if (hart_count < 0) {
1347 error_report("can't find hart count for socket%d", i);
1348 exit(1);
1349 }
1350
1351 soc_name = g_strdup_printf("soc%d", i);
1352 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
1353 TYPE_RISCV_HART_ARRAY);
1354 g_free(soc_name);
1355 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
1356 machine->cpu_type, &error_abort);
1357 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
1358 base_hartid, &error_abort);
1359 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
1360 hart_count, &error_abort);
1361 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
1362
1363 if (!kvm_enabled()) {
1364 if (s->have_aclint) {
1365 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
1366 /* Per-socket ACLINT MTIMER */
1367 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1368 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1369 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1370 base_hartid, hart_count,
1371 RISCV_ACLINT_DEFAULT_MTIMECMP,
1372 RISCV_ACLINT_DEFAULT_MTIME,
1373 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1374 } else {
1375 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1376 riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
1377 i * memmap[VIRT_CLINT].size,
1378 base_hartid, hart_count, false);
1379 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1380 i * memmap[VIRT_CLINT].size +
1381 RISCV_ACLINT_SWI_SIZE,
1382 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1383 base_hartid, hart_count,
1384 RISCV_ACLINT_DEFAULT_MTIMECMP,
1385 RISCV_ACLINT_DEFAULT_MTIME,
1386 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1387 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
1388 i * memmap[VIRT_ACLINT_SSWI].size,
1389 base_hartid, hart_count, true);
1390 }
1391 } else {
1392 /* Per-socket SiFive CLINT */
1393 riscv_aclint_swi_create(
1394 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
1395 base_hartid, hart_count, false);
1396 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1397 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
1398 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
1399 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
1400 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1401 }
1402 }
1403
1404 /* Per-socket interrupt controller */
1405 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1406 s->irqchip[i] = virt_create_plic(memmap, i,
1407 base_hartid, hart_count);
1408 } else {
1409 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
1410 memmap, i, base_hartid,
1411 hart_count);
1412 }
1413
1414 /* Try to use different IRQCHIP instance based device type */
1415 if (i == 0) {
1416 mmio_irqchip = s->irqchip[i];
1417 virtio_irqchip = s->irqchip[i];
1418 pcie_irqchip = s->irqchip[i];
1419 }
1420 if (i == 1) {
1421 virtio_irqchip = s->irqchip[i];
1422 pcie_irqchip = s->irqchip[i];
1423 }
1424 if (i == 2) {
1425 pcie_irqchip = s->irqchip[i];
1426 }
1427 }
1428
1429 if (riscv_is_32bit(&s->soc[0])) {
1430 #if HOST_LONG_BITS == 64
1431 /* limit RAM size in a 32-bit system */
1432 if (machine->ram_size > 10 * GiB) {
1433 machine->ram_size = 10 * GiB;
1434 error_report("Limiting RAM size to 10 GiB");
1435 }
1436 #endif
1437 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
1438 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
1439 } else {
1440 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
1441 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
1442 virt_high_pcie_memmap.base =
1443 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
1444 }
1445
1446 /* register system main memory (actual RAM) */
1447 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
1448 machine->ram);
1449
1450 /* boot rom */
1451 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
1452 memmap[VIRT_MROM].size, &error_fatal);
1453 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
1454 mask_rom);
1455
1456 /* SiFive Test MMIO device */
1457 sifive_test_create(memmap[VIRT_TEST].base);
1458
1459 /* VirtIO MMIO devices */
1460 for (i = 0; i < VIRTIO_COUNT; i++) {
1461 sysbus_create_simple("virtio-mmio",
1462 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
1463 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i));
1464 }
1465
1466 gpex_pcie_init(system_memory,
1467 memmap[VIRT_PCIE_ECAM].base,
1468 memmap[VIRT_PCIE_ECAM].size,
1469 memmap[VIRT_PCIE_MMIO].base,
1470 memmap[VIRT_PCIE_MMIO].size,
1471 virt_high_pcie_memmap.base,
1472 virt_high_pcie_memmap.size,
1473 memmap[VIRT_PCIE_PIO].base,
1474 DEVICE(pcie_irqchip));
1475
1476 create_platform_bus(s, DEVICE(mmio_irqchip));
1477
1478 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
1479 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
1480 serial_hd(0), DEVICE_LITTLE_ENDIAN);
1481
1482 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
1483 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
1484
1485 virt_flash_create(s);
1486
1487 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
1488 /* Map legacy -drive if=pflash to machine properties */
1489 pflash_cfi01_legacy_drive(s->flash[i],
1490 drive_get(IF_PFLASH, 0, i));
1491 }
1492 virt_flash_map(s, system_memory);
1493
1494 /* create device tree */
1495 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
1496 riscv_is_32bit(&s->soc[0]));
1497
1498 s->machine_done.notify = virt_machine_done;
1499 qemu_add_machine_init_done_notifier(&s->machine_done);
1500 }
1501
1502 static void virt_machine_instance_init(Object *obj)
1503 {
1504 }
1505
1506 static char *virt_get_aia_guests(Object *obj, Error **errp)
1507 {
1508 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1509 char val[32];
1510
1511 sprintf(val, "%d", s->aia_guests);
1512 return g_strdup(val);
1513 }
1514
1515 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
1516 {
1517 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1518
1519 s->aia_guests = atoi(val);
1520 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
1521 error_setg(errp, "Invalid number of AIA IMSIC guests");
1522 error_append_hint(errp, "Valid values be between 0 and %d.\n",
1523 VIRT_IRQCHIP_MAX_GUESTS);
1524 }
1525 }
1526
1527 static char *virt_get_aia(Object *obj, Error **errp)
1528 {
1529 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1530 const char *val;
1531
1532 switch (s->aia_type) {
1533 case VIRT_AIA_TYPE_APLIC:
1534 val = "aplic";
1535 break;
1536 case VIRT_AIA_TYPE_APLIC_IMSIC:
1537 val = "aplic-imsic";
1538 break;
1539 default:
1540 val = "none";
1541 break;
1542 };
1543
1544 return g_strdup(val);
1545 }
1546
1547 static void virt_set_aia(Object *obj, const char *val, Error **errp)
1548 {
1549 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1550
1551 if (!strcmp(val, "none")) {
1552 s->aia_type = VIRT_AIA_TYPE_NONE;
1553 } else if (!strcmp(val, "aplic")) {
1554 s->aia_type = VIRT_AIA_TYPE_APLIC;
1555 } else if (!strcmp(val, "aplic-imsic")) {
1556 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
1557 } else {
1558 error_setg(errp, "Invalid AIA interrupt controller type");
1559 error_append_hint(errp, "Valid values are none, aplic, and "
1560 "aplic-imsic.\n");
1561 }
1562 }
1563
1564 static bool virt_get_aclint(Object *obj, Error **errp)
1565 {
1566 MachineState *ms = MACHINE(obj);
1567 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
1568
1569 return s->have_aclint;
1570 }
1571
1572 static void virt_set_aclint(Object *obj, bool value, Error **errp)
1573 {
1574 MachineState *ms = MACHINE(obj);
1575 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
1576
1577 s->have_aclint = value;
1578 }
1579
1580 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1581 DeviceState *dev)
1582 {
1583 MachineClass *mc = MACHINE_GET_CLASS(machine);
1584
1585 if (device_is_dynamic_sysbus(mc, dev)) {
1586 return HOTPLUG_HANDLER(machine);
1587 }
1588 return NULL;
1589 }
1590
1591 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1592 DeviceState *dev, Error **errp)
1593 {
1594 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
1595
1596 if (s->platform_bus_dev) {
1597 MachineClass *mc = MACHINE_GET_CLASS(s);
1598
1599 if (device_is_dynamic_sysbus(mc, dev)) {
1600 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
1601 SYS_BUS_DEVICE(dev));
1602 }
1603 }
1604 }
1605
1606 static void virt_machine_class_init(ObjectClass *oc, void *data)
1607 {
1608 char str[128];
1609 MachineClass *mc = MACHINE_CLASS(oc);
1610 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1611
1612 mc->desc = "RISC-V VirtIO board";
1613 mc->init = virt_machine_init;
1614 mc->max_cpus = VIRT_CPUS_MAX;
1615 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
1616 mc->pci_allow_0_address = true;
1617 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
1618 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
1619 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
1620 mc->numa_mem_supported = true;
1621 mc->default_ram_id = "riscv_virt_board.ram";
1622 assert(!mc->get_hotplug_handler);
1623 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1624
1625 hc->plug = virt_machine_device_plug_cb;
1626
1627 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1628 #ifdef CONFIG_TPM
1629 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
1630 #endif
1631
1632 object_class_property_add_bool(oc, "aclint", virt_get_aclint,
1633 virt_set_aclint);
1634 object_class_property_set_description(oc, "aclint",
1635 "Set on/off to enable/disable "
1636 "emulating ACLINT devices");
1637
1638 object_class_property_add_str(oc, "aia", virt_get_aia,
1639 virt_set_aia);
1640 object_class_property_set_description(oc, "aia",
1641 "Set type of AIA interrupt "
1642 "conttoller. Valid values are "
1643 "none, aplic, and aplic-imsic.");
1644
1645 object_class_property_add_str(oc, "aia-guests",
1646 virt_get_aia_guests,
1647 virt_set_aia_guests);
1648 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
1649 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS);
1650 object_class_property_set_description(oc, "aia-guests", str);
1651 }
1652
1653 static const TypeInfo virt_machine_typeinfo = {
1654 .name = MACHINE_TYPE_NAME("virt"),
1655 .parent = TYPE_MACHINE,
1656 .class_init = virt_machine_class_init,
1657 .instance_init = virt_machine_instance_init,
1658 .instance_size = sizeof(RISCVVirtState),
1659 .interfaces = (InterfaceInfo[]) {
1660 { TYPE_HOTPLUG_HANDLER },
1661 { }
1662 },
1663 };
1664
1665 static void virt_machine_init_register_types(void)
1666 {
1667 type_register_static(&virt_machine_typeinfo);
1668 }
1669
1670 type_init(virt_machine_init_register_types)
AR7 emulation for QEMU