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icount: Take iothread lock when running QEMU timers
[qemu/ar7.git] / hw / riscv / sifive_u.c
blobe4c814a3ea3eb23820358ab986a700fc7e7f692c
1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:
9 *
10 * 0) UART
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 * 7) DMA (Direct Memory Access Controller)
18 * 8) SPI0 connected to an SPI flash
19 * 9) SPI2 connected to an SD card
20 * 10) PWM0 and PWM1
21 *
22 * This board currently generates devicetree dynamically that indicates at least
23 * two harts and up to five harts.
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms and conditions of the GNU General Public License,
27 * version 2 or later, as published by the Free Software Foundation.
28 *
29 * This program is distributed in the hope it will be useful, but WITHOUT
30 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
31 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
32 * more details.
33 *
34 * You should have received a copy of the GNU General Public License along with
35 * this program. If not, see <http://www.gnu.org/licenses/>.
36 */
37
38 #include "qemu/osdep.h"
39 #include "qemu/error-report.h"
40 #include "qapi/error.h"
41 #include "qapi/visitor.h"
42 #include "hw/boards.h"
43 #include "hw/irq.h"
44 #include "hw/loader.h"
45 #include "hw/sysbus.h"
46 #include "hw/char/serial.h"
47 #include "hw/cpu/cluster.h"
48 #include "hw/misc/unimp.h"
49 #include "hw/sd/sd.h"
50 #include "hw/ssi/ssi.h"
51 #include "target/riscv/cpu.h"
52 #include "hw/riscv/riscv_hart.h"
53 #include "hw/riscv/sifive_u.h"
54 #include "hw/riscv/boot.h"
55 #include "hw/char/sifive_uart.h"
56 #include "hw/intc/riscv_aclint.h"
57 #include "hw/intc/sifive_plic.h"
58 #include "chardev/char.h"
59 #include "net/eth.h"
60 #include "sysemu/device_tree.h"
61 #include "sysemu/runstate.h"
62 #include "sysemu/sysemu.h"
63
64 #include <libfdt.h>
65
66 /* CLINT timebase frequency */
67 #define CLINT_TIMEBASE_FREQ 1000000
68
69 static const MemMapEntry sifive_u_memmap[] = {
70 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
71 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
72 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
73 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
74 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
75 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
76 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
77 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
78 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
79 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
80 [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 },
81 [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 },
82 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
83 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },
84 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
85 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
86 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
87 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
88 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
89 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
90 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
91 };
92
93 #define OTP_SERIAL 1
94 #define GEM_REVISION 0x10070109
95
96 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
97 uint64_t mem_size, const char *cmdline, bool is_32_bit)
98 {
99 MachineState *ms = MACHINE(qdev_get_machine());
100 void *fdt;
101 int cpu;
102 uint32_t *cells;
103 char *nodename;
104 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
105 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
106 static const char * const ethclk_names[2] = { "pclk", "hclk" };
107 static const char * const clint_compat[2] = {
108 "sifive,clint0", "riscv,clint0"
109 };
110 static const char * const plic_compat[2] = {
111 "sifive,plic-1.0.0", "riscv,plic0"
112 };
113
114 if (ms->dtb) {
115 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
116 if (!fdt) {
117 error_report("load_device_tree() failed");
118 exit(1);
119 }
120 goto update_bootargs;
121 } else {
122 fdt = s->fdt = create_device_tree(&s->fdt_size);
123 if (!fdt) {
124 error_report("create_device_tree() failed");
125 exit(1);
126 }
127 }
128
129 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
130 qemu_fdt_setprop_string(fdt, "/", "compatible",
131 "sifive,hifive-unleashed-a00");
132 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
133 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
134
135 qemu_fdt_add_subnode(fdt, "/soc");
136 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
137 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
138 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
139 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
140
141 hfclk_phandle = phandle++;
142 nodename = g_strdup_printf("/hfclk");
143 qemu_fdt_add_subnode(fdt, nodename);
144 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
145 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
146 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
147 SIFIVE_U_HFCLK_FREQ);
148 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
149 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
150 g_free(nodename);
151
152 rtcclk_phandle = phandle++;
153 nodename = g_strdup_printf("/rtcclk");
154 qemu_fdt_add_subnode(fdt, nodename);
155 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
156 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
157 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
158 SIFIVE_U_RTCCLK_FREQ);
159 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
160 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
161 g_free(nodename);
162
163 nodename = g_strdup_printf("/memory@%lx",
164 (long)memmap[SIFIVE_U_DEV_DRAM].base);
165 qemu_fdt_add_subnode(fdt, nodename);
166 qemu_fdt_setprop_cells(fdt, nodename, "reg",
167 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
168 mem_size >> 32, mem_size);
169 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
170 g_free(nodename);
171
172 qemu_fdt_add_subnode(fdt, "/cpus");
173 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
174 CLINT_TIMEBASE_FREQ);
175 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
176 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
177
178 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
179 int cpu_phandle = phandle++;
180 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
181 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
182 char *isa;
183 qemu_fdt_add_subnode(fdt, nodename);
184 /* cpu 0 is the management hart that does not have mmu */
185 if (cpu != 0) {
186 if (is_32_bit) {
187 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
188 } else {
189 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
190 }
191 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
192 } else {
193 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
194 }
195 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
196 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
197 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
198 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
199 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
200 qemu_fdt_add_subnode(fdt, intc);
201 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
202 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
203 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
204 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
205 g_free(isa);
206 g_free(intc);
207 g_free(nodename);
208 }
209
210 cells = g_new0(uint32_t, ms->smp.cpus * 4);
211 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
212 nodename =
213 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
214 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
215 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
216 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
217 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
218 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
219 g_free(nodename);
220 }
221 nodename = g_strdup_printf("/soc/clint@%lx",
222 (long)memmap[SIFIVE_U_DEV_CLINT].base);
223 qemu_fdt_add_subnode(fdt, nodename);
224 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
225 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
226 qemu_fdt_setprop_cells(fdt, nodename, "reg",
227 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
228 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
229 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
230 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
231 g_free(cells);
232 g_free(nodename);
233
234 nodename = g_strdup_printf("/soc/otp@%lx",
235 (long)memmap[SIFIVE_U_DEV_OTP].base);
236 qemu_fdt_add_subnode(fdt, nodename);
237 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
238 qemu_fdt_setprop_cells(fdt, nodename, "reg",
239 0x0, memmap[SIFIVE_U_DEV_OTP].base,
240 0x0, memmap[SIFIVE_U_DEV_OTP].size);
241 qemu_fdt_setprop_string(fdt, nodename, "compatible",
242 "sifive,fu540-c000-otp");
243 g_free(nodename);
244
245 prci_phandle = phandle++;
246 nodename = g_strdup_printf("/soc/clock-controller@%lx",
247 (long)memmap[SIFIVE_U_DEV_PRCI].base);
248 qemu_fdt_add_subnode(fdt, nodename);
249 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
250 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
251 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
252 hfclk_phandle, rtcclk_phandle);
253 qemu_fdt_setprop_cells(fdt, nodename, "reg",
254 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
255 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
256 qemu_fdt_setprop_string(fdt, nodename, "compatible",
257 "sifive,fu540-c000-prci");
258 g_free(nodename);
259
260 plic_phandle = phandle++;
261 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
262 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
263 nodename =
264 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
265 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
266 /* cpu 0 is the management hart that does not have S-mode */
267 if (cpu == 0) {
268 cells[0] = cpu_to_be32(intc_phandle);
269 cells[1] = cpu_to_be32(IRQ_M_EXT);
270 } else {
271 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
272 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
273 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
274 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
275 }
276 g_free(nodename);
277 }
278 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
279 (long)memmap[SIFIVE_U_DEV_PLIC].base);
280 qemu_fdt_add_subnode(fdt, nodename);
281 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
282 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
283 (char **)&plic_compat, ARRAY_SIZE(plic_compat));
284 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
285 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
286 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
287 qemu_fdt_setprop_cells(fdt, nodename, "reg",
288 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
289 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
290 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
291 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
292 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
293 g_free(cells);
294 g_free(nodename);
295
296 gpio_phandle = phandle++;
297 nodename = g_strdup_printf("/soc/gpio@%lx",
298 (long)memmap[SIFIVE_U_DEV_GPIO].base);
299 qemu_fdt_add_subnode(fdt, nodename);
300 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
301 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
302 prci_phandle, PRCI_CLK_TLCLK);
303 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
304 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
305 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
306 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
307 qemu_fdt_setprop_cells(fdt, nodename, "reg",
308 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
309 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
310 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
311 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
312 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
313 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
314 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
315 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
316 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
317 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
318 g_free(nodename);
319
320 nodename = g_strdup_printf("/gpio-restart");
321 qemu_fdt_add_subnode(fdt, nodename);
322 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
323 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
324 g_free(nodename);
325
326 nodename = g_strdup_printf("/soc/dma@%lx",
327 (long)memmap[SIFIVE_U_DEV_PDMA].base);
328 qemu_fdt_add_subnode(fdt, nodename);
329 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
330 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
331 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
332 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
333 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
334 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
335 qemu_fdt_setprop_cells(fdt, nodename, "reg",
336 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
337 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
338 qemu_fdt_setprop_string(fdt, nodename, "compatible",
339 "sifive,fu540-c000-pdma");
340 g_free(nodename);
341
342 nodename = g_strdup_printf("/soc/cache-controller@%lx",
343 (long)memmap[SIFIVE_U_DEV_L2CC].base);
344 qemu_fdt_add_subnode(fdt, nodename);
345 qemu_fdt_setprop_cells(fdt, nodename, "reg",
346 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
347 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
348 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
349 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
350 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
351 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
352 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
353 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
354 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
355 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
356 qemu_fdt_setprop_string(fdt, nodename, "compatible",
357 "sifive,fu540-c000-ccache");
358 g_free(nodename);
359
360 nodename = g_strdup_printf("/soc/spi@%lx",
361 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
362 qemu_fdt_add_subnode(fdt, nodename);
363 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
364 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
365 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
366 prci_phandle, PRCI_CLK_TLCLK);
367 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
368 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
369 qemu_fdt_setprop_cells(fdt, nodename, "reg",
370 0x0, memmap[SIFIVE_U_DEV_QSPI2].base,
371 0x0, memmap[SIFIVE_U_DEV_QSPI2].size);
372 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
373 g_free(nodename);
374
375 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
376 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
377 qemu_fdt_add_subnode(fdt, nodename);
378 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
379 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
380 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
381 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
382 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
383 g_free(nodename);
384
385 nodename = g_strdup_printf("/soc/spi@%lx",
386 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
387 qemu_fdt_add_subnode(fdt, nodename);
388 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
389 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
390 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
391 prci_phandle, PRCI_CLK_TLCLK);
392 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
393 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
394 qemu_fdt_setprop_cells(fdt, nodename, "reg",
395 0x0, memmap[SIFIVE_U_DEV_QSPI0].base,
396 0x0, memmap[SIFIVE_U_DEV_QSPI0].size);
397 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
398 g_free(nodename);
399
400 nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
401 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
402 qemu_fdt_add_subnode(fdt, nodename);
403 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
404 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
405 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
406 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
407 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
408 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
409 g_free(nodename);
410
411 phy_phandle = phandle++;
412 nodename = g_strdup_printf("/soc/ethernet@%lx",
413 (long)memmap[SIFIVE_U_DEV_GEM].base);
414 qemu_fdt_add_subnode(fdt, nodename);
415 qemu_fdt_setprop_string(fdt, nodename, "compatible",
416 "sifive,fu540-c000-gem");
417 qemu_fdt_setprop_cells(fdt, nodename, "reg",
418 0x0, memmap[SIFIVE_U_DEV_GEM].base,
419 0x0, memmap[SIFIVE_U_DEV_GEM].size,
420 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
421 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
422 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
423 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
424 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
425 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
426 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
427 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
428 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
429 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
430 (char **)&ethclk_names, ARRAY_SIZE(ethclk_names));
431 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
432 s->soc.gem.conf.macaddr.a, ETH_ALEN);
433 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
434 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
435
436 qemu_fdt_add_subnode(fdt, "/aliases");
437 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
438
439 g_free(nodename);
440
441 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
442 (long)memmap[SIFIVE_U_DEV_GEM].base);
443 qemu_fdt_add_subnode(fdt, nodename);
444 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
445 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
446 g_free(nodename);
447
448 nodename = g_strdup_printf("/soc/pwm@%lx",
449 (long)memmap[SIFIVE_U_DEV_PWM0].base);
450 qemu_fdt_add_subnode(fdt, nodename);
451 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
452 qemu_fdt_setprop_cells(fdt, nodename, "reg",
453 0x0, memmap[SIFIVE_U_DEV_PWM0].base,
454 0x0, memmap[SIFIVE_U_DEV_PWM0].size);
455 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
456 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
457 SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
458 SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
459 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
460 prci_phandle, PRCI_CLK_TLCLK);
461 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
462 g_free(nodename);
463
464 nodename = g_strdup_printf("/soc/pwm@%lx",
465 (long)memmap[SIFIVE_U_DEV_PWM1].base);
466 qemu_fdt_add_subnode(fdt, nodename);
467 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
468 qemu_fdt_setprop_cells(fdt, nodename, "reg",
469 0x0, memmap[SIFIVE_U_DEV_PWM1].base,
470 0x0, memmap[SIFIVE_U_DEV_PWM1].size);
471 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
472 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
473 SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1,
474 SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3);
475 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
476 prci_phandle, PRCI_CLK_TLCLK);
477 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
478 g_free(nodename);
479
480 nodename = g_strdup_printf("/soc/serial@%lx",
481 (long)memmap[SIFIVE_U_DEV_UART1].base);
482 qemu_fdt_add_subnode(fdt, nodename);
483 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
484 qemu_fdt_setprop_cells(fdt, nodename, "reg",
485 0x0, memmap[SIFIVE_U_DEV_UART1].base,
486 0x0, memmap[SIFIVE_U_DEV_UART1].size);
487 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
488 prci_phandle, PRCI_CLK_TLCLK);
489 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
490 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
491
492 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
493 g_free(nodename);
494
495 nodename = g_strdup_printf("/soc/serial@%lx",
496 (long)memmap[SIFIVE_U_DEV_UART0].base);
497 qemu_fdt_add_subnode(fdt, nodename);
498 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
499 qemu_fdt_setprop_cells(fdt, nodename, "reg",
500 0x0, memmap[SIFIVE_U_DEV_UART0].base,
501 0x0, memmap[SIFIVE_U_DEV_UART0].size);
502 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
503 prci_phandle, PRCI_CLK_TLCLK);
504 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
505 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
506
507 qemu_fdt_add_subnode(fdt, "/chosen");
508 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
509 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
510
511 g_free(nodename);
512
513 update_bootargs:
514 if (cmdline && *cmdline) {
515 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
516 }
517 }
518
519 static void sifive_u_machine_reset(void *opaque, int n, int level)
520 {
521 /* gpio pin active low triggers reset */
522 if (!level) {
523 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
524 }
525 }
526
527 static void sifive_u_machine_init(MachineState *machine)
528 {
529 const MemMapEntry *memmap = sifive_u_memmap;
530 SiFiveUState *s = RISCV_U_MACHINE(machine);
531 MemoryRegion *system_memory = get_system_memory();
532 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
533 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
534 target_ulong firmware_end_addr, kernel_start_addr;
535 uint32_t start_addr_hi32 = 0x00000000;
536 int i;
537 uint32_t fdt_load_addr;
538 uint64_t kernel_entry;
539 DriveInfo *dinfo;
540 BlockBackend *blk;
541 DeviceState *flash_dev, *sd_dev, *card_dev;
542 qemu_irq flash_cs, sd_cs;
543
544 /* Initialize SoC */
545 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
546 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
547 &error_abort);
548 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
549 &error_abort);
550 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
551
552 /* register RAM */
553 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
554 machine->ram);
555
556 /* register QSPI0 Flash */
557 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
558 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
559 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
560 flash0);
561
562 /* register gpio-restart */
563 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
564 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
565
566 /* create device tree */
567 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
568 riscv_is_32bit(&s->soc.u_cpus));
569
570 if (s->start_in_flash) {
571 /*
572 * If start_in_flash property is given, assign s->msel to a value
573 * that representing booting from QSPI0 memory-mapped flash.
574 *
575 * This also means that when both start_in_flash and msel properties
576 * are given, start_in_flash takes the precedence over msel.
577 *
578 * Note this is to keep backward compatibility not to break existing
579 * users that use start_in_flash property.
580 */
581 s->msel = MSEL_MEMMAP_QSPI0_FLASH;
582 }
583
584 switch (s->msel) {
585 case MSEL_MEMMAP_QSPI0_FLASH:
586 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
587 break;
588 case MSEL_L2LIM_QSPI0_FLASH:
589 case MSEL_L2LIM_QSPI2_SD:
590 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
591 break;
592 default:
593 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
594 break;
595 }
596
597 if (riscv_is_32bit(&s->soc.u_cpus)) {
598 firmware_end_addr = riscv_find_and_load_firmware(machine,
599 RISCV32_BIOS_BIN, start_addr, NULL);
600 } else {
601 firmware_end_addr = riscv_find_and_load_firmware(machine,
602 RISCV64_BIOS_BIN, start_addr, NULL);
603 }
604
605 if (machine->kernel_filename) {
606 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
607 firmware_end_addr);
608
609 kernel_entry = riscv_load_kernel(machine->kernel_filename,
610 kernel_start_addr, NULL);
611
612 if (machine->initrd_filename) {
613 hwaddr start;
614 hwaddr end = riscv_load_initrd(machine->initrd_filename,
615 machine->ram_size, kernel_entry,
616 &start);
617 qemu_fdt_setprop_cell(s->fdt, "/chosen",
618 "linux,initrd-start", start);
619 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
620 end);
621 }
622 } else {
623 /*
624 * If dynamic firmware is used, it doesn't know where is the next mode
625 * if kernel argument is not set.
626 */
627 kernel_entry = 0;
628 }
629
630 /* Compute the fdt load address in dram */
631 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
632 machine->ram_size, s->fdt);
633 if (!riscv_is_32bit(&s->soc.u_cpus)) {
634 start_addr_hi32 = (uint64_t)start_addr >> 32;
635 }
636
637 /* reset vector */
638 uint32_t reset_vec[12] = {
639 s->msel, /* MSEL pin state */
640 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
641 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
642 0xf1402573, /* csrr a0, mhartid */
643 0,
644 0,
645 0x00028067, /* jr t0 */
646 start_addr, /* start: .dword */
647 start_addr_hi32,
648 fdt_load_addr, /* fdt_laddr: .dword */
649 0x00000000,
650 0x00000000,
651 /* fw_dyn: */
652 };
653 if (riscv_is_32bit(&s->soc.u_cpus)) {
654 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
655 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
656 } else {
657 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
658 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
659 }
660
661
662 /* copy in the reset vector in little_endian byte order */
663 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
664 reset_vec[i] = cpu_to_le32(reset_vec[i]);
665 }
666 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
667 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
668
669 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
670 memmap[SIFIVE_U_DEV_MROM].size,
671 sizeof(reset_vec), kernel_entry);
672
673 /* Connect an SPI flash to SPI0 */
674 flash_dev = qdev_new("is25wp256");
675 dinfo = drive_get(IF_MTD, 0, 0);
676 if (dinfo) {
677 qdev_prop_set_drive_err(flash_dev, "drive",
678 blk_by_legacy_dinfo(dinfo),
679 &error_fatal);
680 }
681 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
682
683 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
684 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
685
686 /* Connect an SD card to SPI2 */
687 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
688
689 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
690 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
691
692 dinfo = drive_get(IF_SD, 0, 0);
693 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
694 card_dev = qdev_new(TYPE_SD_CARD);
695 qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal);
696 qdev_prop_set_bit(card_dev, "spi", true);
697 qdev_realize_and_unref(card_dev,
698 qdev_get_child_bus(sd_dev, "sd-bus"),
699 &error_fatal);
700 }
701
702 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
703 {
704 SiFiveUState *s = RISCV_U_MACHINE(obj);
705
706 return s->start_in_flash;
707 }
708
709 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
710 {
711 SiFiveUState *s = RISCV_U_MACHINE(obj);
712
713 s->start_in_flash = value;
714 }
715
716 static void sifive_u_machine_instance_init(Object *obj)
717 {
718 SiFiveUState *s = RISCV_U_MACHINE(obj);
719
720 s->start_in_flash = false;
721 s->msel = 0;
722 object_property_add_uint32_ptr(obj, "msel", &s->msel,
723 OBJ_PROP_FLAG_READWRITE);
724 object_property_set_description(obj, "msel",
725 "Mode Select (MSEL[3:0]) pin state");
726
727 s->serial = OTP_SERIAL;
728 object_property_add_uint32_ptr(obj, "serial", &s->serial,
729 OBJ_PROP_FLAG_READWRITE);
730 object_property_set_description(obj, "serial", "Board serial number");
731 }
732
733 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
734 {
735 MachineClass *mc = MACHINE_CLASS(oc);
736
737 mc->desc = "RISC-V Board compatible with SiFive U SDK";
738 mc->init = sifive_u_machine_init;
739 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
740 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
741 mc->default_cpu_type = SIFIVE_U_CPU;
742 mc->default_cpus = mc->min_cpus;
743 mc->default_ram_id = "riscv.sifive.u.ram";
744
745 object_class_property_add_bool(oc, "start-in-flash",
746 sifive_u_machine_get_start_in_flash,
747 sifive_u_machine_set_start_in_flash);
748 object_class_property_set_description(oc, "start-in-flash",
749 "Set on to tell QEMU's ROM to jump to "
750 "flash. Otherwise QEMU will jump to DRAM "
751 "or L2LIM depending on the msel value");
752 }
753
754 static const TypeInfo sifive_u_machine_typeinfo = {
755 .name = MACHINE_TYPE_NAME("sifive_u"),
756 .parent = TYPE_MACHINE,
757 .class_init = sifive_u_machine_class_init,
758 .instance_init = sifive_u_machine_instance_init,
759 .instance_size = sizeof(SiFiveUState),
760 };
761
762 static void sifive_u_machine_init_register_types(void)
763 {
764 type_register_static(&sifive_u_machine_typeinfo);
765 }
766
767 type_init(sifive_u_machine_init_register_types)
768
769 static void sifive_u_soc_instance_init(Object *obj)
770 {
771 SiFiveUSoCState *s = RISCV_U_SOC(obj);
772
773 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
774 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
775
776 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
777 TYPE_RISCV_HART_ARRAY);
778 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
779 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
780 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
781 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
782
783 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
784 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
785
786 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
787 TYPE_RISCV_HART_ARRAY);
788
789 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
790 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
791 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
792 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
793 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
794 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
795 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
796 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM);
797 object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM);
798 }
799
800 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
801 {
802 MachineState *ms = MACHINE(qdev_get_machine());
803 SiFiveUSoCState *s = RISCV_U_SOC(dev);
804 const MemMapEntry *memmap = sifive_u_memmap;
805 MemoryRegion *system_memory = get_system_memory();
806 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
807 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
808 char *plic_hart_config;
809 int i, j;
810 NICInfo *nd = &nd_table[0];
811
812 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
813 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
814 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
815 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
816
817 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
818 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
819 /*
820 * The cluster must be realized after the RISC-V hart array container,
821 * as the container's CPU object is only created on realize, and the
822 * CPU must exist and have been parented into the cluster before the
823 * cluster is realized.
824 */
825 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
826 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
827
828 /* boot rom */
829 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
830 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
831 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
832 mask_rom);
833
834 /*
835 * Add L2-LIM at reset size.
836 * This should be reduced in size as the L2 Cache Controller WayEnable
837 * register is incremented. Unfortunately I don't see a nice (or any) way
838 * to handle reducing or blocking out the L2 LIM while still allowing it
839 * be re returned to all enabled after a reset. For the time being, just
840 * leave it enabled all the time. This won't break anything, but will be
841 * too generous to misbehaving guests.
842 */
843 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
844 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
845 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
846 l2lim_mem);
847
848 /* create PLIC hart topology configuration string */
849 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
850
851 /* MMIO */
852 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
853 plic_hart_config, ms->smp.cpus, 0,
854 SIFIVE_U_PLIC_NUM_SOURCES,
855 SIFIVE_U_PLIC_NUM_PRIORITIES,
856 SIFIVE_U_PLIC_PRIORITY_BASE,
857 SIFIVE_U_PLIC_PENDING_BASE,
858 SIFIVE_U_PLIC_ENABLE_BASE,
859 SIFIVE_U_PLIC_ENABLE_STRIDE,
860 SIFIVE_U_PLIC_CONTEXT_BASE,
861 SIFIVE_U_PLIC_CONTEXT_STRIDE,
862 memmap[SIFIVE_U_DEV_PLIC].size);
863 g_free(plic_hart_config);
864 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
865 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
866 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
867 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
868 riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0,
869 ms->smp.cpus, false);
870 riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base +
871 RISCV_ACLINT_SWI_SIZE,
872 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
873 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
874 CLINT_TIMEBASE_FREQ, false);
875
876 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
877 return;
878 }
879 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
880
881 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
882 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
883 return;
884 }
885 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
886
887 /* Pass all GPIOs to the SOC layer so they are available to the board */
888 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
889
890 /* Connect GPIO interrupts to the PLIC */
891 for (i = 0; i < 16; i++) {
892 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
893 qdev_get_gpio_in(DEVICE(s->plic),
894 SIFIVE_U_GPIO_IRQ0 + i));
895 }
896
897 /* PDMA */
898 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
899 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
900
901 /* Connect PDMA interrupts to the PLIC */
902 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
903 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
904 qdev_get_gpio_in(DEVICE(s->plic),
905 SIFIVE_U_PDMA_IRQ0 + i));
906 }
907
908 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
909 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
910 return;
911 }
912 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
913
914 /* FIXME use qdev NIC properties instead of nd_table[] */
915 if (nd->used) {
916 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
917 qdev_set_nic_properties(DEVICE(&s->gem), nd);
918 }
919 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
920 &error_abort);
921 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
922 return;
923 }
924 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
925 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
926 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
927
928 /* PWM */
929 for (i = 0; i < 2; i++) {
930 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) {
931 return;
932 }
933 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0,
934 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i));
935
936 /* Connect PWM interrupts to the PLIC */
937 for (j = 0; j < SIFIVE_PWM_IRQS; j++) {
938 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j,
939 qdev_get_gpio_in(DEVICE(s->plic),
940 SIFIVE_U_PWM0_IRQ0 + (i * 4) + j));
941 }
942 }
943
944 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
945 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
946
947 create_unimplemented_device("riscv.sifive.u.dmc",
948 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
949
950 create_unimplemented_device("riscv.sifive.u.l2cc",
951 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
952
953 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
954 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
955 memmap[SIFIVE_U_DEV_QSPI0].base);
956 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
957 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));
958 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
959 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
960 memmap[SIFIVE_U_DEV_QSPI2].base);
961 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
962 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
963 }
964
965 static Property sifive_u_soc_props[] = {
966 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
967 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
968 DEFINE_PROP_END_OF_LIST()
969 };
970
971 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
972 {
973 DeviceClass *dc = DEVICE_CLASS(oc);
974
975 device_class_set_props(dc, sifive_u_soc_props);
976 dc->realize = sifive_u_soc_realize;
977 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
978 dc->user_creatable = false;
979 }
980
981 static const TypeInfo sifive_u_soc_type_info = {
982 .name = TYPE_RISCV_U_SOC,
983 .parent = TYPE_DEVICE,
984 .instance_size = sizeof(SiFiveUSoCState),
985 .instance_init = sifive_u_soc_instance_init,
986 .class_init = sifive_u_soc_class_init,
987 };
988
989 static void sifive_u_soc_register_types(void)
990 {
991 type_register_static(&sifive_u_soc_type_info);
992 }
993
994 type_init(sifive_u_soc_register_types)
AR7 emulation for QEMU