hw/riscv/opentitan.c

   1 /*
   2  * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * Provides a board compatible with the OpenTitan FPGA platform:
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/cutils.h"
  23 #include "hw/riscv/opentitan.h"
  24 #include "qapi/error.h"
  25 #include "hw/boards.h"
  26 #include "hw/misc/unimp.h"
  27 #include "hw/riscv/boot.h"
  28 #include "qemu/units.h"
  29 #include "sysemu/sysemu.h"
  30
  31 static const MemMapEntry ibex_memmap[] = {
  32     [IBEX_DEV_ROM] =            {  0x00008000, 16 * KiB },
  33     [IBEX_DEV_RAM] =            {  0x10000000,  0x10000 },
  34     [IBEX_DEV_FLASH] =          {  0x20000000,  0x80000 },
  35     [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
  36     [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
  37     [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
  38     [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
  39     [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
  40     [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
  41     [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
  42     [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
  43     [IBEX_DEV_USBDEV] =         {  0x40150000,  0x1000  },
  44     [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
  45     [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
  46     [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
  47     [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
  48     [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
  49     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
  50     [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
  51     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
  52     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
  53     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
  54     [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
  55     [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
  56     [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
  57     [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
  58     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
  59     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
  60     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
  61     [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
  62     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
  63     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
  64     [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000  },
  65     [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
  66 };
  67
  68 static void opentitan_board_init(MachineState *machine)
  69 {
  70     MachineClass *mc = MACHINE_GET_CLASS(machine);
  71     const MemMapEntry *memmap = ibex_memmap;
  72     OpenTitanState *s = g_new0(OpenTitanState, 1);
  73     MemoryRegion *sys_mem = get_system_memory();
  74
  75     if (machine->ram_size != mc->default_ram_size) {
  76         char *sz = size_to_str(mc->default_ram_size);
  77         error_report("Invalid RAM size, should be %s", sz);
  78         g_free(sz);
  79         exit(EXIT_FAILURE);
  80     }
  81
  82     /* Initialize SoC */
  83     object_initialize_child(OBJECT(machine), "soc", &s->soc,
  84                             TYPE_RISCV_IBEX_SOC);
  85     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
  86
  87     memory_region_add_subregion(sys_mem,
  88         memmap[IBEX_DEV_RAM].base, machine->ram);
  89
  90     if (machine->firmware) {
  91         riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
  92     }
  93
  94     if (machine->kernel_filename) {
  95         riscv_load_kernel(machine->kernel_filename,
  96                           memmap[IBEX_DEV_RAM].base, NULL);
  97     }
  98 }
  99
 100 static void opentitan_machine_init(MachineClass *mc)
 101 {
 102     mc->desc = "RISC-V Board compatible with OpenTitan";
 103     mc->init = opentitan_board_init;
 104     mc->max_cpus = 1;
 105     mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
 106     mc->default_ram_id = "riscv.lowrisc.ibex.ram";
 107     mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
 108 }
 109
 110 DEFINE_MACHINE("opentitan", opentitan_machine_init)
 111
 112 static void lowrisc_ibex_soc_init(Object *obj)
 113 {
 114     LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
 115
 116     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 117
 118     object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
 119
 120     object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
 121
 122     object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
 123
 124     for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
 125         object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
 126                                 TYPE_IBEX_SPI_HOST);
 127     }
 128 }
 129
 130 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
 131 {
 132     const MemMapEntry *memmap = ibex_memmap;
 133     DeviceState *dev;
 134     SysBusDevice *busdev;
 135     MachineState *ms = MACHINE(qdev_get_machine());
 136     LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
 137     MemoryRegion *sys_mem = get_system_memory();
 138     int i;
 139
 140     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
 141                             &error_abort);
 142     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
 143                             &error_abort);
 144     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
 145     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 146
 147     /* Boot ROM */
 148     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
 149                            memmap[IBEX_DEV_ROM].size, &error_fatal);
 150     memory_region_add_subregion(sys_mem,
 151         memmap[IBEX_DEV_ROM].base, &s->rom);
 152
 153     /* Flash memory */
 154     memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
 155                            memmap[IBEX_DEV_FLASH].size, &error_fatal);
 156     memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
 157                              "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
 158                              memmap[IBEX_DEV_FLASH_VIRTUAL].size);
 159     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
 160                                 &s->flash_mem);
 161     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
 162                                 &s->flash_alias);
 163
 164     /* PLIC */
 165     qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
 166     qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
 167     qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
 168     qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
 169     qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
 170     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
 171     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
 172     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
 173     qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
 174     qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
 175     qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
 176
 177     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
 178         return;
 179     }
 180     sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
 181
 182     for (i = 0; i < ms->smp.cpus; i++) {
 183         CPUState *cpu = qemu_get_cpu(i);
 184
 185         qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
 186                               qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
 187     }
 188
 189     /* UART */
 190     qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
 191     if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
 192         return;
 193     }
 194     sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
 195     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 196                        0, qdev_get_gpio_in(DEVICE(&s->plic),
 197                        IBEX_UART0_TX_WATERMARK_IRQ));
 198     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 199                        1, qdev_get_gpio_in(DEVICE(&s->plic),
 200                        IBEX_UART0_RX_WATERMARK_IRQ));
 201     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 202                        2, qdev_get_gpio_in(DEVICE(&s->plic),
 203                        IBEX_UART0_TX_EMPTY_IRQ));
 204     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 205                        3, qdev_get_gpio_in(DEVICE(&s->plic),
 206                        IBEX_UART0_RX_OVERFLOW_IRQ));
 207
 208     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
 209         return;
 210     }
 211     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
 212     sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
 213                        0, qdev_get_gpio_in(DEVICE(&s->plic),
 214                        IBEX_TIMER_TIMEREXPIRED0_0));
 215     qdev_connect_gpio_out(DEVICE(&s->timer), 0,
 216                           qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
 217                                            IRQ_M_TIMER));
 218
 219     /* SPI-Hosts */
 220     for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
 221         dev = DEVICE(&(s->spi_host[i]));
 222         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
 223             return;
 224         }
 225         busdev = SYS_BUS_DEVICE(dev);
 226         sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
 227
 228         switch (i) {
 229         case OPENTITAN_SPI_HOST0:
 230             sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
 231                                 IBEX_SPI_HOST0_ERR_IRQ));
 232             sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
 233                                 IBEX_SPI_HOST0_SPI_EVENT_IRQ));
 234             break;
 235         case OPENTITAN_SPI_HOST1:
 236             sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
 237                                 IBEX_SPI_HOST1_ERR_IRQ));
 238             sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
 239                                 IBEX_SPI_HOST1_SPI_EVENT_IRQ));
 240             break;
 241         }
 242     }
 243
 244     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
 245         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
 246     create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
 247         memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
 248     create_unimplemented_device("riscv.lowrisc.ibex.i2c",
 249         memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
 250     create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
 251         memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
 252     create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
 253         memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
 254     create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
 255         memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
 256     create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
 257         memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
 258     create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
 259         memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
 260     create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
 261         memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
 262     create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
 263         memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
 264     create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
 265         memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
 266     create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
 267         memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
 268     create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
 269         memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
 270     create_unimplemented_device("riscv.lowrisc.ibex.aes",
 271         memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
 272     create_unimplemented_device("riscv.lowrisc.ibex.hmac",
 273         memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
 274     create_unimplemented_device("riscv.lowrisc.ibex.kmac",
 275         memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
 276     create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
 277         memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
 278     create_unimplemented_device("riscv.lowrisc.ibex.csrng",
 279         memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
 280     create_unimplemented_device("riscv.lowrisc.ibex.entropy",
 281         memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
 282     create_unimplemented_device("riscv.lowrisc.ibex.edn0",
 283         memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
 284     create_unimplemented_device("riscv.lowrisc.ibex.edn1",
 285         memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
 286     create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
 287         memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
 288     create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
 289         memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
 290     create_unimplemented_device("riscv.lowrisc.ibex.otbn",
 291         memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
 292     create_unimplemented_device("riscv.lowrisc.ibex.peri",
 293         memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
 294 }
 295
 296 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
 297 {
 298     DeviceClass *dc = DEVICE_CLASS(oc);
 299
 300     dc->realize = lowrisc_ibex_soc_realize;
 301     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 302     dc->user_creatable = false;
 303 }
 304
 305 static const TypeInfo lowrisc_ibex_soc_type_info = {
 306     .name = TYPE_RISCV_IBEX_SOC,
 307     .parent = TYPE_DEVICE,
 308     .instance_size = sizeof(LowRISCIbexSoCState),
 309     .instance_init = lowrisc_ibex_soc_init,
 310     .class_init = lowrisc_ibex_soc_class_init,
 311 };
 312
 313 static void lowrisc_ibex_soc_register_types(void)
 314 {
 315     type_register_static(&lowrisc_ibex_soc_type_info);
 316 }
 317
 318 type_init(lowrisc_ibex_soc_register_types)