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icount: Take iothread lock when running QEMU timers
[qemu/ar7.git] / hw / ppc / ppc405_uc.c
blobd6420c88d3a66de3468e9dcdceeed0f632da222e
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu/log.h"
29 #include "cpu.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/i2c/ppc4xx_i2c.h"
32 #include "hw/irq.h"
33 #include "ppc405.h"
34 #include "hw/char/serial.h"
35 #include "qemu/timer.h"
36 #include "sysemu/reset.h"
37 #include "sysemu/sysemu.h"
38 #include "exec/address-spaces.h"
39 #include "hw/intc/ppc-uic.h"
40 #include "hw/qdev-properties.h"
41 #include "qapi/error.h"
42 #include "trace.h"
43
44 static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
45 ram_addr_t ram_size)
46 {
47 memset(bd, 0, sizeof(*bd));
48
49 bd->bi_memstart = PPC405EP_SDRAM_BASE;
50 bd->bi_memsize = ram_size;
51 bd->bi_sramstart = PPC405EP_SRAM_BASE;
52 bd->bi_sramsize = PPC405EP_SRAM_SIZE;
53 bd->bi_bootflags = 0;
54 bd->bi_intfreq = 133333333;
55 bd->bi_busfreq = 33333333;
56 bd->bi_baudrate = 115200;
57 bd->bi_s_version[0] = 'Q';
58 bd->bi_s_version[1] = 'M';
59 bd->bi_s_version[2] = 'U';
60 bd->bi_s_version[3] = '\0';
61 bd->bi_r_version[0] = 'Q';
62 bd->bi_r_version[1] = 'E';
63 bd->bi_r_version[2] = 'M';
64 bd->bi_r_version[3] = 'U';
65 bd->bi_r_version[4] = '\0';
66 bd->bi_procfreq = 133333333;
67 bd->bi_plb_busfreq = 33333333;
68 bd->bi_pci_busfreq = 33333333;
69 bd->bi_opbfreq = 33333333;
70 }
71
72 static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
73 {
74 CPUState *cs = env_cpu(env);
75 ram_addr_t bdloc;
76 int i, n;
77
78 /* We put the bd structure at the top of memory */
79 if (bd->bi_memsize >= 0x01000000UL)
80 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
81 else
82 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
83 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
84 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
85 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
86 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
87 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
88 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
89 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
90 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
91 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
92 for (i = 0; i < 6; i++) {
93 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
94 }
95 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
96 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
97 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
98 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
99 for (i = 0; i < 4; i++) {
100 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
101 }
102 for (i = 0; i < 32; i++) {
103 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
104 }
105 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
106 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
107 stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
108 for (i = 0; i < 6; i++) {
109 stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
110 }
111 n = 0x70; /* includes 2 bytes hole */
112 for (i = 0; i < 6; i++) {
113 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
114 }
115 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
116 n += 4;
117 for (i = 0; i < 2; i++) {
118 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
119 n += 4;
120 }
121
122 return bdloc;
123 }
124
125 ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
126 {
127 ppc4xx_bd_info_t bd;
128
129 memset(&bd, 0, sizeof(bd));
130
131 ppc405_set_default_bootinfo(&bd, ram_size);
132
133 return __ppc405_set_bootinfo(env, &bd);
134 }
135
136 /*****************************************************************************/
137 /* Shared peripherals */
138
139 /*****************************************************************************/
140 /* Peripheral local bus arbitrer */
141 enum {
142 PLB3A0_ACR = 0x077,
143 PLB4A0_ACR = 0x081,
144 PLB0_BESR = 0x084,
145 PLB0_BEAR = 0x086,
146 PLB0_ACR = 0x087,
147 PLB4A1_ACR = 0x089,
148 };
149
150 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
151 struct ppc4xx_plb_t {
152 uint32_t acr;
153 uint32_t bear;
154 uint32_t besr;
155 };
156
157 static uint32_t dcr_read_plb (void *opaque, int dcrn)
158 {
159 ppc4xx_plb_t *plb;
160 uint32_t ret;
161
162 plb = opaque;
163 switch (dcrn) {
164 case PLB0_ACR:
165 ret = plb->acr;
166 break;
167 case PLB0_BEAR:
168 ret = plb->bear;
169 break;
170 case PLB0_BESR:
171 ret = plb->besr;
172 break;
173 default:
174 /* Avoid gcc warning */
175 ret = 0;
176 break;
177 }
178
179 return ret;
180 }
181
182 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
183 {
184 ppc4xx_plb_t *plb;
185
186 plb = opaque;
187 switch (dcrn) {
188 case PLB0_ACR:
189 /* We don't care about the actual parameters written as
190 * we don't manage any priorities on the bus
191 */
192 plb->acr = val & 0xF8000000;
193 break;
194 case PLB0_BEAR:
195 /* Read only */
196 break;
197 case PLB0_BESR:
198 /* Write-clear */
199 plb->besr &= ~val;
200 break;
201 }
202 }
203
204 static void ppc4xx_plb_reset (void *opaque)
205 {
206 ppc4xx_plb_t *plb;
207
208 plb = opaque;
209 plb->acr = 0x00000000;
210 plb->bear = 0x00000000;
211 plb->besr = 0x00000000;
212 }
213
214 void ppc4xx_plb_init(CPUPPCState *env)
215 {
216 ppc4xx_plb_t *plb;
217
218 plb = g_new0(ppc4xx_plb_t, 1);
219 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
220 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
221 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
222 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
223 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
224 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
225 qemu_register_reset(ppc4xx_plb_reset, plb);
226 }
227
228 /*****************************************************************************/
229 /* PLB to OPB bridge */
230 enum {
231 POB0_BESR0 = 0x0A0,
232 POB0_BESR1 = 0x0A2,
233 POB0_BEAR = 0x0A4,
234 };
235
236 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
237 struct ppc4xx_pob_t {
238 uint32_t bear;
239 uint32_t besr0;
240 uint32_t besr1;
241 };
242
243 static uint32_t dcr_read_pob (void *opaque, int dcrn)
244 {
245 ppc4xx_pob_t *pob;
246 uint32_t ret;
247
248 pob = opaque;
249 switch (dcrn) {
250 case POB0_BEAR:
251 ret = pob->bear;
252 break;
253 case POB0_BESR0:
254 ret = pob->besr0;
255 break;
256 case POB0_BESR1:
257 ret = pob->besr1;
258 break;
259 default:
260 /* Avoid gcc warning */
261 ret = 0;
262 break;
263 }
264
265 return ret;
266 }
267
268 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
269 {
270 ppc4xx_pob_t *pob;
271
272 pob = opaque;
273 switch (dcrn) {
274 case POB0_BEAR:
275 /* Read only */
276 break;
277 case POB0_BESR0:
278 /* Write-clear */
279 pob->besr0 &= ~val;
280 break;
281 case POB0_BESR1:
282 /* Write-clear */
283 pob->besr1 &= ~val;
284 break;
285 }
286 }
287
288 static void ppc4xx_pob_reset (void *opaque)
289 {
290 ppc4xx_pob_t *pob;
291
292 pob = opaque;
293 /* No error */
294 pob->bear = 0x00000000;
295 pob->besr0 = 0x0000000;
296 pob->besr1 = 0x0000000;
297 }
298
299 static void ppc4xx_pob_init(CPUPPCState *env)
300 {
301 ppc4xx_pob_t *pob;
302
303 pob = g_new0(ppc4xx_pob_t, 1);
304 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
305 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
306 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
307 qemu_register_reset(ppc4xx_pob_reset, pob);
308 }
309
310 /*****************************************************************************/
311 /* OPB arbitrer */
312 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
313 struct ppc4xx_opba_t {
314 MemoryRegion io;
315 uint8_t cr;
316 uint8_t pr;
317 };
318
319 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
320 {
321 ppc4xx_opba_t *opba = opaque;
322 uint32_t ret;
323
324 switch (addr) {
325 case 0x00:
326 ret = opba->cr;
327 break;
328 case 0x01:
329 ret = opba->pr;
330 break;
331 default:
332 ret = 0x00;
333 break;
334 }
335
336 trace_opba_readb(addr, ret);
337 return ret;
338 }
339
340 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
341 unsigned size)
342 {
343 ppc4xx_opba_t *opba = opaque;
344
345 trace_opba_writeb(addr, value);
346
347 switch (addr) {
348 case 0x00:
349 opba->cr = value & 0xF8;
350 break;
351 case 0x01:
352 opba->pr = value & 0xFF;
353 break;
354 default:
355 break;
356 }
357 }
358 static const MemoryRegionOps opba_ops = {
359 .read = opba_readb,
360 .write = opba_writeb,
361 .impl.min_access_size = 1,
362 .impl.max_access_size = 1,
363 .valid.min_access_size = 1,
364 .valid.max_access_size = 4,
365 .endianness = DEVICE_BIG_ENDIAN,
366 };
367
368 static void ppc4xx_opba_reset (void *opaque)
369 {
370 ppc4xx_opba_t *opba;
371
372 opba = opaque;
373 opba->cr = 0x00; /* No dynamic priorities - park disabled */
374 opba->pr = 0x11;
375 }
376
377 static void ppc4xx_opba_init(hwaddr base)
378 {
379 ppc4xx_opba_t *opba;
380
381 trace_opba_init(base);
382
383 opba = g_new0(ppc4xx_opba_t, 1);
384 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
385 memory_region_add_subregion(get_system_memory(), base, &opba->io);
386 qemu_register_reset(ppc4xx_opba_reset, opba);
387 }
388
389 /*****************************************************************************/
390 /* Code decompression controller */
391 /* XXX: TODO */
392
393 /*****************************************************************************/
394 /* Peripheral controller */
395 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
396 struct ppc4xx_ebc_t {
397 uint32_t addr;
398 uint32_t bcr[8];
399 uint32_t bap[8];
400 uint32_t bear;
401 uint32_t besr0;
402 uint32_t besr1;
403 uint32_t cfg;
404 };
405
406 enum {
407 EBC0_CFGADDR = 0x012,
408 EBC0_CFGDATA = 0x013,
409 };
410
411 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
412 {
413 ppc4xx_ebc_t *ebc;
414 uint32_t ret;
415
416 ebc = opaque;
417 switch (dcrn) {
418 case EBC0_CFGADDR:
419 ret = ebc->addr;
420 break;
421 case EBC0_CFGDATA:
422 switch (ebc->addr) {
423 case 0x00: /* B0CR */
424 ret = ebc->bcr[0];
425 break;
426 case 0x01: /* B1CR */
427 ret = ebc->bcr[1];
428 break;
429 case 0x02: /* B2CR */
430 ret = ebc->bcr[2];
431 break;
432 case 0x03: /* B3CR */
433 ret = ebc->bcr[3];
434 break;
435 case 0x04: /* B4CR */
436 ret = ebc->bcr[4];
437 break;
438 case 0x05: /* B5CR */
439 ret = ebc->bcr[5];
440 break;
441 case 0x06: /* B6CR */
442 ret = ebc->bcr[6];
443 break;
444 case 0x07: /* B7CR */
445 ret = ebc->bcr[7];
446 break;
447 case 0x10: /* B0AP */
448 ret = ebc->bap[0];
449 break;
450 case 0x11: /* B1AP */
451 ret = ebc->bap[1];
452 break;
453 case 0x12: /* B2AP */
454 ret = ebc->bap[2];
455 break;
456 case 0x13: /* B3AP */
457 ret = ebc->bap[3];
458 break;
459 case 0x14: /* B4AP */
460 ret = ebc->bap[4];
461 break;
462 case 0x15: /* B5AP */
463 ret = ebc->bap[5];
464 break;
465 case 0x16: /* B6AP */
466 ret = ebc->bap[6];
467 break;
468 case 0x17: /* B7AP */
469 ret = ebc->bap[7];
470 break;
471 case 0x20: /* BEAR */
472 ret = ebc->bear;
473 break;
474 case 0x21: /* BESR0 */
475 ret = ebc->besr0;
476 break;
477 case 0x22: /* BESR1 */
478 ret = ebc->besr1;
479 break;
480 case 0x23: /* CFG */
481 ret = ebc->cfg;
482 break;
483 default:
484 ret = 0x00000000;
485 break;
486 }
487 break;
488 default:
489 ret = 0x00000000;
490 break;
491 }
492
493 return ret;
494 }
495
496 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
497 {
498 ppc4xx_ebc_t *ebc;
499
500 ebc = opaque;
501 switch (dcrn) {
502 case EBC0_CFGADDR:
503 ebc->addr = val;
504 break;
505 case EBC0_CFGDATA:
506 switch (ebc->addr) {
507 case 0x00: /* B0CR */
508 break;
509 case 0x01: /* B1CR */
510 break;
511 case 0x02: /* B2CR */
512 break;
513 case 0x03: /* B3CR */
514 break;
515 case 0x04: /* B4CR */
516 break;
517 case 0x05: /* B5CR */
518 break;
519 case 0x06: /* B6CR */
520 break;
521 case 0x07: /* B7CR */
522 break;
523 case 0x10: /* B0AP */
524 break;
525 case 0x11: /* B1AP */
526 break;
527 case 0x12: /* B2AP */
528 break;
529 case 0x13: /* B3AP */
530 break;
531 case 0x14: /* B4AP */
532 break;
533 case 0x15: /* B5AP */
534 break;
535 case 0x16: /* B6AP */
536 break;
537 case 0x17: /* B7AP */
538 break;
539 case 0x20: /* BEAR */
540 break;
541 case 0x21: /* BESR0 */
542 break;
543 case 0x22: /* BESR1 */
544 break;
545 case 0x23: /* CFG */
546 break;
547 default:
548 break;
549 }
550 break;
551 default:
552 break;
553 }
554 }
555
556 static void ebc_reset (void *opaque)
557 {
558 ppc4xx_ebc_t *ebc;
559 int i;
560
561 ebc = opaque;
562 ebc->addr = 0x00000000;
563 ebc->bap[0] = 0x7F8FFE80;
564 ebc->bcr[0] = 0xFFE28000;
565 for (i = 0; i < 8; i++) {
566 ebc->bap[i] = 0x00000000;
567 ebc->bcr[i] = 0x00000000;
568 }
569 ebc->besr0 = 0x00000000;
570 ebc->besr1 = 0x00000000;
571 ebc->cfg = 0x80400000;
572 }
573
574 void ppc405_ebc_init(CPUPPCState *env)
575 {
576 ppc4xx_ebc_t *ebc;
577
578 ebc = g_new0(ppc4xx_ebc_t, 1);
579 qemu_register_reset(&ebc_reset, ebc);
580 ppc_dcr_register(env, EBC0_CFGADDR,
581 ebc, &dcr_read_ebc, &dcr_write_ebc);
582 ppc_dcr_register(env, EBC0_CFGDATA,
583 ebc, &dcr_read_ebc, &dcr_write_ebc);
584 }
585
586 /*****************************************************************************/
587 /* DMA controller */
588 enum {
589 DMA0_CR0 = 0x100,
590 DMA0_CT0 = 0x101,
591 DMA0_DA0 = 0x102,
592 DMA0_SA0 = 0x103,
593 DMA0_SG0 = 0x104,
594 DMA0_CR1 = 0x108,
595 DMA0_CT1 = 0x109,
596 DMA0_DA1 = 0x10A,
597 DMA0_SA1 = 0x10B,
598 DMA0_SG1 = 0x10C,
599 DMA0_CR2 = 0x110,
600 DMA0_CT2 = 0x111,
601 DMA0_DA2 = 0x112,
602 DMA0_SA2 = 0x113,
603 DMA0_SG2 = 0x114,
604 DMA0_CR3 = 0x118,
605 DMA0_CT3 = 0x119,
606 DMA0_DA3 = 0x11A,
607 DMA0_SA3 = 0x11B,
608 DMA0_SG3 = 0x11C,
609 DMA0_SR = 0x120,
610 DMA0_SGC = 0x123,
611 DMA0_SLP = 0x125,
612 DMA0_POL = 0x126,
613 };
614
615 typedef struct ppc405_dma_t ppc405_dma_t;
616 struct ppc405_dma_t {
617 qemu_irq irqs[4];
618 uint32_t cr[4];
619 uint32_t ct[4];
620 uint32_t da[4];
621 uint32_t sa[4];
622 uint32_t sg[4];
623 uint32_t sr;
624 uint32_t sgc;
625 uint32_t slp;
626 uint32_t pol;
627 };
628
629 static uint32_t dcr_read_dma (void *opaque, int dcrn)
630 {
631 return 0;
632 }
633
634 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
635 {
636 }
637
638 static void ppc405_dma_reset (void *opaque)
639 {
640 ppc405_dma_t *dma;
641 int i;
642
643 dma = opaque;
644 for (i = 0; i < 4; i++) {
645 dma->cr[i] = 0x00000000;
646 dma->ct[i] = 0x00000000;
647 dma->da[i] = 0x00000000;
648 dma->sa[i] = 0x00000000;
649 dma->sg[i] = 0x00000000;
650 }
651 dma->sr = 0x00000000;
652 dma->sgc = 0x00000000;
653 dma->slp = 0x7C000000;
654 dma->pol = 0x00000000;
655 }
656
657 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
658 {
659 ppc405_dma_t *dma;
660
661 dma = g_new0(ppc405_dma_t, 1);
662 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
663 qemu_register_reset(&ppc405_dma_reset, dma);
664 ppc_dcr_register(env, DMA0_CR0,
665 dma, &dcr_read_dma, &dcr_write_dma);
666 ppc_dcr_register(env, DMA0_CT0,
667 dma, &dcr_read_dma, &dcr_write_dma);
668 ppc_dcr_register(env, DMA0_DA0,
669 dma, &dcr_read_dma, &dcr_write_dma);
670 ppc_dcr_register(env, DMA0_SA0,
671 dma, &dcr_read_dma, &dcr_write_dma);
672 ppc_dcr_register(env, DMA0_SG0,
673 dma, &dcr_read_dma, &dcr_write_dma);
674 ppc_dcr_register(env, DMA0_CR1,
675 dma, &dcr_read_dma, &dcr_write_dma);
676 ppc_dcr_register(env, DMA0_CT1,
677 dma, &dcr_read_dma, &dcr_write_dma);
678 ppc_dcr_register(env, DMA0_DA1,
679 dma, &dcr_read_dma, &dcr_write_dma);
680 ppc_dcr_register(env, DMA0_SA1,
681 dma, &dcr_read_dma, &dcr_write_dma);
682 ppc_dcr_register(env, DMA0_SG1,
683 dma, &dcr_read_dma, &dcr_write_dma);
684 ppc_dcr_register(env, DMA0_CR2,
685 dma, &dcr_read_dma, &dcr_write_dma);
686 ppc_dcr_register(env, DMA0_CT2,
687 dma, &dcr_read_dma, &dcr_write_dma);
688 ppc_dcr_register(env, DMA0_DA2,
689 dma, &dcr_read_dma, &dcr_write_dma);
690 ppc_dcr_register(env, DMA0_SA2,
691 dma, &dcr_read_dma, &dcr_write_dma);
692 ppc_dcr_register(env, DMA0_SG2,
693 dma, &dcr_read_dma, &dcr_write_dma);
694 ppc_dcr_register(env, DMA0_CR3,
695 dma, &dcr_read_dma, &dcr_write_dma);
696 ppc_dcr_register(env, DMA0_CT3,
697 dma, &dcr_read_dma, &dcr_write_dma);
698 ppc_dcr_register(env, DMA0_DA3,
699 dma, &dcr_read_dma, &dcr_write_dma);
700 ppc_dcr_register(env, DMA0_SA3,
701 dma, &dcr_read_dma, &dcr_write_dma);
702 ppc_dcr_register(env, DMA0_SG3,
703 dma, &dcr_read_dma, &dcr_write_dma);
704 ppc_dcr_register(env, DMA0_SR,
705 dma, &dcr_read_dma, &dcr_write_dma);
706 ppc_dcr_register(env, DMA0_SGC,
707 dma, &dcr_read_dma, &dcr_write_dma);
708 ppc_dcr_register(env, DMA0_SLP,
709 dma, &dcr_read_dma, &dcr_write_dma);
710 ppc_dcr_register(env, DMA0_POL,
711 dma, &dcr_read_dma, &dcr_write_dma);
712 }
713
714 /*****************************************************************************/
715 /* GPIO */
716 typedef struct ppc405_gpio_t ppc405_gpio_t;
717 struct ppc405_gpio_t {
718 MemoryRegion io;
719 uint32_t or;
720 uint32_t tcr;
721 uint32_t osrh;
722 uint32_t osrl;
723 uint32_t tsrh;
724 uint32_t tsrl;
725 uint32_t odr;
726 uint32_t ir;
727 uint32_t rr1;
728 uint32_t isr1h;
729 uint32_t isr1l;
730 };
731
732 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
733 {
734 trace_ppc405_gpio_read(addr, size);
735 return 0;
736 }
737
738 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
739 unsigned size)
740 {
741 trace_ppc405_gpio_write(addr, size, value);
742 }
743
744 static const MemoryRegionOps ppc405_gpio_ops = {
745 .read = ppc405_gpio_read,
746 .write = ppc405_gpio_write,
747 .endianness = DEVICE_NATIVE_ENDIAN,
748 };
749
750 static void ppc405_gpio_reset (void *opaque)
751 {
752 }
753
754 static void ppc405_gpio_init(hwaddr base)
755 {
756 ppc405_gpio_t *gpio;
757
758 trace_ppc405_gpio_init(base);
759
760 gpio = g_new0(ppc405_gpio_t, 1);
761 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
762 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
763 qemu_register_reset(&ppc405_gpio_reset, gpio);
764 }
765
766 /*****************************************************************************/
767 /* On Chip Memory */
768 enum {
769 OCM0_ISARC = 0x018,
770 OCM0_ISACNTL = 0x019,
771 OCM0_DSARC = 0x01A,
772 OCM0_DSACNTL = 0x01B,
773 };
774
775 typedef struct ppc405_ocm_t ppc405_ocm_t;
776 struct ppc405_ocm_t {
777 MemoryRegion ram;
778 MemoryRegion isarc_ram;
779 MemoryRegion dsarc_ram;
780 uint32_t isarc;
781 uint32_t isacntl;
782 uint32_t dsarc;
783 uint32_t dsacntl;
784 };
785
786 static void ocm_update_mappings (ppc405_ocm_t *ocm,
787 uint32_t isarc, uint32_t isacntl,
788 uint32_t dsarc, uint32_t dsacntl)
789 {
790 trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
791 ocm->isacntl, ocm->dsarc, ocm->dsacntl);
792
793 if (ocm->isarc != isarc ||
794 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
795 if (ocm->isacntl & 0x80000000) {
796 /* Unmap previously assigned memory region */
797 trace_ocm_unmap("ISA", ocm->isarc);
798 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
799 }
800 if (isacntl & 0x80000000) {
801 /* Map new instruction memory region */
802 trace_ocm_map("ISA", isarc);
803 memory_region_add_subregion(get_system_memory(), isarc,
804 &ocm->isarc_ram);
805 }
806 }
807 if (ocm->dsarc != dsarc ||
808 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
809 if (ocm->dsacntl & 0x80000000) {
810 /* Beware not to unmap the region we just mapped */
811 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
812 /* Unmap previously assigned memory region */
813 trace_ocm_unmap("DSA", ocm->dsarc);
814 memory_region_del_subregion(get_system_memory(),
815 &ocm->dsarc_ram);
816 }
817 }
818 if (dsacntl & 0x80000000) {
819 /* Beware not to remap the region we just mapped */
820 if (!(isacntl & 0x80000000) || dsarc != isarc) {
821 /* Map new data memory region */
822 trace_ocm_map("DSA", dsarc);
823 memory_region_add_subregion(get_system_memory(), dsarc,
824 &ocm->dsarc_ram);
825 }
826 }
827 }
828 }
829
830 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
831 {
832 ppc405_ocm_t *ocm;
833 uint32_t ret;
834
835 ocm = opaque;
836 switch (dcrn) {
837 case OCM0_ISARC:
838 ret = ocm->isarc;
839 break;
840 case OCM0_ISACNTL:
841 ret = ocm->isacntl;
842 break;
843 case OCM0_DSARC:
844 ret = ocm->dsarc;
845 break;
846 case OCM0_DSACNTL:
847 ret = ocm->dsacntl;
848 break;
849 default:
850 ret = 0;
851 break;
852 }
853
854 return ret;
855 }
856
857 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
858 {
859 ppc405_ocm_t *ocm;
860 uint32_t isarc, dsarc, isacntl, dsacntl;
861
862 ocm = opaque;
863 isarc = ocm->isarc;
864 dsarc = ocm->dsarc;
865 isacntl = ocm->isacntl;
866 dsacntl = ocm->dsacntl;
867 switch (dcrn) {
868 case OCM0_ISARC:
869 isarc = val & 0xFC000000;
870 break;
871 case OCM0_ISACNTL:
872 isacntl = val & 0xC0000000;
873 break;
874 case OCM0_DSARC:
875 isarc = val & 0xFC000000;
876 break;
877 case OCM0_DSACNTL:
878 isacntl = val & 0xC0000000;
879 break;
880 }
881 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
882 ocm->isarc = isarc;
883 ocm->dsarc = dsarc;
884 ocm->isacntl = isacntl;
885 ocm->dsacntl = dsacntl;
886 }
887
888 static void ocm_reset (void *opaque)
889 {
890 ppc405_ocm_t *ocm;
891 uint32_t isarc, dsarc, isacntl, dsacntl;
892
893 ocm = opaque;
894 isarc = 0x00000000;
895 isacntl = 0x00000000;
896 dsarc = 0x00000000;
897 dsacntl = 0x00000000;
898 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
899 ocm->isarc = isarc;
900 ocm->dsarc = dsarc;
901 ocm->isacntl = isacntl;
902 ocm->dsacntl = dsacntl;
903 }
904
905 static void ppc405_ocm_init(CPUPPCState *env)
906 {
907 ppc405_ocm_t *ocm;
908
909 ocm = g_new0(ppc405_ocm_t, 1);
910 /* XXX: Size is 4096 or 0x04000000 */
911 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
912 &error_fatal);
913 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
914 &ocm->isarc_ram, 0, 4 * KiB);
915 qemu_register_reset(&ocm_reset, ocm);
916 ppc_dcr_register(env, OCM0_ISARC,
917 ocm, &dcr_read_ocm, &dcr_write_ocm);
918 ppc_dcr_register(env, OCM0_ISACNTL,
919 ocm, &dcr_read_ocm, &dcr_write_ocm);
920 ppc_dcr_register(env, OCM0_DSARC,
921 ocm, &dcr_read_ocm, &dcr_write_ocm);
922 ppc_dcr_register(env, OCM0_DSACNTL,
923 ocm, &dcr_read_ocm, &dcr_write_ocm);
924 }
925
926 /*****************************************************************************/
927 /* General purpose timers */
928 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
929 struct ppc4xx_gpt_t {
930 MemoryRegion iomem;
931 int64_t tb_offset;
932 uint32_t tb_freq;
933 QEMUTimer *timer;
934 qemu_irq irqs[5];
935 uint32_t oe;
936 uint32_t ol;
937 uint32_t im;
938 uint32_t is;
939 uint32_t ie;
940 uint32_t comp[5];
941 uint32_t mask[5];
942 };
943
944 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
945 {
946 /* XXX: TODO */
947 return 0;
948 }
949
950 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
951 {
952 /* XXX: TODO */
953 }
954
955 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
956 {
957 uint32_t mask;
958 int i;
959
960 mask = 0x80000000;
961 for (i = 0; i < 5; i++) {
962 if (gpt->oe & mask) {
963 /* Output is enabled */
964 if (ppc4xx_gpt_compare(gpt, i)) {
965 /* Comparison is OK */
966 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
967 } else {
968 /* Comparison is KO */
969 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
970 }
971 }
972 mask = mask >> 1;
973 }
974 }
975
976 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
977 {
978 uint32_t mask;
979 int i;
980
981 mask = 0x00008000;
982 for (i = 0; i < 5; i++) {
983 if (gpt->is & gpt->im & mask)
984 qemu_irq_raise(gpt->irqs[i]);
985 else
986 qemu_irq_lower(gpt->irqs[i]);
987 mask = mask >> 1;
988 }
989 }
990
991 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
992 {
993 /* XXX: TODO */
994 }
995
996 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
997 {
998 ppc4xx_gpt_t *gpt = opaque;
999 uint32_t ret;
1000 int idx;
1001
1002 trace_ppc4xx_gpt_read(addr, size);
1003
1004 switch (addr) {
1005 case 0x00:
1006 /* Time base counter */
1007 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1008 gpt->tb_freq, NANOSECONDS_PER_SECOND);
1009 break;
1010 case 0x10:
1011 /* Output enable */
1012 ret = gpt->oe;
1013 break;
1014 case 0x14:
1015 /* Output level */
1016 ret = gpt->ol;
1017 break;
1018 case 0x18:
1019 /* Interrupt mask */
1020 ret = gpt->im;
1021 break;
1022 case 0x1C:
1023 case 0x20:
1024 /* Interrupt status */
1025 ret = gpt->is;
1026 break;
1027 case 0x24:
1028 /* Interrupt enable */
1029 ret = gpt->ie;
1030 break;
1031 case 0x80 ... 0x90:
1032 /* Compare timer */
1033 idx = (addr - 0x80) >> 2;
1034 ret = gpt->comp[idx];
1035 break;
1036 case 0xC0 ... 0xD0:
1037 /* Compare mask */
1038 idx = (addr - 0xC0) >> 2;
1039 ret = gpt->mask[idx];
1040 break;
1041 default:
1042 ret = -1;
1043 break;
1044 }
1045
1046 return ret;
1047 }
1048
1049 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
1050 unsigned size)
1051 {
1052 ppc4xx_gpt_t *gpt = opaque;
1053 int idx;
1054
1055 trace_ppc4xx_gpt_write(addr, size, value);
1056
1057 switch (addr) {
1058 case 0x00:
1059 /* Time base counter */
1060 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq)
1061 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1062 ppc4xx_gpt_compute_timer(gpt);
1063 break;
1064 case 0x10:
1065 /* Output enable */
1066 gpt->oe = value & 0xF8000000;
1067 ppc4xx_gpt_set_outputs(gpt);
1068 break;
1069 case 0x14:
1070 /* Output level */
1071 gpt->ol = value & 0xF8000000;
1072 ppc4xx_gpt_set_outputs(gpt);
1073 break;
1074 case 0x18:
1075 /* Interrupt mask */
1076 gpt->im = value & 0x0000F800;
1077 break;
1078 case 0x1C:
1079 /* Interrupt status set */
1080 gpt->is |= value & 0x0000F800;
1081 ppc4xx_gpt_set_irqs(gpt);
1082 break;
1083 case 0x20:
1084 /* Interrupt status clear */
1085 gpt->is &= ~(value & 0x0000F800);
1086 ppc4xx_gpt_set_irqs(gpt);
1087 break;
1088 case 0x24:
1089 /* Interrupt enable */
1090 gpt->ie = value & 0x0000F800;
1091 ppc4xx_gpt_set_irqs(gpt);
1092 break;
1093 case 0x80 ... 0x90:
1094 /* Compare timer */
1095 idx = (addr - 0x80) >> 2;
1096 gpt->comp[idx] = value & 0xF8000000;
1097 ppc4xx_gpt_compute_timer(gpt);
1098 break;
1099 case 0xC0 ... 0xD0:
1100 /* Compare mask */
1101 idx = (addr - 0xC0) >> 2;
1102 gpt->mask[idx] = value & 0xF8000000;
1103 ppc4xx_gpt_compute_timer(gpt);
1104 break;
1105 }
1106 }
1107
1108 static const MemoryRegionOps gpt_ops = {
1109 .read = ppc4xx_gpt_read,
1110 .write = ppc4xx_gpt_write,
1111 .valid.min_access_size = 4,
1112 .valid.max_access_size = 4,
1113 .endianness = DEVICE_NATIVE_ENDIAN,
1114 };
1115
1116 static void ppc4xx_gpt_cb (void *opaque)
1117 {
1118 ppc4xx_gpt_t *gpt;
1119
1120 gpt = opaque;
1121 ppc4xx_gpt_set_irqs(gpt);
1122 ppc4xx_gpt_set_outputs(gpt);
1123 ppc4xx_gpt_compute_timer(gpt);
1124 }
1125
1126 static void ppc4xx_gpt_reset (void *opaque)
1127 {
1128 ppc4xx_gpt_t *gpt;
1129 int i;
1130
1131 gpt = opaque;
1132 timer_del(gpt->timer);
1133 gpt->oe = 0x00000000;
1134 gpt->ol = 0x00000000;
1135 gpt->im = 0x00000000;
1136 gpt->is = 0x00000000;
1137 gpt->ie = 0x00000000;
1138 for (i = 0; i < 5; i++) {
1139 gpt->comp[i] = 0x00000000;
1140 gpt->mask[i] = 0x00000000;
1141 }
1142 }
1143
1144 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1145 {
1146 ppc4xx_gpt_t *gpt;
1147 int i;
1148
1149 trace_ppc4xx_gpt_init(base);
1150
1151 gpt = g_new0(ppc4xx_gpt_t, 1);
1152 for (i = 0; i < 5; i++) {
1153 gpt->irqs[i] = irqs[i];
1154 }
1155 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1156 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1157 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1158 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1159 }
1160
1161 /*****************************************************************************/
1162 /* PowerPC 405EP */
1163 /* CPU control */
1164 enum {
1165 PPC405EP_CPC0_PLLMR0 = 0x0F0,
1166 PPC405EP_CPC0_BOOT = 0x0F1,
1167 PPC405EP_CPC0_EPCTL = 0x0F3,
1168 PPC405EP_CPC0_PLLMR1 = 0x0F4,
1169 PPC405EP_CPC0_UCR = 0x0F5,
1170 PPC405EP_CPC0_SRR = 0x0F6,
1171 PPC405EP_CPC0_JTAGID = 0x0F7,
1172 PPC405EP_CPC0_PCI = 0x0F9,
1173 #if 0
1174 PPC405EP_CPC0_ER = xxx,
1175 PPC405EP_CPC0_FR = xxx,
1176 PPC405EP_CPC0_SR = xxx,
1177 #endif
1178 };
1179
1180 enum {
1181 PPC405EP_CPU_CLK = 0,
1182 PPC405EP_PLB_CLK = 1,
1183 PPC405EP_OPB_CLK = 2,
1184 PPC405EP_EBC_CLK = 3,
1185 PPC405EP_MAL_CLK = 4,
1186 PPC405EP_PCI_CLK = 5,
1187 PPC405EP_UART0_CLK = 6,
1188 PPC405EP_UART1_CLK = 7,
1189 PPC405EP_CLK_NB = 8,
1190 };
1191
1192 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
1193 struct ppc405ep_cpc_t {
1194 uint32_t sysclk;
1195 clk_setup_t clk_setup[PPC405EP_CLK_NB];
1196 uint32_t boot;
1197 uint32_t epctl;
1198 uint32_t pllmr[2];
1199 uint32_t ucr;
1200 uint32_t srr;
1201 uint32_t jtagid;
1202 uint32_t pci;
1203 /* Clock and power management */
1204 uint32_t er;
1205 uint32_t fr;
1206 uint32_t sr;
1207 };
1208
1209 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
1210 {
1211 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
1212 uint32_t UART0_clk, UART1_clk;
1213 uint64_t VCO_out, PLL_out;
1214 int M, D;
1215
1216 VCO_out = 0;
1217 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
1218 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
1219 trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M);
1220 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
1221 trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D);
1222 VCO_out = (uint64_t)cpc->sysclk * M * D;
1223 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
1224 /* Error - unlock the PLL */
1225 qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n",
1226 VCO_out);
1227 #if 0
1228 cpc->pllmr[1] &= ~0x80000000;
1229 goto pll_bypass;
1230 #endif
1231 }
1232 PLL_out = VCO_out / D;
1233 /* Pretend the PLL is locked */
1234 cpc->boot |= 0x00000001;
1235 } else {
1236 #if 0
1237 pll_bypass:
1238 #endif
1239 PLL_out = cpc->sysclk;
1240 if (cpc->pllmr[1] & 0x40000000) {
1241 /* Pretend the PLL is not locked */
1242 cpc->boot &= ~0x00000001;
1243 }
1244 }
1245 /* Now, compute all other clocks */
1246 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
1247 trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D);
1248 CPU_clk = PLL_out / D;
1249 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
1250 trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D);
1251 PLB_clk = CPU_clk / D;
1252 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
1253 trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D);
1254 OPB_clk = PLB_clk / D;
1255 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
1256 trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D);
1257 EBC_clk = PLB_clk / D;
1258 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
1259 trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D);
1260 MAL_clk = PLB_clk / D;
1261 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
1262 trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D);
1263 PCI_clk = PLB_clk / D;
1264 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
1265 trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D);
1266 UART0_clk = PLL_out / D;
1267 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
1268 trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D);
1269 UART1_clk = PLL_out / D;
1270
1271 if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) {
1272 g_autofree char *trace = g_strdup_printf(
1273 "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
1274 " PLL out %" PRIu64 " Hz\n"
1275 "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
1276 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
1277 " UART1 %" PRIu32 "\n",
1278 cpc->sysclk, VCO_out, PLL_out,
1279 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
1280 UART0_clk, UART1_clk);
1281 trace_ppc405ep_clocks_setup(trace);
1282 }
1283
1284 /* Setup CPU clocks */
1285 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
1286 /* Setup PLB clock */
1287 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
1288 /* Setup OPB clock */
1289 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
1290 /* Setup external clock */
1291 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
1292 /* Setup MAL clock */
1293 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
1294 /* Setup PCI clock */
1295 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
1296 /* Setup UART0 clock */
1297 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
1298 /* Setup UART1 clock */
1299 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
1300 }
1301
1302 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
1303 {
1304 ppc405ep_cpc_t *cpc;
1305 uint32_t ret;
1306
1307 cpc = opaque;
1308 switch (dcrn) {
1309 case PPC405EP_CPC0_BOOT:
1310 ret = cpc->boot;
1311 break;
1312 case PPC405EP_CPC0_EPCTL:
1313 ret = cpc->epctl;
1314 break;
1315 case PPC405EP_CPC0_PLLMR0:
1316 ret = cpc->pllmr[0];
1317 break;
1318 case PPC405EP_CPC0_PLLMR1:
1319 ret = cpc->pllmr[1];
1320 break;
1321 case PPC405EP_CPC0_UCR:
1322 ret = cpc->ucr;
1323 break;
1324 case PPC405EP_CPC0_SRR:
1325 ret = cpc->srr;
1326 break;
1327 case PPC405EP_CPC0_JTAGID:
1328 ret = cpc->jtagid;
1329 break;
1330 case PPC405EP_CPC0_PCI:
1331 ret = cpc->pci;
1332 break;
1333 default:
1334 /* Avoid gcc warning */
1335 ret = 0;
1336 break;
1337 }
1338
1339 return ret;
1340 }
1341
1342 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
1343 {
1344 ppc405ep_cpc_t *cpc;
1345
1346 cpc = opaque;
1347 switch (dcrn) {
1348 case PPC405EP_CPC0_BOOT:
1349 /* Read-only register */
1350 break;
1351 case PPC405EP_CPC0_EPCTL:
1352 /* Don't care for now */
1353 cpc->epctl = val & 0xC00000F3;
1354 break;
1355 case PPC405EP_CPC0_PLLMR0:
1356 cpc->pllmr[0] = val & 0x00633333;
1357 ppc405ep_compute_clocks(cpc);
1358 break;
1359 case PPC405EP_CPC0_PLLMR1:
1360 cpc->pllmr[1] = val & 0xC0F73FFF;
1361 ppc405ep_compute_clocks(cpc);
1362 break;
1363 case PPC405EP_CPC0_UCR:
1364 /* UART control - don't care for now */
1365 cpc->ucr = val & 0x003F7F7F;
1366 break;
1367 case PPC405EP_CPC0_SRR:
1368 cpc->srr = val;
1369 break;
1370 case PPC405EP_CPC0_JTAGID:
1371 /* Read-only */
1372 break;
1373 case PPC405EP_CPC0_PCI:
1374 cpc->pci = val;
1375 break;
1376 }
1377 }
1378
1379 static void ppc405ep_cpc_reset (void *opaque)
1380 {
1381 ppc405ep_cpc_t *cpc = opaque;
1382
1383 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
1384 cpc->epctl = 0x00000000;
1385 cpc->pllmr[0] = 0x00021002;
1386 cpc->pllmr[1] = 0x80a552be;
1387 cpc->ucr = 0x00004646;
1388 cpc->srr = 0x00040000;
1389 cpc->pci = 0x00000000;
1390 cpc->er = 0x00000000;
1391 cpc->fr = 0x00000000;
1392 cpc->sr = 0x00000000;
1393 ppc405ep_compute_clocks(cpc);
1394 }
1395
1396 /* XXX: sysclk should be between 25 and 100 MHz */
1397 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
1398 uint32_t sysclk)
1399 {
1400 ppc405ep_cpc_t *cpc;
1401
1402 cpc = g_new0(ppc405ep_cpc_t, 1);
1403 memcpy(cpc->clk_setup, clk_setup,
1404 PPC405EP_CLK_NB * sizeof(clk_setup_t));
1405 cpc->jtagid = 0x20267049;
1406 cpc->sysclk = sysclk;
1407 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
1408 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
1409 &dcr_read_epcpc, &dcr_write_epcpc);
1410 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
1411 &dcr_read_epcpc, &dcr_write_epcpc);
1412 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
1413 &dcr_read_epcpc, &dcr_write_epcpc);
1414 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
1415 &dcr_read_epcpc, &dcr_write_epcpc);
1416 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
1417 &dcr_read_epcpc, &dcr_write_epcpc);
1418 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
1419 &dcr_read_epcpc, &dcr_write_epcpc);
1420 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
1421 &dcr_read_epcpc, &dcr_write_epcpc);
1422 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
1423 &dcr_read_epcpc, &dcr_write_epcpc);
1424 #if 0
1425 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
1426 &dcr_read_epcpc, &dcr_write_epcpc);
1427 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
1428 &dcr_read_epcpc, &dcr_write_epcpc);
1429 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
1430 &dcr_read_epcpc, &dcr_write_epcpc);
1431 #endif
1432 }
1433
1434 PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
1435 MemoryRegion ram_memories[2],
1436 hwaddr ram_bases[2],
1437 hwaddr ram_sizes[2],
1438 uint32_t sysclk, DeviceState **uicdevp,
1439 int do_init)
1440 {
1441 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
1442 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
1443 PowerPCCPU *cpu;
1444 CPUPPCState *env;
1445 DeviceState *uicdev;
1446 SysBusDevice *uicsbd;
1447
1448 memset(clk_setup, 0, sizeof(clk_setup));
1449 /* init CPUs */
1450 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
1451 &clk_setup[PPC405EP_CPU_CLK],
1452 &tlb_clk_setup, sysclk);
1453 env = &cpu->env;
1454 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
1455 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
1456 /* Internal devices init */
1457 /* Memory mapped devices registers */
1458 /* PLB arbitrer */
1459 ppc4xx_plb_init(env);
1460 /* PLB to OPB bridge */
1461 ppc4xx_pob_init(env);
1462 /* OBP arbitrer */
1463 ppc4xx_opba_init(0xef600600);
1464 /* Universal interrupt controller */
1465 uicdev = qdev_new(TYPE_PPC_UIC);
1466 uicsbd = SYS_BUS_DEVICE(uicdev);
1467
1468 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
1469 &error_fatal);
1470 sysbus_realize_and_unref(uicsbd, &error_fatal);
1471
1472 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
1473 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
1474 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
1475 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
1476
1477 *uicdevp = uicdev;
1478
1479 /* SDRAM controller */
1480 /* XXX 405EP has no ECC interrupt */
1481 ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
1482 ram_bases, ram_sizes, do_init);
1483 /* External bus controller */
1484 ppc405_ebc_init(env);
1485 /* DMA controller */
1486 dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
1487 dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
1488 dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
1489 dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
1490 ppc405_dma_init(env, dma_irqs);
1491 /* IIC controller */
1492 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
1493 qdev_get_gpio_in(uicdev, 2));
1494 /* GPIO */
1495 ppc405_gpio_init(0xef600700);
1496 /* Serial ports */
1497 if (serial_hd(0) != NULL) {
1498 serial_mm_init(address_space_mem, 0xef600300, 0,
1499 qdev_get_gpio_in(uicdev, 0),
1500 PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
1501 DEVICE_BIG_ENDIAN);
1502 }
1503 if (serial_hd(1) != NULL) {
1504 serial_mm_init(address_space_mem, 0xef600400, 0,
1505 qdev_get_gpio_in(uicdev, 1),
1506 PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
1507 DEVICE_BIG_ENDIAN);
1508 }
1509 /* OCM */
1510 ppc405_ocm_init(env);
1511 /* GPT */
1512 gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
1513 gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
1514 gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
1515 gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
1516 gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
1517 ppc4xx_gpt_init(0xef600000, gpt_irqs);
1518 /* PCI */
1519 /* Uses UIC IRQs 3, 16, 18 */
1520 /* MAL */
1521 mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
1522 mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
1523 mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
1524 mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
1525 ppc4xx_mal_init(env, 4, 2, mal_irqs);
1526 /* Ethernet */
1527 /* Uses UIC IRQs 9, 15, 17 */
1528 /* CPU control */
1529 ppc405ep_cpc_init(env, clk_setup, sysclk);
1530
1531 return cpu;
1532 }
AR7 emulation for QEMU