hw/ppc/pnv_lpc.c

   1 /*
   2  * QEMU PowerPC PowerNV LPC controller
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "target/ppc/cpu.h"
  22 #include "qapi/error.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "hw/irq.h"
  26 #include "hw/isa/isa.h"
  27 #include "hw/qdev-properties.h"
  28 #include "hw/ppc/pnv.h"
  29 #include "hw/ppc/pnv_lpc.h"
  30 #include "hw/ppc/pnv_xscom.h"
  31 #include "hw/ppc/fdt.h"
  32
  33 #include <libfdt.h>
  34
  35 enum {
  36     ECCB_CTL    = 0,
  37     ECCB_RESET  = 1,
  38     ECCB_STAT   = 2,
  39     ECCB_DATA   = 3,
  40 };
  41
  42 /* OPB Master LS registers */
  43 #define OPB_MASTER_LS_ROUTE0    0x8
  44 #define OPB_MASTER_LS_ROUTE1    0xC
  45 #define OPB_MASTER_LS_IRQ_STAT  0x50
  46 #define   OPB_MASTER_IRQ_LPC            0x00000800
  47 #define OPB_MASTER_LS_IRQ_MASK  0x54
  48 #define OPB_MASTER_LS_IRQ_POL   0x58
  49 #define OPB_MASTER_LS_IRQ_INPUT 0x5c
  50
  51 /* LPC HC registers */
  52 #define LPC_HC_FW_SEG_IDSEL     0x24
  53 #define LPC_HC_FW_RD_ACC_SIZE   0x28
  54 #define   LPC_HC_FW_RD_1B               0x00000000
  55 #define   LPC_HC_FW_RD_2B               0x01000000
  56 #define   LPC_HC_FW_RD_4B               0x02000000
  57 #define   LPC_HC_FW_RD_16B              0x04000000
  58 #define   LPC_HC_FW_RD_128B             0x07000000
  59 #define LPC_HC_IRQSER_CTRL      0x30
  60 #define   LPC_HC_IRQSER_EN              0x80000000
  61 #define   LPC_HC_IRQSER_QMODE           0x40000000
  62 #define   LPC_HC_IRQSER_START_MASK      0x03000000
  63 #define   LPC_HC_IRQSER_START_4CLK      0x00000000
  64 #define   LPC_HC_IRQSER_START_6CLK      0x01000000
  65 #define   LPC_HC_IRQSER_START_8CLK      0x02000000
  66 #define LPC_HC_IRQMASK          0x34    /* same bit defs as LPC_HC_IRQSTAT */
  67 #define LPC_HC_IRQSTAT          0x38
  68 #define   LPC_HC_IRQ_SERIRQ0            0x80000000 /* all bits down to ... */
  69 #define   LPC_HC_IRQ_SERIRQ16           0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
  70 #define   LPC_HC_IRQ_SERIRQ_ALL         0xffff8000
  71 #define   LPC_HC_IRQ_LRESET             0x00000400
  72 #define   LPC_HC_IRQ_SYNC_ABNORM_ERR    0x00000080
  73 #define   LPC_HC_IRQ_SYNC_NORESP_ERR    0x00000040
  74 #define   LPC_HC_IRQ_SYNC_NORM_ERR      0x00000020
  75 #define   LPC_HC_IRQ_SYNC_TIMEOUT_ERR   0x00000010
  76 #define   LPC_HC_IRQ_SYNC_TARG_TAR_ERR  0x00000008
  77 #define   LPC_HC_IRQ_SYNC_BM_TAR_ERR    0x00000004
  78 #define   LPC_HC_IRQ_SYNC_BM0_REQ       0x00000002
  79 #define   LPC_HC_IRQ_SYNC_BM1_REQ       0x00000001
  80 #define LPC_HC_ERROR_ADDRESS    0x40
  81
  82 #define LPC_OPB_SIZE            0x100000000ull
  83
  84 #define ISA_IO_SIZE             0x00010000
  85 #define ISA_MEM_SIZE            0x10000000
  86 #define ISA_FW_SIZE             0x10000000
  87 #define LPC_IO_OPB_ADDR         0xd0010000
  88 #define LPC_IO_OPB_SIZE         0x00010000
  89 #define LPC_MEM_OPB_ADDR        0xe0000000
  90 #define LPC_MEM_OPB_SIZE        0x10000000
  91 #define LPC_FW_OPB_ADDR         0xf0000000
  92 #define LPC_FW_OPB_SIZE         0x10000000
  93
  94 #define LPC_OPB_REGS_OPB_ADDR   0xc0010000
  95 #define LPC_OPB_REGS_OPB_SIZE   0x00000060
  96 #define LPC_OPB_REGS_OPBA_ADDR  0xc0011000
  97 #define LPC_OPB_REGS_OPBA_SIZE  0x00000008
  98 #define LPC_HC_REGS_OPB_ADDR    0xc0012000
  99 #define LPC_HC_REGS_OPB_SIZE    0x00000100
 100
 101 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 102 {
 103     const char compat[] = "ibm,power8-lpc\0ibm,lpc";
 104     char *name;
 105     int offset;
 106     uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
 107     uint32_t reg[] = {
 108         cpu_to_be32(lpc_pcba),
 109         cpu_to_be32(PNV_XSCOM_LPC_SIZE)
 110     };
 111
 112     name = g_strdup_printf("isa@%x", lpc_pcba);
 113     offset = fdt_add_subnode(fdt, xscom_offset, name);
 114     _FDT(offset);
 115     g_free(name);
 116
 117     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 118     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 119     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 120     _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
 121     return 0;
 122 }
 123
 124 /* POWER9 only */
 125 int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr,
 126                uint64_t lpcm_size)
 127 {
 128     const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
 129     const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
 130     char *name;
 131     int offset, lpcm_offset;
 132     uint32_t opb_ranges[8] = { 0,
 133                                cpu_to_be32(lpcm_addr >> 32),
 134                                cpu_to_be32((uint32_t)lpcm_addr),
 135                                cpu_to_be32(lpcm_size / 2),
 136                                cpu_to_be32(lpcm_size / 2),
 137                                cpu_to_be32(lpcm_addr >> 32),
 138                                cpu_to_be32(lpcm_size / 2),
 139                                cpu_to_be32(lpcm_size / 2),
 140     };
 141     uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
 142                             cpu_to_be32((uint32_t)lpcm_addr),
 143                             cpu_to_be32(lpcm_size >> 32),
 144                             cpu_to_be32((uint32_t)lpcm_size),
 145     };
 146     uint32_t lpc_ranges[12] = { 0, 0,
 147                                 cpu_to_be32(LPC_MEM_OPB_ADDR),
 148                                 cpu_to_be32(LPC_MEM_OPB_SIZE),
 149                                 cpu_to_be32(1), 0,
 150                                 cpu_to_be32(LPC_IO_OPB_ADDR),
 151                                 cpu_to_be32(LPC_IO_OPB_SIZE),
 152                                 cpu_to_be32(3), 0,
 153                                 cpu_to_be32(LPC_FW_OPB_ADDR),
 154                                 cpu_to_be32(LPC_FW_OPB_SIZE),
 155     };
 156     uint32_t reg[2];
 157
 158     /*
 159      * OPB bus
 160      */
 161     name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr);
 162     lpcm_offset = fdt_add_subnode(fdt, root_offset, name);
 163     _FDT(lpcm_offset);
 164     g_free(name);
 165
 166     _FDT((fdt_setprop(fdt, lpcm_offset, "reg", opb_reg, sizeof(opb_reg))));
 167     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1)));
 168     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1)));
 169     _FDT((fdt_setprop(fdt, lpcm_offset, "compatible", compat, sizeof(compat))));
 170     _FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id)));
 171     _FDT((fdt_setprop(fdt, lpcm_offset, "ranges", opb_ranges,
 172                       sizeof(opb_ranges))));
 173
 174     /*
 175      * OPB Master registers
 176      */
 177     name = g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR);
 178     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 179     _FDT(offset);
 180     g_free(name);
 181
 182     reg[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR);
 183     reg[1] = cpu_to_be32(LPC_OPB_REGS_OPB_SIZE);
 184     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 185     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 186                              "ibm,power9-lpcm-opb-master")));
 187
 188     /*
 189      * OPB arbitrer registers
 190      */
 191     name = g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR);
 192     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 193     _FDT(offset);
 194     g_free(name);
 195
 196     reg[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR);
 197     reg[1] = cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE);
 198     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 199     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 200                              "ibm,power9-lpcm-opb-arbiter")));
 201
 202     /*
 203      * LPC Host Controller registers
 204      */
 205     name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR);
 206     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 207     _FDT(offset);
 208     g_free(name);
 209
 210     reg[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR);
 211     reg[1] = cpu_to_be32(LPC_HC_REGS_OPB_SIZE);
 212     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 213     _FDT((fdt_setprop_string(fdt, offset, "compatible",
 214                              "ibm,power9-lpc-controller")));
 215
 216     name = g_strdup_printf("lpc@0");
 217     offset = fdt_add_subnode(fdt, lpcm_offset, name);
 218     _FDT(offset);
 219     g_free(name);
 220     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 221     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 222     _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat,
 223                       sizeof(lpc_compat))));
 224     _FDT((fdt_setprop(fdt, offset, "ranges", lpc_ranges,
 225                       sizeof(lpc_ranges))));
 226
 227     return 0;
 228 }
 229
 230 /*
 231  * These read/write handlers of the OPB address space should be common
 232  * with the P9 LPC Controller which uses direct MMIOs.
 233  *
 234  * TODO: rework to use address_space_stq() and address_space_ldq()
 235  * instead.
 236  */
 237 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 238                      int sz)
 239 {
 240     /* XXX Handle access size limits and FW read caching here */
 241     return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 242                                data, sz);
 243 }
 244
 245 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 246                       int sz)
 247 {
 248     /* XXX Handle access size limits here */
 249     return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 250                                 data, sz);
 251 }
 252
 253 #define ECCB_CTL_READ           PPC_BIT(15)
 254 #define ECCB_CTL_SZ_LSH         (63 - 7)
 255 #define ECCB_CTL_SZ_MASK        PPC_BITMASK(4, 7)
 256 #define ECCB_CTL_ADDR_MASK      PPC_BITMASK(32, 63)
 257
 258 #define ECCB_STAT_OP_DONE       PPC_BIT(52)
 259 #define ECCB_STAT_OP_ERR        PPC_BIT(52)
 260 #define ECCB_STAT_RD_DATA_LSH   (63 - 37)
 261 #define ECCB_STAT_RD_DATA_MASK  (0xffffffff << ECCB_STAT_RD_DATA_LSH)
 262
 263 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
 264 {
 265     /* XXX Check for magic bits at the top, addr size etc... */
 266     unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
 267     uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
 268     uint8_t data[8];
 269     bool success;
 270
 271     if (sz > sizeof(data)) {
 272         qemu_log_mask(LOG_GUEST_ERROR,
 273             "ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz);
 274         return;
 275     }
 276
 277     if (cmd & ECCB_CTL_READ) {
 278         success = opb_read(lpc, opb_addr, data, sz);
 279         if (success) {
 280             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 281                     (((uint64_t)data[0]) << 24 |
 282                      ((uint64_t)data[1]) << 16 |
 283                      ((uint64_t)data[2]) <<  8 |
 284                      ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH;
 285         } else {
 286             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 287                     (0xffffffffull << ECCB_STAT_RD_DATA_LSH);
 288         }
 289     } else {
 290         data[0] = lpc->eccb_data_reg >> 24;
 291         data[1] = lpc->eccb_data_reg >> 16;
 292         data[2] = lpc->eccb_data_reg >>  8;
 293         data[3] = lpc->eccb_data_reg;
 294
 295         success = opb_write(lpc, opb_addr, data, sz);
 296         lpc->eccb_stat_reg = ECCB_STAT_OP_DONE;
 297     }
 298     /* XXX Which error bit (if any) to signal OPB error ? */
 299 }
 300
 301 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size)
 302 {
 303     PnvLpcController *lpc = PNV_LPC(opaque);
 304     uint32_t offset = addr >> 3;
 305     uint64_t val = 0;
 306
 307     switch (offset & 3) {
 308     case ECCB_CTL:
 309     case ECCB_RESET:
 310         val = 0;
 311         break;
 312     case ECCB_STAT:
 313         val = lpc->eccb_stat_reg;
 314         lpc->eccb_stat_reg = 0;
 315         break;
 316     case ECCB_DATA:
 317         val = ((uint64_t)lpc->eccb_data_reg) << 32;
 318         break;
 319     }
 320     return val;
 321 }
 322
 323 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr,
 324                                 uint64_t val, unsigned size)
 325 {
 326     PnvLpcController *lpc = PNV_LPC(opaque);
 327     uint32_t offset = addr >> 3;
 328
 329     switch (offset & 3) {
 330     case ECCB_CTL:
 331         pnv_lpc_do_eccb(lpc, val);
 332         break;
 333     case ECCB_RESET:
 334         /*  XXXX  */
 335         break;
 336     case ECCB_STAT:
 337         break;
 338     case ECCB_DATA:
 339         lpc->eccb_data_reg = val >> 32;
 340         break;
 341     }
 342 }
 343
 344 static const MemoryRegionOps pnv_lpc_xscom_ops = {
 345     .read = pnv_lpc_xscom_read,
 346     .write = pnv_lpc_xscom_write,
 347     .valid.min_access_size = 8,
 348     .valid.max_access_size = 8,
 349     .impl.min_access_size = 8,
 350     .impl.max_access_size = 8,
 351     .endianness = DEVICE_BIG_ENDIAN,
 352 };
 353
 354 static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size)
 355 {
 356     PnvLpcController *lpc = PNV_LPC(opaque);
 357     uint64_t val = 0;
 358     uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
 359     MemTxResult result;
 360
 361     switch (size) {
 362     case 4:
 363         val = address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
 364                                 &result);
 365         break;
 366     case 1:
 367         val = address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
 368                                  &result);
 369         break;
 370     default:
 371         qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
 372                       HWADDR_PRIx " invalid size %d\n", addr, size);
 373         return 0;
 374     }
 375
 376     if (result != MEMTX_OK) {
 377         qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
 378                       HWADDR_PRIx "\n", addr);
 379     }
 380
 381     return val;
 382 }
 383
 384 static void pnv_lpc_mmio_write(void *opaque, hwaddr addr,
 385                                 uint64_t val, unsigned size)
 386 {
 387     PnvLpcController *lpc = PNV_LPC(opaque);
 388     uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
 389     MemTxResult result;
 390
 391     switch (size) {
 392     case 4:
 393         address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
 394                           &result);
 395          break;
 396     case 1:
 397         address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
 398                           &result);
 399         break;
 400     default:
 401         qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
 402                       HWADDR_PRIx " invalid size %d\n", addr, size);
 403         return;
 404     }
 405
 406     if (result != MEMTX_OK) {
 407         qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
 408                       HWADDR_PRIx "\n", addr);
 409     }
 410 }
 411
 412 static const MemoryRegionOps pnv_lpc_mmio_ops = {
 413     .read = pnv_lpc_mmio_read,
 414     .write = pnv_lpc_mmio_write,
 415     .impl = {
 416         .min_access_size = 1,
 417         .max_access_size = 4,
 418     },
 419     .endianness = DEVICE_BIG_ENDIAN,
 420 };
 421
 422 static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
 423 {
 424     bool lpc_to_opb_irq = false;
 425
 426     /* Update LPC controller to OPB line */
 427     if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
 428         uint32_t irqs;
 429
 430         irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
 431         lpc_to_opb_irq = (irqs != 0);
 432     }
 433
 434     /* We don't honor the polarity register, it's pointless and unused
 435      * anyway
 436      */
 437     if (lpc_to_opb_irq) {
 438         lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
 439     } else {
 440         lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
 441     }
 442
 443     /* Update OPB internal latch */
 444     lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
 445
 446     /* Reflect the interrupt */
 447     qemu_set_irq(lpc->psi_irq, lpc->opb_irq_stat != 0);
 448 }
 449
 450 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
 451 {
 452     PnvLpcController *lpc = opaque;
 453     uint64_t val = 0xfffffffffffffffful;
 454
 455     switch (addr) {
 456     case LPC_HC_FW_SEG_IDSEL:
 457         val =  lpc->lpc_hc_fw_seg_idsel;
 458         break;
 459     case LPC_HC_FW_RD_ACC_SIZE:
 460         val =  lpc->lpc_hc_fw_rd_acc_size;
 461         break;
 462     case LPC_HC_IRQSER_CTRL:
 463         val =  lpc->lpc_hc_irqser_ctrl;
 464         break;
 465     case LPC_HC_IRQMASK:
 466         val =  lpc->lpc_hc_irqmask;
 467         break;
 468     case LPC_HC_IRQSTAT:
 469         val =  lpc->lpc_hc_irqstat;
 470         break;
 471     case LPC_HC_ERROR_ADDRESS:
 472         val =  lpc->lpc_hc_error_addr;
 473         break;
 474     default:
 475         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
 476                       HWADDR_PRIx "\n", addr);
 477     }
 478     return val;
 479 }
 480
 481 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
 482                          unsigned size)
 483 {
 484     PnvLpcController *lpc = opaque;
 485
 486     /* XXX Filter out reserved bits */
 487
 488     switch (addr) {
 489     case LPC_HC_FW_SEG_IDSEL:
 490         /* XXX Actually figure out how that works as this impact
 491          * memory regions/aliases
 492          */
 493         lpc->lpc_hc_fw_seg_idsel = val;
 494         break;
 495     case LPC_HC_FW_RD_ACC_SIZE:
 496         lpc->lpc_hc_fw_rd_acc_size = val;
 497         break;
 498     case LPC_HC_IRQSER_CTRL:
 499         lpc->lpc_hc_irqser_ctrl = val;
 500         pnv_lpc_eval_irqs(lpc);
 501         break;
 502     case LPC_HC_IRQMASK:
 503         lpc->lpc_hc_irqmask = val;
 504         pnv_lpc_eval_irqs(lpc);
 505         break;
 506     case LPC_HC_IRQSTAT:
 507         lpc->lpc_hc_irqstat &= ~val;
 508         pnv_lpc_eval_irqs(lpc);
 509         break;
 510     case LPC_HC_ERROR_ADDRESS:
 511         break;
 512     default:
 513         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
 514                       HWADDR_PRIx "\n", addr);
 515     }
 516 }
 517
 518 static const MemoryRegionOps lpc_hc_ops = {
 519     .read = lpc_hc_read,
 520     .write = lpc_hc_write,
 521     .endianness = DEVICE_BIG_ENDIAN,
 522     .valid = {
 523         .min_access_size = 4,
 524         .max_access_size = 4,
 525     },
 526     .impl = {
 527         .min_access_size = 4,
 528         .max_access_size = 4,
 529     },
 530 };
 531
 532 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
 533 {
 534     PnvLpcController *lpc = opaque;
 535     uint64_t val = 0xfffffffffffffffful;
 536
 537     switch (addr) {
 538     case OPB_MASTER_LS_ROUTE0: /* TODO */
 539         val = lpc->opb_irq_route0;
 540         break;
 541     case OPB_MASTER_LS_ROUTE1: /* TODO */
 542         val = lpc->opb_irq_route1;
 543         break;
 544     case OPB_MASTER_LS_IRQ_STAT:
 545         val = lpc->opb_irq_stat;
 546         break;
 547     case OPB_MASTER_LS_IRQ_MASK:
 548         val = lpc->opb_irq_mask;
 549         break;
 550     case OPB_MASTER_LS_IRQ_POL:
 551         val = lpc->opb_irq_pol;
 552         break;
 553     case OPB_MASTER_LS_IRQ_INPUT:
 554         val = lpc->opb_irq_input;
 555         break;
 556     default:
 557         qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
 558                       HWADDR_PRIx "\n", addr);
 559     }
 560
 561     return val;
 562 }
 563
 564 static void opb_master_write(void *opaque, hwaddr addr,
 565                              uint64_t val, unsigned size)
 566 {
 567     PnvLpcController *lpc = opaque;
 568
 569     switch (addr) {
 570     case OPB_MASTER_LS_ROUTE0: /* TODO */
 571         lpc->opb_irq_route0 = val;
 572         break;
 573     case OPB_MASTER_LS_ROUTE1: /* TODO */
 574         lpc->opb_irq_route1 = val;
 575         break;
 576     case OPB_MASTER_LS_IRQ_STAT:
 577         lpc->opb_irq_stat &= ~val;
 578         pnv_lpc_eval_irqs(lpc);
 579         break;
 580     case OPB_MASTER_LS_IRQ_MASK:
 581         lpc->opb_irq_mask = val;
 582         pnv_lpc_eval_irqs(lpc);
 583         break;
 584     case OPB_MASTER_LS_IRQ_POL:
 585         lpc->opb_irq_pol = val;
 586         pnv_lpc_eval_irqs(lpc);
 587         break;
 588     case OPB_MASTER_LS_IRQ_INPUT:
 589         /* Read only */
 590         break;
 591     default:
 592         qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
 593                       HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
 594     }
 595 }
 596
 597 static const MemoryRegionOps opb_master_ops = {
 598     .read = opb_master_read,
 599     .write = opb_master_write,
 600     .endianness = DEVICE_BIG_ENDIAN,
 601     .valid = {
 602         .min_access_size = 4,
 603         .max_access_size = 4,
 604     },
 605     .impl = {
 606         .min_access_size = 4,
 607         .max_access_size = 4,
 608     },
 609 };
 610
 611 static void pnv_lpc_power8_realize(DeviceState *dev, Error **errp)
 612 {
 613     PnvLpcController *lpc = PNV_LPC(dev);
 614     PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
 615     Error *local_err = NULL;
 616
 617     plc->parent_realize(dev, &local_err);
 618     if (local_err) {
 619         error_propagate(errp, local_err);
 620         return;
 621     }
 622
 623     /* P8 uses a XSCOM region for LPC registers */
 624     pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc),
 625                           &pnv_lpc_xscom_ops, lpc, "xscom-lpc",
 626                           PNV_XSCOM_LPC_SIZE);
 627 }
 628
 629 static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data)
 630 {
 631     DeviceClass *dc = DEVICE_CLASS(klass);
 632     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 633     PnvLpcClass *plc = PNV_LPC_CLASS(klass);
 634
 635     dc->desc = "PowerNV LPC Controller POWER8";
 636
 637     xdc->dt_xscom = pnv_lpc_dt_xscom;
 638
 639     device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
 640                                     &plc->parent_realize);
 641 }
 642
 643 static const TypeInfo pnv_lpc_power8_info = {
 644     .name          = TYPE_PNV8_LPC,
 645     .parent        = TYPE_PNV_LPC,
 646     .class_init    = pnv_lpc_power8_class_init,
 647     .interfaces = (InterfaceInfo[]) {
 648         { TYPE_PNV_XSCOM_INTERFACE },
 649         { }
 650     }
 651 };
 652
 653 static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp)
 654 {
 655     PnvLpcController *lpc = PNV_LPC(dev);
 656     PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
 657     Error *local_err = NULL;
 658
 659     plc->parent_realize(dev, &local_err);
 660     if (local_err) {
 661         error_propagate(errp, local_err);
 662         return;
 663     }
 664
 665     /* P9 uses a MMIO region */
 666     memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops,
 667                           lpc, "lpcm", PNV9_LPCM_SIZE);
 668 }
 669
 670 static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data)
 671 {
 672     DeviceClass *dc = DEVICE_CLASS(klass);
 673     PnvLpcClass *plc = PNV_LPC_CLASS(klass);
 674
 675     dc->desc = "PowerNV LPC Controller POWER9";
 676
 677     device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
 678                                     &plc->parent_realize);
 679 }
 680
 681 static const TypeInfo pnv_lpc_power9_info = {
 682     .name          = TYPE_PNV9_LPC,
 683     .parent        = TYPE_PNV_LPC,
 684     .class_init    = pnv_lpc_power9_class_init,
 685 };
 686
 687 static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data)
 688 {
 689     DeviceClass *dc = DEVICE_CLASS(klass);
 690
 691     dc->desc = "PowerNV LPC Controller POWER10";
 692 }
 693
 694 static const TypeInfo pnv_lpc_power10_info = {
 695     .name          = TYPE_PNV10_LPC,
 696     .parent        = TYPE_PNV9_LPC,
 697     .class_init    = pnv_lpc_power10_class_init,
 698 };
 699
 700 static void pnv_lpc_realize(DeviceState *dev, Error **errp)
 701 {
 702     PnvLpcController *lpc = PNV_LPC(dev);
 703
 704     /* Reg inits */
 705     lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
 706
 707     /* Create address space and backing MR for the OPB bus */
 708     memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull);
 709     address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb");
 710
 711     /* Create ISA IO and Mem space regions which are the root of
 712      * the ISA bus (ie, ISA address spaces). We don't create a
 713      * separate one for FW which we alias to memory.
 714      */
 715     memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE);
 716     memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE);
 717     memory_region_init(&lpc->isa_fw, OBJECT(dev),  "isa-fw", ISA_FW_SIZE);
 718
 719     /* Create windows from the OPB space to the ISA space */
 720     memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io",
 721                              &lpc->isa_io, 0, LPC_IO_OPB_SIZE);
 722     memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR,
 723                                 &lpc->opb_isa_io);
 724     memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem",
 725                              &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE);
 726     memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR,
 727                                 &lpc->opb_isa_mem);
 728     memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw",
 729                              &lpc->isa_fw, 0, LPC_FW_OPB_SIZE);
 730     memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR,
 731                                 &lpc->opb_isa_fw);
 732
 733     /* Create MMIO regions for LPC HC and OPB registers */
 734     memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops,
 735                           lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE);
 736     memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR,
 737                                 &lpc->opb_master_regs);
 738     memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc,
 739                           "lpc-hc", LPC_HC_REGS_OPB_SIZE);
 740     memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
 741                                 &lpc->lpc_hc_regs);
 742
 743     qdev_init_gpio_out(DEVICE(dev), &lpc->psi_irq, 1);
 744 }
 745
 746 static void pnv_lpc_class_init(ObjectClass *klass, void *data)
 747 {
 748     DeviceClass *dc = DEVICE_CLASS(klass);
 749
 750     dc->realize = pnv_lpc_realize;
 751     dc->desc = "PowerNV LPC Controller";
 752     dc->user_creatable = false;
 753 }
 754
 755 static const TypeInfo pnv_lpc_info = {
 756     .name          = TYPE_PNV_LPC,
 757     .parent        = TYPE_DEVICE,
 758     .instance_size = sizeof(PnvLpcController),
 759     .class_init    = pnv_lpc_class_init,
 760     .class_size    = sizeof(PnvLpcClass),
 761     .abstract      = true,
 762 };
 763
 764 static void pnv_lpc_register_types(void)
 765 {
 766     type_register_static(&pnv_lpc_info);
 767     type_register_static(&pnv_lpc_power8_info);
 768     type_register_static(&pnv_lpc_power9_info);
 769     type_register_static(&pnv_lpc_power10_info);
 770 }
 771
 772 type_init(pnv_lpc_register_types)
 773
 774 /* If we don't use the built-in LPC interrupt deserializer, we need
 775  * to provide a set of qirqs for the ISA bus or things will go bad.
 776  *
 777  * Most machines using pre-Naples chips (without said deserializer)
 778  * have a CPLD that will collect the SerIRQ and shoot them as a
 779  * single level interrupt to the P8 chip. So let's setup a hook
 780  * for doing just that.
 781  */
 782 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
 783 {
 784     PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
 785     uint32_t old_state = pnv->cpld_irqstate;
 786     PnvLpcController *lpc = PNV_LPC(opaque);
 787
 788     if (level) {
 789         pnv->cpld_irqstate |= 1u << n;
 790     } else {
 791         pnv->cpld_irqstate &= ~(1u << n);
 792     }
 793
 794     if (pnv->cpld_irqstate != old_state) {
 795         qemu_set_irq(lpc->psi_irq, pnv->cpld_irqstate != 0);
 796     }
 797 }
 798
 799 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
 800 {
 801     PnvLpcController *lpc = PNV_LPC(opaque);
 802
 803     /* The Naples HW latches the 1 levels, clearing is done by SW */
 804     if (level) {
 805         lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
 806         pnv_lpc_eval_irqs(lpc);
 807     }
 808 }
 809
 810 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
 811 {
 812     Error *local_err = NULL;
 813     ISABus *isa_bus;
 814     qemu_irq *irqs;
 815     qemu_irq_handler handler;
 816
 817     /* let isa_bus_new() create its own bridge on SysBus otherwise
 818      * devices specified on the command line won't find the bus and
 819      * will fail to create.
 820      */
 821     isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
 822     if (local_err) {
 823         error_propagate(errp, local_err);
 824         return NULL;
 825     }
 826
 827     /* Not all variants have a working serial irq decoder. If not,
 828      * handling of LPC interrupts becomes a platform issue (some
 829      * platforms have a CPLD to do it).
 830      */
 831     if (use_cpld) {
 832         handler = pnv_lpc_isa_irq_handler_cpld;
 833     } else {
 834         handler = pnv_lpc_isa_irq_handler;
 835     }
 836
 837     irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
 838
 839     isa_bus_irqs(isa_bus, irqs);
 840
 841     return isa_bus;
 842 }