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icount: Take iothread lock when running QEMU timers
[qemu/ar7.git] / hw / net / e1000e_core.c
blob208e3e0d798cf7b6449b96c92899c6d18a84dc56
1 /*
2 * Core code for QEMU e1000e emulation
3 *
4 * Software developer's manuals:
5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6 *
7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 *
10 * Authors:
11 * Dmitry Fleytman <dmitry@daynix.com>
12 * Leonid Bloch <leonid@daynix.com>
13 * Yan Vugenfirer <yan@daynix.com>
14 *
15 * Based on work done by:
16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17 * Copyright (c) 2008 Qumranet
18 * Based on work done by:
19 * Copyright (c) 2007 Dan Aloni
20 * Copyright (c) 2004 Antony T Curtis
21 *
22 * This library is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU Lesser General Public
24 * License as published by the Free Software Foundation; either
25 * version 2.1 of the License, or (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30 * Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34 */
35
36 #include "qemu/osdep.h"
37 #include "qemu/log.h"
38 #include "net/net.h"
39 #include "net/tap.h"
40 #include "hw/pci/msi.h"
41 #include "hw/pci/msix.h"
42 #include "sysemu/runstate.h"
43
44 #include "net_tx_pkt.h"
45 #include "net_rx_pkt.h"
46
47 #include "e1000x_common.h"
48 #include "e1000e_core.h"
49
50 #include "trace.h"
51
52 #define E1000E_MIN_XITR (500) /* No more then 7813 interrupts per
53 second according to spec 10.2.4.2 */
54 #define E1000E_MAX_TX_FRAGS (64)
55
56 static inline void
57 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
58
59 static inline void
60 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp)
61 {
62 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
63 trace_e1000e_wrn_no_ts_support();
64 }
65 }
66
67 static inline void
68 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
69 {
70 if (cmd_and_length & E1000_TXD_CMD_SNAP) {
71 trace_e1000e_wrn_no_snap_support();
72 }
73 }
74
75 static inline void
76 e1000e_raise_legacy_irq(E1000ECore *core)
77 {
78 trace_e1000e_irq_legacy_notify(true);
79 e1000x_inc_reg_if_not_full(core->mac, IAC);
80 pci_set_irq(core->owner, 1);
81 }
82
83 static inline void
84 e1000e_lower_legacy_irq(E1000ECore *core)
85 {
86 trace_e1000e_irq_legacy_notify(false);
87 pci_set_irq(core->owner, 0);
88 }
89
90 static inline void
91 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
92 {
93 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
94 timer->delay_resolution_ns;
95
96 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
97
98 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
99
100 timer->running = true;
101 }
102
103 static void
104 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
105 {
106 if (timer->running) {
107 e1000e_intrmgr_rearm_timer(timer);
108 }
109 }
110
111 static void
112 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer)
113 {
114 if (timer->running) {
115 timer_del(timer->timer);
116 }
117 }
118
119 static inline void
120 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
121 {
122 if (timer->running) {
123 timer_del(timer->timer);
124 timer->running = false;
125 }
126 }
127
128 static inline void
129 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
130 {
131 trace_e1000e_irq_fire_delayed_interrupts();
132 e1000e_set_interrupt_cause(core, 0);
133 }
134
135 static void
136 e1000e_intrmgr_on_timer(void *opaque)
137 {
138 E1000IntrDelayTimer *timer = opaque;
139
140 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
141
142 timer->running = false;
143 e1000e_intrmgr_fire_delayed_interrupts(timer->core);
144 }
145
146 static void
147 e1000e_intrmgr_on_throttling_timer(void *opaque)
148 {
149 E1000IntrDelayTimer *timer = opaque;
150
151 assert(!msix_enabled(timer->core->owner));
152
153 timer->running = false;
154
155 if (!timer->core->itr_intr_pending) {
156 trace_e1000e_irq_throttling_no_pending_interrupts();
157 return;
158 }
159
160 if (msi_enabled(timer->core->owner)) {
161 trace_e1000e_irq_msi_notify_postponed();
162 /* Clear msi_causes_pending to fire MSI eventually */
163 timer->core->msi_causes_pending = 0;
164 e1000e_set_interrupt_cause(timer->core, 0);
165 } else {
166 trace_e1000e_irq_legacy_notify_postponed();
167 e1000e_set_interrupt_cause(timer->core, 0);
168 }
169 }
170
171 static void
172 e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
173 {
174 E1000IntrDelayTimer *timer = opaque;
175 int idx = timer - &timer->core->eitr[0];
176
177 assert(msix_enabled(timer->core->owner));
178
179 timer->running = false;
180
181 if (!timer->core->eitr_intr_pending[idx]) {
182 trace_e1000e_irq_throttling_no_pending_vec(idx);
183 return;
184 }
185
186 trace_e1000e_irq_msix_notify_postponed_vec(idx);
187 msix_notify(timer->core->owner, idx);
188 }
189
190 static void
191 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
192 {
193 int i;
194
195 core->radv.delay_reg = RADV;
196 core->rdtr.delay_reg = RDTR;
197 core->raid.delay_reg = RAID;
198 core->tadv.delay_reg = TADV;
199 core->tidv.delay_reg = TIDV;
200
201 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
202 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
203 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
204 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
205 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
206
207 core->radv.core = core;
208 core->rdtr.core = core;
209 core->raid.core = core;
210 core->tadv.core = core;
211 core->tidv.core = core;
212
213 core->itr.core = core;
214 core->itr.delay_reg = ITR;
215 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
216
217 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
218 core->eitr[i].core = core;
219 core->eitr[i].delay_reg = EITR + i;
220 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
221 }
222
223 if (!create) {
224 return;
225 }
226
227 core->radv.timer =
228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
229 core->rdtr.timer =
230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
231 core->raid.timer =
232 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
233
234 core->tadv.timer =
235 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
236 core->tidv.timer =
237 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
238
239 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
240 e1000e_intrmgr_on_throttling_timer,
241 &core->itr);
242
243 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
244 core->eitr[i].timer =
245 timer_new_ns(QEMU_CLOCK_VIRTUAL,
246 e1000e_intrmgr_on_msix_throttling_timer,
247 &core->eitr[i]);
248 }
249 }
250
251 static inline void
252 e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
253 {
254 e1000e_intrmgr_stop_timer(&core->radv);
255 e1000e_intrmgr_stop_timer(&core->rdtr);
256 e1000e_intrmgr_stop_timer(&core->raid);
257 e1000e_intrmgr_stop_timer(&core->tidv);
258 e1000e_intrmgr_stop_timer(&core->tadv);
259 }
260
261 static bool
262 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes)
263 {
264 uint32_t delayable_causes;
265 uint32_t rdtr = core->mac[RDTR];
266 uint32_t radv = core->mac[RADV];
267 uint32_t raid = core->mac[RAID];
268
269 if (msix_enabled(core->owner)) {
270 return false;
271 }
272
273 delayable_causes = E1000_ICR_RXQ0 |
274 E1000_ICR_RXQ1 |
275 E1000_ICR_RXT0;
276
277 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
278 delayable_causes |= E1000_ICR_ACK;
279 }
280
281 /* Clean up all causes that may be delayed */
282 core->delayed_causes |= *causes & delayable_causes;
283 *causes &= ~delayable_causes;
284
285 /* Check if delayed RX interrupts disabled by client
286 or if there are causes that cannot be delayed */
287 if ((rdtr == 0) || (*causes != 0)) {
288 return false;
289 }
290
291 /* Check if delayed RX ACK interrupts disabled by client
292 and there is an ACK packet received */
293 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
294 return false;
295 }
296
297 /* All causes delayed */
298 e1000e_intrmgr_rearm_timer(&core->rdtr);
299
300 if (!core->radv.running && (radv != 0)) {
301 e1000e_intrmgr_rearm_timer(&core->radv);
302 }
303
304 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
305 e1000e_intrmgr_rearm_timer(&core->raid);
306 }
307
308 return true;
309 }
310
311 static bool
312 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes)
313 {
314 static const uint32_t delayable_causes = E1000_ICR_TXQ0 |
315 E1000_ICR_TXQ1 |
316 E1000_ICR_TXQE |
317 E1000_ICR_TXDW;
318
319 if (msix_enabled(core->owner)) {
320 return false;
321 }
322
323 /* Clean up all causes that may be delayed */
324 core->delayed_causes |= *causes & delayable_causes;
325 *causes &= ~delayable_causes;
326
327 /* If there are causes that cannot be delayed */
328 if (*causes != 0) {
329 return false;
330 }
331
332 /* All causes delayed */
333 e1000e_intrmgr_rearm_timer(&core->tidv);
334
335 if (!core->tadv.running && (core->mac[TADV] != 0)) {
336 e1000e_intrmgr_rearm_timer(&core->tadv);
337 }
338
339 return true;
340 }
341
342 static uint32_t
343 e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
344 {
345 uint32_t res;
346
347 if (msix_enabled(core->owner)) {
348 assert(core->delayed_causes == 0);
349 return 0;
350 }
351
352 res = core->delayed_causes;
353 core->delayed_causes = 0;
354
355 e1000e_intrmgr_stop_delay_timers(core);
356
357 return res;
358 }
359
360 static void
361 e1000e_intrmgr_fire_all_timers(E1000ECore *core)
362 {
363 int i;
364 uint32_t val = e1000e_intmgr_collect_delayed_causes(core);
365
366 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]);
367 core->mac[ICR] |= val;
368
369 if (core->itr.running) {
370 timer_del(core->itr.timer);
371 e1000e_intrmgr_on_throttling_timer(&core->itr);
372 }
373
374 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
375 if (core->eitr[i].running) {
376 timer_del(core->eitr[i].timer);
377 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
378 }
379 }
380 }
381
382 static void
383 e1000e_intrmgr_resume(E1000ECore *core)
384 {
385 int i;
386
387 e1000e_intmgr_timer_resume(&core->radv);
388 e1000e_intmgr_timer_resume(&core->rdtr);
389 e1000e_intmgr_timer_resume(&core->raid);
390 e1000e_intmgr_timer_resume(&core->tidv);
391 e1000e_intmgr_timer_resume(&core->tadv);
392
393 e1000e_intmgr_timer_resume(&core->itr);
394
395 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
396 e1000e_intmgr_timer_resume(&core->eitr[i]);
397 }
398 }
399
400 static void
401 e1000e_intrmgr_pause(E1000ECore *core)
402 {
403 int i;
404
405 e1000e_intmgr_timer_pause(&core->radv);
406 e1000e_intmgr_timer_pause(&core->rdtr);
407 e1000e_intmgr_timer_pause(&core->raid);
408 e1000e_intmgr_timer_pause(&core->tidv);
409 e1000e_intmgr_timer_pause(&core->tadv);
410
411 e1000e_intmgr_timer_pause(&core->itr);
412
413 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
414 e1000e_intmgr_timer_pause(&core->eitr[i]);
415 }
416 }
417
418 static void
419 e1000e_intrmgr_reset(E1000ECore *core)
420 {
421 int i;
422
423 core->delayed_causes = 0;
424
425 e1000e_intrmgr_stop_delay_timers(core);
426
427 e1000e_intrmgr_stop_timer(&core->itr);
428
429 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
430 e1000e_intrmgr_stop_timer(&core->eitr[i]);
431 }
432 }
433
434 static void
435 e1000e_intrmgr_pci_unint(E1000ECore *core)
436 {
437 int i;
438
439 timer_free(core->radv.timer);
440 timer_free(core->rdtr.timer);
441 timer_free(core->raid.timer);
442
443 timer_free(core->tadv.timer);
444 timer_free(core->tidv.timer);
445
446 timer_free(core->itr.timer);
447
448 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
449 timer_free(core->eitr[i].timer);
450 }
451 }
452
453 static void
454 e1000e_intrmgr_pci_realize(E1000ECore *core)
455 {
456 e1000e_intrmgr_initialize_all_timers(core, true);
457 }
458
459 static inline bool
460 e1000e_rx_csum_enabled(E1000ECore *core)
461 {
462 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
463 }
464
465 static inline bool
466 e1000e_rx_use_legacy_descriptor(E1000ECore *core)
467 {
468 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
469 }
470
471 static inline bool
472 e1000e_rx_use_ps_descriptor(E1000ECore *core)
473 {
474 return !e1000e_rx_use_legacy_descriptor(core) &&
475 (core->mac[RCTL] & E1000_RCTL_DTYP_PS);
476 }
477
478 static inline bool
479 e1000e_rss_enabled(E1000ECore *core)
480 {
481 return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
482 !e1000e_rx_csum_enabled(core) &&
483 !e1000e_rx_use_legacy_descriptor(core);
484 }
485
486 typedef struct E1000E_RSSInfo_st {
487 bool enabled;
488 uint32_t hash;
489 uint32_t queue;
490 uint32_t type;
491 } E1000E_RSSInfo;
492
493 static uint32_t
494 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt)
495 {
496 bool isip4, isip6, isudp, istcp;
497
498 assert(e1000e_rss_enabled(core));
499
500 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
501
502 if (isip4) {
503 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
504
505 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC],
506 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
507 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
508
509 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
510 return E1000_MRQ_RSS_TYPE_IPV4TCP;
511 }
512
513 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
514 return E1000_MRQ_RSS_TYPE_IPV4;
515 }
516 } else if (isip6) {
517 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
518
519 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
520 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
521
522 /*
523 * Following two traces must not be combined because resulting
524 * event will have 11 arguments totally and some trace backends
525 * (at least "ust") have limitation of maximum 10 arguments per
526 * event. Events with more arguments fail to compile for
527 * backends like these.
528 */
529 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
530 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, istcp,
531 ip6info->has_ext_hdrs,
532 ip6info->rss_ex_dst_valid,
533 ip6info->rss_ex_src_valid,
534 core->mac[MRQC],
535 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
536 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
537 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
538
539 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
540 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
541 ip6info->rss_ex_src_valid))) {
542
543 if (istcp && !ip6info->fragment &&
544 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
545 return E1000_MRQ_RSS_TYPE_IPV6TCP;
546 }
547
548 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
549 return E1000_MRQ_RSS_TYPE_IPV6EX;
550 }
551
552 }
553
554 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
555 return E1000_MRQ_RSS_TYPE_IPV6;
556 }
557
558 }
559
560 return E1000_MRQ_RSS_TYPE_NONE;
561 }
562
563 static uint32_t
564 e1000e_rss_calc_hash(E1000ECore *core,
565 struct NetRxPkt *pkt,
566 E1000E_RSSInfo *info)
567 {
568 NetRxPktRssType type;
569
570 assert(e1000e_rss_enabled(core));
571
572 switch (info->type) {
573 case E1000_MRQ_RSS_TYPE_IPV4:
574 type = NetPktRssIpV4;
575 break;
576 case E1000_MRQ_RSS_TYPE_IPV4TCP:
577 type = NetPktRssIpV4Tcp;
578 break;
579 case E1000_MRQ_RSS_TYPE_IPV6TCP:
580 type = NetPktRssIpV6TcpEx;
581 break;
582 case E1000_MRQ_RSS_TYPE_IPV6:
583 type = NetPktRssIpV6;
584 break;
585 case E1000_MRQ_RSS_TYPE_IPV6EX:
586 type = NetPktRssIpV6Ex;
587 break;
588 default:
589 assert(false);
590 return 0;
591 }
592
593 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
594 }
595
596 static void
597 e1000e_rss_parse_packet(E1000ECore *core,
598 struct NetRxPkt *pkt,
599 E1000E_RSSInfo *info)
600 {
601 trace_e1000e_rx_rss_started();
602
603 if (!e1000e_rss_enabled(core)) {
604 info->enabled = false;
605 info->hash = 0;
606 info->queue = 0;
607 info->type = 0;
608 trace_e1000e_rx_rss_disabled();
609 return;
610 }
611
612 info->enabled = true;
613
614 info->type = e1000e_rss_get_hash_type(core, pkt);
615
616 trace_e1000e_rx_rss_type(info->type);
617
618 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
619 info->hash = 0;
620 info->queue = 0;
621 return;
622 }
623
624 info->hash = e1000e_rss_calc_hash(core, pkt, info);
625 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
626 }
627
628 static void
629 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx)
630 {
631 if (tx->props.tse && tx->cptse) {
632 net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss);
633 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
634 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
635 return;
636 }
637
638 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
639 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0);
640 }
641
642 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
643 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
644 }
645 }
646
647 static bool
648 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index)
649 {
650 int target_queue = MIN(core->max_queue_num, queue_index);
651 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
652
653 e1000e_setup_tx_offloads(core, tx);
654
655 net_tx_pkt_dump(tx->tx_pkt);
656
657 if ((core->phy[0][PHY_CTRL] & MII_CR_LOOPBACK) ||
658 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
659 return net_tx_pkt_send_loopback(tx->tx_pkt, queue);
660 } else {
661 return net_tx_pkt_send(tx->tx_pkt, queue);
662 }
663 }
664
665 static void
666 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt)
667 {
668 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
669 PTC1023, PTC1522 };
670
671 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt);
672
673 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
674 e1000x_inc_reg_if_not_full(core->mac, TPT);
675 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
676
677 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
678 case ETH_PKT_BCAST:
679 e1000x_inc_reg_if_not_full(core->mac, BPTC);
680 break;
681 case ETH_PKT_MCAST:
682 e1000x_inc_reg_if_not_full(core->mac, MPTC);
683 break;
684 case ETH_PKT_UCAST:
685 break;
686 default:
687 g_assert_not_reached();
688 }
689
690 core->mac[GPTC] = core->mac[TPT];
691 core->mac[GOTCL] = core->mac[TOTL];
692 core->mac[GOTCH] = core->mac[TOTH];
693 }
694
695 static void
696 e1000e_process_tx_desc(E1000ECore *core,
697 struct e1000e_tx *tx,
698 struct e1000_tx_desc *dp,
699 int queue_index)
700 {
701 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
702 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
703 unsigned int split_size = txd_lower & 0xffff;
704 uint64_t addr;
705 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
706 bool eop = txd_lower & E1000_TXD_CMD_EOP;
707
708 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
709 e1000x_read_tx_ctx_descr(xp, &tx->props);
710 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
711 return;
712 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
713 /* data descriptor */
714 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
715 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
716 e1000e_process_ts_option(core, dp);
717 } else {
718 /* legacy descriptor */
719 e1000e_process_ts_option(core, dp);
720 tx->cptse = 0;
721 }
722
723 addr = le64_to_cpu(dp->buffer_addr);
724
725 if (!tx->skip_cp) {
726 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) {
727 tx->skip_cp = true;
728 }
729 }
730
731 if (eop) {
732 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
733 if (e1000x_vlan_enabled(core->mac) &&
734 e1000x_is_vlan_txd(txd_lower)) {
735 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
736 le16_to_cpu(dp->upper.fields.special), core->mac[VET]);
737 }
738 if (e1000e_tx_pkt_send(core, tx, queue_index)) {
739 e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
740 }
741 }
742
743 tx->skip_cp = false;
744 net_tx_pkt_reset(tx->tx_pkt);
745
746 tx->sum_needed = 0;
747 tx->cptse = 0;
748 }
749 }
750
751 static inline uint32_t
752 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
753 {
754 if (!msix_enabled(core->owner)) {
755 return E1000_ICR_TXDW;
756 }
757
758 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
759 }
760
761 static inline uint32_t
762 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
763 bool min_threshold_hit)
764 {
765 if (!msix_enabled(core->owner)) {
766 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
767 }
768
769 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
770 }
771
772 static uint32_t
773 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
774 struct e1000_tx_desc *dp, bool *ide, int queue_idx)
775 {
776 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
777
778 if (!(txd_lower & E1000_TXD_CMD_RS) &&
779 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
780 return 0;
781 }
782
783 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
784
785 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD;
786
787 dp->upper.data = cpu_to_le32(txd_upper);
788 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp),
789 &dp->upper, sizeof(dp->upper));
790 return e1000e_tx_wb_interrupt_cause(core, queue_idx);
791 }
792
793 typedef struct E1000E_RingInfo_st {
794 int dbah;
795 int dbal;
796 int dlen;
797 int dh;
798 int dt;
799 int idx;
800 } E1000E_RingInfo;
801
802 static inline bool
803 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r)
804 {
805 return core->mac[r->dh] == core->mac[r->dt] ||
806 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
807 }
808
809 static inline uint64_t
810 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r)
811 {
812 uint64_t bah = core->mac[r->dbah];
813 uint64_t bal = core->mac[r->dbal];
814
815 return (bah << 32) + bal;
816 }
817
818 static inline uint64_t
819 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r)
820 {
821 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
822 }
823
824 static inline void
825 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count)
826 {
827 core->mac[r->dh] += count;
828
829 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
830 core->mac[r->dh] = 0;
831 }
832 }
833
834 static inline uint32_t
835 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r)
836 {
837 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
838 core->mac[r->dh], core->mac[r->dt]);
839
840 if (core->mac[r->dh] <= core->mac[r->dt]) {
841 return core->mac[r->dt] - core->mac[r->dh];
842 }
843
844 if (core->mac[r->dh] > core->mac[r->dt]) {
845 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
846 core->mac[r->dt] - core->mac[r->dh];
847 }
848
849 g_assert_not_reached();
850 return 0;
851 }
852
853 static inline bool
854 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r)
855 {
856 return core->mac[r->dlen] > 0;
857 }
858
859 static inline uint32_t
860 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r)
861 {
862 return core->mac[r->dlen];
863 }
864
865 typedef struct E1000E_TxRing_st {
866 const E1000E_RingInfo *i;
867 struct e1000e_tx *tx;
868 } E1000E_TxRing;
869
870 static inline int
871 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
872 {
873 return (reg_idx - base_reg_idx) / (0x100 >> 2);
874 }
875
876 static inline void
877 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx)
878 {
879 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
880 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 },
881 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
882 };
883
884 assert(idx < ARRAY_SIZE(i));
885
886 txr->i = &i[idx];
887 txr->tx = &core->tx[idx];
888 }
889
890 typedef struct E1000E_RxRing_st {
891 const E1000E_RingInfo *i;
892 } E1000E_RxRing;
893
894 static inline void
895 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx)
896 {
897 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
898 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
899 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
900 };
901
902 assert(idx < ARRAY_SIZE(i));
903
904 rxr->i = &i[idx];
905 }
906
907 static void
908 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr)
909 {
910 dma_addr_t base;
911 struct e1000_tx_desc desc;
912 bool ide = false;
913 const E1000E_RingInfo *txi = txr->i;
914 uint32_t cause = E1000_ICS_TXQE;
915
916 if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
917 trace_e1000e_tx_disabled();
918 return;
919 }
920
921 while (!e1000e_ring_empty(core, txi)) {
922 base = e1000e_ring_head_descr(core, txi);
923
924 pci_dma_read(core->owner, base, &desc, sizeof(desc));
925
926 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
927 desc.lower.data, desc.upper.data);
928
929 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
930 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
931
932 e1000e_ring_advance(core, txi, 1);
933 }
934
935 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
936 e1000e_set_interrupt_cause(core, cause);
937 }
938 }
939
940 static bool
941 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r,
942 size_t total_size)
943 {
944 uint32_t bufs = e1000e_ring_free_descr_num(core, r);
945
946 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
947 core->rx_desc_buf_size);
948
949 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
950 core->rx_desc_buf_size;
951 }
952
953 void
954 e1000e_start_recv(E1000ECore *core)
955 {
956 int i;
957
958 trace_e1000e_rx_start_recv();
959
960 for (i = 0; i <= core->max_queue_num; i++) {
961 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
962 }
963 }
964
965 bool
966 e1000e_can_receive(E1000ECore *core)
967 {
968 int i;
969
970 if (!e1000x_rx_ready(core->owner, core->mac)) {
971 return false;
972 }
973
974 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
975 E1000E_RxRing rxr;
976
977 e1000e_rx_ring_init(core, &rxr, i);
978 if (e1000e_ring_enabled(core, rxr.i) &&
979 e1000e_has_rxbufs(core, rxr.i, 1)) {
980 trace_e1000e_rx_can_recv();
981 return true;
982 }
983 }
984
985 trace_e1000e_rx_can_recv_rings_full();
986 return false;
987 }
988
989 ssize_t
990 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size)
991 {
992 const struct iovec iov = {
993 .iov_base = (uint8_t *)buf,
994 .iov_len = size
995 };
996
997 return e1000e_receive_iov(core, &iov, 1);
998 }
999
1000 static inline bool
1001 e1000e_rx_l3_cso_enabled(E1000ECore *core)
1002 {
1003 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
1004 }
1005
1006 static inline bool
1007 e1000e_rx_l4_cso_enabled(E1000ECore *core)
1008 {
1009 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
1010 }
1011
1012 static bool
1013 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size)
1014 {
1015 uint32_t rctl = core->mac[RCTL];
1016
1017 if (e1000x_is_vlan_packet(buf, core->mac[VET]) &&
1018 e1000x_vlan_rx_filter_enabled(core->mac)) {
1019 uint16_t vid = lduw_be_p(buf + 14);
1020 uint32_t vfta = ldl_le_p((uint32_t *)(core->mac + VFTA) +
1021 ((vid >> 5) & 0x7f));
1022 if ((vfta & (1 << (vid & 0x1f))) == 0) {
1023 trace_e1000e_rx_flt_vlan_mismatch(vid);
1024 return false;
1025 } else {
1026 trace_e1000e_rx_flt_vlan_match(vid);
1027 }
1028 }
1029
1030 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1031 case ETH_PKT_UCAST:
1032 if (rctl & E1000_RCTL_UPE) {
1033 return true; /* promiscuous ucast */
1034 }
1035 break;
1036
1037 case ETH_PKT_BCAST:
1038 if (rctl & E1000_RCTL_BAM) {
1039 return true; /* broadcast enabled */
1040 }
1041 break;
1042
1043 case ETH_PKT_MCAST:
1044 if (rctl & E1000_RCTL_MPE) {
1045 return true; /* promiscuous mcast */
1046 }
1047 break;
1048
1049 default:
1050 g_assert_not_reached();
1051 }
1052
1053 return e1000x_rx_group_filter(core->mac, buf);
1054 }
1055
1056 static inline void
1057 e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1058 {
1059 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1060 *buff_addr = le64_to_cpu(d->buffer_addr);
1061 }
1062
1063 static inline void
1064 e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1065 {
1066 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1067 *buff_addr = le64_to_cpu(d->read.buffer_addr);
1068 }
1069
1070 static inline void
1071 e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1072 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1073 {
1074 int i;
1075 union e1000_rx_desc_packet_split *d =
1076 (union e1000_rx_desc_packet_split *) desc;
1077
1078 for (i = 0; i < MAX_PS_BUFFERS; i++) {
1079 (*buff_addr)[i] = le64_to_cpu(d->read.buffer_addr[i]);
1080 }
1081
1082 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1],
1083 (*buff_addr)[2], (*buff_addr)[3]);
1084 }
1085
1086 static inline void
1087 e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc,
1088 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1089 {
1090 if (e1000e_rx_use_legacy_descriptor(core)) {
1091 e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]);
1092 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1093 } else {
1094 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1095 e1000e_read_ps_rx_descr(core, desc, buff_addr);
1096 } else {
1097 e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]);
1098 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1099 }
1100 }
1101 }
1102
1103 static void
1104 e1000e_verify_csum_in_sw(E1000ECore *core,
1105 struct NetRxPkt *pkt,
1106 uint32_t *status_flags,
1107 bool istcp, bool isudp)
1108 {
1109 bool csum_valid;
1110 uint32_t csum_error;
1111
1112 if (e1000e_rx_l3_cso_enabled(core)) {
1113 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1114 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1115 } else {
1116 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1117 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1118 }
1119 } else {
1120 trace_e1000e_rx_metadata_l3_cso_disabled();
1121 }
1122
1123 if (!e1000e_rx_l4_cso_enabled(core)) {
1124 trace_e1000e_rx_metadata_l4_cso_disabled();
1125 return;
1126 }
1127
1128 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1129 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1130 return;
1131 }
1132
1133 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1134
1135 if (istcp) {
1136 *status_flags |= E1000_RXD_STAT_TCPCS |
1137 csum_error;
1138 } else if (isudp) {
1139 *status_flags |= E1000_RXD_STAT_TCPCS |
1140 E1000_RXD_STAT_UDPCS |
1141 csum_error;
1142 }
1143 }
1144
1145 static inline bool
1146 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt)
1147 {
1148 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1149 return false;
1150 }
1151
1152 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1153 return !net_rx_pkt_has_tcp_data(rx_pkt);
1154 }
1155
1156 return true;
1157 }
1158
1159 static void
1160 e1000e_build_rx_metadata(E1000ECore *core,
1161 struct NetRxPkt *pkt,
1162 bool is_eop,
1163 const E1000E_RSSInfo *rss_info,
1164 uint32_t *rss, uint32_t *mrq,
1165 uint32_t *status_flags,
1166 uint16_t *ip_id,
1167 uint16_t *vlan_tag)
1168 {
1169 struct virtio_net_hdr *vhdr;
1170 bool isip4, isip6, istcp, isudp;
1171 uint32_t pkt_type;
1172
1173 *status_flags = E1000_RXD_STAT_DD;
1174
1175 /* No additional metadata needed for non-EOP descriptors */
1176 if (!is_eop) {
1177 goto func_exit;
1178 }
1179
1180 *status_flags |= E1000_RXD_STAT_EOP;
1181
1182 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1183 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp);
1184
1185 /* VLAN state */
1186 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1187 *status_flags |= E1000_RXD_STAT_VP;
1188 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1189 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1190 }
1191
1192 /* Packet parsing results */
1193 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1194 if (rss_info->enabled) {
1195 *rss = cpu_to_le32(rss_info->hash);
1196 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8));
1197 trace_e1000e_rx_metadata_rss(*rss, *mrq);
1198 }
1199 } else if (isip4) {
1200 *status_flags |= E1000_RXD_STAT_IPIDV;
1201 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1202 trace_e1000e_rx_metadata_ip_id(*ip_id);
1203 }
1204
1205 if (istcp && e1000e_is_tcp_ack(core, pkt)) {
1206 *status_flags |= E1000_RXD_STAT_ACK;
1207 trace_e1000e_rx_metadata_ack();
1208 }
1209
1210 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1211 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1212 pkt_type = E1000_RXD_PKT_MAC;
1213 } else if (istcp || isudp) {
1214 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1215 } else if (isip4 || isip6) {
1216 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1217 } else {
1218 pkt_type = E1000_RXD_PKT_MAC;
1219 }
1220
1221 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1222 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1223
1224 /* RX CSO information */
1225 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1226 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1227 goto func_exit;
1228 }
1229
1230 if (!net_rx_pkt_has_virt_hdr(pkt)) {
1231 trace_e1000e_rx_metadata_no_virthdr();
1232 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1233 goto func_exit;
1234 }
1235
1236 vhdr = net_rx_pkt_get_vhdr(pkt);
1237
1238 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1239 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1240 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1241 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1242 goto func_exit;
1243 }
1244
1245 if (e1000e_rx_l3_cso_enabled(core)) {
1246 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0;
1247 } else {
1248 trace_e1000e_rx_metadata_l3_cso_disabled();
1249 }
1250
1251 if (e1000e_rx_l4_cso_enabled(core)) {
1252 if (istcp) {
1253 *status_flags |= E1000_RXD_STAT_TCPCS;
1254 } else if (isudp) {
1255 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1256 }
1257 } else {
1258 trace_e1000e_rx_metadata_l4_cso_disabled();
1259 }
1260
1261 trace_e1000e_rx_metadata_status_flags(*status_flags);
1262
1263 func_exit:
1264 *status_flags = cpu_to_le32(*status_flags);
1265 }
1266
1267 static inline void
1268 e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc,
1269 struct NetRxPkt *pkt,
1270 const E1000E_RSSInfo *rss_info,
1271 uint16_t length)
1272 {
1273 uint32_t status_flags, rss, mrq;
1274 uint16_t ip_id;
1275
1276 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1277
1278 assert(!rss_info->enabled);
1279
1280 d->length = cpu_to_le16(length);
1281 d->csum = 0;
1282
1283 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1284 rss_info,
1285 &rss, &mrq,
1286 &status_flags, &ip_id,
1287 &d->special);
1288 d->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1289 d->status = (uint8_t) le32_to_cpu(status_flags);
1290 }
1291
1292 static inline void
1293 e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc,
1294 struct NetRxPkt *pkt,
1295 const E1000E_RSSInfo *rss_info,
1296 uint16_t length)
1297 {
1298 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1299
1300 memset(&d->wb, 0, sizeof(d->wb));
1301
1302 d->wb.upper.length = cpu_to_le16(length);
1303
1304 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1305 rss_info,
1306 &d->wb.lower.hi_dword.rss,
1307 &d->wb.lower.mrq,
1308 &d->wb.upper.status_error,
1309 &d->wb.lower.hi_dword.csum_ip.ip_id,
1310 &d->wb.upper.vlan);
1311 }
1312
1313 static inline void
1314 e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1315 struct NetRxPkt *pkt,
1316 const E1000E_RSSInfo *rss_info,
1317 size_t ps_hdr_len,
1318 uint16_t(*written)[MAX_PS_BUFFERS])
1319 {
1320 int i;
1321 union e1000_rx_desc_packet_split *d =
1322 (union e1000_rx_desc_packet_split *) desc;
1323
1324 memset(&d->wb, 0, sizeof(d->wb));
1325
1326 d->wb.middle.length0 = cpu_to_le16((*written)[0]);
1327
1328 for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1329 d->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1330 }
1331
1332 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1333 rss_info,
1334 &d->wb.lower.hi_dword.rss,
1335 &d->wb.lower.mrq,
1336 &d->wb.middle.status_error,
1337 &d->wb.lower.hi_dword.csum_ip.ip_id,
1338 &d->wb.middle.vlan);
1339
1340 d->wb.upper.header_status =
1341 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1342
1343 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1],
1344 (*written)[2], (*written)[3]);
1345 }
1346
1347 static inline void
1348 e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc,
1349 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
1350 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1351 {
1352 if (e1000e_rx_use_legacy_descriptor(core)) {
1353 assert(ps_hdr_len == 0);
1354 e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0]);
1355 } else {
1356 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1357 e1000e_write_ps_rx_descr(core, desc, pkt, rss_info,
1358 ps_hdr_len, written);
1359 } else {
1360 assert(ps_hdr_len == 0);
1361 e1000e_write_ext_rx_descr(core, desc, pkt, rss_info,
1362 (*written)[0]);
1363 }
1364 }
1365 }
1366
1367 typedef struct e1000e_ba_state_st {
1368 uint16_t written[MAX_PS_BUFFERS];
1369 uint8_t cur_idx;
1370 } e1000e_ba_state;
1371
1372 static inline void
1373 e1000e_write_hdr_to_rx_buffers(E1000ECore *core,
1374 hwaddr (*ba)[MAX_PS_BUFFERS],
1375 e1000e_ba_state *bastate,
1376 const char *data,
1377 dma_addr_t data_len)
1378 {
1379 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1380
1381 pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_len);
1382 bastate->written[0] += data_len;
1383
1384 bastate->cur_idx = 1;
1385 }
1386
1387 static void
1388 e1000e_write_to_rx_buffers(E1000ECore *core,
1389 hwaddr (*ba)[MAX_PS_BUFFERS],
1390 e1000e_ba_state *bastate,
1391 const char *data,
1392 dma_addr_t data_len)
1393 {
1394 while (data_len > 0) {
1395 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1396 uint32_t cur_buf_bytes_left = cur_buf_len -
1397 bastate->written[bastate->cur_idx];
1398 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1399
1400 trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1401 (*ba)[bastate->cur_idx],
1402 bastate->written[bastate->cur_idx],
1403 data,
1404 bytes_to_write);
1405
1406 pci_dma_write(core->owner,
1407 (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1408 data, bytes_to_write);
1409
1410 bastate->written[bastate->cur_idx] += bytes_to_write;
1411 data += bytes_to_write;
1412 data_len -= bytes_to_write;
1413
1414 if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1415 bastate->cur_idx++;
1416 }
1417
1418 assert(bastate->cur_idx < MAX_PS_BUFFERS);
1419 }
1420 }
1421
1422 static void
1423 e1000e_update_rx_stats(E1000ECore *core,
1424 size_t data_size,
1425 size_t data_fcs_size)
1426 {
1427 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
1428
1429 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1430 case ETH_PKT_BCAST:
1431 e1000x_inc_reg_if_not_full(core->mac, BPRC);
1432 break;
1433
1434 case ETH_PKT_MCAST:
1435 e1000x_inc_reg_if_not_full(core->mac, MPRC);
1436 break;
1437
1438 default:
1439 break;
1440 }
1441 }
1442
1443 static inline bool
1444 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi)
1445 {
1446 return e1000e_ring_free_descr_num(core, rxi) ==
1447 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1448 }
1449
1450 static bool
1451 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len)
1452 {
1453 bool isip4, isip6, isudp, istcp;
1454 bool fragment;
1455
1456 if (!e1000e_rx_use_ps_descriptor(core)) {
1457 return false;
1458 }
1459
1460 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1461
1462 if (isip4) {
1463 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1464 } else if (isip6) {
1465 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1466 } else {
1467 return false;
1468 }
1469
1470 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1471 return false;
1472 }
1473
1474 if (!fragment && (isudp || istcp)) {
1475 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1476 } else {
1477 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1478 }
1479
1480 if ((*hdr_len > core->rxbuf_sizes[0]) ||
1481 (*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1482 return false;
1483 }
1484
1485 return true;
1486 }
1487
1488 static void
1489 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt,
1490 const E1000E_RxRing *rxr,
1491 const E1000E_RSSInfo *rss_info)
1492 {
1493 PCIDevice *d = core->owner;
1494 dma_addr_t base;
1495 uint8_t desc[E1000_MAX_RX_DESC_LEN];
1496 size_t desc_size;
1497 size_t desc_offset = 0;
1498 size_t iov_ofs = 0;
1499
1500 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1501 size_t size = net_rx_pkt_get_total_len(pkt);
1502 size_t total_size = size + e1000x_fcs_len(core->mac);
1503 const E1000E_RingInfo *rxi;
1504 size_t ps_hdr_len = 0;
1505 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1506 bool is_first = true;
1507
1508 rxi = rxr->i;
1509
1510 do {
1511 hwaddr ba[MAX_PS_BUFFERS];
1512 e1000e_ba_state bastate = { { 0 } };
1513 bool is_last = false;
1514
1515 desc_size = total_size - desc_offset;
1516
1517 if (desc_size > core->rx_desc_buf_size) {
1518 desc_size = core->rx_desc_buf_size;
1519 }
1520
1521 if (e1000e_ring_empty(core, rxi)) {
1522 return;
1523 }
1524
1525 base = e1000e_ring_head_descr(core, rxi);
1526
1527 pci_dma_read(d, base, &desc, core->rx_desc_len);
1528
1529 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1530
1531 e1000e_read_rx_descr(core, desc, &ba);
1532
1533 if (ba[0]) {
1534 if (desc_offset < size) {
1535 static const uint32_t fcs_pad;
1536 size_t iov_copy;
1537 size_t copy_size = size - desc_offset;
1538 if (copy_size > core->rx_desc_buf_size) {
1539 copy_size = core->rx_desc_buf_size;
1540 }
1541
1542 /* For PS mode copy the packet header first */
1543 if (do_ps) {
1544 if (is_first) {
1545 size_t ps_hdr_copied = 0;
1546 do {
1547 iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1548 iov->iov_len - iov_ofs);
1549
1550 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1551 iov->iov_base, iov_copy);
1552
1553 copy_size -= iov_copy;
1554 ps_hdr_copied += iov_copy;
1555
1556 iov_ofs += iov_copy;
1557 if (iov_ofs == iov->iov_len) {
1558 iov++;
1559 iov_ofs = 0;
1560 }
1561 } while (ps_hdr_copied < ps_hdr_len);
1562
1563 is_first = false;
1564 } else {
1565 /* Leave buffer 0 of each descriptor except first */
1566 /* empty as per spec 7.1.5.1 */
1567 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1568 NULL, 0);
1569 }
1570 }
1571
1572 /* Copy packet payload */
1573 while (copy_size) {
1574 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1575
1576 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1577 iov->iov_base + iov_ofs, iov_copy);
1578
1579 copy_size -= iov_copy;
1580 iov_ofs += iov_copy;
1581 if (iov_ofs == iov->iov_len) {
1582 iov++;
1583 iov_ofs = 0;
1584 }
1585 }
1586
1587 if (desc_offset + desc_size >= total_size) {
1588 /* Simulate FCS checksum presence in the last descriptor */
1589 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1590 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1591 }
1592 }
1593 } else { /* as per intel docs; skip descriptors with null buf addr */
1594 trace_e1000e_rx_null_descriptor();
1595 }
1596 desc_offset += desc_size;
1597 if (desc_offset >= total_size) {
1598 is_last = true;
1599 }
1600
1601 e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL,
1602 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1603 pci_dma_write(d, base, &desc, core->rx_desc_len);
1604
1605 e1000e_ring_advance(core, rxi,
1606 core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1607
1608 } while (desc_offset < total_size);
1609
1610 e1000e_update_rx_stats(core, size, total_size);
1611 }
1612
1613 static inline void
1614 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
1615 {
1616 if (net_rx_pkt_has_virt_hdr(pkt)) {
1617 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1618
1619 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1620 net_rx_pkt_fix_l4_csum(pkt);
1621 }
1622 }
1623 }
1624
1625 ssize_t
1626 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
1627 {
1628 static const int maximum_ethernet_hdr_len = (14 + 4);
1629 /* Min. octets in an ethernet frame sans FCS */
1630 static const int min_buf_size = 60;
1631
1632 uint32_t n = 0;
1633 uint8_t min_buf[min_buf_size];
1634 struct iovec min_iov;
1635 uint8_t *filter_buf;
1636 size_t size, orig_size;
1637 size_t iov_ofs = 0;
1638 E1000E_RxRing rxr;
1639 E1000E_RSSInfo rss_info;
1640 size_t total_size;
1641 ssize_t retval;
1642 bool rdmts_hit;
1643
1644 trace_e1000e_rx_receive_iov(iovcnt);
1645
1646 if (!e1000x_hw_rx_enabled(core->mac)) {
1647 return -1;
1648 }
1649
1650 /* Pull virtio header in */
1651 if (core->has_vnet) {
1652 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1653 iov_ofs = sizeof(struct virtio_net_hdr);
1654 }
1655
1656 filter_buf = iov->iov_base + iov_ofs;
1657 orig_size = iov_size(iov, iovcnt);
1658 size = orig_size - iov_ofs;
1659
1660 /* Pad to minimum Ethernet frame length */
1661 if (size < sizeof(min_buf)) {
1662 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
1663 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1664 e1000x_inc_reg_if_not_full(core->mac, RUC);
1665 min_iov.iov_base = filter_buf = min_buf;
1666 min_iov.iov_len = size = sizeof(min_buf);
1667 iovcnt = 1;
1668 iov = &min_iov;
1669 iov_ofs = 0;
1670 } else if (iov->iov_len < maximum_ethernet_hdr_len) {
1671 /* This is very unlikely, but may happen. */
1672 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
1673 filter_buf = min_buf;
1674 }
1675
1676 /* Discard oversized packets if !LPE and !SBP. */
1677 if (e1000x_is_oversized(core->mac, size)) {
1678 return orig_size;
1679 }
1680
1681 net_rx_pkt_set_packet_type(core->rx_pkt,
1682 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf)));
1683
1684 if (!e1000e_receive_filter(core, filter_buf, size)) {
1685 trace_e1000e_rx_flt_dropped();
1686 return orig_size;
1687 }
1688
1689 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1690 e1000x_vlan_enabled(core->mac), core->mac[VET]);
1691
1692 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1693 e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1694
1695 trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
1696
1697 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1698 e1000x_fcs_len(core->mac);
1699
1700 if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1701 e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1702
1703 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1704
1705 retval = orig_size;
1706
1707 /* Perform small receive detection (RSRPD) */
1708 if (total_size < core->mac[RSRPD]) {
1709 n |= E1000_ICS_SRPD;
1710 }
1711
1712 /* Perform ACK receive detection */
1713 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1714 (e1000e_is_tcp_ack(core, core->rx_pkt))) {
1715 n |= E1000_ICS_ACK;
1716 }
1717
1718 /* Check if receive descriptor minimum threshold hit */
1719 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1720 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1721
1722 trace_e1000e_rx_written_to_guest(n);
1723 } else {
1724 n |= E1000_ICS_RXO;
1725 retval = 0;
1726
1727 trace_e1000e_rx_not_written_to_guest(n);
1728 }
1729
1730 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) {
1731 trace_e1000e_rx_interrupt_set(n);
1732 e1000e_set_interrupt_cause(core, n);
1733 } else {
1734 trace_e1000e_rx_interrupt_delayed(n);
1735 }
1736
1737 return retval;
1738 }
1739
1740 static inline bool
1741 e1000e_have_autoneg(E1000ECore *core)
1742 {
1743 return core->phy[0][PHY_CTRL] & MII_CR_AUTO_NEG_EN;
1744 }
1745
1746 static void e1000e_update_flowctl_status(E1000ECore *core)
1747 {
1748 if (e1000e_have_autoneg(core) &&
1749 core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE) {
1750 trace_e1000e_link_autoneg_flowctl(true);
1751 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1752 } else {
1753 trace_e1000e_link_autoneg_flowctl(false);
1754 }
1755 }
1756
1757 static inline void
1758 e1000e_link_down(E1000ECore *core)
1759 {
1760 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1761 e1000e_update_flowctl_status(core);
1762 }
1763
1764 static inline void
1765 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1766 {
1767 /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */
1768 core->phy[0][PHY_CTRL] = val & ~(0x3f |
1769 MII_CR_RESET |
1770 MII_CR_RESTART_AUTO_NEG);
1771
1772 if ((val & MII_CR_RESTART_AUTO_NEG) &&
1773 e1000e_have_autoneg(core)) {
1774 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1775 }
1776 }
1777
1778 static void
1779 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1780 {
1781 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1782
1783 if (val & BIT(10)) {
1784 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1785 }
1786 }
1787
1788 static void
1789 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1790 {
1791 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1792 }
1793
1794 void
1795 e1000e_core_set_link_status(E1000ECore *core)
1796 {
1797 NetClientState *nc = qemu_get_queue(core->owner_nic);
1798 uint32_t old_status = core->mac[STATUS];
1799
1800 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1801
1802 if (nc->link_down) {
1803 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1804 } else {
1805 if (e1000e_have_autoneg(core) &&
1806 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
1807 e1000x_restart_autoneg(core->mac, core->phy[0],
1808 core->autoneg_timer);
1809 } else {
1810 e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1811 e1000e_start_recv(core);
1812 }
1813 }
1814
1815 if (core->mac[STATUS] != old_status) {
1816 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1817 }
1818 }
1819
1820 static void
1821 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1822 {
1823 trace_e1000e_core_ctrl_write(index, val);
1824
1825 /* RST is self clearing */
1826 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1827 core->mac[CTRL_DUP] = core->mac[CTRL];
1828
1829 trace_e1000e_link_set_params(
1830 !!(val & E1000_CTRL_ASDE),
1831 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1832 !!(val & E1000_CTRL_FRCSPD),
1833 !!(val & E1000_CTRL_FRCDPX),
1834 !!(val & E1000_CTRL_RFCE),
1835 !!(val & E1000_CTRL_TFCE));
1836
1837 if (val & E1000_CTRL_RST) {
1838 trace_e1000e_core_ctrl_sw_reset();
1839 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
1840 }
1841
1842 if (val & E1000_CTRL_PHY_RST) {
1843 trace_e1000e_core_ctrl_phy_reset();
1844 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1845 }
1846 }
1847
1848 static void
1849 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1850 {
1851 trace_e1000e_rx_set_rfctl(val);
1852
1853 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1854 trace_e1000e_wrn_iscsi_filtering_not_supported();
1855 }
1856
1857 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1858 trace_e1000e_wrn_nfsw_filtering_not_supported();
1859 }
1860
1861 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1862 trace_e1000e_wrn_nfsr_filtering_not_supported();
1863 }
1864
1865 core->mac[RFCTL] = val;
1866 }
1867
1868 static void
1869 e1000e_calc_per_desc_buf_size(E1000ECore *core)
1870 {
1871 int i;
1872 core->rx_desc_buf_size = 0;
1873
1874 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1875 core->rx_desc_buf_size += core->rxbuf_sizes[i];
1876 }
1877 }
1878
1879 static void
1880 e1000e_parse_rxbufsize(E1000ECore *core)
1881 {
1882 uint32_t rctl = core->mac[RCTL];
1883
1884 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1885
1886 if (rctl & E1000_RCTL_DTYP_MASK) {
1887 uint32_t bsize;
1888
1889 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1890 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1891
1892 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1893 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1894
1895 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1896 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1897
1898 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1899 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1900 } else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1901 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1902 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1903 } else {
1904 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1905 }
1906
1907 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1908 core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1909
1910 e1000e_calc_per_desc_buf_size(core);
1911 }
1912
1913 static void
1914 e1000e_calc_rxdesclen(E1000ECore *core)
1915 {
1916 if (e1000e_rx_use_legacy_descriptor(core)) {
1917 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1918 } else {
1919 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1920 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1921 } else {
1922 core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1923 }
1924 }
1925 trace_e1000e_rx_desc_len(core->rx_desc_len);
1926 }
1927
1928 static void
1929 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1930 {
1931 core->mac[RCTL] = val;
1932 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1933
1934 if (val & E1000_RCTL_EN) {
1935 e1000e_parse_rxbufsize(core);
1936 e1000e_calc_rxdesclen(core);
1937 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
1938 E1000_RING_DESC_LEN_SHIFT;
1939
1940 e1000e_start_recv(core);
1941 }
1942 }
1943
1944 static
1945 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
1946 (E1000ECore *, int, uint16_t) = {
1947 [0] = {
1948 [PHY_CTRL] = e1000e_set_phy_ctrl,
1949 [PHY_PAGE] = e1000e_set_phy_page,
1950 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits
1951 }
1952 };
1953
1954 static inline void
1955 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits)
1956 {
1957 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1958 core->mac[IMS] &= ~bits;
1959 }
1960
1961 static inline bool
1962 e1000e_postpone_interrupt(bool *interrupt_pending,
1963 E1000IntrDelayTimer *timer)
1964 {
1965 if (timer->running) {
1966 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1967
1968 *interrupt_pending = true;
1969 return true;
1970 }
1971
1972 if (timer->core->mac[timer->delay_reg] != 0) {
1973 e1000e_intrmgr_rearm_timer(timer);
1974 }
1975
1976 return false;
1977 }
1978
1979 static inline bool
1980 e1000e_itr_should_postpone(E1000ECore *core)
1981 {
1982 return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr);
1983 }
1984
1985 static inline bool
1986 e1000e_eitr_should_postpone(E1000ECore *core, int idx)
1987 {
1988 return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx],
1989 &core->eitr[idx]);
1990 }
1991
1992 static void
1993 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
1994 {
1995 uint32_t effective_eiac;
1996
1997 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
1998 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
1999 if (vec < E1000E_MSIX_VEC_NUM) {
2000 if (!e1000e_eitr_should_postpone(core, vec)) {
2001 trace_e1000e_irq_msix_notify_vec(vec);
2002 msix_notify(core->owner, vec);
2003 }
2004 } else {
2005 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2006 }
2007 } else {
2008 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2009 }
2010
2011 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
2012 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2013 core->mac[IAM] &= ~cause;
2014 }
2015
2016 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2017
2018 effective_eiac = core->mac[EIAC] & cause;
2019
2020 core->mac[ICR] &= ~effective_eiac;
2021 core->msi_causes_pending &= ~effective_eiac;
2022
2023 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2024 core->mac[IMS] &= ~effective_eiac;
2025 }
2026 }
2027
2028 static void
2029 e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2030 {
2031 if (causes & E1000_ICR_RXQ0) {
2032 e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2033 E1000_IVAR_RXQ0(core->mac[IVAR]));
2034 }
2035
2036 if (causes & E1000_ICR_RXQ1) {
2037 e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2038 E1000_IVAR_RXQ1(core->mac[IVAR]));
2039 }
2040
2041 if (causes & E1000_ICR_TXQ0) {
2042 e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2043 E1000_IVAR_TXQ0(core->mac[IVAR]));
2044 }
2045
2046 if (causes & E1000_ICR_TXQ1) {
2047 e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2048 E1000_IVAR_TXQ1(core->mac[IVAR]));
2049 }
2050
2051 if (causes & E1000_ICR_OTHER) {
2052 e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2053 E1000_IVAR_OTHER(core->mac[IVAR]));
2054 }
2055 }
2056
2057 static void
2058 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2059 {
2060 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2061 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2062 if (vec < E1000E_MSIX_VEC_NUM) {
2063 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2064 msix_clr_pending(core->owner, vec);
2065 } else {
2066 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2067 }
2068 } else {
2069 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2070 }
2071 }
2072
2073 static void
2074 e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2075 {
2076 if (causes & E1000_ICR_RXQ0) {
2077 e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2078 E1000_IVAR_RXQ0(core->mac[IVAR]));
2079 }
2080
2081 if (causes & E1000_ICR_RXQ1) {
2082 e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2083 E1000_IVAR_RXQ1(core->mac[IVAR]));
2084 }
2085
2086 if (causes & E1000_ICR_TXQ0) {
2087 e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2088 E1000_IVAR_TXQ0(core->mac[IVAR]));
2089 }
2090
2091 if (causes & E1000_ICR_TXQ1) {
2092 e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2093 E1000_IVAR_TXQ1(core->mac[IVAR]));
2094 }
2095
2096 if (causes & E1000_ICR_OTHER) {
2097 e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2098 E1000_IVAR_OTHER(core->mac[IVAR]));
2099 }
2100 }
2101
2102 static inline void
2103 e1000e_fix_icr_asserted(E1000ECore *core)
2104 {
2105 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2106 if (core->mac[ICR]) {
2107 core->mac[ICR] |= E1000_ICR_ASSERTED;
2108 }
2109
2110 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2111 }
2112
2113 static void
2114 e1000e_send_msi(E1000ECore *core, bool msix)
2115 {
2116 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED;
2117
2118 core->msi_causes_pending &= causes;
2119 causes ^= core->msi_causes_pending;
2120 if (causes == 0) {
2121 return;
2122 }
2123 core->msi_causes_pending |= causes;
2124
2125 if (msix) {
2126 e1000e_msix_notify(core, causes);
2127 } else {
2128 if (!e1000e_itr_should_postpone(core)) {
2129 trace_e1000e_irq_msi_notify(causes);
2130 msi_notify(core->owner, 0);
2131 }
2132 }
2133 }
2134
2135 static void
2136 e1000e_update_interrupt_state(E1000ECore *core)
2137 {
2138 bool interrupts_pending;
2139 bool is_msix = msix_enabled(core->owner);
2140
2141 /* Set ICR[OTHER] for MSI-X */
2142 if (is_msix) {
2143 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2144 core->mac[ICR] |= E1000_ICR_OTHER;
2145 trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2146 }
2147 }
2148
2149 e1000e_fix_icr_asserted(core);
2150
2151 /*
2152 * Make sure ICR and ICS registers have the same value.
2153 * The spec says that the ICS register is write-only. However in practice,
2154 * on real hardware ICS is readable, and for reads it has the same value as
2155 * ICR (except that ICS does not have the clear on read behaviour of ICR).
2156 *
2157 * The VxWorks PRO/1000 driver uses this behaviour.
2158 */
2159 core->mac[ICS] = core->mac[ICR];
2160
2161 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false;
2162 if (!interrupts_pending) {
2163 core->msi_causes_pending = 0;
2164 }
2165
2166 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2167 core->mac[ICR], core->mac[IMS]);
2168
2169 if (is_msix || msi_enabled(core->owner)) {
2170 if (interrupts_pending) {
2171 e1000e_send_msi(core, is_msix);
2172 }
2173 } else {
2174 if (interrupts_pending) {
2175 if (!e1000e_itr_should_postpone(core)) {
2176 e1000e_raise_legacy_irq(core);
2177 }
2178 } else {
2179 e1000e_lower_legacy_irq(core);
2180 }
2181 }
2182 }
2183
2184 static void
2185 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2186 {
2187 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
2188
2189 val |= e1000e_intmgr_collect_delayed_causes(core);
2190 core->mac[ICR] |= val;
2191
2192 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
2193
2194 e1000e_update_interrupt_state(core);
2195 }
2196
2197 static inline void
2198 e1000e_autoneg_timer(void *opaque)
2199 {
2200 E1000ECore *core = opaque;
2201 if (!qemu_get_queue(core->owner_nic)->link_down) {
2202 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2203 e1000e_start_recv(core);
2204
2205 e1000e_update_flowctl_status(core);
2206 /* signal link status change to the guest */
2207 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2208 }
2209 }
2210
2211 static inline uint16_t
2212 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2213 {
2214 uint16_t index = (addr & 0x1ffff) >> 2;
2215 return index + (mac_reg_access[index] & 0xfffe);
2216 }
2217
2218 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2219 [0] = {
2220 [PHY_CTRL] = PHY_ANYPAGE | PHY_RW,
2221 [PHY_STATUS] = PHY_ANYPAGE | PHY_R,
2222 [PHY_ID1] = PHY_ANYPAGE | PHY_R,
2223 [PHY_ID2] = PHY_ANYPAGE | PHY_R,
2224 [PHY_AUTONEG_ADV] = PHY_ANYPAGE | PHY_RW,
2225 [PHY_LP_ABILITY] = PHY_ANYPAGE | PHY_R,
2226 [PHY_AUTONEG_EXP] = PHY_ANYPAGE | PHY_R,
2227 [PHY_NEXT_PAGE_TX] = PHY_ANYPAGE | PHY_RW,
2228 [PHY_LP_NEXT_PAGE] = PHY_ANYPAGE | PHY_R,
2229 [PHY_1000T_CTRL] = PHY_ANYPAGE | PHY_RW,
2230 [PHY_1000T_STATUS] = PHY_ANYPAGE | PHY_R,
2231 [PHY_EXT_STATUS] = PHY_ANYPAGE | PHY_R,
2232 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW,
2233
2234 [PHY_COPPER_CTRL1] = PHY_RW,
2235 [PHY_COPPER_STAT1] = PHY_R,
2236 [PHY_COPPER_CTRL3] = PHY_RW,
2237 [PHY_RX_ERR_CNTR] = PHY_R,
2238 [PHY_OEM_BITS] = PHY_RW,
2239 [PHY_BIAS_1] = PHY_RW,
2240 [PHY_BIAS_2] = PHY_RW,
2241 [PHY_COPPER_INT_ENABLE] = PHY_RW,
2242 [PHY_COPPER_STAT2] = PHY_R,
2243 [PHY_COPPER_CTRL2] = PHY_RW
2244 },
2245 [2] = {
2246 [PHY_MAC_CTRL1] = PHY_RW,
2247 [PHY_MAC_INT_ENABLE] = PHY_RW,
2248 [PHY_MAC_STAT] = PHY_R,
2249 [PHY_MAC_CTRL2] = PHY_RW
2250 },
2251 [3] = {
2252 [PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2253 [PHY_LED_03_POL_CTRL] = PHY_RW,
2254 [PHY_LED_TIMER_CTRL] = PHY_RW,
2255 [PHY_LED_45_CTRL] = PHY_RW
2256 },
2257 [5] = {
2258 [PHY_1000T_SKEW] = PHY_R,
2259 [PHY_1000T_SWAP] = PHY_R
2260 },
2261 [6] = {
2262 [PHY_CRC_COUNTERS] = PHY_R
2263 }
2264 };
2265
2266 static bool
2267 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2268 char cap, uint8_t *page)
2269 {
2270 *page =
2271 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2272 : core->phy[0][PHY_PAGE];
2273
2274 if (*page >= E1000E_PHY_PAGES) {
2275 return false;
2276 }
2277
2278 return e1000e_phy_regcap[*page][addr] & cap;
2279 }
2280
2281 static void
2282 e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2283 uint32_t addr, uint16_t data)
2284 {
2285 assert(page < E1000E_PHY_PAGES);
2286 assert(addr < E1000E_PHY_PAGE_SIZE);
2287
2288 if (e1000e_phyreg_writeops[page][addr]) {
2289 e1000e_phyreg_writeops[page][addr](core, addr, data);
2290 } else {
2291 core->phy[page][addr] = data;
2292 }
2293 }
2294
2295 static void
2296 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2297 {
2298 uint32_t data = val & E1000_MDIC_DATA_MASK;
2299 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2300 uint8_t page;
2301
2302 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2303 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2304 } else if (val & E1000_MDIC_OP_READ) {
2305 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2306 trace_e1000e_core_mdic_read_unhandled(page, addr);
2307 val |= E1000_MDIC_ERROR;
2308 } else {
2309 val = (val ^ data) | core->phy[page][addr];
2310 trace_e1000e_core_mdic_read(page, addr, val);
2311 }
2312 } else if (val & E1000_MDIC_OP_WRITE) {
2313 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2314 trace_e1000e_core_mdic_write_unhandled(page, addr);
2315 val |= E1000_MDIC_ERROR;
2316 } else {
2317 trace_e1000e_core_mdic_write(page, addr, data);
2318 e1000e_phy_reg_write(core, page, addr, data);
2319 }
2320 }
2321 core->mac[MDIC] = val | E1000_MDIC_READY;
2322
2323 if (val & E1000_MDIC_INT_EN) {
2324 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2325 }
2326 }
2327
2328 static void
2329 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2330 {
2331 core->mac[index] = val & 0xffff;
2332 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2333 e1000e_start_recv(core);
2334 }
2335
2336 static void
2337 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2338 {
2339 if ((val & E1000_STATUS_PHYRA) == 0) {
2340 core->mac[index] &= ~E1000_STATUS_PHYRA;
2341 }
2342 }
2343
2344 static void
2345 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2346 {
2347 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2348 !!(val & E1000_CTRL_EXT_SPD_BYPS));
2349
2350 /* Zero self-clearing bits */
2351 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2352 core->mac[CTRL_EXT] = val;
2353 }
2354
2355 static void
2356 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2357 {
2358 int i;
2359
2360 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2361
2362 if (!msix_enabled(core->owner)) {
2363 return;
2364 }
2365
2366 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2367 if (core->mac[PBACLR] & BIT(i)) {
2368 msix_clr_pending(core->owner, i);
2369 }
2370 }
2371 }
2372
2373 static void
2374 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2375 {
2376 core->mac[FCRTH] = val & 0xFFF8;
2377 }
2378
2379 static void
2380 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2381 {
2382 core->mac[FCRTL] = val & 0x8000FFF8;
2383 }
2384
2385 static inline void
2386 e1000e_set_16bit(E1000ECore *core, int index, uint32_t val)
2387 {
2388 core->mac[index] = val & 0xffff;
2389 }
2390
2391 static void
2392 e1000e_set_12bit(E1000ECore *core, int index, uint32_t val)
2393 {
2394 core->mac[index] = val & 0xfff;
2395 }
2396
2397 static void
2398 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2399 {
2400 core->mac[VET] = val & 0xffff;
2401 trace_e1000e_vlan_vet(core->mac[VET]);
2402 }
2403
2404 static void
2405 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2406 {
2407 core->mac[index] = val & E1000_XDLEN_MASK;
2408 }
2409
2410 static void
2411 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2412 {
2413 core->mac[index] = val & E1000_XDBAL_MASK;
2414 }
2415
2416 static void
2417 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2418 {
2419 E1000E_TxRing txr;
2420 core->mac[index] = val;
2421
2422 if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2423 e1000e_tx_ring_init(core, &txr, 0);
2424 e1000e_start_xmit(core, &txr);
2425 }
2426
2427 if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2428 e1000e_tx_ring_init(core, &txr, 1);
2429 e1000e_start_xmit(core, &txr);
2430 }
2431 }
2432
2433 static void
2434 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2435 {
2436 E1000E_TxRing txr;
2437 int qidx = e1000e_mq_queue_idx(TDT, index);
2438 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2439
2440 core->mac[index] = val & 0xffff;
2441
2442 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2443 e1000e_tx_ring_init(core, &txr, qidx);
2444 e1000e_start_xmit(core, &txr);
2445 }
2446 }
2447
2448 static void
2449 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2450 {
2451 trace_e1000e_irq_write_ics(val);
2452 e1000e_set_interrupt_cause(core, val);
2453 }
2454
2455 static void
2456 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2457 {
2458 uint32_t icr = 0;
2459 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2460 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2461 trace_e1000e_irq_icr_process_iame();
2462 e1000e_clear_ims_bits(core, core->mac[IAM]);
2463 }
2464
2465 icr = core->mac[ICR] & ~val;
2466 /* Windows driver expects that the "receive overrun" bit and other
2467 * ones to be cleared when the "Other" bit (#24) is cleared.
2468 */
2469 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
2470 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
2471 core->mac[ICR] = icr;
2472 e1000e_update_interrupt_state(core);
2473 }
2474
2475 static void
2476 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2477 {
2478 trace_e1000e_irq_ims_clear_set_imc(val);
2479 e1000e_clear_ims_bits(core, val);
2480 e1000e_update_interrupt_state(core);
2481 }
2482
2483 static void
2484 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2485 {
2486 static const uint32_t ims_ext_mask =
2487 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 |
2488 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2489 E1000_IMS_OTHER;
2490
2491 static const uint32_t ims_valid_mask =
2492 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC |
2493 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 |
2494 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD |
2495 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 |
2496 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2497 E1000_IMS_OTHER;
2498
2499 uint32_t valid_val = val & ims_valid_mask;
2500
2501 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2502 core->mac[IMS] |= valid_val;
2503
2504 if ((valid_val & ims_ext_mask) &&
2505 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2506 msix_enabled(core->owner)) {
2507 e1000e_msix_clear(core, valid_val);
2508 }
2509
2510 if ((valid_val == ims_valid_mask) &&
2511 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2512 trace_e1000e_irq_fire_all_timers(val);
2513 e1000e_intrmgr_fire_all_timers(core);
2514 }
2515
2516 e1000e_update_interrupt_state(core);
2517 }
2518
2519 static void
2520 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2521 {
2522 e1000e_set_16bit(core, index, val);
2523
2524 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2525 trace_e1000e_irq_rdtr_fpd_running();
2526 e1000e_intrmgr_fire_delayed_interrupts(core);
2527 } else {
2528 trace_e1000e_irq_rdtr_fpd_not_running();
2529 }
2530 }
2531
2532 static void
2533 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2534 {
2535 e1000e_set_16bit(core, index, val);
2536
2537 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2538 trace_e1000e_irq_tidv_fpd_running();
2539 e1000e_intrmgr_fire_delayed_interrupts(core);
2540 } else {
2541 trace_e1000e_irq_tidv_fpd_not_running();
2542 }
2543 }
2544
2545 static uint32_t
2546 e1000e_mac_readreg(E1000ECore *core, int index)
2547 {
2548 return core->mac[index];
2549 }
2550
2551 static uint32_t
2552 e1000e_mac_ics_read(E1000ECore *core, int index)
2553 {
2554 trace_e1000e_irq_read_ics(core->mac[ICS]);
2555 return core->mac[ICS];
2556 }
2557
2558 static uint32_t
2559 e1000e_mac_ims_read(E1000ECore *core, int index)
2560 {
2561 trace_e1000e_irq_read_ims(core->mac[IMS]);
2562 return core->mac[IMS];
2563 }
2564
2565 #define E1000E_LOW_BITS_READ_FUNC(num) \
2566 static uint32_t \
2567 e1000e_mac_low##num##_read(E1000ECore *core, int index) \
2568 { \
2569 return core->mac[index] & (BIT(num) - 1); \
2570 } \
2571
2572 #define E1000E_LOW_BITS_READ(num) \
2573 e1000e_mac_low##num##_read
2574
2575 E1000E_LOW_BITS_READ_FUNC(4);
2576 E1000E_LOW_BITS_READ_FUNC(6);
2577 E1000E_LOW_BITS_READ_FUNC(11);
2578 E1000E_LOW_BITS_READ_FUNC(13);
2579 E1000E_LOW_BITS_READ_FUNC(16);
2580
2581 static uint32_t
2582 e1000e_mac_swsm_read(E1000ECore *core, int index)
2583 {
2584 uint32_t val = core->mac[SWSM];
2585 core->mac[SWSM] = val | 1;
2586 return val;
2587 }
2588
2589 static uint32_t
2590 e1000e_mac_itr_read(E1000ECore *core, int index)
2591 {
2592 return core->itr_guest_value;
2593 }
2594
2595 static uint32_t
2596 e1000e_mac_eitr_read(E1000ECore *core, int index)
2597 {
2598 return core->eitr_guest_value[index - EITR];
2599 }
2600
2601 static uint32_t
2602 e1000e_mac_icr_read(E1000ECore *core, int index)
2603 {
2604 uint32_t ret = core->mac[ICR];
2605 trace_e1000e_irq_icr_read_entry(ret);
2606
2607 if (core->mac[IMS] == 0) {
2608 trace_e1000e_irq_icr_clear_zero_ims();
2609 core->mac[ICR] = 0;
2610 }
2611
2612 if (!msix_enabled(core->owner)) {
2613 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2614 core->mac[ICR] = 0;
2615 }
2616
2617 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2618 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2619 trace_e1000e_irq_icr_clear_iame();
2620 core->mac[ICR] = 0;
2621 trace_e1000e_irq_icr_process_iame();
2622 e1000e_clear_ims_bits(core, core->mac[IAM]);
2623 }
2624
2625 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2626 e1000e_update_interrupt_state(core);
2627 return ret;
2628 }
2629
2630 static uint32_t
2631 e1000e_mac_read_clr4(E1000ECore *core, int index)
2632 {
2633 uint32_t ret = core->mac[index];
2634
2635 core->mac[index] = 0;
2636 return ret;
2637 }
2638
2639 static uint32_t
2640 e1000e_mac_read_clr8(E1000ECore *core, int index)
2641 {
2642 uint32_t ret = core->mac[index];
2643
2644 core->mac[index] = 0;
2645 core->mac[index - 1] = 0;
2646 return ret;
2647 }
2648
2649 static uint32_t
2650 e1000e_get_ctrl(E1000ECore *core, int index)
2651 {
2652 uint32_t val = core->mac[CTRL];
2653
2654 trace_e1000e_link_read_params(
2655 !!(val & E1000_CTRL_ASDE),
2656 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2657 !!(val & E1000_CTRL_FRCSPD),
2658 !!(val & E1000_CTRL_FRCDPX),
2659 !!(val & E1000_CTRL_RFCE),
2660 !!(val & E1000_CTRL_TFCE));
2661
2662 return val;
2663 }
2664
2665 static uint32_t
2666 e1000e_get_status(E1000ECore *core, int index)
2667 {
2668 uint32_t res = core->mac[STATUS];
2669
2670 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2671 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2672 }
2673
2674 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2675 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2676 } else {
2677 res |= E1000_STATUS_FD;
2678 }
2679
2680 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2681 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2682 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2683 case E1000_CTRL_SPD_10:
2684 res |= E1000_STATUS_SPEED_10;
2685 break;
2686 case E1000_CTRL_SPD_100:
2687 res |= E1000_STATUS_SPEED_100;
2688 break;
2689 case E1000_CTRL_SPD_1000:
2690 default:
2691 res |= E1000_STATUS_SPEED_1000;
2692 break;
2693 }
2694 } else {
2695 res |= E1000_STATUS_SPEED_1000;
2696 }
2697
2698 trace_e1000e_link_status(
2699 !!(res & E1000_STATUS_LU),
2700 !!(res & E1000_STATUS_FD),
2701 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2702 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2703
2704 return res;
2705 }
2706
2707 static uint32_t
2708 e1000e_get_tarc(E1000ECore *core, int index)
2709 {
2710 return core->mac[index] & ((BIT(11) - 1) |
2711 BIT(27) |
2712 BIT(28) |
2713 BIT(29) |
2714 BIT(30));
2715 }
2716
2717 static void
2718 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2719 {
2720 core->mac[index] = val;
2721 }
2722
2723 static void
2724 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2725 {
2726 uint32_t macaddr[2];
2727
2728 core->mac[index] = val;
2729
2730 macaddr[0] = cpu_to_le32(core->mac[RA]);
2731 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2732 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2733 (uint8_t *) macaddr);
2734
2735 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2736 }
2737
2738 static void
2739 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2740 {
2741 static const uint32_t ro_bits = E1000_EECD_PRES |
2742 E1000_EECD_AUTO_RD |
2743 E1000_EECD_SIZE_EX_MASK;
2744
2745 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2746 }
2747
2748 static void
2749 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2750 {
2751 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2752 uint32_t flags = 0;
2753 uint32_t data = 0;
2754
2755 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2756 data = core->eeprom[addr];
2757 flags = E1000_EERW_DONE;
2758 }
2759
2760 core->mac[EERD] = flags |
2761 (addr << E1000_EERW_ADDR_SHIFT) |
2762 (data << E1000_EERW_DATA_SHIFT);
2763 }
2764
2765 static void
2766 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2767 {
2768 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2769 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2770 uint32_t flags = 0;
2771
2772 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2773 core->eeprom[addr] = data;
2774 flags = E1000_EERW_DONE;
2775 }
2776
2777 core->mac[EERD] = flags |
2778 (addr << E1000_EERW_ADDR_SHIFT) |
2779 (data << E1000_EERW_DATA_SHIFT);
2780 }
2781
2782 static void
2783 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2784 {
2785 core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2786 }
2787
2788 static void
2789 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2790 {
2791 uint32_t interval = val & 0xffff;
2792
2793 trace_e1000e_irq_itr_set(val);
2794
2795 core->itr_guest_value = interval;
2796 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2797 }
2798
2799 static void
2800 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2801 {
2802 uint32_t interval = val & 0xffff;
2803 uint32_t eitr_num = index - EITR;
2804
2805 trace_e1000e_irq_eitr_set(eitr_num, val);
2806
2807 core->eitr_guest_value[eitr_num] = interval;
2808 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2809 }
2810
2811 static void
2812 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2813 {
2814 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) {
2815
2816 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2817 qemu_log_mask(LOG_GUEST_ERROR,
2818 "e1000e: PSRCTL.BSIZE0 cannot be zero");
2819 return;
2820 }
2821
2822 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2823 qemu_log_mask(LOG_GUEST_ERROR,
2824 "e1000e: PSRCTL.BSIZE1 cannot be zero");
2825 return;
2826 }
2827 }
2828
2829 core->mac[PSRCTL] = val;
2830 }
2831
2832 static void
2833 e1000e_update_rx_offloads(E1000ECore *core)
2834 {
2835 int cso_state = e1000e_rx_l4_cso_enabled(core);
2836
2837 trace_e1000e_rx_set_cso(cso_state);
2838
2839 if (core->has_vnet) {
2840 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2841 cso_state, 0, 0, 0, 0);
2842 }
2843 }
2844
2845 static void
2846 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2847 {
2848 core->mac[RXCSUM] = val;
2849 e1000e_update_rx_offloads(core);
2850 }
2851
2852 static void
2853 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2854 {
2855 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2856 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2857 }
2858
2859 #define e1000e_getreg(x) [x] = e1000e_mac_readreg
2860 typedef uint32_t (*readops)(E1000ECore *, int);
2861 static const readops e1000e_macreg_readops[] = {
2862 e1000e_getreg(PBA),
2863 e1000e_getreg(WUFC),
2864 e1000e_getreg(MANC),
2865 e1000e_getreg(TOTL),
2866 e1000e_getreg(RDT0),
2867 e1000e_getreg(RDBAH0),
2868 e1000e_getreg(TDBAL1),
2869 e1000e_getreg(RDLEN0),
2870 e1000e_getreg(RDH1),
2871 e1000e_getreg(LATECOL),
2872 e1000e_getreg(SEQEC),
2873 e1000e_getreg(XONTXC),
2874 e1000e_getreg(WUS),
2875 e1000e_getreg(GORCL),
2876 e1000e_getreg(MGTPRC),
2877 e1000e_getreg(EERD),
2878 e1000e_getreg(EIAC),
2879 e1000e_getreg(PSRCTL),
2880 e1000e_getreg(MANC2H),
2881 e1000e_getreg(RXCSUM),
2882 e1000e_getreg(GSCL_3),
2883 e1000e_getreg(GSCN_2),
2884 e1000e_getreg(RSRPD),
2885 e1000e_getreg(RDBAL1),
2886 e1000e_getreg(FCAH),
2887 e1000e_getreg(FCRTH),
2888 e1000e_getreg(FLOP),
2889 e1000e_getreg(FLASHT),
2890 e1000e_getreg(RXSTMPH),
2891 e1000e_getreg(TXSTMPL),
2892 e1000e_getreg(TIMADJL),
2893 e1000e_getreg(TXDCTL),
2894 e1000e_getreg(RDH0),
2895 e1000e_getreg(TDT1),
2896 e1000e_getreg(TNCRS),
2897 e1000e_getreg(RJC),
2898 e1000e_getreg(IAM),
2899 e1000e_getreg(GSCL_2),
2900 e1000e_getreg(RDBAH1),
2901 e1000e_getreg(FLSWDATA),
2902 e1000e_getreg(RXSATRH),
2903 e1000e_getreg(TIPG),
2904 e1000e_getreg(FLMNGCTL),
2905 e1000e_getreg(FLMNGCNT),
2906 e1000e_getreg(TSYNCTXCTL),
2907 e1000e_getreg(EXTCNF_SIZE),
2908 e1000e_getreg(EXTCNF_CTRL),
2909 e1000e_getreg(EEMNGDATA),
2910 e1000e_getreg(CTRL_EXT),
2911 e1000e_getreg(SYSTIMH),
2912 e1000e_getreg(EEMNGCTL),
2913 e1000e_getreg(FLMNGDATA),
2914 e1000e_getreg(TSYNCRXCTL),
2915 e1000e_getreg(TDH),
2916 e1000e_getreg(LEDCTL),
2917 e1000e_getreg(TCTL),
2918 e1000e_getreg(TDBAL),
2919 e1000e_getreg(TDLEN),
2920 e1000e_getreg(TDH1),
2921 e1000e_getreg(RADV),
2922 e1000e_getreg(ECOL),
2923 e1000e_getreg(DC),
2924 e1000e_getreg(RLEC),
2925 e1000e_getreg(XOFFTXC),
2926 e1000e_getreg(RFC),
2927 e1000e_getreg(RNBC),
2928 e1000e_getreg(MGTPTC),
2929 e1000e_getreg(TIMINCA),
2930 e1000e_getreg(RXCFGL),
2931 e1000e_getreg(MFUTP01),
2932 e1000e_getreg(FACTPS),
2933 e1000e_getreg(GSCL_1),
2934 e1000e_getreg(GSCN_0),
2935 e1000e_getreg(GCR2),
2936 e1000e_getreg(RDT1),
2937 e1000e_getreg(PBACLR),
2938 e1000e_getreg(FCTTV),
2939 e1000e_getreg(EEWR),
2940 e1000e_getreg(FLSWCTL),
2941 e1000e_getreg(RXDCTL1),
2942 e1000e_getreg(RXSATRL),
2943 e1000e_getreg(SYSTIML),
2944 e1000e_getreg(RXUDP),
2945 e1000e_getreg(TORL),
2946 e1000e_getreg(TDLEN1),
2947 e1000e_getreg(MCC),
2948 e1000e_getreg(WUC),
2949 e1000e_getreg(EECD),
2950 e1000e_getreg(MFUTP23),
2951 e1000e_getreg(RAID),
2952 e1000e_getreg(FCRTV),
2953 e1000e_getreg(TXDCTL1),
2954 e1000e_getreg(RCTL),
2955 e1000e_getreg(TDT),
2956 e1000e_getreg(MDIC),
2957 e1000e_getreg(FCRUC),
2958 e1000e_getreg(VET),
2959 e1000e_getreg(RDBAL0),
2960 e1000e_getreg(TDBAH1),
2961 e1000e_getreg(RDTR),
2962 e1000e_getreg(SCC),
2963 e1000e_getreg(COLC),
2964 e1000e_getreg(CEXTERR),
2965 e1000e_getreg(XOFFRXC),
2966 e1000e_getreg(IPAV),
2967 e1000e_getreg(GOTCL),
2968 e1000e_getreg(MGTPDC),
2969 e1000e_getreg(GCR),
2970 e1000e_getreg(IVAR),
2971 e1000e_getreg(POEMB),
2972 e1000e_getreg(MFVAL),
2973 e1000e_getreg(FUNCTAG),
2974 e1000e_getreg(GSCL_4),
2975 e1000e_getreg(GSCN_3),
2976 e1000e_getreg(MRQC),
2977 e1000e_getreg(RDLEN1),
2978 e1000e_getreg(FCT),
2979 e1000e_getreg(FLA),
2980 e1000e_getreg(FLOL),
2981 e1000e_getreg(RXDCTL),
2982 e1000e_getreg(RXSTMPL),
2983 e1000e_getreg(TXSTMPH),
2984 e1000e_getreg(TIMADJH),
2985 e1000e_getreg(FCRTL),
2986 e1000e_getreg(TDBAH),
2987 e1000e_getreg(TADV),
2988 e1000e_getreg(XONRXC),
2989 e1000e_getreg(TSCTFC),
2990 e1000e_getreg(RFCTL),
2991 e1000e_getreg(GSCN_1),
2992 e1000e_getreg(FCAL),
2993 e1000e_getreg(FLSWCNT),
2994
2995 [TOTH] = e1000e_mac_read_clr8,
2996 [GOTCH] = e1000e_mac_read_clr8,
2997 [PRC64] = e1000e_mac_read_clr4,
2998 [PRC255] = e1000e_mac_read_clr4,
2999 [PRC1023] = e1000e_mac_read_clr4,
3000 [PTC64] = e1000e_mac_read_clr4,
3001 [PTC255] = e1000e_mac_read_clr4,
3002 [PTC1023] = e1000e_mac_read_clr4,
3003 [GPRC] = e1000e_mac_read_clr4,
3004 [TPT] = e1000e_mac_read_clr4,
3005 [RUC] = e1000e_mac_read_clr4,
3006 [BPRC] = e1000e_mac_read_clr4,
3007 [MPTC] = e1000e_mac_read_clr4,
3008 [IAC] = e1000e_mac_read_clr4,
3009 [ICR] = e1000e_mac_icr_read,
3010 [RDFH] = E1000E_LOW_BITS_READ(13),
3011 [RDFHS] = E1000E_LOW_BITS_READ(13),
3012 [RDFPC] = E1000E_LOW_BITS_READ(13),
3013 [TDFH] = E1000E_LOW_BITS_READ(13),
3014 [TDFHS] = E1000E_LOW_BITS_READ(13),
3015 [STATUS] = e1000e_get_status,
3016 [TARC0] = e1000e_get_tarc,
3017 [PBS] = E1000E_LOW_BITS_READ(6),
3018 [ICS] = e1000e_mac_ics_read,
3019 [AIT] = E1000E_LOW_BITS_READ(16),
3020 [TORH] = e1000e_mac_read_clr8,
3021 [GORCH] = e1000e_mac_read_clr8,
3022 [PRC127] = e1000e_mac_read_clr4,
3023 [PRC511] = e1000e_mac_read_clr4,
3024 [PRC1522] = e1000e_mac_read_clr4,
3025 [PTC127] = e1000e_mac_read_clr4,
3026 [PTC511] = e1000e_mac_read_clr4,
3027 [PTC1522] = e1000e_mac_read_clr4,
3028 [GPTC] = e1000e_mac_read_clr4,
3029 [TPR] = e1000e_mac_read_clr4,
3030 [ROC] = e1000e_mac_read_clr4,
3031 [MPRC] = e1000e_mac_read_clr4,
3032 [BPTC] = e1000e_mac_read_clr4,
3033 [TSCTC] = e1000e_mac_read_clr4,
3034 [ITR] = e1000e_mac_itr_read,
3035 [RDFT] = E1000E_LOW_BITS_READ(13),
3036 [RDFTS] = E1000E_LOW_BITS_READ(13),
3037 [TDFPC] = E1000E_LOW_BITS_READ(13),
3038 [TDFT] = E1000E_LOW_BITS_READ(13),
3039 [TDFTS] = E1000E_LOW_BITS_READ(13),
3040 [CTRL] = e1000e_get_ctrl,
3041 [TARC1] = e1000e_get_tarc,
3042 [SWSM] = e1000e_mac_swsm_read,
3043 [IMS] = e1000e_mac_ims_read,
3044
3045 [CRCERRS ... MPC] = e1000e_mac_readreg,
3046 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg,
3047 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg,
3048 [RA ... RA + 31] = e1000e_mac_readreg,
3049 [WUPM ... WUPM + 31] = e1000e_mac_readreg,
3050 [MTA ... MTA + 127] = e1000e_mac_readreg,
3051 [VFTA ... VFTA + 127] = e1000e_mac_readreg,
3052 [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4),
3053 [FFVT ... FFVT + 254] = e1000e_mac_readreg,
3054 [MDEF ... MDEF + 7] = e1000e_mac_readreg,
3055 [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11),
3056 [FTFT ... FTFT + 254] = e1000e_mac_readreg,
3057 [PBM ... PBM + 10239] = e1000e_mac_readreg,
3058 [RETA ... RETA + 31] = e1000e_mac_readreg,
3059 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3060 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg,
3061 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3062 };
3063 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3064
3065 #define e1000e_putreg(x) [x] = e1000e_mac_writereg
3066 typedef void (*writeops)(E1000ECore *, int, uint32_t);
3067 static const writeops e1000e_macreg_writeops[] = {
3068 e1000e_putreg(PBA),
3069 e1000e_putreg(SWSM),
3070 e1000e_putreg(WUFC),
3071 e1000e_putreg(RDBAH1),
3072 e1000e_putreg(TDBAH),
3073 e1000e_putreg(TXDCTL),
3074 e1000e_putreg(RDBAH0),
3075 e1000e_putreg(LEDCTL),
3076 e1000e_putreg(FCAL),
3077 e1000e_putreg(FCRUC),
3078 e1000e_putreg(AIT),
3079 e1000e_putreg(TDFH),
3080 e1000e_putreg(TDFT),
3081 e1000e_putreg(TDFHS),
3082 e1000e_putreg(TDFTS),
3083 e1000e_putreg(TDFPC),
3084 e1000e_putreg(WUC),
3085 e1000e_putreg(WUS),
3086 e1000e_putreg(RDFH),
3087 e1000e_putreg(RDFT),
3088 e1000e_putreg(RDFHS),
3089 e1000e_putreg(RDFTS),
3090 e1000e_putreg(RDFPC),
3091 e1000e_putreg(IPAV),
3092 e1000e_putreg(TDBAH1),
3093 e1000e_putreg(TIMINCA),
3094 e1000e_putreg(IAM),
3095 e1000e_putreg(EIAC),
3096 e1000e_putreg(IVAR),
3097 e1000e_putreg(TARC0),
3098 e1000e_putreg(TARC1),
3099 e1000e_putreg(FLSWDATA),
3100 e1000e_putreg(POEMB),
3101 e1000e_putreg(PBS),
3102 e1000e_putreg(MFUTP01),
3103 e1000e_putreg(MFUTP23),
3104 e1000e_putreg(MANC),
3105 e1000e_putreg(MANC2H),
3106 e1000e_putreg(MFVAL),
3107 e1000e_putreg(EXTCNF_CTRL),
3108 e1000e_putreg(FACTPS),
3109 e1000e_putreg(FUNCTAG),
3110 e1000e_putreg(GSCL_1),
3111 e1000e_putreg(GSCL_2),
3112 e1000e_putreg(GSCL_3),
3113 e1000e_putreg(GSCL_4),
3114 e1000e_putreg(GSCN_0),
3115 e1000e_putreg(GSCN_1),
3116 e1000e_putreg(GSCN_2),
3117 e1000e_putreg(GSCN_3),
3118 e1000e_putreg(GCR2),
3119 e1000e_putreg(MRQC),
3120 e1000e_putreg(FLOP),
3121 e1000e_putreg(FLOL),
3122 e1000e_putreg(FLSWCTL),
3123 e1000e_putreg(FLSWCNT),
3124 e1000e_putreg(FLA),
3125 e1000e_putreg(RXDCTL1),
3126 e1000e_putreg(TXDCTL1),
3127 e1000e_putreg(TIPG),
3128 e1000e_putreg(RXSTMPH),
3129 e1000e_putreg(RXSTMPL),
3130 e1000e_putreg(RXSATRL),
3131 e1000e_putreg(RXSATRH),
3132 e1000e_putreg(TXSTMPL),
3133 e1000e_putreg(TXSTMPH),
3134 e1000e_putreg(SYSTIML),
3135 e1000e_putreg(SYSTIMH),
3136 e1000e_putreg(TIMADJL),
3137 e1000e_putreg(TIMADJH),
3138 e1000e_putreg(RXUDP),
3139 e1000e_putreg(RXCFGL),
3140 e1000e_putreg(TSYNCRXCTL),
3141 e1000e_putreg(TSYNCTXCTL),
3142 e1000e_putreg(EXTCNF_SIZE),
3143 e1000e_putreg(EEMNGCTL),
3144 e1000e_putreg(RA),
3145
3146 [TDH1] = e1000e_set_16bit,
3147 [TDT1] = e1000e_set_tdt,
3148 [TCTL] = e1000e_set_tctl,
3149 [TDT] = e1000e_set_tdt,
3150 [MDIC] = e1000e_set_mdic,
3151 [ICS] = e1000e_set_ics,
3152 [TDH] = e1000e_set_16bit,
3153 [RDH0] = e1000e_set_16bit,
3154 [RDT0] = e1000e_set_rdt,
3155 [IMC] = e1000e_set_imc,
3156 [IMS] = e1000e_set_ims,
3157 [ICR] = e1000e_set_icr,
3158 [EECD] = e1000e_set_eecd,
3159 [RCTL] = e1000e_set_rx_control,
3160 [CTRL] = e1000e_set_ctrl,
3161 [RDTR] = e1000e_set_rdtr,
3162 [RADV] = e1000e_set_16bit,
3163 [TADV] = e1000e_set_16bit,
3164 [ITR] = e1000e_set_itr,
3165 [EERD] = e1000e_set_eerd,
3166 [GCR] = e1000e_set_gcr,
3167 [PSRCTL] = e1000e_set_psrctl,
3168 [RXCSUM] = e1000e_set_rxcsum,
3169 [RAID] = e1000e_set_16bit,
3170 [RSRPD] = e1000e_set_12bit,
3171 [TIDV] = e1000e_set_tidv,
3172 [TDLEN1] = e1000e_set_dlen,
3173 [TDLEN] = e1000e_set_dlen,
3174 [RDLEN0] = e1000e_set_dlen,
3175 [RDLEN1] = e1000e_set_dlen,
3176 [TDBAL] = e1000e_set_dbal,
3177 [TDBAL1] = e1000e_set_dbal,
3178 [RDBAL0] = e1000e_set_dbal,
3179 [RDBAL1] = e1000e_set_dbal,
3180 [RDH1] = e1000e_set_16bit,
3181 [RDT1] = e1000e_set_rdt,
3182 [STATUS] = e1000e_set_status,
3183 [PBACLR] = e1000e_set_pbaclr,
3184 [CTRL_EXT] = e1000e_set_ctrlext,
3185 [FCAH] = e1000e_set_16bit,
3186 [FCT] = e1000e_set_16bit,
3187 [FCTTV] = e1000e_set_16bit,
3188 [FCRTV] = e1000e_set_16bit,
3189 [FCRTH] = e1000e_set_fcrth,
3190 [FCRTL] = e1000e_set_fcrtl,
3191 [VET] = e1000e_set_vet,
3192 [RXDCTL] = e1000e_set_rxdctl,
3193 [FLASHT] = e1000e_set_16bit,
3194 [EEWR] = e1000e_set_eewr,
3195 [CTRL_DUP] = e1000e_set_ctrl,
3196 [RFCTL] = e1000e_set_rfctl,
3197 [RA + 1] = e1000e_mac_setmacaddr,
3198
3199 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg,
3200 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg,
3201 [RA + 2 ... RA + 31] = e1000e_mac_writereg,
3202 [WUPM ... WUPM + 31] = e1000e_mac_writereg,
3203 [MTA ... MTA + 127] = e1000e_mac_writereg,
3204 [VFTA ... VFTA + 127] = e1000e_mac_writereg,
3205 [FFMT ... FFMT + 254] = e1000e_mac_writereg,
3206 [FFVT ... FFVT + 254] = e1000e_mac_writereg,
3207 [PBM ... PBM + 10239] = e1000e_mac_writereg,
3208 [MDEF ... MDEF + 7] = e1000e_mac_writereg,
3209 [FFLT ... FFLT + 10] = e1000e_mac_writereg,
3210 [FTFT ... FTFT + 254] = e1000e_mac_writereg,
3211 [RETA ... RETA + 31] = e1000e_mac_writereg,
3212 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
3213 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg,
3214 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3215 };
3216 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3217
3218 enum { MAC_ACCESS_PARTIAL = 1 };
3219
3220 /* The array below combines alias offsets of the index values for the
3221 * MAC registers that have aliases, with the indication of not fully
3222 * implemented registers (lowest bit). This combination is possible
3223 * because all of the offsets are even. */
3224 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3225 /* Alias index offsets */
3226 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3227 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6,
3228 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3229 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8,
3230 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3231 [RA_A ... RA_A + 31] = 0x14f0,
3232 [VFTA_A ... VFTA_A + 127] = 0x1400,
3233 [RDBAL0_A ... RDLEN0_A] = 0x09bc,
3234 [TDBAL_A ... TDLEN_A] = 0x0cf8,
3235 /* Access options */
3236 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3237 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3238 [RDFPC] = MAC_ACCESS_PARTIAL,
3239 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3240 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3241 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3242 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL,
3243 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3244 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3245 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3246 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL,
3247 [TXDCTL1] = MAC_ACCESS_PARTIAL,
3248 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3249 };
3250
3251 void
3252 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3253 {
3254 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3255
3256 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3257 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3258 trace_e1000e_wrn_regs_write_trivial(index << 2);
3259 }
3260 trace_e1000e_core_write(index << 2, size, val);
3261 e1000e_macreg_writeops[index](core, index, val);
3262 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3263 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3264 } else {
3265 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3266 }
3267 }
3268
3269 uint64_t
3270 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3271 {
3272 uint64_t val;
3273 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3274
3275 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3276 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3277 trace_e1000e_wrn_regs_read_trivial(index << 2);
3278 }
3279 val = e1000e_macreg_readops[index](core, index);
3280 trace_e1000e_core_read(index << 2, size, val);
3281 return val;
3282 } else {
3283 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3284 }
3285 return 0;
3286 }
3287
3288 static inline void
3289 e1000e_autoneg_pause(E1000ECore *core)
3290 {
3291 timer_del(core->autoneg_timer);
3292 }
3293
3294 static void
3295 e1000e_autoneg_resume(E1000ECore *core)
3296 {
3297 if (e1000e_have_autoneg(core) &&
3298 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
3299 qemu_get_queue(core->owner_nic)->link_down = false;
3300 timer_mod(core->autoneg_timer,
3301 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3302 }
3303 }
3304
3305 static void
3306 e1000e_vm_state_change(void *opaque, bool running, RunState state)
3307 {
3308 E1000ECore *core = opaque;
3309
3310 if (running) {
3311 trace_e1000e_vm_state_running();
3312 e1000e_intrmgr_resume(core);
3313 e1000e_autoneg_resume(core);
3314 } else {
3315 trace_e1000e_vm_state_stopped();
3316 e1000e_autoneg_pause(core);
3317 e1000e_intrmgr_pause(core);
3318 }
3319 }
3320
3321 void
3322 e1000e_core_pci_realize(E1000ECore *core,
3323 const uint16_t *eeprom_templ,
3324 uint32_t eeprom_size,
3325 const uint8_t *macaddr)
3326 {
3327 int i;
3328
3329 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3330 e1000e_autoneg_timer, core);
3331 e1000e_intrmgr_pci_realize(core);
3332
3333 core->vmstate =
3334 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);
3335
3336 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3337 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner,
3338 E1000E_MAX_TX_FRAGS, core->has_vnet);
3339 }
3340
3341 net_rx_pkt_init(&core->rx_pkt, core->has_vnet);
3342
3343 e1000x_core_prepare_eeprom(core->eeprom,
3344 eeprom_templ,
3345 eeprom_size,
3346 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3347 macaddr);
3348 e1000e_update_rx_offloads(core);
3349 }
3350
3351 void
3352 e1000e_core_pci_uninit(E1000ECore *core)
3353 {
3354 int i;
3355
3356 timer_free(core->autoneg_timer);
3357
3358 e1000e_intrmgr_pci_unint(core);
3359
3360 qemu_del_vm_change_state_handler(core->vmstate);
3361
3362 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3363 net_tx_pkt_reset(core->tx[i].tx_pkt);
3364 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3365 }
3366
3367 net_rx_pkt_uninit(core->rx_pkt);
3368 }
3369
3370 static const uint16_t
3371 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3372 [0] = {
3373 [PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
3374 MII_CR_FULL_DUPLEX |
3375 MII_CR_AUTO_NEG_EN,
3376
3377 [PHY_STATUS] = MII_SR_EXTENDED_CAPS |
3378 MII_SR_LINK_STATUS |
3379 MII_SR_AUTONEG_CAPS |
3380 MII_SR_PREAMBLE_SUPPRESS |
3381 MII_SR_EXTENDED_STATUS |
3382 MII_SR_10T_HD_CAPS |
3383 MII_SR_10T_FD_CAPS |
3384 MII_SR_100X_HD_CAPS |
3385 MII_SR_100X_FD_CAPS,
3386
3387 [PHY_ID1] = 0x141,
3388 [PHY_ID2] = E1000_PHY_ID2_82574x,
3389 [PHY_AUTONEG_ADV] = 0xde1,
3390 [PHY_LP_ABILITY] = 0x7e0,
3391 [PHY_AUTONEG_EXP] = BIT(2),
3392 [PHY_NEXT_PAGE_TX] = BIT(0) | BIT(13),
3393 [PHY_1000T_CTRL] = BIT(8) | BIT(9) | BIT(10) | BIT(11),
3394 [PHY_1000T_STATUS] = 0x3c00,
3395 [PHY_EXT_STATUS] = BIT(12) | BIT(13),
3396
3397 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) |
3398 BIT(12) | BIT(13),
3399 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15)
3400 },
3401 [2] = {
3402 [PHY_MAC_CTRL1] = BIT(3) | BIT(7),
3403 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12)
3404 },
3405 [3] = {
3406 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14)
3407 }
3408 };
3409
3410 static const uint32_t e1000e_mac_reg_init[] = {
3411 [PBA] = 0x00140014,
3412 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),
3413 [EXTCNF_CTRL] = BIT(3),
3414 [EEMNGCTL] = BIT(31),
3415 [FLASHT] = 0x2,
3416 [FLSWCTL] = BIT(30) | BIT(31),
3417 [FLOL] = BIT(0),
3418 [RXDCTL] = BIT(16),
3419 [RXDCTL1] = BIT(16),
3420 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20),
3421 [RXCFGL] = 0x88F7,
3422 [RXUDP] = 0x319,
3423 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
3424 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU |
3425 E1000_CTRL_ADVD3WUC,
3426 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU,
3427 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) |
3428 (4 << E1000_PSRCTL_BSIZE1_SHIFT) |
3429 (4 << E1000_PSRCTL_BSIZE2_SHIFT),
3430 [TARC0] = 0x3 | E1000_TARC_ENABLE,
3431 [TARC1] = 0x3 | E1000_TARC_ENABLE,
3432 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES,
3433 [EERD] = E1000_EERW_DONE,
3434 [EEWR] = E1000_EERW_DONE,
3435 [GCR] = E1000_L0S_ADJUST |
3436 E1000_L1_ENTRY_LATENCY_MSB |
3437 E1000_L1_ENTRY_LATENCY_LSB,
3438 [TDFH] = 0x600,
3439 [TDFT] = 0x600,
3440 [TDFHS] = 0x600,
3441 [TDFTS] = 0x600,
3442 [POEMB] = 0x30D,
3443 [PBS] = 0x028,
3444 [MANC] = E1000_MANC_DIS_IP_CHK_ARP,
3445 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000,
3446 [SWSM] = 1,
3447 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
3448 [ITR] = E1000E_MIN_XITR,
3449 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3450 };
3451
3452 void
3453 e1000e_core_reset(E1000ECore *core)
3454 {
3455 int i;
3456
3457 timer_del(core->autoneg_timer);
3458
3459 e1000e_intrmgr_reset(core);
3460
3461 memset(core->phy, 0, sizeof core->phy);
3462 memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3463 memset(core->mac, 0, sizeof core->mac);
3464 memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init);
3465
3466 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3467
3468 if (qemu_get_queue(core->owner_nic)->link_down) {
3469 e1000e_link_down(core);
3470 }
3471
3472 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3473
3474 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3475 net_tx_pkt_reset(core->tx[i].tx_pkt);
3476 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3477 core->tx[i].skip_cp = false;
3478 }
3479 }
3480
3481 void e1000e_core_pre_save(E1000ECore *core)
3482 {
3483 int i;
3484 NetClientState *nc = qemu_get_queue(core->owner_nic);
3485
3486 /*
3487 * If link is down and auto-negotiation is supported and ongoing,
3488 * complete auto-negotiation immediately. This allows us to look
3489 * at MII_SR_AUTONEG_COMPLETE to infer link status on load.
3490 */
3491 if (nc->link_down && e1000e_have_autoneg(core)) {
3492 core->phy[0][PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
3493 e1000e_update_flowctl_status(core);
3494 }
3495
3496 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3497 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3498 core->tx[i].skip_cp = true;
3499 }
3500 }
3501 }
3502
3503 int
3504 e1000e_core_post_load(E1000ECore *core)
3505 {
3506 NetClientState *nc = qemu_get_queue(core->owner_nic);
3507
3508 /* nc.link_down can't be migrated, so infer link_down according
3509 * to link status bit in core.mac[STATUS].
3510 */
3511 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3512
3513 return 0;
3514 }
AR7 emulation for QEMU