hw/net/e1000e.c

   1 /*
   2 * QEMU INTEL 82574 GbE NIC emulation
   3 *
   4 * Software developer's manuals:
   5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
   6 *
   7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   8 * Developed by Daynix Computing LTD (http://www.daynix.com)
   9 *
  10 * Authors:
  11 * Dmitry Fleytman <dmitry@daynix.com>
  12 * Leonid Bloch <leonid@daynix.com>
  13 * Yan Vugenfirer <yan@daynix.com>
  14 *
  15 * Based on work done by:
  16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
  17 * Copyright (c) 2008 Qumranet
  18 * Based on work done by:
  19 * Copyright (c) 2007 Dan Aloni
  20 * Copyright (c) 2004 Antony T Curtis
  21 *
  22 * This library is free software; you can redistribute it and/or
  23 * modify it under the terms of the GNU Lesser General Public
  24 * License as published by the Free Software Foundation; either
  25 * version 2.1 of the License, or (at your option) any later version.
  26 *
  27 * This library is distributed in the hope that it will be useful,
  28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  30 * Lesser General Public License for more details.
  31 *
  32 * You should have received a copy of the GNU Lesser General Public
  33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  34 */
  35
  36 #include "qemu/osdep.h"
  37 #include "qemu/units.h"
  38 #include "net/eth.h"
  39 #include "net/net.h"
  40 #include "net/tap.h"
  41 #include "qemu/module.h"
  42 #include "qemu/range.h"
  43 #include "sysemu/sysemu.h"
  44 #include "hw/hw.h"
  45 #include "hw/pci/msi.h"
  46 #include "hw/pci/msix.h"
  47 #include "hw/qdev-properties.h"
  48 #include "migration/vmstate.h"
  49
  50 #include "e1000_regs.h"
  51
  52 #include "e1000x_common.h"
  53 #include "e1000e_core.h"
  54
  55 #include "trace.h"
  56 #include "qapi/error.h"
  57 #include "qom/object.h"
  58
  59 #define TYPE_E1000E "e1000e"
  60 OBJECT_DECLARE_SIMPLE_TYPE(E1000EState, E1000E)
  61
  62 struct E1000EState {
  63     PCIDevice parent_obj;
  64     NICState *nic;
  65     NICConf conf;
  66
  67     MemoryRegion mmio;
  68     MemoryRegion flash;
  69     MemoryRegion io;
  70     MemoryRegion msix;
  71
  72     uint32_t ioaddr;
  73
  74     uint16_t subsys_ven;
  75     uint16_t subsys;
  76
  77     uint16_t subsys_ven_used;
  78     uint16_t subsys_used;
  79
  80     bool disable_vnet;
  81
  82     E1000ECore core;
  83     bool init_vet;
  84 };
  85
  86 #define E1000E_MMIO_IDX     0
  87 #define E1000E_FLASH_IDX    1
  88 #define E1000E_IO_IDX       2
  89 #define E1000E_MSIX_IDX     3
  90
  91 #define E1000E_MMIO_SIZE    (128 * KiB)
  92 #define E1000E_FLASH_SIZE   (128 * KiB)
  93 #define E1000E_IO_SIZE      (32)
  94 #define E1000E_MSIX_SIZE    (16 * KiB)
  95
  96 #define E1000E_MSIX_TABLE   (0x0000)
  97 #define E1000E_MSIX_PBA     (0x2000)
  98
  99 static uint64_t
 100 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
 101 {
 102     E1000EState *s = opaque;
 103     return e1000e_core_read(&s->core, addr, size);
 104 }
 105
 106 static void
 107 e1000e_mmio_write(void *opaque, hwaddr addr,
 108                    uint64_t val, unsigned size)
 109 {
 110     E1000EState *s = opaque;
 111     e1000e_core_write(&s->core, addr, val, size);
 112 }
 113
 114 static bool
 115 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
 116 {
 117     if (s->ioaddr < 0x1FFFF) {
 118         *idx = s->ioaddr;
 119         return true;
 120     }
 121
 122     if (s->ioaddr < 0x7FFFF) {
 123         trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
 124         return false;
 125     }
 126
 127     if (s->ioaddr < 0xFFFFF) {
 128         trace_e1000e_wrn_io_addr_flash(s->ioaddr);
 129         return false;
 130     }
 131
 132     trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
 133     return false;
 134 }
 135
 136 static uint64_t
 137 e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
 138 {
 139     E1000EState *s = opaque;
 140     uint32_t idx = 0;
 141     uint64_t val;
 142
 143     switch (addr) {
 144     case E1000_IOADDR:
 145         trace_e1000e_io_read_addr(s->ioaddr);
 146         return s->ioaddr;
 147     case E1000_IODATA:
 148         if (e1000e_io_get_reg_index(s, &idx)) {
 149             val = e1000e_core_read(&s->core, idx, sizeof(val));
 150             trace_e1000e_io_read_data(idx, val);
 151             return val;
 152         }
 153         return 0;
 154     default:
 155         trace_e1000e_wrn_io_read_unknown(addr);
 156         return 0;
 157     }
 158 }
 159
 160 static void
 161 e1000e_io_write(void *opaque, hwaddr addr,
 162                 uint64_t val, unsigned size)
 163 {
 164     E1000EState *s = opaque;
 165     uint32_t idx = 0;
 166
 167     switch (addr) {
 168     case E1000_IOADDR:
 169         trace_e1000e_io_write_addr(val);
 170         s->ioaddr = (uint32_t) val;
 171         return;
 172     case E1000_IODATA:
 173         if (e1000e_io_get_reg_index(s, &idx)) {
 174             trace_e1000e_io_write_data(idx, val);
 175             e1000e_core_write(&s->core, idx, val, sizeof(val));
 176         }
 177         return;
 178     default:
 179         trace_e1000e_wrn_io_write_unknown(addr);
 180         return;
 181     }
 182 }
 183
 184 static const MemoryRegionOps mmio_ops = {
 185     .read = e1000e_mmio_read,
 186     .write = e1000e_mmio_write,
 187     .endianness = DEVICE_LITTLE_ENDIAN,
 188     .impl = {
 189         .min_access_size = 4,
 190         .max_access_size = 4,
 191     },
 192 };
 193
 194 static const MemoryRegionOps io_ops = {
 195     .read = e1000e_io_read,
 196     .write = e1000e_io_write,
 197     .endianness = DEVICE_LITTLE_ENDIAN,
 198     .impl = {
 199         .min_access_size = 4,
 200         .max_access_size = 4,
 201     },
 202 };
 203
 204 static bool
 205 e1000e_nc_can_receive(NetClientState *nc)
 206 {
 207     E1000EState *s = qemu_get_nic_opaque(nc);
 208     return e1000e_can_receive(&s->core);
 209 }
 210
 211 static ssize_t
 212 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
 213 {
 214     E1000EState *s = qemu_get_nic_opaque(nc);
 215     return e1000e_receive_iov(&s->core, iov, iovcnt);
 216 }
 217
 218 static ssize_t
 219 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 220 {
 221     E1000EState *s = qemu_get_nic_opaque(nc);
 222     return e1000e_receive(&s->core, buf, size);
 223 }
 224
 225 static void
 226 e1000e_set_link_status(NetClientState *nc)
 227 {
 228     E1000EState *s = qemu_get_nic_opaque(nc);
 229     e1000e_core_set_link_status(&s->core);
 230 }
 231
 232 static NetClientInfo net_e1000e_info = {
 233     .type = NET_CLIENT_DRIVER_NIC,
 234     .size = sizeof(NICState),
 235     .can_receive = e1000e_nc_can_receive,
 236     .receive = e1000e_nc_receive,
 237     .receive_iov = e1000e_nc_receive_iov,
 238     .link_status_changed = e1000e_set_link_status,
 239 };
 240
 241 /*
 242 * EEPROM (NVM) contents documented in Table 36, section 6.1
 243 * and generally 6.1.2 Software accessed words.
 244 */
 245 static const uint16_t e1000e_eeprom_template[64] = {
 246   /*        Address        |    Compat.    | ImVer |   Compat.     */
 247     0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
 248   /*      PBA      |ICtrl1 | SSID  | SVID  | DevID |-------|ICtrl2 */
 249     0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
 250   /*    NVM words 1,2,3    |-------------------------------|PCI-EID*/
 251     0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
 252   /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */
 253     0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
 254   /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/
 255     0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
 256   /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP  */
 257     0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
 258   /*                            SW Section                         */
 259     0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
 260   /*                      SW Section                       |CHKSUM */
 261     0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
 262 };
 263
 264 static void e1000e_core_realize(E1000EState *s)
 265 {
 266     s->core.owner = &s->parent_obj;
 267     s->core.owner_nic = s->nic;
 268 }
 269
 270 static void
 271 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
 272 {
 273     int i;
 274     for (i = 0; i < num_vectors; i++) {
 275         msix_vector_unuse(PCI_DEVICE(s), i);
 276     }
 277 }
 278
 279 static bool
 280 e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
 281 {
 282     int i;
 283     for (i = 0; i < num_vectors; i++) {
 284         int res = msix_vector_use(PCI_DEVICE(s), i);
 285         if (res < 0) {
 286             trace_e1000e_msix_use_vector_fail(i, res);
 287             e1000e_unuse_msix_vectors(s, i);
 288             return false;
 289         }
 290     }
 291     return true;
 292 }
 293
 294 static void
 295 e1000e_init_msix(E1000EState *s)
 296 {
 297     PCIDevice *d = PCI_DEVICE(s);
 298     int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
 299                         &s->msix,
 300                         E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
 301                         &s->msix,
 302                         E1000E_MSIX_IDX, E1000E_MSIX_PBA,
 303                         0xA0, NULL);
 304
 305     if (res < 0) {
 306         trace_e1000e_msix_init_fail(res);
 307     } else {
 308         if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) {
 309             msix_uninit(d, &s->msix, &s->msix);
 310         }
 311     }
 312 }
 313
 314 static void
 315 e1000e_cleanup_msix(E1000EState *s)
 316 {
 317     if (msix_present(PCI_DEVICE(s))) {
 318         e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
 319         msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
 320     }
 321 }
 322
 323 static void
 324 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
 325 {
 326     DeviceState *dev = DEVICE(pci_dev);
 327     NetClientState *nc;
 328     int i;
 329
 330     s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
 331         object_get_typename(OBJECT(s)), dev->id, s);
 332
 333     s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0;
 334
 335     trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
 336     memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
 337
 338     qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
 339
 340     /* Setup virtio headers */
 341     if (s->disable_vnet) {
 342         s->core.has_vnet = false;
 343         trace_e1000e_cfg_support_virtio(false);
 344         return;
 345     } else {
 346         s->core.has_vnet = true;
 347     }
 348
 349     for (i = 0; i < s->conf.peers.queues; i++) {
 350         nc = qemu_get_subqueue(s->nic, i);
 351         if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
 352             s->core.has_vnet = false;
 353             trace_e1000e_cfg_support_virtio(false);
 354             return;
 355         }
 356     }
 357
 358     trace_e1000e_cfg_support_virtio(true);
 359
 360     for (i = 0; i < s->conf.peers.queues; i++) {
 361         nc = qemu_get_subqueue(s->nic, i);
 362         qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
 363         qemu_using_vnet_hdr(nc->peer, true);
 364     }
 365 }
 366
 367 static inline uint64_t
 368 e1000e_gen_dsn(uint8_t *mac)
 369 {
 370     return (uint64_t)(mac[5])        |
 371            (uint64_t)(mac[4])  << 8  |
 372            (uint64_t)(mac[3])  << 16 |
 373            (uint64_t)(0x00FF)  << 24 |
 374            (uint64_t)(0x00FF)  << 32 |
 375            (uint64_t)(mac[2])  << 40 |
 376            (uint64_t)(mac[1])  << 48 |
 377            (uint64_t)(mac[0])  << 56;
 378 }
 379
 380 static int
 381 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
 382 {
 383     Error *local_err = NULL;
 384     int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
 385                                  PCI_PM_SIZEOF, &local_err);
 386
 387     if (local_err) {
 388         error_report_err(local_err);
 389         return ret;
 390     }
 391
 392     pci_set_word(pdev->config + offset + PCI_PM_PMC,
 393                  PCI_PM_CAP_VER_1_1 |
 394                  pmc);
 395
 396     pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
 397                  PCI_PM_CTRL_STATE_MASK |
 398                  PCI_PM_CTRL_PME_ENABLE |
 399                  PCI_PM_CTRL_DATA_SEL_MASK);
 400
 401     pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
 402                  PCI_PM_CTRL_PME_STATUS);
 403
 404     return ret;
 405 }
 406
 407 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
 408                                 uint32_t val, int len)
 409 {
 410     E1000EState *s = E1000E(pci_dev);
 411
 412     pci_default_write_config(pci_dev, address, val, len);
 413
 414     if (range_covers_byte(address, len, PCI_COMMAND) &&
 415         (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
 416         e1000e_start_recv(&s->core);
 417     }
 418 }
 419
 420 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
 421 {
 422     static const uint16_t e1000e_pmrb_offset = 0x0C8;
 423     static const uint16_t e1000e_pcie_offset = 0x0E0;
 424     static const uint16_t e1000e_aer_offset =  0x100;
 425     static const uint16_t e1000e_dsn_offset =  0x140;
 426     E1000EState *s = E1000E(pci_dev);
 427     uint8_t *macaddr;
 428     int ret;
 429
 430     trace_e1000e_cb_pci_realize();
 431
 432     pci_dev->config_write = e1000e_write_config;
 433
 434     pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
 435     pci_dev->config[PCI_INTERRUPT_PIN] = 1;
 436
 437     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
 438     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
 439
 440     s->subsys_ven_used = s->subsys_ven;
 441     s->subsys_used = s->subsys;
 442
 443     /* Define IO/MMIO regions */
 444     memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
 445                           "e1000e-mmio", E1000E_MMIO_SIZE);
 446     pci_register_bar(pci_dev, E1000E_MMIO_IDX,
 447                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
 448
 449     /*
 450      * We provide a dummy implementation for the flash BAR
 451      * for drivers that may theoretically probe for its presence.
 452      */
 453     memory_region_init(&s->flash, OBJECT(s),
 454                        "e1000e-flash", E1000E_FLASH_SIZE);
 455     pci_register_bar(pci_dev, E1000E_FLASH_IDX,
 456                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
 457
 458     memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
 459                           "e1000e-io", E1000E_IO_SIZE);
 460     pci_register_bar(pci_dev, E1000E_IO_IDX,
 461                      PCI_BASE_ADDRESS_SPACE_IO, &s->io);
 462
 463     memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
 464                        E1000E_MSIX_SIZE);
 465     pci_register_bar(pci_dev, E1000E_MSIX_IDX,
 466                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
 467
 468     /* Create networking backend */
 469     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 470     macaddr = s->conf.macaddr.a;
 471
 472     e1000e_init_msix(s);
 473
 474     if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
 475         hw_error("Failed to initialize PCIe capability");
 476     }
 477
 478     ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);
 479     if (ret) {
 480         trace_e1000e_msi_init_fail(ret);
 481     }
 482
 483     if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
 484                                   PCI_PM_CAP_DSI) < 0) {
 485         hw_error("Failed to initialize PM capability");
 486     }
 487
 488     if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
 489                       PCI_ERR_SIZEOF, NULL) < 0) {
 490         hw_error("Failed to initialize AER capability");
 491     }
 492
 493     pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
 494                           e1000e_gen_dsn(macaddr));
 495
 496     e1000e_init_net_peer(s, pci_dev, macaddr);
 497
 498     /* Initialize core */
 499     e1000e_core_realize(s);
 500
 501     e1000e_core_pci_realize(&s->core,
 502                             e1000e_eeprom_template,
 503                             sizeof(e1000e_eeprom_template),
 504                             macaddr);
 505 }
 506
 507 static void e1000e_pci_uninit(PCIDevice *pci_dev)
 508 {
 509     E1000EState *s = E1000E(pci_dev);
 510
 511     trace_e1000e_cb_pci_uninit();
 512
 513     e1000e_core_pci_uninit(&s->core);
 514
 515     pcie_aer_exit(pci_dev);
 516     pcie_cap_exit(pci_dev);
 517
 518     qemu_del_nic(s->nic);
 519
 520     e1000e_cleanup_msix(s);
 521     msi_uninit(pci_dev);
 522 }
 523
 524 static void e1000e_qdev_reset(DeviceState *dev)
 525 {
 526     E1000EState *s = E1000E(dev);
 527
 528     trace_e1000e_cb_qdev_reset();
 529
 530     e1000e_core_reset(&s->core);
 531
 532     if (s->init_vet) {
 533         s->core.mac[VET] = ETH_P_VLAN;
 534     }
 535 }
 536
 537 static int e1000e_pre_save(void *opaque)
 538 {
 539     E1000EState *s = opaque;
 540
 541     trace_e1000e_cb_pre_save();
 542
 543     e1000e_core_pre_save(&s->core);
 544
 545     return 0;
 546 }
 547
 548 static int e1000e_post_load(void *opaque, int version_id)
 549 {
 550     E1000EState *s = opaque;
 551
 552     trace_e1000e_cb_post_load();
 553
 554     if ((s->subsys != s->subsys_used) ||
 555         (s->subsys_ven != s->subsys_ven_used)) {
 556         fprintf(stderr,
 557             "ERROR: Cannot migrate while device properties "
 558             "(subsys/subsys_ven) differ");
 559         return -1;
 560     }
 561
 562     return e1000e_core_post_load(&s->core);
 563 }
 564
 565 static const VMStateDescription e1000e_vmstate_tx = {
 566     .name = "e1000e-tx",
 567     .version_id = 1,
 568     .minimum_version_id = 1,
 569     .fields = (VMStateField[]) {
 570         VMSTATE_UINT8(sum_needed, struct e1000e_tx),
 571         VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
 572         VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
 573         VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
 574         VMSTATE_UINT8(props.tucss, struct e1000e_tx),
 575         VMSTATE_UINT8(props.tucso, struct e1000e_tx),
 576         VMSTATE_UINT16(props.tucse, struct e1000e_tx),
 577         VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
 578         VMSTATE_UINT16(props.mss, struct e1000e_tx),
 579         VMSTATE_UINT32(props.paylen, struct e1000e_tx),
 580         VMSTATE_INT8(props.ip, struct e1000e_tx),
 581         VMSTATE_INT8(props.tcp, struct e1000e_tx),
 582         VMSTATE_BOOL(props.tse, struct e1000e_tx),
 583         VMSTATE_BOOL(cptse, struct e1000e_tx),
 584         VMSTATE_BOOL(skip_cp, struct e1000e_tx),
 585         VMSTATE_END_OF_LIST()
 586     }
 587 };
 588
 589 static const VMStateDescription e1000e_vmstate_intr_timer = {
 590     .name = "e1000e-intr-timer",
 591     .version_id = 1,
 592     .minimum_version_id = 1,
 593     .fields = (VMStateField[]) {
 594         VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
 595         VMSTATE_BOOL(running, E1000IntrDelayTimer),
 596         VMSTATE_END_OF_LIST()
 597     }
 598 };
 599
 600 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s)                     \
 601     VMSTATE_STRUCT(_f, _s, 0,                                       \
 602                    e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
 603
 604 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num)         \
 605     VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0,                           \
 606                          e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
 607
 608 static const VMStateDescription e1000e_vmstate = {
 609     .name = "e1000e",
 610     .version_id = 1,
 611     .minimum_version_id = 1,
 612     .pre_save = e1000e_pre_save,
 613     .post_load = e1000e_post_load,
 614     .fields = (VMStateField[]) {
 615         VMSTATE_PCI_DEVICE(parent_obj, E1000EState),
 616         VMSTATE_MSIX(parent_obj, E1000EState),
 617
 618         VMSTATE_UINT32(ioaddr, E1000EState),
 619         VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
 620         VMSTATE_UINT8(core.rx_desc_len, E1000EState),
 621         VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
 622                              E1000_PSRCTL_BUFFS_PER_DESC),
 623         VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
 624         VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
 625         VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
 626                                E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
 627         VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
 628         VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
 629
 630         VMSTATE_UINT32(core.delayed_causes, E1000EState),
 631
 632         VMSTATE_UINT16(subsys, E1000EState),
 633         VMSTATE_UINT16(subsys_ven, E1000EState),
 634
 635         VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
 636         VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
 637         VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
 638         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
 639         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
 640
 641         VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
 642         VMSTATE_BOOL(core.itr_intr_pending, E1000EState),
 643
 644         VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
 645                                               E1000E_MSIX_VEC_NUM),
 646         VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState,
 647                            E1000E_MSIX_VEC_NUM),
 648
 649         VMSTATE_UINT32(core.itr_guest_value, E1000EState),
 650         VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
 651                              E1000E_MSIX_VEC_NUM),
 652
 653         VMSTATE_UINT16(core.vet, E1000EState),
 654
 655         VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
 656                              e1000e_vmstate_tx, struct e1000e_tx),
 657         VMSTATE_END_OF_LIST()
 658     }
 659 };
 660
 661 static PropertyInfo e1000e_prop_disable_vnet,
 662                     e1000e_prop_subsys_ven,
 663                     e1000e_prop_subsys;
 664
 665 static Property e1000e_properties[] = {
 666     DEFINE_NIC_PROPERTIES(E1000EState, conf),
 667     DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false,
 668                         e1000e_prop_disable_vnet, bool),
 669     DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven,
 670                         PCI_VENDOR_ID_INTEL,
 671                         e1000e_prop_subsys_ven, uint16_t),
 672     DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
 673                         e1000e_prop_subsys, uint16_t),
 674     DEFINE_PROP_BOOL("init-vet", E1000EState, init_vet, true),
 675     DEFINE_PROP_END_OF_LIST(),
 676 };
 677
 678 static void e1000e_class_init(ObjectClass *class, void *data)
 679 {
 680     DeviceClass *dc = DEVICE_CLASS(class);
 681     PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
 682
 683     c->realize = e1000e_pci_realize;
 684     c->exit = e1000e_pci_uninit;
 685     c->vendor_id = PCI_VENDOR_ID_INTEL;
 686     c->device_id = E1000_DEV_ID_82574L;
 687     c->revision = 0;
 688     c->romfile = "efi-e1000e.rom";
 689     c->class_id = PCI_CLASS_NETWORK_ETHERNET;
 690
 691     dc->desc = "Intel 82574L GbE Controller";
 692     dc->reset = e1000e_qdev_reset;
 693     dc->vmsd = &e1000e_vmstate;
 694
 695     e1000e_prop_disable_vnet = qdev_prop_uint8;
 696     e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
 697                                            "perform SW offloads emulation "
 698                                            "instead";
 699
 700     e1000e_prop_subsys_ven = qdev_prop_uint16;
 701     e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
 702
 703     e1000e_prop_subsys = qdev_prop_uint16;
 704     e1000e_prop_subsys.description = "PCI device Subsystem ID";
 705
 706     device_class_set_props(dc, e1000e_properties);
 707     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 708 }
 709
 710 static void e1000e_instance_init(Object *obj)
 711 {
 712     E1000EState *s = E1000E(obj);
 713     device_add_bootindex_property(obj, &s->conf.bootindex,
 714                                   "bootindex", "/ethernet-phy@0",
 715                                   DEVICE(obj));
 716 }
 717
 718 static const TypeInfo e1000e_info = {
 719     .name = TYPE_E1000E,
 720     .parent = TYPE_PCI_DEVICE,
 721     .instance_size = sizeof(E1000EState),
 722     .class_init = e1000e_class_init,
 723     .instance_init = e1000e_instance_init,
 724     .interfaces = (InterfaceInfo[]) {
 725         { INTERFACE_PCIE_DEVICE },
 726         { }
 727     },
 728 };
 729
 730 static void e1000e_register_types(void)
 731 {
 732     type_register_static(&e1000e_info);
 733 }
 734
 735 type_init(e1000e_register_types)