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icount: Take iothread lock when running QEMU timers
[qemu/ar7.git] / hw / i386 / pc.c
blob7280c02ce3d5c229a83e285cc9e1cc9e66feb149
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/pci-bridge/pci_expander_bridge.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/timer/hpet.h"
43 #include "hw/firmware/smbios.h"
44 #include "hw/loader.h"
45 #include "elf.h"
46 #include "migration/vmstate.h"
47 #include "multiboot.h"
48 #include "hw/rtc/mc146818rtc.h"
49 #include "hw/intc/i8259.h"
50 #include "hw/dma/i8257.h"
51 #include "hw/timer/i8254.h"
52 #include "hw/input/i8042.h"
53 #include "hw/irq.h"
54 #include "hw/audio/pcspk.h"
55 #include "hw/pci/msi.h"
56 #include "hw/sysbus.h"
57 #include "sysemu/sysemu.h"
58 #include "sysemu/tcg.h"
59 #include "sysemu/numa.h"
60 #include "sysemu/kvm.h"
61 #include "sysemu/xen.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm/kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "acpi-build.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/cxl/cxl.h"
80 #include "hw/cxl/cxl_host.h"
81 #include "qapi/error.h"
82 #include "qapi/qapi-visit-common.h"
83 #include "qapi/qapi-visit-machine.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
86 #include "hw/usb.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-iommu.h"
91 #include "hw/virtio/virtio-pmem-pci.h"
92 #include "hw/virtio/virtio-mem-pci.h"
93 #include "hw/mem/memory-device.h"
94 #include "sysemu/replay.h"
95 #include "qapi/qmp/qerror.h"
96 #include "e820_memory_layout.h"
97 #include "fw_cfg.h"
98 #include "trace.h"
99 #include CONFIG_DEVICES
100
101 /*
102 * Helper for setting model-id for CPU models that changed model-id
103 * depending on QEMU versions up to QEMU 2.4.
104 */
105 #define PC_CPU_MODEL_IDS(v) \
106 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
107 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
108 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
109
110 GlobalProperty pc_compat_7_0[] = {};
111 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
112
113 GlobalProperty pc_compat_6_2[] = {
114 { "virtio-mem", "unplugged-inaccessible", "off" },
115 };
116 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
117
118 GlobalProperty pc_compat_6_1[] = {
119 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
120 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
121 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
123 };
124 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
125
126 GlobalProperty pc_compat_6_0[] = {
127 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
128 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
129 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
130 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
131 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
132 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
133 };
134 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
135
136 GlobalProperty pc_compat_5_2[] = {
137 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
138 };
139 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
140
141 GlobalProperty pc_compat_5_1[] = {
142 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
143 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
144 };
145 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
146
147 GlobalProperty pc_compat_5_0[] = {
148 };
149 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
150
151 GlobalProperty pc_compat_4_2[] = {
152 { "mch", "smbase-smram", "off" },
153 };
154 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
155
156 GlobalProperty pc_compat_4_1[] = {};
157 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
158
159 GlobalProperty pc_compat_4_0[] = {};
160 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
161
162 GlobalProperty pc_compat_3_1[] = {
163 { "intel-iommu", "dma-drain", "off" },
164 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
165 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
166 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
167 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
168 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
169 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
170 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
171 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
172 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
173 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
174 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
175 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
176 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
177 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
178 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
179 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
180 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
181 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
182 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
183 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
184 };
185 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
186
187 GlobalProperty pc_compat_3_0[] = {
188 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
189 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
190 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
191 };
192 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
193
194 GlobalProperty pc_compat_2_12[] = {
195 { TYPE_X86_CPU, "legacy-cache", "on" },
196 { TYPE_X86_CPU, "topoext", "off" },
197 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
198 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
199 };
200 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
201
202 GlobalProperty pc_compat_2_11[] = {
203 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
204 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
205 };
206 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
207
208 GlobalProperty pc_compat_2_10[] = {
209 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
210 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
211 { "q35-pcihost", "x-pci-hole64-fix", "off" },
212 };
213 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
214
215 GlobalProperty pc_compat_2_9[] = {
216 { "mch", "extended-tseg-mbytes", "0" },
217 };
218 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
219
220 GlobalProperty pc_compat_2_8[] = {
221 { TYPE_X86_CPU, "tcg-cpuid", "off" },
222 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
223 { "ICH9-LPC", "x-smi-broadcast", "off" },
224 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
225 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
226 };
227 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
228
229 GlobalProperty pc_compat_2_7[] = {
230 { TYPE_X86_CPU, "l3-cache", "off" },
231 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
232 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
233 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
234 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
235 { "isa-pcspk", "migrate", "off" },
236 };
237 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
238
239 GlobalProperty pc_compat_2_6[] = {
240 { TYPE_X86_CPU, "cpuid-0xb", "off" },
241 { "vmxnet3", "romfile", "" },
242 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
243 { "apic-common", "legacy-instance-id", "on", }
244 };
245 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
246
247 GlobalProperty pc_compat_2_5[] = {};
248 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
249
250 GlobalProperty pc_compat_2_4[] = {
251 PC_CPU_MODEL_IDS("2.4.0")
252 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
253 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
254 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
255 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
256 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
257 { TYPE_X86_CPU, "check", "off" },
258 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
259 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
260 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
261 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
262 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
263 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
264 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
265 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
266 };
267 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
268
269 GlobalProperty pc_compat_2_3[] = {
270 PC_CPU_MODEL_IDS("2.3.0")
271 { TYPE_X86_CPU, "arat", "off" },
272 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
273 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
274 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
275 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
276 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
277 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
278 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
279 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
280 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
281 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
282 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
283 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
284 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
285 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
286 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
287 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
288 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
289 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
290 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
291 };
292 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
293
294 GlobalProperty pc_compat_2_2[] = {
295 PC_CPU_MODEL_IDS("2.2.0")
296 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
297 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
298 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
299 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
300 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
301 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
302 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
303 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
304 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
305 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
306 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
307 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
308 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
309 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
310 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
311 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
312 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
313 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
314 };
315 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
316
317 GlobalProperty pc_compat_2_1[] = {
318 PC_CPU_MODEL_IDS("2.1.0")
319 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
320 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
321 };
322 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
323
324 GlobalProperty pc_compat_2_0[] = {
325 PC_CPU_MODEL_IDS("2.0.0")
326 { "virtio-scsi-pci", "any_layout", "off" },
327 { "PIIX4_PM", "memory-hotplug-support", "off" },
328 { "apic", "version", "0x11" },
329 { "nec-usb-xhci", "superspeed-ports-first", "off" },
330 { "nec-usb-xhci", "force-pcie-endcap", "on" },
331 { "pci-serial", "prog_if", "0" },
332 { "pci-serial-2x", "prog_if", "0" },
333 { "pci-serial-4x", "prog_if", "0" },
334 { "virtio-net-pci", "guest_announce", "off" },
335 { "ICH9-LPC", "memory-hotplug-support", "off" },
336 };
337 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
338
339 GlobalProperty pc_compat_1_7[] = {
340 PC_CPU_MODEL_IDS("1.7.0")
341 { TYPE_USB_DEVICE, "msos-desc", "no" },
342 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
343 { "hpet", HPET_INTCAP, "4" },
344 };
345 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
346
347 GlobalProperty pc_compat_1_6[] = {
348 PC_CPU_MODEL_IDS("1.6.0")
349 { "e1000", "mitigation", "off" },
350 { "qemu64-" TYPE_X86_CPU, "model", "2" },
351 { "qemu32-" TYPE_X86_CPU, "model", "3" },
352 { "i440FX-pcihost", "short_root_bus", "1" },
353 { "q35-pcihost", "short_root_bus", "1" },
354 };
355 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
356
357 GlobalProperty pc_compat_1_5[] = {
358 PC_CPU_MODEL_IDS("1.5.0")
359 { "Conroe-" TYPE_X86_CPU, "model", "2" },
360 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
361 { "Penryn-" TYPE_X86_CPU, "model", "2" },
362 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
363 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
364 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
365 { "virtio-net-pci", "any_layout", "off" },
366 { TYPE_X86_CPU, "pmu", "on" },
367 { "i440FX-pcihost", "short_root_bus", "0" },
368 { "q35-pcihost", "short_root_bus", "0" },
369 };
370 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
371
372 GlobalProperty pc_compat_1_4[] = {
373 PC_CPU_MODEL_IDS("1.4.0")
374 { "scsi-hd", "discard_granularity", "0" },
375 { "scsi-cd", "discard_granularity", "0" },
376 { "ide-hd", "discard_granularity", "0" },
377 { "ide-cd", "discard_granularity", "0" },
378 { "virtio-blk-pci", "discard_granularity", "0" },
379 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
380 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
381 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
382 { "e1000", "romfile", "pxe-e1000.rom" },
383 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
384 { "pcnet", "romfile", "pxe-pcnet.rom" },
385 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
386 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
387 { "486-" TYPE_X86_CPU, "model", "0" },
388 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
389 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
390 };
391 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
392
393 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
394 {
395 GSIState *s;
396
397 s = g_new0(GSIState, 1);
398 if (kvm_ioapic_in_kernel()) {
399 kvm_pc_setup_irq_routing(pci_enabled);
400 }
401 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
402
403 return s;
404 }
405
406 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
407 unsigned size)
408 {
409 }
410
411 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
412 {
413 return 0xffffffffffffffffULL;
414 }
415
416 /* MSDOS compatibility mode FPU exception support */
417 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
418 unsigned size)
419 {
420 if (tcg_enabled()) {
421 cpu_set_ignne();
422 }
423 }
424
425 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
426 {
427 return 0xffffffffffffffffULL;
428 }
429
430 /* PC cmos mappings */
431
432 #define REG_EQUIPMENT_BYTE 0x14
433
434 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
435 int16_t cylinders, int8_t heads, int8_t sectors)
436 {
437 rtc_set_memory(s, type_ofs, 47);
438 rtc_set_memory(s, info_ofs, cylinders);
439 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
440 rtc_set_memory(s, info_ofs + 2, heads);
441 rtc_set_memory(s, info_ofs + 3, 0xff);
442 rtc_set_memory(s, info_ofs + 4, 0xff);
443 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
444 rtc_set_memory(s, info_ofs + 6, cylinders);
445 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
446 rtc_set_memory(s, info_ofs + 8, sectors);
447 }
448
449 /* convert boot_device letter to something recognizable by the bios */
450 static int boot_device2nibble(char boot_device)
451 {
452 switch(boot_device) {
453 case 'a':
454 case 'b':
455 return 0x01; /* floppy boot */
456 case 'c':
457 return 0x02; /* hard drive boot */
458 case 'd':
459 return 0x03; /* CD-ROM boot */
460 case 'n':
461 return 0x04; /* Network boot */
462 }
463 return 0;
464 }
465
466 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
467 {
468 #define PC_MAX_BOOT_DEVICES 3
469 int nbds, bds[3] = { 0, };
470 int i;
471
472 nbds = strlen(boot_device);
473 if (nbds > PC_MAX_BOOT_DEVICES) {
474 error_setg(errp, "Too many boot devices for PC");
475 return;
476 }
477 for (i = 0; i < nbds; i++) {
478 bds[i] = boot_device2nibble(boot_device[i]);
479 if (bds[i] == 0) {
480 error_setg(errp, "Invalid boot device for PC: '%c'",
481 boot_device[i]);
482 return;
483 }
484 }
485 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
486 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
487 }
488
489 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
490 {
491 set_boot_dev(opaque, boot_device, errp);
492 }
493
494 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
495 {
496 int val, nb, i;
497 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
498 FLOPPY_DRIVE_TYPE_NONE };
499
500 /* floppy type */
501 if (floppy) {
502 for (i = 0; i < 2; i++) {
503 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
504 }
505 }
506 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
507 cmos_get_fd_drive_type(fd_type[1]);
508 rtc_set_memory(rtc_state, 0x10, val);
509
510 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
511 nb = 0;
512 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
513 nb++;
514 }
515 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
516 nb++;
517 }
518 switch (nb) {
519 case 0:
520 break;
521 case 1:
522 val |= 0x01; /* 1 drive, ready for boot */
523 break;
524 case 2:
525 val |= 0x41; /* 2 drives, ready for boot */
526 break;
527 }
528 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
529 }
530
531 typedef struct pc_cmos_init_late_arg {
532 ISADevice *rtc_state;
533 BusState *idebus[2];
534 } pc_cmos_init_late_arg;
535
536 typedef struct check_fdc_state {
537 ISADevice *floppy;
538 bool multiple;
539 } CheckFdcState;
540
541 static int check_fdc(Object *obj, void *opaque)
542 {
543 CheckFdcState *state = opaque;
544 Object *fdc;
545 uint32_t iobase;
546 Error *local_err = NULL;
547
548 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
549 if (!fdc) {
550 return 0;
551 }
552
553 iobase = object_property_get_uint(obj, "iobase", &local_err);
554 if (local_err || iobase != 0x3f0) {
555 error_free(local_err);
556 return 0;
557 }
558
559 if (state->floppy) {
560 state->multiple = true;
561 } else {
562 state->floppy = ISA_DEVICE(obj);
563 }
564 return 0;
565 }
566
567 static const char * const fdc_container_path[] = {
568 "/unattached", "/peripheral", "/peripheral-anon"
569 };
570
571 /*
572 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
573 * and ACPI objects.
574 */
575 static ISADevice *pc_find_fdc0(void)
576 {
577 int i;
578 Object *container;
579 CheckFdcState state = { 0 };
580
581 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
582 container = container_get(qdev_get_machine(), fdc_container_path[i]);
583 object_child_foreach(container, check_fdc, &state);
584 }
585
586 if (state.multiple) {
587 warn_report("multiple floppy disk controllers with "
588 "iobase=0x3f0 have been found");
589 error_printf("the one being picked for CMOS setup might not reflect "
590 "your intent");
591 }
592
593 return state.floppy;
594 }
595
596 static void pc_cmos_init_late(void *opaque)
597 {
598 pc_cmos_init_late_arg *arg = opaque;
599 ISADevice *s = arg->rtc_state;
600 int16_t cylinders;
601 int8_t heads, sectors;
602 int val;
603 int i, trans;
604
605 val = 0;
606 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
607 &cylinders, &heads, &sectors) >= 0) {
608 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
609 val |= 0xf0;
610 }
611 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
612 &cylinders, &heads, &sectors) >= 0) {
613 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
614 val |= 0x0f;
615 }
616 rtc_set_memory(s, 0x12, val);
617
618 val = 0;
619 for (i = 0; i < 4; i++) {
620 /* NOTE: ide_get_geometry() returns the physical
621 geometry. It is always such that: 1 <= sects <= 63, 1
622 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
623 geometry can be different if a translation is done. */
624 if (arg->idebus[i / 2] &&
625 ide_get_geometry(arg->idebus[i / 2], i % 2,
626 &cylinders, &heads, &sectors) >= 0) {
627 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
628 assert((trans & ~3) == 0);
629 val |= trans << (i * 2);
630 }
631 }
632 rtc_set_memory(s, 0x39, val);
633
634 pc_cmos_init_floppy(s, pc_find_fdc0());
635
636 qemu_unregister_reset(pc_cmos_init_late, opaque);
637 }
638
639 void pc_cmos_init(PCMachineState *pcms,
640 BusState *idebus0, BusState *idebus1,
641 ISADevice *s)
642 {
643 int val;
644 static pc_cmos_init_late_arg arg;
645 X86MachineState *x86ms = X86_MACHINE(pcms);
646
647 /* various important CMOS locations needed by PC/Bochs bios */
648
649 /* memory size */
650 /* base memory (first MiB) */
651 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
652 rtc_set_memory(s, 0x15, val);
653 rtc_set_memory(s, 0x16, val >> 8);
654 /* extended memory (next 64MiB) */
655 if (x86ms->below_4g_mem_size > 1 * MiB) {
656 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
657 } else {
658 val = 0;
659 }
660 if (val > 65535)
661 val = 65535;
662 rtc_set_memory(s, 0x17, val);
663 rtc_set_memory(s, 0x18, val >> 8);
664 rtc_set_memory(s, 0x30, val);
665 rtc_set_memory(s, 0x31, val >> 8);
666 /* memory between 16MiB and 4GiB */
667 if (x86ms->below_4g_mem_size > 16 * MiB) {
668 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
669 } else {
670 val = 0;
671 }
672 if (val > 65535)
673 val = 65535;
674 rtc_set_memory(s, 0x34, val);
675 rtc_set_memory(s, 0x35, val >> 8);
676 /* memory above 4GiB */
677 val = x86ms->above_4g_mem_size / 65536;
678 rtc_set_memory(s, 0x5b, val);
679 rtc_set_memory(s, 0x5c, val >> 8);
680 rtc_set_memory(s, 0x5d, val >> 16);
681
682 object_property_add_link(OBJECT(pcms), "rtc_state",
683 TYPE_ISA_DEVICE,
684 (Object **)&x86ms->rtc,
685 object_property_allow_set_link,
686 OBJ_PROP_LINK_STRONG);
687 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
688 &error_abort);
689
690 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
691
692 val = 0;
693 val |= 0x02; /* FPU is there */
694 val |= 0x04; /* PS/2 mouse installed */
695 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
696
697 /* hard drives and FDC */
698 arg.rtc_state = s;
699 arg.idebus[0] = idebus0;
700 arg.idebus[1] = idebus1;
701 qemu_register_reset(pc_cmos_init_late, &arg);
702 }
703
704 static void handle_a20_line_change(void *opaque, int irq, int level)
705 {
706 X86CPU *cpu = opaque;
707
708 /* XXX: send to all CPUs ? */
709 /* XXX: add logic to handle multiple A20 line sources */
710 x86_cpu_set_a20(cpu, level);
711 }
712
713 #define NE2000_NB_MAX 6
714
715 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
716 0x280, 0x380 };
717 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
718
719 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
720 {
721 static int nb_ne2k = 0;
722
723 if (nb_ne2k == NE2000_NB_MAX)
724 return;
725 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
726 ne2000_irq[nb_ne2k], nd);
727 nb_ne2k++;
728 }
729
730 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
731 {
732 X86CPU *cpu = opaque;
733
734 if (level) {
735 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
736 }
737 }
738
739 static
740 void pc_machine_done(Notifier *notifier, void *data)
741 {
742 PCMachineState *pcms = container_of(notifier,
743 PCMachineState, machine_done);
744 X86MachineState *x86ms = X86_MACHINE(pcms);
745
746 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
747 &error_fatal);
748
749 if (pcms->cxl_devices_state.is_enabled) {
750 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
751 }
752
753 /* set the number of CPUs */
754 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
755
756 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
757
758 acpi_setup();
759 if (x86ms->fw_cfg) {
760 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
761 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
762 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
763 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
764 }
765 }
766
767 void pc_guest_info_init(PCMachineState *pcms)
768 {
769 X86MachineState *x86ms = X86_MACHINE(pcms);
770
771 x86ms->apic_xrupt_override = true;
772 pcms->machine_done.notify = pc_machine_done;
773 qemu_add_machine_init_done_notifier(&pcms->machine_done);
774 }
775
776 /* setup pci memory address space mapping into system address space */
777 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
778 MemoryRegion *pci_address_space)
779 {
780 /* Set to lower priority than RAM */
781 memory_region_add_subregion_overlap(system_memory, 0x0,
782 pci_address_space, -1);
783 }
784
785 void xen_load_linux(PCMachineState *pcms)
786 {
787 int i;
788 FWCfgState *fw_cfg;
789 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
790 X86MachineState *x86ms = X86_MACHINE(pcms);
791
792 assert(MACHINE(pcms)->kernel_filename != NULL);
793
794 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
795 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
796 rom_set_fw(fw_cfg);
797
798 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
799 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
800 for (i = 0; i < nb_option_roms; i++) {
801 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
802 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
803 !strcmp(option_rom[i].name, "pvh.bin") ||
804 !strcmp(option_rom[i].name, "multiboot.bin") ||
805 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
806 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
807 }
808 x86ms->fw_cfg = fw_cfg;
809 }
810
811 #define PC_ROM_MIN_VGA 0xc0000
812 #define PC_ROM_MIN_OPTION 0xc8000
813 #define PC_ROM_MAX 0xe0000
814 #define PC_ROM_ALIGN 0x800
815 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
816
817 static hwaddr pc_above_4g_end(PCMachineState *pcms)
818 {
819 X86MachineState *x86ms = X86_MACHINE(pcms);
820
821 if (pcms->sgx_epc.size != 0) {
822 return sgx_epc_above_4g_end(&pcms->sgx_epc);
823 }
824
825 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
826 }
827
828 static void pc_get_device_memory_range(PCMachineState *pcms,
829 hwaddr *base,
830 ram_addr_t *device_mem_size)
831 {
832 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
833 MachineState *machine = MACHINE(pcms);
834 ram_addr_t size;
835 hwaddr addr;
836
837 size = machine->maxram_size - machine->ram_size;
838 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
839
840 if (pcmc->enforce_aligned_dimm) {
841 /* size device region assuming 1G page max alignment per slot */
842 size += (1 * GiB) * machine->ram_slots;
843 }
844
845 *base = addr;
846 *device_mem_size = size;
847 }
848
849 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
850 {
851 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
852 hwaddr cxl_base;
853 ram_addr_t size;
854
855 if (pcmc->has_reserved_memory) {
856 pc_get_device_memory_range(pcms, &cxl_base, &size);
857 cxl_base += size;
858 } else {
859 cxl_base = pc_above_4g_end(pcms);
860 }
861
862 return cxl_base;
863 }
864
865 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
866 {
867 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
868
869 if (pcms->cxl_devices_state.fixed_windows) {
870 GList *it;
871
872 start = ROUND_UP(start, 256 * MiB);
873 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
874 CXLFixedWindow *fw = it->data;
875 start += fw->size;
876 }
877 }
878
879 return start;
880 }
881
882 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
883 {
884 X86CPU *cpu = X86_CPU(first_cpu);
885
886 /* 32-bit systems don't have hole64 thus return max CPU address */
887 if (cpu->phys_bits <= 32) {
888 return ((hwaddr)1 << cpu->phys_bits) - 1;
889 }
890
891 return pc_pci_hole64_start() + pci_hole64_size - 1;
892 }
893
894 /*
895 * AMD systems with an IOMMU have an additional hole close to the
896 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
897 * on kernel version, VFIO may or may not let you DMA map those ranges.
898 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
899 * with certain memory sizes. It's also wrong to use those IOVA ranges
900 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
901 * The ranges reserved for Hyper-Transport are:
902 *
903 * FD_0000_0000h - FF_FFFF_FFFFh
904 *
905 * The ranges represent the following:
906 *
907 * Base Address Top Address Use
908 *
909 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
910 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
911 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
912 * FD_F910_0000h FD_F91F_FFFFh System Management
913 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
914 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
915 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
916 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
917 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
918 * FE_2000_0000h FF_FFFF_FFFFh Reserved
919 *
920 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
921 * Table 3: Special Address Controls (GPA) for more information.
922 */
923 #define AMD_HT_START 0xfd00000000UL
924 #define AMD_HT_END 0xffffffffffUL
925 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
926 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
927
928 void pc_memory_init(PCMachineState *pcms,
929 MemoryRegion *system_memory,
930 MemoryRegion *rom_memory,
931 MemoryRegion **ram_memory,
932 uint64_t pci_hole64_size)
933 {
934 int linux_boot, i;
935 MemoryRegion *option_rom_mr;
936 MemoryRegion *ram_below_4g, *ram_above_4g;
937 FWCfgState *fw_cfg;
938 MachineState *machine = MACHINE(pcms);
939 MachineClass *mc = MACHINE_GET_CLASS(machine);
940 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
941 X86MachineState *x86ms = X86_MACHINE(pcms);
942 hwaddr maxphysaddr, maxusedaddr;
943 hwaddr cxl_base, cxl_resv_end = 0;
944 X86CPU *cpu = X86_CPU(first_cpu);
945
946 assert(machine->ram_size == x86ms->below_4g_mem_size +
947 x86ms->above_4g_mem_size);
948
949 linux_boot = (machine->kernel_filename != NULL);
950
951 /*
952 * The HyperTransport range close to the 1T boundary is unique to AMD
953 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
954 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
955 * older machine types (<= 7.0) for compatibility purposes.
956 */
957 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
958 /* Bail out if max possible address does not cross HT range */
959 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
960 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
961 }
962
963 /*
964 * Advertise the HT region if address space covers the reserved
965 * region or if we relocate.
966 */
967 if (cpu->phys_bits >= 40) {
968 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
969 }
970 }
971
972 /*
973 * phys-bits is required to be appropriately configured
974 * to make sure max used GPA is reachable.
975 */
976 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
977 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
978 if (maxphysaddr < maxusedaddr) {
979 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
980 " phys-bits too low (%u)",
981 maxphysaddr, maxusedaddr, cpu->phys_bits);
982 exit(EXIT_FAILURE);
983 }
984
985 /*
986 * Split single memory region and use aliases to address portions of it,
987 * done for backwards compatibility with older qemus.
988 */
989 *ram_memory = machine->ram;
990 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
991 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
992 0, x86ms->below_4g_mem_size);
993 memory_region_add_subregion(system_memory, 0, ram_below_4g);
994 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
995 if (x86ms->above_4g_mem_size > 0) {
996 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
997 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
998 machine->ram,
999 x86ms->below_4g_mem_size,
1000 x86ms->above_4g_mem_size);
1001 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
1002 ram_above_4g);
1003 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
1004 E820_RAM);
1005 }
1006
1007 if (pcms->sgx_epc.size != 0) {
1008 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
1009 }
1010
1011 if (!pcmc->has_reserved_memory &&
1012 (machine->ram_slots ||
1013 (machine->maxram_size > machine->ram_size))) {
1014
1015 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1016 mc->name);
1017 exit(EXIT_FAILURE);
1018 }
1019
1020 /* always allocate the device memory information */
1021 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1022
1023 /* initialize device memory address space */
1024 if (pcmc->has_reserved_memory &&
1025 (machine->ram_size < machine->maxram_size)) {
1026 ram_addr_t device_mem_size;
1027
1028 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1029 error_report("unsupported amount of memory slots: %"PRIu64,
1030 machine->ram_slots);
1031 exit(EXIT_FAILURE);
1032 }
1033
1034 if (QEMU_ALIGN_UP(machine->maxram_size,
1035 TARGET_PAGE_SIZE) != machine->maxram_size) {
1036 error_report("maximum memory size must by aligned to multiple of "
1037 "%d bytes", TARGET_PAGE_SIZE);
1038 exit(EXIT_FAILURE);
1039 }
1040
1041 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size);
1042
1043 if ((machine->device_memory->base + device_mem_size) <
1044 device_mem_size) {
1045 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1046 machine->maxram_size);
1047 exit(EXIT_FAILURE);
1048 }
1049
1050 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1051 "device-memory", device_mem_size);
1052 memory_region_add_subregion(system_memory, machine->device_memory->base,
1053 &machine->device_memory->mr);
1054 }
1055
1056 if (pcms->cxl_devices_state.is_enabled) {
1057 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1058 hwaddr cxl_size = MiB;
1059
1060 cxl_base = pc_get_cxl_range_start(pcms);
1061 e820_add_entry(cxl_base, cxl_size, E820_RESERVED);
1062 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1063 memory_region_add_subregion(system_memory, cxl_base, mr);
1064 cxl_resv_end = cxl_base + cxl_size;
1065 if (pcms->cxl_devices_state.fixed_windows) {
1066 hwaddr cxl_fmw_base;
1067 GList *it;
1068
1069 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1070 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1071 CXLFixedWindow *fw = it->data;
1072
1073 fw->base = cxl_fmw_base;
1074 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1075 "cxl-fixed-memory-region", fw->size);
1076 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1077 e820_add_entry(fw->base, fw->size, E820_RESERVED);
1078 cxl_fmw_base += fw->size;
1079 cxl_resv_end = cxl_fmw_base;
1080 }
1081 }
1082 }
1083
1084 /* Initialize PC system firmware */
1085 pc_system_firmware_init(pcms, rom_memory);
1086
1087 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1088 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1089 &error_fatal);
1090 if (pcmc->pci_enabled) {
1091 memory_region_set_readonly(option_rom_mr, true);
1092 }
1093 memory_region_add_subregion_overlap(rom_memory,
1094 PC_ROM_MIN_VGA,
1095 option_rom_mr,
1096 1);
1097
1098 fw_cfg = fw_cfg_arch_create(machine,
1099 x86ms->boot_cpus, x86ms->apic_id_limit);
1100
1101 rom_set_fw(fw_cfg);
1102
1103 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1104 uint64_t *val = g_malloc(sizeof(*val));
1105 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1106 uint64_t res_mem_end = machine->device_memory->base;
1107
1108 if (!pcmc->broken_reserved_end) {
1109 res_mem_end += memory_region_size(&machine->device_memory->mr);
1110 }
1111
1112 if (pcms->cxl_devices_state.is_enabled) {
1113 res_mem_end = cxl_resv_end;
1114 }
1115 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1116 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1117 }
1118
1119 if (linux_boot) {
1120 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1121 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
1122 }
1123
1124 for (i = 0; i < nb_option_roms; i++) {
1125 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1126 }
1127 x86ms->fw_cfg = fw_cfg;
1128
1129 /* Init default IOAPIC address space */
1130 x86ms->ioapic_as = &address_space_memory;
1131
1132 /* Init ACPI memory hotplug IO base address */
1133 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1134 }
1135
1136 /*
1137 * The 64bit pci hole starts after "above 4G RAM" and
1138 * potentially the space reserved for memory hotplug.
1139 */
1140 uint64_t pc_pci_hole64_start(void)
1141 {
1142 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1143 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1144 MachineState *ms = MACHINE(pcms);
1145 uint64_t hole64_start = 0;
1146 ram_addr_t size = 0;
1147
1148 if (pcms->cxl_devices_state.is_enabled) {
1149 hole64_start = pc_get_cxl_range_end(pcms);
1150 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1151 pc_get_device_memory_range(pcms, &hole64_start, &size);
1152 if (!pcmc->broken_reserved_end) {
1153 hole64_start += size;
1154 }
1155 } else {
1156 hole64_start = pc_above_4g_end(pcms);
1157 }
1158
1159 return ROUND_UP(hole64_start, 1 * GiB);
1160 }
1161
1162 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1163 {
1164 DeviceState *dev = NULL;
1165
1166 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1167 if (pci_bus) {
1168 PCIDevice *pcidev = pci_vga_init(pci_bus);
1169 dev = pcidev ? &pcidev->qdev : NULL;
1170 } else if (isa_bus) {
1171 ISADevice *isadev = isa_vga_init(isa_bus);
1172 dev = isadev ? DEVICE(isadev) : NULL;
1173 }
1174 rom_reset_order_override();
1175 return dev;
1176 }
1177
1178 static const MemoryRegionOps ioport80_io_ops = {
1179 .write = ioport80_write,
1180 .read = ioport80_read,
1181 .endianness = DEVICE_NATIVE_ENDIAN,
1182 .impl = {
1183 .min_access_size = 1,
1184 .max_access_size = 1,
1185 },
1186 };
1187
1188 static const MemoryRegionOps ioportF0_io_ops = {
1189 .write = ioportF0_write,
1190 .read = ioportF0_read,
1191 .endianness = DEVICE_NATIVE_ENDIAN,
1192 .impl = {
1193 .min_access_size = 1,
1194 .max_access_size = 1,
1195 },
1196 };
1197
1198 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1199 bool create_i8042, bool no_vmport)
1200 {
1201 int i;
1202 DriveInfo *fd[MAX_FD];
1203 qemu_irq *a20_line;
1204 ISADevice *fdc, *i8042, *port92, *vmmouse;
1205
1206 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1207 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1208
1209 for (i = 0; i < MAX_FD; i++) {
1210 fd[i] = drive_get(IF_FLOPPY, 0, i);
1211 create_fdctrl |= !!fd[i];
1212 }
1213 if (create_fdctrl) {
1214 fdc = isa_new(TYPE_ISA_FDC);
1215 if (fdc) {
1216 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1217 isa_fdc_init_drives(fdc, fd);
1218 }
1219 }
1220
1221 if (!create_i8042) {
1222 return;
1223 }
1224
1225 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1226 if (!no_vmport) {
1227 isa_create_simple(isa_bus, TYPE_VMPORT);
1228 vmmouse = isa_try_new("vmmouse");
1229 } else {
1230 vmmouse = NULL;
1231 }
1232 if (vmmouse) {
1233 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1234 &error_abort);
1235 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1236 }
1237 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1238
1239 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1240 i8042_setup_a20_line(i8042, a20_line[0]);
1241 qdev_connect_gpio_out_named(DEVICE(port92),
1242 PORT92_A20_LINE, 0, a20_line[1]);
1243 g_free(a20_line);
1244 }
1245
1246 void pc_basic_device_init(struct PCMachineState *pcms,
1247 ISABus *isa_bus, qemu_irq *gsi,
1248 ISADevice **rtc_state,
1249 bool create_fdctrl,
1250 uint32_t hpet_irqs)
1251 {
1252 int i;
1253 DeviceState *hpet = NULL;
1254 int pit_isa_irq = 0;
1255 qemu_irq pit_alt_irq = NULL;
1256 qemu_irq rtc_irq = NULL;
1257 ISADevice *pit = NULL;
1258 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1259 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1260 X86MachineState *x86ms = X86_MACHINE(pcms);
1261
1262 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1263 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1264
1265 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1266 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1267
1268 /*
1269 * Check if an HPET shall be created.
1270 *
1271 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1272 * when the HPET wants to take over. Thus we have to disable the latter.
1273 */
1274 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1275 kvm_has_pit_state2())) {
1276 hpet = qdev_try_new(TYPE_HPET);
1277 if (!hpet) {
1278 error_report("couldn't create HPET device");
1279 exit(1);
1280 }
1281 /*
1282 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1283 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1284 * IRQ2.
1285 */
1286 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1287 HPET_INTCAP, NULL);
1288 if (!compat) {
1289 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1290 }
1291 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1292 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1293
1294 for (i = 0; i < GSI_NUM_PINS; i++) {
1295 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1296 }
1297 pit_isa_irq = -1;
1298 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1299 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1300 }
1301 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1302
1303 qemu_register_boot_set(pc_boot_set, *rtc_state);
1304
1305 if (!xen_enabled() &&
1306 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1307 if (kvm_pit_in_kernel()) {
1308 pit = kvm_pit_init(isa_bus, 0x40);
1309 } else {
1310 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1311 }
1312 if (hpet) {
1313 /* connect PIT to output control line of the HPET */
1314 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1315 }
1316 pcspk_init(pcms->pcspk, isa_bus, pit);
1317 }
1318
1319 i8257_dma_init(isa_bus, 0);
1320
1321 /* Super I/O */
1322 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1323 pcms->vmport != ON_OFF_AUTO_ON);
1324 }
1325
1326 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1327 {
1328 int i;
1329
1330 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1331 for (i = 0; i < nb_nics; i++) {
1332 NICInfo *nd = &nd_table[i];
1333 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1334
1335 if (g_str_equal(model, "ne2k_isa")) {
1336 pc_init_ne2k_isa(isa_bus, nd);
1337 } else {
1338 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1339 }
1340 }
1341 rom_reset_order_override();
1342 }
1343
1344 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1345 {
1346 qemu_irq *i8259;
1347
1348 if (kvm_pic_in_kernel()) {
1349 i8259 = kvm_i8259_init(isa_bus);
1350 } else if (xen_enabled()) {
1351 i8259 = xen_interrupt_controller_init();
1352 } else {
1353 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1354 }
1355
1356 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1357 i8259_irqs[i] = i8259[i];
1358 }
1359
1360 g_free(i8259);
1361 }
1362
1363 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1364 Error **errp)
1365 {
1366 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1367 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1368 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1369 const MachineState *ms = MACHINE(hotplug_dev);
1370 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1371 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1372 Error *local_err = NULL;
1373
1374 /*
1375 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1376 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1377 * addition to cover this case.
1378 */
1379 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1380 error_setg(errp,
1381 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1382 return;
1383 }
1384
1385 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1386 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1387 return;
1388 }
1389
1390 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1391 if (local_err) {
1392 error_propagate(errp, local_err);
1393 return;
1394 }
1395
1396 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1397 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1398 }
1399
1400 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1401 DeviceState *dev, Error **errp)
1402 {
1403 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1404 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1405 MachineState *ms = MACHINE(hotplug_dev);
1406 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1407
1408 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1409
1410 if (is_nvdimm) {
1411 nvdimm_plug(ms->nvdimms_state);
1412 }
1413
1414 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1415 }
1416
1417 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1418 DeviceState *dev, Error **errp)
1419 {
1420 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1421
1422 /*
1423 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1424 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1425 * addition to cover this case.
1426 */
1427 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1428 error_setg(errp,
1429 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1430 return;
1431 }
1432
1433 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1434 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1435 return;
1436 }
1437
1438 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1439 errp);
1440 }
1441
1442 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1443 DeviceState *dev, Error **errp)
1444 {
1445 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1446 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1447 Error *local_err = NULL;
1448
1449 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1450 if (local_err) {
1451 goto out;
1452 }
1453
1454 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1455 qdev_unrealize(dev);
1456 out:
1457 error_propagate(errp, local_err);
1458 }
1459
1460 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1461 DeviceState *dev, Error **errp)
1462 {
1463 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1464 Error *local_err = NULL;
1465
1466 if (!hotplug_dev2 && dev->hotplugged) {
1467 /*
1468 * Without a bus hotplug handler, we cannot control the plug/unplug
1469 * order. We should never reach this point when hotplugging on x86,
1470 * however, better add a safety net.
1471 */
1472 error_setg(errp, "hotplug of virtio based memory devices not supported"
1473 " on this bus.");
1474 return;
1475 }
1476 /*
1477 * First, see if we can plug this memory device at all. If that
1478 * succeeds, branch of to the actual hotplug handler.
1479 */
1480 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1481 &local_err);
1482 if (!local_err && hotplug_dev2) {
1483 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1484 }
1485 error_propagate(errp, local_err);
1486 }
1487
1488 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1489 DeviceState *dev, Error **errp)
1490 {
1491 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1492 Error *local_err = NULL;
1493
1494 /*
1495 * Plug the memory device first and then branch off to the actual
1496 * hotplug handler. If that one fails, we can easily undo the memory
1497 * device bits.
1498 */
1499 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1500 if (hotplug_dev2) {
1501 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1502 if (local_err) {
1503 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1504 }
1505 }
1506 error_propagate(errp, local_err);
1507 }
1508
1509 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1510 DeviceState *dev, Error **errp)
1511 {
1512 /* We don't support hot unplug of virtio based memory devices */
1513 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1514 }
1515
1516 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1517 DeviceState *dev, Error **errp)
1518 {
1519 /* We don't support hot unplug of virtio based memory devices */
1520 }
1521
1522 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1523 DeviceState *dev, Error **errp)
1524 {
1525 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1526 pc_memory_pre_plug(hotplug_dev, dev, errp);
1527 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1528 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1529 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1530 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1531 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1532 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1533 /* Declare the APIC range as the reserved MSI region */
1534 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1535 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1536
1537 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1538 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1539 resv_prop_str, errp);
1540 g_free(resv_prop_str);
1541 }
1542
1543 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1544 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1545 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1546
1547 if (pcms->iommu) {
1548 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1549 "for x86 yet.");
1550 return;
1551 }
1552 pcms->iommu = dev;
1553 }
1554 }
1555
1556 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1557 DeviceState *dev, Error **errp)
1558 {
1559 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1560 pc_memory_plug(hotplug_dev, dev, errp);
1561 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1562 x86_cpu_plug(hotplug_dev, dev, errp);
1563 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1564 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1565 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1566 }
1567 }
1568
1569 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1570 DeviceState *dev, Error **errp)
1571 {
1572 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1573 pc_memory_unplug_request(hotplug_dev, dev, errp);
1574 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1575 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1576 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1577 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1578 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1579 } else {
1580 error_setg(errp, "acpi: device unplug request for not supported device"
1581 " type: %s", object_get_typename(OBJECT(dev)));
1582 }
1583 }
1584
1585 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1586 DeviceState *dev, Error **errp)
1587 {
1588 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1589 pc_memory_unplug(hotplug_dev, dev, errp);
1590 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1591 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1592 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1593 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1594 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1595 } else {
1596 error_setg(errp, "acpi: device unplug for not supported device"
1597 " type: %s", object_get_typename(OBJECT(dev)));
1598 }
1599 }
1600
1601 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1602 DeviceState *dev)
1603 {
1604 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1605 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1606 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1607 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
1608 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1609 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1610 return HOTPLUG_HANDLER(machine);
1611 }
1612
1613 return NULL;
1614 }
1615
1616 static void
1617 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1618 const char *name, void *opaque,
1619 Error **errp)
1620 {
1621 MachineState *ms = MACHINE(obj);
1622 int64_t value = 0;
1623
1624 if (ms->device_memory) {
1625 value = memory_region_size(&ms->device_memory->mr);
1626 }
1627
1628 visit_type_int(v, name, &value, errp);
1629 }
1630
1631 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1632 void *opaque, Error **errp)
1633 {
1634 PCMachineState *pcms = PC_MACHINE(obj);
1635 OnOffAuto vmport = pcms->vmport;
1636
1637 visit_type_OnOffAuto(v, name, &vmport, errp);
1638 }
1639
1640 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1641 void *opaque, Error **errp)
1642 {
1643 PCMachineState *pcms = PC_MACHINE(obj);
1644
1645 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1646 }
1647
1648 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1649 {
1650 PCMachineState *pcms = PC_MACHINE(obj);
1651
1652 return pcms->smbus_enabled;
1653 }
1654
1655 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1656 {
1657 PCMachineState *pcms = PC_MACHINE(obj);
1658
1659 pcms->smbus_enabled = value;
1660 }
1661
1662 static bool pc_machine_get_sata(Object *obj, Error **errp)
1663 {
1664 PCMachineState *pcms = PC_MACHINE(obj);
1665
1666 return pcms->sata_enabled;
1667 }
1668
1669 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1670 {
1671 PCMachineState *pcms = PC_MACHINE(obj);
1672
1673 pcms->sata_enabled = value;
1674 }
1675
1676 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1677 {
1678 PCMachineState *pcms = PC_MACHINE(obj);
1679
1680 return pcms->hpet_enabled;
1681 }
1682
1683 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1684 {
1685 PCMachineState *pcms = PC_MACHINE(obj);
1686
1687 pcms->hpet_enabled = value;
1688 }
1689
1690 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1691 {
1692 PCMachineState *pcms = PC_MACHINE(obj);
1693
1694 return pcms->i8042_enabled;
1695 }
1696
1697 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1698 {
1699 PCMachineState *pcms = PC_MACHINE(obj);
1700
1701 pcms->i8042_enabled = value;
1702 }
1703
1704 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1705 {
1706 PCMachineState *pcms = PC_MACHINE(obj);
1707
1708 return pcms->default_bus_bypass_iommu;
1709 }
1710
1711 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1712 Error **errp)
1713 {
1714 PCMachineState *pcms = PC_MACHINE(obj);
1715
1716 pcms->default_bus_bypass_iommu = value;
1717 }
1718
1719 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1720 void *opaque, Error **errp)
1721 {
1722 PCMachineState *pcms = PC_MACHINE(obj);
1723 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1724
1725 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1726 }
1727
1728 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1729 void *opaque, Error **errp)
1730 {
1731 PCMachineState *pcms = PC_MACHINE(obj);
1732
1733 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1734 }
1735
1736 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1737 const char *name, void *opaque,
1738 Error **errp)
1739 {
1740 PCMachineState *pcms = PC_MACHINE(obj);
1741 uint64_t value = pcms->max_ram_below_4g;
1742
1743 visit_type_size(v, name, &value, errp);
1744 }
1745
1746 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1747 const char *name, void *opaque,
1748 Error **errp)
1749 {
1750 PCMachineState *pcms = PC_MACHINE(obj);
1751 uint64_t value;
1752
1753 if (!visit_type_size(v, name, &value, errp)) {
1754 return;
1755 }
1756 if (value > 4 * GiB) {
1757 error_setg(errp,
1758 "Machine option 'max-ram-below-4g=%"PRIu64
1759 "' expects size less than or equal to 4G", value);
1760 return;
1761 }
1762
1763 if (value < 1 * MiB) {
1764 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1765 "BIOS may not work with less than 1MiB", value);
1766 }
1767
1768 pcms->max_ram_below_4g = value;
1769 }
1770
1771 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1772 const char *name, void *opaque,
1773 Error **errp)
1774 {
1775 PCMachineState *pcms = PC_MACHINE(obj);
1776 uint64_t value = pcms->max_fw_size;
1777
1778 visit_type_size(v, name, &value, errp);
1779 }
1780
1781 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1782 const char *name, void *opaque,
1783 Error **errp)
1784 {
1785 PCMachineState *pcms = PC_MACHINE(obj);
1786 Error *error = NULL;
1787 uint64_t value;
1788
1789 visit_type_size(v, name, &value, &error);
1790 if (error) {
1791 error_propagate(errp, error);
1792 return;
1793 }
1794
1795 /*
1796 * We don't have a theoretically justifiable exact lower bound on the base
1797 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1798 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1799 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1800 * size.
1801 */
1802 if (value > 16 * MiB) {
1803 error_setg(errp,
1804 "User specified max allowed firmware size %" PRIu64 " is "
1805 "greater than 16MiB. If combined firwmare size exceeds "
1806 "16MiB the system may not boot, or experience intermittent"
1807 "stability issues.",
1808 value);
1809 return;
1810 }
1811
1812 pcms->max_fw_size = value;
1813 }
1814
1815
1816 static void pc_machine_initfn(Object *obj)
1817 {
1818 PCMachineState *pcms = PC_MACHINE(obj);
1819
1820 #ifdef CONFIG_VMPORT
1821 pcms->vmport = ON_OFF_AUTO_AUTO;
1822 #else
1823 pcms->vmport = ON_OFF_AUTO_OFF;
1824 #endif /* CONFIG_VMPORT */
1825 pcms->max_ram_below_4g = 0; /* use default */
1826 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1827
1828 /* acpi build is enabled by default if machine supports it */
1829 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1830 pcms->smbus_enabled = true;
1831 pcms->sata_enabled = true;
1832 pcms->i8042_enabled = true;
1833 pcms->max_fw_size = 8 * MiB;
1834 #ifdef CONFIG_HPET
1835 pcms->hpet_enabled = true;
1836 #endif
1837 pcms->default_bus_bypass_iommu = false;
1838
1839 pc_system_flash_create(pcms);
1840 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1841 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1842 OBJECT(pcms->pcspk), "audiodev");
1843 cxl_machine_init(obj, &pcms->cxl_devices_state);
1844 }
1845
1846 static void pc_machine_reset(MachineState *machine)
1847 {
1848 CPUState *cs;
1849 X86CPU *cpu;
1850
1851 qemu_devices_reset();
1852
1853 /* Reset APIC after devices have been reset to cancel
1854 * any changes that qemu_devices_reset() might have done.
1855 */
1856 CPU_FOREACH(cs) {
1857 cpu = X86_CPU(cs);
1858
1859 if (cpu->apic_state) {
1860 device_legacy_reset(cpu->apic_state);
1861 }
1862 }
1863 }
1864
1865 static void pc_machine_wakeup(MachineState *machine)
1866 {
1867 cpu_synchronize_all_states();
1868 pc_machine_reset(machine);
1869 cpu_synchronize_all_post_reset();
1870 }
1871
1872 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1873 {
1874 X86IOMMUState *iommu = x86_iommu_get_default();
1875 IntelIOMMUState *intel_iommu;
1876
1877 if (iommu &&
1878 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1879 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1880 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1881 if (!intel_iommu->caching_mode) {
1882 error_setg(errp, "Device assignment is not allowed without "
1883 "enabling caching-mode=on for Intel IOMMU.");
1884 return false;
1885 }
1886 }
1887
1888 return true;
1889 }
1890
1891 static void pc_machine_class_init(ObjectClass *oc, void *data)
1892 {
1893 MachineClass *mc = MACHINE_CLASS(oc);
1894 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1895 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1896
1897 pcmc->pci_enabled = true;
1898 pcmc->has_acpi_build = true;
1899 pcmc->rsdp_in_ram = true;
1900 pcmc->smbios_defaults = true;
1901 pcmc->smbios_uuid_encoded = true;
1902 pcmc->gigabyte_align = true;
1903 pcmc->has_reserved_memory = true;
1904 pcmc->kvmclock_enabled = true;
1905 pcmc->enforce_aligned_dimm = true;
1906 pcmc->enforce_amd_1tb_hole = true;
1907 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1908 * to be used at the moment, 32K should be enough for a while. */
1909 pcmc->acpi_data_size = 0x20000 + 0x8000;
1910 pcmc->pvh_enabled = true;
1911 pcmc->kvmclock_create_always = true;
1912 assert(!mc->get_hotplug_handler);
1913 mc->get_hotplug_handler = pc_get_hotplug_handler;
1914 mc->hotplug_allowed = pc_hotplug_allowed;
1915 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1916 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1917 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1918 mc->auto_enable_numa_with_memhp = true;
1919 mc->auto_enable_numa_with_memdev = true;
1920 mc->has_hotpluggable_cpus = true;
1921 mc->default_boot_order = "cad";
1922 mc->block_default_type = IF_IDE;
1923 mc->max_cpus = 255;
1924 mc->reset = pc_machine_reset;
1925 mc->wakeup = pc_machine_wakeup;
1926 hc->pre_plug = pc_machine_device_pre_plug_cb;
1927 hc->plug = pc_machine_device_plug_cb;
1928 hc->unplug_request = pc_machine_device_unplug_request_cb;
1929 hc->unplug = pc_machine_device_unplug_cb;
1930 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1931 mc->nvdimm_supported = true;
1932 mc->smp_props.dies_supported = true;
1933 mc->default_ram_id = "pc.ram";
1934
1935 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1936 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1937 NULL, NULL);
1938 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1939 "Maximum ram below the 4G boundary (32bit boundary)");
1940
1941 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1942 pc_machine_get_device_memory_region_size, NULL,
1943 NULL, NULL);
1944
1945 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1946 pc_machine_get_vmport, pc_machine_set_vmport,
1947 NULL, NULL);
1948 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1949 "Enable vmport (pc & q35)");
1950
1951 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1952 pc_machine_get_smbus, pc_machine_set_smbus);
1953 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1954 "Enable/disable system management bus");
1955
1956 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1957 pc_machine_get_sata, pc_machine_set_sata);
1958 object_class_property_set_description(oc, PC_MACHINE_SATA,
1959 "Enable/disable Serial ATA bus");
1960
1961 object_class_property_add_bool(oc, "hpet",
1962 pc_machine_get_hpet, pc_machine_set_hpet);
1963 object_class_property_set_description(oc, "hpet",
1964 "Enable/disable high precision event timer emulation");
1965
1966 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1967 pc_machine_get_i8042, pc_machine_set_i8042);
1968
1969 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1970 pc_machine_get_default_bus_bypass_iommu,
1971 pc_machine_set_default_bus_bypass_iommu);
1972
1973 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1974 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1975 NULL, NULL);
1976 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1977 "Maximum combined firmware size");
1978
1979 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1980 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1981 NULL, NULL);
1982 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1983 "SMBIOS Entry Point type [32, 64]");
1984 }
1985
1986 static const TypeInfo pc_machine_info = {
1987 .name = TYPE_PC_MACHINE,
1988 .parent = TYPE_X86_MACHINE,
1989 .abstract = true,
1990 .instance_size = sizeof(PCMachineState),
1991 .instance_init = pc_machine_initfn,
1992 .class_size = sizeof(PCMachineClass),
1993 .class_init = pc_machine_class_init,
1994 .interfaces = (InterfaceInfo[]) {
1995 { TYPE_HOTPLUG_HANDLER },
1996 { }
1997 },
1998 };
1999
2000 static void pc_machine_register_types(void)
2001 {
2002 type_register_static(&pc_machine_info);
2003 }
2004
2005 type_init(pc_machine_register_types)
AR7 emulation for QEMU