hw/timer/cadence_ttc.c

   1 /*
   2  * Xilinx Zynq cadence TTC model
   3  *
   4  * Copyright (c) 2011 Xilinx Inc.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
   6  * Copyright (c) 2012 PetaLogix Pty Ltd.
   7  * Written By Haibing Ma
   8  *            M. Habib
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "hw/sysbus.h"
  20 #include "qemu/timer.h"
  21
  22 #ifdef CADENCE_TTC_ERR_DEBUG
  23 #define DB_PRINT(...) do { \
  24     fprintf(stderr,  ": %s: ", __func__); \
  25     fprintf(stderr, ## __VA_ARGS__); \
  26     } while (0);
  27 #else
  28     #define DB_PRINT(...)
  29 #endif
  30
  31 #define COUNTER_INTR_IV     0x00000001
  32 #define COUNTER_INTR_M1     0x00000002
  33 #define COUNTER_INTR_M2     0x00000004
  34 #define COUNTER_INTR_M3     0x00000008
  35 #define COUNTER_INTR_OV     0x00000010
  36 #define COUNTER_INTR_EV     0x00000020
  37
  38 #define COUNTER_CTRL_DIS    0x00000001
  39 #define COUNTER_CTRL_INT    0x00000002
  40 #define COUNTER_CTRL_DEC    0x00000004
  41 #define COUNTER_CTRL_MATCH  0x00000008
  42 #define COUNTER_CTRL_RST    0x00000010
  43
  44 #define CLOCK_CTRL_PS_EN    0x00000001
  45 #define CLOCK_CTRL_PS_V     0x0000001e
  46
  47 typedef struct {
  48     QEMUTimer *timer;
  49     int freq;
  50
  51     uint32_t reg_clock;
  52     uint32_t reg_count;
  53     uint32_t reg_value;
  54     uint16_t reg_interval;
  55     uint16_t reg_match[3];
  56     uint32_t reg_intr;
  57     uint32_t reg_intr_en;
  58     uint32_t reg_event_ctrl;
  59     uint32_t reg_event;
  60
  61     uint64_t cpu_time;
  62     unsigned int cpu_time_valid;
  63
  64     qemu_irq irq;
  65 } CadenceTimerState;
  66
  67 #define TYPE_CADENCE_TTC "cadence_ttc"
  68 #define CADENCE_TTC(obj) \
  69     OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC)
  70
  71 typedef struct CadenceTTCState {
  72     SysBusDevice parent_obj;
  73
  74     MemoryRegion iomem;
  75     CadenceTimerState timer[3];
  76 } CadenceTTCState;
  77
  78 static void cadence_timer_update(CadenceTimerState *s)
  79 {
  80     qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
  81 }
  82
  83 static CadenceTimerState *cadence_timer_from_addr(void *opaque,
  84                                         hwaddr offset)
  85 {
  86     unsigned int index;
  87     CadenceTTCState *s = (CadenceTTCState *)opaque;
  88
  89     index = (offset >> 2) % 3;
  90
  91     return &s->timer[index];
  92 }
  93
  94 static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t timer_steps)
  95 {
  96     /* timer_steps has max value of 0x100000000. double check it
  97      * (or overflow can happen below) */
  98     assert(timer_steps <= 1ULL << 32);
  99
 100     uint64_t r = timer_steps * 1000000000ULL;
 101     if (s->reg_clock & CLOCK_CTRL_PS_EN) {
 102         r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
 103     } else {
 104         r >>= 16;
 105     }
 106     r /= (uint64_t)s->freq;
 107     return r;
 108 }
 109
 110 static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns)
 111 {
 112     uint64_t to_divide = 1000000000ULL;
 113
 114     uint64_t r = ns;
 115      /* for very large intervals (> 8s) do some division first to stop
 116       * overflow (costs some prescision) */
 117     while (r >= 8ULL << 30 && to_divide > 1) {
 118         r /= 1000;
 119         to_divide /= 1000;
 120     }
 121     r <<= 16;
 122     /* keep early-dividing as needed */
 123     while (r >= 8ULL << 30 && to_divide > 1) {
 124         r /= 1000;
 125         to_divide /= 1000;
 126     }
 127     r *= (uint64_t)s->freq;
 128     if (s->reg_clock & CLOCK_CTRL_PS_EN) {
 129         r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
 130     }
 131
 132     r /= to_divide;
 133     return r;
 134 }
 135
 136 /* determine if x is in between a and b, exclusive of a, inclusive of b */
 137
 138 static inline int64_t is_between(int64_t x, int64_t a, int64_t b)
 139 {
 140     if (a < b) {
 141         return x > a && x <= b;
 142     }
 143     return x < a && x >= b;
 144 }
 145
 146 static void cadence_timer_run(CadenceTimerState *s)
 147 {
 148     int i;
 149     int64_t event_interval, next_value;
 150
 151     assert(s->cpu_time_valid); /* cadence_timer_sync must be called first */
 152
 153     if (s->reg_count & COUNTER_CTRL_DIS) {
 154         s->cpu_time_valid = 0;
 155         return;
 156     }
 157
 158     { /* figure out what's going to happen next (rollover or match) */
 159         int64_t interval = (uint64_t)((s->reg_count & COUNTER_CTRL_INT) ?
 160                 (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
 161         next_value = (s->reg_count & COUNTER_CTRL_DEC) ? -1ULL : interval;
 162         for (i = 0; i < 3; ++i) {
 163             int64_t cand = (uint64_t)s->reg_match[i] << 16;
 164             if (is_between(cand, (uint64_t)s->reg_value, next_value)) {
 165                 next_value = cand;
 166             }
 167         }
 168     }
 169     DB_PRINT("next timer event value: %09llx\n",
 170             (unsigned long long)next_value);
 171
 172     event_interval = next_value - (int64_t)s->reg_value;
 173     event_interval = (event_interval < 0) ? -event_interval : event_interval;
 174
 175     timer_mod(s->timer, s->cpu_time +
 176                 cadence_timer_get_ns(s, event_interval));
 177 }
 178
 179 static void cadence_timer_sync(CadenceTimerState *s)
 180 {
 181     int i;
 182     int64_t r, x;
 183     int64_t interval = ((s->reg_count & COUNTER_CTRL_INT) ?
 184             (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
 185     uint64_t old_time = s->cpu_time;
 186
 187     s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 188     DB_PRINT("cpu time: %lld ns\n", (long long)old_time);
 189
 190     if (!s->cpu_time_valid || old_time == s->cpu_time) {
 191         s->cpu_time_valid = 1;
 192         return;
 193     }
 194
 195     r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time);
 196     x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r);
 197
 198     for (i = 0; i < 3; ++i) {
 199         int64_t m = (int64_t)s->reg_match[i] << 16;
 200         if (m > interval) {
 201             continue;
 202         }
 203         /* check to see if match event has occurred. check m +/- interval
 204          * to account for match events in wrap around cases */
 205         if (is_between(m, s->reg_value, x) ||
 206             is_between(m + interval, s->reg_value, x) ||
 207             is_between(m - interval, s->reg_value, x)) {
 208             s->reg_intr |= (2 << i);
 209         }
 210     }
 211     while (x < 0) {
 212         x += interval;
 213     }
 214     s->reg_value = (uint32_t)(x % interval);
 215
 216     if (s->reg_value != x) {
 217         s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ?
 218             COUNTER_INTR_IV : COUNTER_INTR_OV;
 219     }
 220     cadence_timer_update(s);
 221 }
 222
 223 static void cadence_timer_tick(void *opaque)
 224 {
 225     CadenceTimerState *s = opaque;
 226
 227     DB_PRINT("\n");
 228     cadence_timer_sync(s);
 229     cadence_timer_run(s);
 230 }
 231
 232 static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset)
 233 {
 234     CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
 235     uint32_t value;
 236
 237     cadence_timer_sync(s);
 238     cadence_timer_run(s);
 239
 240     switch (offset) {
 241     case 0x00: /* clock control */
 242     case 0x04:
 243     case 0x08:
 244         return s->reg_clock;
 245
 246     case 0x0c: /* counter control */
 247     case 0x10:
 248     case 0x14:
 249         return s->reg_count;
 250
 251     case 0x18: /* counter value */
 252     case 0x1c:
 253     case 0x20:
 254         return (uint16_t)(s->reg_value >> 16);
 255
 256     case 0x24: /* reg_interval counter */
 257     case 0x28:
 258     case 0x2c:
 259         return s->reg_interval;
 260
 261     case 0x30: /* match 1 counter */
 262     case 0x34:
 263     case 0x38:
 264         return s->reg_match[0];
 265
 266     case 0x3c: /* match 2 counter */
 267     case 0x40:
 268     case 0x44:
 269         return s->reg_match[1];
 270
 271     case 0x48: /* match 3 counter */
 272     case 0x4c:
 273     case 0x50:
 274         return s->reg_match[2];
 275
 276     case 0x54: /* interrupt register */
 277     case 0x58:
 278     case 0x5c:
 279         /* cleared after read */
 280         value = s->reg_intr;
 281         s->reg_intr = 0;
 282         cadence_timer_update(s);
 283         return value;
 284
 285     case 0x60: /* interrupt enable */
 286     case 0x64:
 287     case 0x68:
 288         return s->reg_intr_en;
 289
 290     case 0x6c:
 291     case 0x70:
 292     case 0x74:
 293         return s->reg_event_ctrl;
 294
 295     case 0x78:
 296     case 0x7c:
 297     case 0x80:
 298         return s->reg_event;
 299
 300     default:
 301         return 0;
 302     }
 303 }
 304
 305 static uint64_t cadence_ttc_read(void *opaque, hwaddr offset,
 306     unsigned size)
 307 {
 308     uint32_t ret = cadence_ttc_read_imp(opaque, offset);
 309
 310     DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret);
 311     return ret;
 312 }
 313
 314 static void cadence_ttc_write(void *opaque, hwaddr offset,
 315         uint64_t value, unsigned size)
 316 {
 317     CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
 318
 319     DB_PRINT("addr: %08x data %08x\n", (unsigned)offset, (unsigned)value);
 320
 321     cadence_timer_sync(s);
 322
 323     switch (offset) {
 324     case 0x00: /* clock control */
 325     case 0x04:
 326     case 0x08:
 327         s->reg_clock = value & 0x3F;
 328         break;
 329
 330     case 0x0c: /* counter control */
 331     case 0x10:
 332     case 0x14:
 333         if (value & COUNTER_CTRL_RST) {
 334             s->reg_value = 0;
 335         }
 336         s->reg_count = value & 0x3f & ~COUNTER_CTRL_RST;
 337         break;
 338
 339     case 0x24: /* interval register */
 340     case 0x28:
 341     case 0x2c:
 342         s->reg_interval = value & 0xffff;
 343         break;
 344
 345     case 0x30: /* match register */
 346     case 0x34:
 347     case 0x38:
 348         s->reg_match[0] = value & 0xffff;
 349         break;
 350
 351     case 0x3c: /* match register */
 352     case 0x40:
 353     case 0x44:
 354         s->reg_match[1] = value & 0xffff;
 355         break;
 356
 357     case 0x48: /* match register */
 358     case 0x4c:
 359     case 0x50:
 360         s->reg_match[2] = value & 0xffff;
 361         break;
 362
 363     case 0x54: /* interrupt register */
 364     case 0x58:
 365     case 0x5c:
 366         break;
 367
 368     case 0x60: /* interrupt enable */
 369     case 0x64:
 370     case 0x68:
 371         s->reg_intr_en = value & 0x3f;
 372         break;
 373
 374     case 0x6c: /* event control */
 375     case 0x70:
 376     case 0x74:
 377         s->reg_event_ctrl = value & 0x07;
 378         break;
 379
 380     default:
 381         return;
 382     }
 383
 384     cadence_timer_run(s);
 385     cadence_timer_update(s);
 386 }
 387
 388 static const MemoryRegionOps cadence_ttc_ops = {
 389     .read = cadence_ttc_read,
 390     .write = cadence_ttc_write,
 391     .endianness = DEVICE_NATIVE_ENDIAN,
 392 };
 393
 394 static void cadence_timer_reset(CadenceTimerState *s)
 395 {
 396    s->reg_count = 0x21;
 397 }
 398
 399 static void cadence_timer_init(uint32_t freq, CadenceTimerState *s)
 400 {
 401     memset(s, 0, sizeof(CadenceTimerState));
 402     s->freq = freq;
 403
 404     cadence_timer_reset(s);
 405
 406     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s);
 407 }
 408
 409 static void cadence_ttc_init(Object *obj)
 410 {
 411     CadenceTTCState *s = CADENCE_TTC(obj);
 412     int i;
 413
 414     for (i = 0; i < 3; ++i) {
 415         cadence_timer_init(133000000, &s->timer[i]);
 416         sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->timer[i].irq);
 417     }
 418
 419     memory_region_init_io(&s->iomem, obj, &cadence_ttc_ops, s,
 420                           "timer", 0x1000);
 421     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 422 }
 423
 424 static void cadence_timer_pre_save(void *opaque)
 425 {
 426     cadence_timer_sync((CadenceTimerState *)opaque);
 427 }
 428
 429 static int cadence_timer_post_load(void *opaque, int version_id)
 430 {
 431     CadenceTimerState *s = opaque;
 432
 433     s->cpu_time_valid = 0;
 434     cadence_timer_sync(s);
 435     cadence_timer_run(s);
 436     cadence_timer_update(s);
 437     return 0;
 438 }
 439
 440 static const VMStateDescription vmstate_cadence_timer = {
 441     .name = "cadence_timer",
 442     .version_id = 1,
 443     .minimum_version_id = 1,
 444     .pre_save = cadence_timer_pre_save,
 445     .post_load = cadence_timer_post_load,
 446     .fields = (VMStateField[]) {
 447         VMSTATE_UINT32(reg_clock, CadenceTimerState),
 448         VMSTATE_UINT32(reg_count, CadenceTimerState),
 449         VMSTATE_UINT32(reg_value, CadenceTimerState),
 450         VMSTATE_UINT16(reg_interval, CadenceTimerState),
 451         VMSTATE_UINT16_ARRAY(reg_match, CadenceTimerState, 3),
 452         VMSTATE_UINT32(reg_intr, CadenceTimerState),
 453         VMSTATE_UINT32(reg_intr_en, CadenceTimerState),
 454         VMSTATE_UINT32(reg_event_ctrl, CadenceTimerState),
 455         VMSTATE_UINT32(reg_event, CadenceTimerState),
 456         VMSTATE_END_OF_LIST()
 457     }
 458 };
 459
 460 static const VMStateDescription vmstate_cadence_ttc = {
 461     .name = "cadence_TTC",
 462     .version_id = 1,
 463     .minimum_version_id = 1,
 464     .fields = (VMStateField[]) {
 465         VMSTATE_STRUCT_ARRAY(timer, CadenceTTCState, 3, 0,
 466                             vmstate_cadence_timer,
 467                             CadenceTimerState),
 468         VMSTATE_END_OF_LIST()
 469     }
 470 };
 471
 472 static void cadence_ttc_class_init(ObjectClass *klass, void *data)
 473 {
 474     DeviceClass *dc = DEVICE_CLASS(klass);
 475
 476     dc->vmsd = &vmstate_cadence_ttc;
 477 }
 478
 479 static const TypeInfo cadence_ttc_info = {
 480     .name  = TYPE_CADENCE_TTC,
 481     .parent = TYPE_SYS_BUS_DEVICE,
 482     .instance_size  = sizeof(CadenceTTCState),
 483     .instance_init = cadence_ttc_init,
 484     .class_init = cadence_ttc_class_init,
 485 };
 486
 487 static void cadence_ttc_register_types(void)
 488 {
 489     type_register_static(&cadence_ttc_info);
 490 }
 491
 492 type_init(cadence_ttc_register_types)