hw/ppc/e500.c

   1 /*
   2  * QEMU PowerPC e500-based platforms
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "e500.h"
  20 #include "e500-ccsr.h"
  21 #include "net/net.h"
  22 #include "qemu/config-file.h"
  23 #include "hw/hw.h"
  24 #include "hw/char/serial.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/kvm.h"
  29 #include "kvm_ppc.h"
  30 #include "sysemu/device_tree.h"
  31 #include "hw/ppc/openpic.h"
  32 #include "hw/ppc/ppc.h"
  33 #include "hw/loader.h"
  34 #include "elf.h"
  35 #include "hw/sysbus.h"
  36 #include "exec/address-spaces.h"
  37 #include "qemu/host-utils.h"
  38 #include "hw/pci-host/ppce500.h"
  39
  40 #define EPAPR_MAGIC                (0x45504150)
  41 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  42 #define DTC_LOAD_PAD               0x1800000
  43 #define DTC_PAD_MASK               0xFFFFF
  44 #define DTB_MAX_SIZE               (8 * 1024 * 1024)
  45 #define INITRD_LOAD_PAD            0x2000000
  46 #define INITRD_PAD_MASK            0xFFFFFF
  47
  48 #define RAM_SIZES_ALIGN            (64UL << 20)
  49
  50 /* TODO: parameterize */
  51 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
  52 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
  53 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
  54 #define MPC8544_MSI_REGS_OFFSET   0x41600ULL
  55 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
  56 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
  57 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
  58 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + \
  59                                     MPC8544_PCI_REGS_OFFSET)
  60 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
  61 #define MPC8544_PCI_IO             0xE1000000ULL
  62 #define MPC8544_UTIL_OFFSET        0xe0000ULL
  63 #define MPC8544_SPIN_BASE          0xEF000000ULL
  64
  65 struct boot_info
  66 {
  67     uint32_t dt_base;
  68     uint32_t dt_size;
  69     uint32_t entry;
  70 };
  71
  72 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
  73                                 int nr_slots, int *len)
  74 {
  75     int i = 0;
  76     int slot;
  77     int pci_irq;
  78     int host_irq;
  79     int last_slot = first_slot + nr_slots;
  80     uint32_t *pci_map;
  81
  82     *len = nr_slots * 4 * 7 * sizeof(uint32_t);
  83     pci_map = g_malloc(*len);
  84
  85     for (slot = first_slot; slot < last_slot; slot++) {
  86         for (pci_irq = 0; pci_irq < 4; pci_irq++) {
  87             pci_map[i++] = cpu_to_be32(slot << 11);
  88             pci_map[i++] = cpu_to_be32(0x0);
  89             pci_map[i++] = cpu_to_be32(0x0);
  90             pci_map[i++] = cpu_to_be32(pci_irq + 1);
  91             pci_map[i++] = cpu_to_be32(mpic);
  92             host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
  93             pci_map[i++] = cpu_to_be32(host_irq + 1);
  94             pci_map[i++] = cpu_to_be32(0x1);
  95         }
  96     }
  97
  98     assert((i * sizeof(uint32_t)) == *len);
  99
 100     return pci_map;
 101 }
 102
 103 static void dt_serial_create(void *fdt, unsigned long long offset,
 104                              const char *soc, const char *mpic,
 105                              const char *alias, int idx, bool defcon)
 106 {
 107     char ser[128];
 108
 109     snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
 110     qemu_fdt_add_subnode(fdt, ser);
 111     qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
 112     qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
 113     qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
 114     qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
 115     qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
 116     qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
 117     qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
 118     qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
 119
 120     if (defcon) {
 121         qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
 122     }
 123 }
 124
 125 static int ppce500_load_device_tree(MachineState *machine,
 126                                     PPCE500Params *params,
 127                                     hwaddr addr,
 128                                     hwaddr initrd_base,
 129                                     hwaddr initrd_size,
 130                                     hwaddr kernel_base,
 131                                     hwaddr kernel_size,
 132                                     bool dry_run)
 133 {
 134     CPUPPCState *env = first_cpu->env_ptr;
 135     int ret = -1;
 136     uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
 137     int fdt_size;
 138     void *fdt;
 139     uint8_t hypercall[16];
 140     uint32_t clock_freq = 400000000;
 141     uint32_t tb_freq = 400000000;
 142     int i;
 143     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
 144     char soc[128];
 145     char mpic[128];
 146     uint32_t mpic_ph;
 147     uint32_t msi_ph;
 148     char gutil[128];
 149     char pci[128];
 150     char msi[128];
 151     uint32_t *pci_map = NULL;
 152     int len;
 153     uint32_t pci_ranges[14] =
 154         {
 155             0x2000000, 0x0, 0xc0000000,
 156             0x0, 0xc0000000,
 157             0x0, 0x20000000,
 158
 159             0x1000000, 0x0, 0x0,
 160             0x0, 0xe1000000,
 161             0x0, 0x10000,
 162         };
 163     QemuOpts *machine_opts = qemu_get_machine_opts();
 164     const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
 165     const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
 166
 167     if (dtb_file) {
 168         char *filename;
 169         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
 170         if (!filename) {
 171             goto out;
 172         }
 173
 174         fdt = load_device_tree(filename, &fdt_size);
 175         if (!fdt) {
 176             goto out;
 177         }
 178         goto done;
 179     }
 180
 181     fdt = create_device_tree(&fdt_size);
 182     if (fdt == NULL) {
 183         goto out;
 184     }
 185
 186     /* Manipulate device tree in memory. */
 187     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
 188     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
 189
 190     qemu_fdt_add_subnode(fdt, "/memory");
 191     qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
 192     qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
 193                      sizeof(mem_reg_property));
 194
 195     qemu_fdt_add_subnode(fdt, "/chosen");
 196     if (initrd_size) {
 197         ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 198                                     initrd_base);
 199         if (ret < 0) {
 200             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 201         }
 202
 203         ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 204                                     (initrd_base + initrd_size));
 205         if (ret < 0) {
 206             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 207         }
 208
 209     }
 210
 211     if (kernel_base != -1ULL) {
 212         qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
 213                                      kernel_base >> 32, kernel_base,
 214                                      kernel_size >> 32, kernel_size);
 215     }
 216
 217     ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
 218                                       machine->kernel_cmdline);
 219     if (ret < 0)
 220         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 221
 222     if (kvm_enabled()) {
 223         /* Read out host's frequencies */
 224         clock_freq = kvmppc_get_clockfreq();
 225         tb_freq = kvmppc_get_tbfreq();
 226
 227         /* indicate KVM hypercall interface */
 228         qemu_fdt_add_subnode(fdt, "/hypervisor");
 229         qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
 230                                 "linux,kvm");
 231         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 232         qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
 233                          hypercall, sizeof(hypercall));
 234         /* if KVM supports the idle hcall, set property indicating this */
 235         if (kvmppc_get_hasidle(env)) {
 236             qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
 237         }
 238     }
 239
 240     /* Create CPU nodes */
 241     qemu_fdt_add_subnode(fdt, "/cpus");
 242     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
 243     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
 244
 245     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 246        the first node as boot node and be happy */
 247     for (i = smp_cpus - 1; i >= 0; i--) {
 248         CPUState *cpu;
 249         PowerPCCPU *pcpu;
 250         char cpu_name[128];
 251         uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
 252
 253         cpu = qemu_get_cpu(i);
 254         if (cpu == NULL) {
 255             continue;
 256         }
 257         env = cpu->env_ptr;
 258         pcpu = POWERPC_CPU(cpu);
 259
 260         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
 261                  ppc_get_vcpu_dt_id(pcpu));
 262         qemu_fdt_add_subnode(fdt, cpu_name);
 263         qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 264         qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 265         qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
 266         qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
 267                               ppc_get_vcpu_dt_id(pcpu));
 268         qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 269                               env->dcache_line_size);
 270         qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 271                               env->icache_line_size);
 272         qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 273         qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 274         qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 275         if (cpu->cpu_index) {
 276             qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
 277             qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
 278                                     "spin-table");
 279             qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
 280                                  cpu_release_addr);
 281         } else {
 282             qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
 283         }
 284     }
 285
 286     qemu_fdt_add_subnode(fdt, "/aliases");
 287     /* XXX These should go into their respective devices' code */
 288     snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
 289     qemu_fdt_add_subnode(fdt, soc);
 290     qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
 291     qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
 292                      sizeof(compatible_sb));
 293     qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
 294     qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
 295     qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
 296                            MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
 297                            MPC8544_CCSRBAR_SIZE);
 298     /* XXX should contain a reasonable value */
 299     qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
 300
 301     snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
 302     qemu_fdt_add_subnode(fdt, mpic);
 303     qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
 304     qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
 305     qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
 306                            0x40000);
 307     qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
 308     qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
 309     mpic_ph = qemu_fdt_alloc_phandle(fdt);
 310     qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
 311     qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
 312     qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
 313
 314     /*
 315      * We have to generate ser1 first, because Linux takes the first
 316      * device it finds in the dt as serial output device. And we generate
 317      * devices in reverse order to the dt.
 318      */
 319     if (serial_hds[1]) {
 320         dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
 321                          soc, mpic, "serial1", 1, false);
 322     }
 323
 324     if (serial_hds[0]) {
 325         dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
 326                          soc, mpic, "serial0", 0, true);
 327     }
 328
 329     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
 330              MPC8544_UTIL_OFFSET);
 331     qemu_fdt_add_subnode(fdt, gutil);
 332     qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
 333     qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
 334     qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 335
 336     snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
 337     qemu_fdt_add_subnode(fdt, msi);
 338     qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
 339     qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
 340     msi_ph = qemu_fdt_alloc_phandle(fdt);
 341     qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
 342     qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
 343     qemu_fdt_setprop_cells(fdt, msi, "interrupts",
 344         0xe0, 0x0,
 345         0xe1, 0x0,
 346         0xe2, 0x0,
 347         0xe3, 0x0,
 348         0xe4, 0x0,
 349         0xe5, 0x0,
 350         0xe6, 0x0,
 351         0xe7, 0x0);
 352     qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
 353     qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
 354
 355     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
 356     qemu_fdt_add_subnode(fdt, pci);
 357     qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
 358     qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
 359     qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
 360     qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
 361                            0x0, 0x7);
 362     pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
 363                              params->pci_first_slot, params->pci_nr_slots,
 364                              &len);
 365     qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
 366     qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
 367     qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
 368     qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
 369     for (i = 0; i < 14; i++) {
 370         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
 371     }
 372     qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
 373     qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
 374     qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
 375                            MPC8544_PCI_REGS_BASE, 0, 0x1000);
 376     qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
 377     qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
 378     qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
 379     qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
 380     qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
 381
 382     params->fixup_devtree(params, fdt);
 383
 384     if (toplevel_compat) {
 385         qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
 386                          strlen(toplevel_compat) + 1);
 387     }
 388
 389 done:
 390     if (!dry_run) {
 391         qemu_fdt_dumpdtb(fdt, fdt_size);
 392         cpu_physical_memory_write(addr, fdt, fdt_size);
 393     }
 394     ret = fdt_size;
 395
 396 out:
 397     g_free(pci_map);
 398
 399     return ret;
 400 }
 401
 402 typedef struct DeviceTreeParams {
 403     MachineState *machine;
 404     PPCE500Params params;
 405     hwaddr addr;
 406     hwaddr initrd_base;
 407     hwaddr initrd_size;
 408     hwaddr kernel_base;
 409     hwaddr kernel_size;
 410 } DeviceTreeParams;
 411
 412 static void ppce500_reset_device_tree(void *opaque)
 413 {
 414     DeviceTreeParams *p = opaque;
 415     ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base,
 416                              p->initrd_size, p->kernel_base, p->kernel_size,
 417                              false);
 418 }
 419
 420 static int ppce500_prep_device_tree(MachineState *machine,
 421                                     PPCE500Params *params,
 422                                     hwaddr addr,
 423                                     hwaddr initrd_base,
 424                                     hwaddr initrd_size,
 425                                     hwaddr kernel_base,
 426                                     hwaddr kernel_size)
 427 {
 428     DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
 429     p->machine = machine;
 430     p->params = *params;
 431     p->addr = addr;
 432     p->initrd_base = initrd_base;
 433     p->initrd_size = initrd_size;
 434     p->kernel_base = kernel_base;
 435     p->kernel_size = kernel_size;
 436
 437     qemu_register_reset(ppce500_reset_device_tree, p);
 438
 439     /* Issue the device tree loader once, so that we get the size of the blob */
 440     return ppce500_load_device_tree(machine, params, addr, initrd_base,
 441                                     initrd_size, kernel_base, kernel_size,
 442                                     true);
 443 }
 444
 445 /* Create -kernel TLB entries for BookE.  */
 446 static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
 447 {
 448     return 63 - clz64(size >> 10);
 449 }
 450
 451 static int booke206_initial_map_tsize(CPUPPCState *env)
 452 {
 453     struct boot_info *bi = env->load_info;
 454     hwaddr dt_end;
 455     int ps;
 456
 457     /* Our initial TLB entry needs to cover everything from 0 to
 458        the device tree top */
 459     dt_end = bi->dt_base + bi->dt_size;
 460     ps = booke206_page_size_to_tlb(dt_end) + 1;
 461     if (ps & 1) {
 462         /* e500v2 can only do even TLB size bits */
 463         ps++;
 464     }
 465     return ps;
 466 }
 467
 468 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
 469 {
 470     int tsize;
 471
 472     tsize = booke206_initial_map_tsize(env);
 473     return (1ULL << 10 << tsize);
 474 }
 475
 476 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 477 {
 478     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 479     hwaddr size;
 480     int ps;
 481
 482     ps = booke206_initial_map_tsize(env);
 483     size = (ps << MAS1_TSIZE_SHIFT);
 484     tlb->mas1 = MAS1_VALID | size;
 485     tlb->mas2 = 0;
 486     tlb->mas7_3 = 0;
 487     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 488
 489     env->tlb_dirty = true;
 490 }
 491
 492 static void ppce500_cpu_reset_sec(void *opaque)
 493 {
 494     PowerPCCPU *cpu = opaque;
 495     CPUState *cs = CPU(cpu);
 496
 497     cpu_reset(cs);
 498
 499     /* Secondary CPU starts in halted state for now. Needs to change when
 500        implementing non-kernel boot. */
 501     cs->halted = 1;
 502     cs->exception_index = EXCP_HLT;
 503 }
 504
 505 static void ppce500_cpu_reset(void *opaque)
 506 {
 507     PowerPCCPU *cpu = opaque;
 508     CPUState *cs = CPU(cpu);
 509     CPUPPCState *env = &cpu->env;
 510     struct boot_info *bi = env->load_info;
 511
 512     cpu_reset(cs);
 513
 514     /* Set initial guest state. */
 515     cs->halted = 0;
 516     env->gpr[1] = (16<<20) - 8;
 517     env->gpr[3] = bi->dt_base;
 518     env->gpr[4] = 0;
 519     env->gpr[5] = 0;
 520     env->gpr[6] = EPAPR_MAGIC;
 521     env->gpr[7] = mmubooke_initial_mapsize(env);
 522     env->gpr[8] = 0;
 523     env->gpr[9] = 0;
 524     env->nip = bi->entry;
 525     mmubooke_create_initial_mapping(env);
 526 }
 527
 528 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
 529                                            qemu_irq **irqs)
 530 {
 531     DeviceState *dev;
 532     SysBusDevice *s;
 533     int i, j, k;
 534
 535     dev = qdev_create(NULL, TYPE_OPENPIC);
 536     qdev_prop_set_uint32(dev, "model", params->mpic_version);
 537     qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
 538
 539     qdev_init_nofail(dev);
 540     s = SYS_BUS_DEVICE(dev);
 541
 542     k = 0;
 543     for (i = 0; i < smp_cpus; i++) {
 544         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
 545             sysbus_connect_irq(s, k++, irqs[i][j]);
 546         }
 547     }
 548
 549     return dev;
 550 }
 551
 552 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
 553                                           qemu_irq **irqs)
 554 {
 555     DeviceState *dev;
 556     CPUState *cs;
 557     int r;
 558
 559     dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
 560     qdev_prop_set_uint32(dev, "model", params->mpic_version);
 561
 562     r = qdev_init(dev);
 563     if (r) {
 564         return NULL;
 565     }
 566
 567     CPU_FOREACH(cs) {
 568         if (kvm_openpic_connect_vcpu(dev, cs)) {
 569             fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
 570                     __func__);
 571             abort();
 572         }
 573     }
 574
 575     return dev;
 576 }
 577
 578 static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr,
 579                                    qemu_irq **irqs)
 580 {
 581     qemu_irq *mpic;
 582     DeviceState *dev = NULL;
 583     SysBusDevice *s;
 584     int i;
 585
 586     mpic = g_new(qemu_irq, 256);
 587
 588     if (kvm_enabled()) {
 589         QemuOpts *machine_opts = qemu_get_machine_opts();
 590         bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
 591                                                 "kernel_irqchip", true);
 592         bool irqchip_required = qemu_opt_get_bool(machine_opts,
 593                                                   "kernel_irqchip", false);
 594
 595         if (irqchip_allowed) {
 596             dev = ppce500_init_mpic_kvm(params, irqs);
 597         }
 598
 599         if (irqchip_required && !dev) {
 600             fprintf(stderr, "%s: irqchip requested but unavailable\n",
 601                     __func__);
 602             abort();
 603         }
 604     }
 605
 606     if (!dev) {
 607         dev = ppce500_init_mpic_qemu(params, irqs);
 608     }
 609
 610     for (i = 0; i < 256; i++) {
 611         mpic[i] = qdev_get_gpio_in(dev, i);
 612     }
 613
 614     s = SYS_BUS_DEVICE(dev);
 615     memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
 616                                 s->mmio[0].memory);
 617
 618     return mpic;
 619 }
 620
 621 void ppce500_init(MachineState *machine, PPCE500Params *params)
 622 {
 623     MemoryRegion *address_space_mem = get_system_memory();
 624     MemoryRegion *ram = g_new(MemoryRegion, 1);
 625     PCIBus *pci_bus;
 626     CPUPPCState *env = NULL;
 627     uint64_t loadaddr;
 628     hwaddr kernel_base = -1LL;
 629     int kernel_size = 0;
 630     hwaddr dt_base = 0;
 631     hwaddr initrd_base = 0;
 632     int initrd_size = 0;
 633     hwaddr cur_base = 0;
 634     char *filename;
 635     hwaddr bios_entry = 0;
 636     target_long bios_size;
 637     struct boot_info *boot_info;
 638     int dt_size;
 639     int i;
 640     /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
 641      * 4 respectively */
 642     unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
 643     qemu_irq **irqs, *mpic;
 644     DeviceState *dev;
 645     CPUPPCState *firstenv = NULL;
 646     MemoryRegion *ccsr_addr_space;
 647     SysBusDevice *s;
 648     PPCE500CCSRState *ccsr;
 649
 650     /* Setup CPUs */
 651     if (machine->cpu_model == NULL) {
 652         machine->cpu_model = "e500v2_v30";
 653     }
 654
 655     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 656     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 657     for (i = 0; i < smp_cpus; i++) {
 658         PowerPCCPU *cpu;
 659         CPUState *cs;
 660         qemu_irq *input;
 661
 662         cpu = cpu_ppc_init(machine->cpu_model);
 663         if (cpu == NULL) {
 664             fprintf(stderr, "Unable to initialize CPU!\n");
 665             exit(1);
 666         }
 667         env = &cpu->env;
 668         cs = CPU(cpu);
 669
 670         if (!firstenv) {
 671             firstenv = env;
 672         }
 673
 674         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 675         input = (qemu_irq *)env->irq_inputs;
 676         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 677         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 678         env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
 679         env->mpic_iack = MPC8544_CCSRBAR_BASE +
 680                          MPC8544_MPIC_REGS_OFFSET + 0xa0;
 681
 682         ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
 683
 684         /* Register reset handler */
 685         if (!i) {
 686             /* Primary CPU */
 687             struct boot_info *boot_info;
 688             boot_info = g_malloc0(sizeof(struct boot_info));
 689             qemu_register_reset(ppce500_cpu_reset, cpu);
 690             env->load_info = boot_info;
 691         } else {
 692             /* Secondary CPUs */
 693             qemu_register_reset(ppce500_cpu_reset_sec, cpu);
 694         }
 695     }
 696
 697     env = firstenv;
 698
 699     /* Fixup Memory size on a alignment boundary */
 700     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 701     machine->ram_size = ram_size;
 702
 703     /* Register Memory */
 704     memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size);
 705     memory_region_add_subregion(address_space_mem, 0, ram);
 706
 707     dev = qdev_create(NULL, "e500-ccsr");
 708     object_property_add_child(qdev_get_machine(), "e500-ccsr",
 709                               OBJECT(dev), NULL);
 710     qdev_init_nofail(dev);
 711     ccsr = CCSR(dev);
 712     ccsr_addr_space = &ccsr->ccsr_space;
 713     memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
 714                                 ccsr_addr_space);
 715
 716     mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
 717
 718     /* Serial */
 719     if (serial_hds[0]) {
 720         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
 721                        0, mpic[42], 399193,
 722                        serial_hds[0], DEVICE_BIG_ENDIAN);
 723     }
 724
 725     if (serial_hds[1]) {
 726         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
 727                        0, mpic[42], 399193,
 728                        serial_hds[1], DEVICE_BIG_ENDIAN);
 729     }
 730
 731     /* General Utility device */
 732     dev = qdev_create(NULL, "mpc8544-guts");
 733     qdev_init_nofail(dev);
 734     s = SYS_BUS_DEVICE(dev);
 735     memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
 736                                 sysbus_mmio_get_region(s, 0));
 737
 738     /* PCI */
 739     dev = qdev_create(NULL, "e500-pcihost");
 740     qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
 741     qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
 742     qdev_init_nofail(dev);
 743     s = SYS_BUS_DEVICE(dev);
 744     for (i = 0; i < PCI_NUM_PINS; i++) {
 745         sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]);
 746     }
 747
 748     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
 749                                 sysbus_mmio_get_region(s, 0));
 750
 751     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 752     if (!pci_bus)
 753         printf("couldn't create PCI controller!\n");
 754
 755     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
 756
 757     if (pci_bus) {
 758         /* Register network interfaces. */
 759         for (i = 0; i < nb_nics; i++) {
 760             pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL);
 761         }
 762     }
 763
 764     /* Register spinning region */
 765     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 766
 767     if (cur_base < (32 * 1024 * 1024)) {
 768         /* u-boot occupies memory up to 32MB, so load blobs above */
 769         cur_base = (32 * 1024 * 1024);
 770     }
 771
 772     /* Load kernel. */
 773     if (machine->kernel_filename) {
 774         kernel_base = cur_base;
 775         kernel_size = load_image_targphys(machine->kernel_filename,
 776                                           cur_base,
 777                                           ram_size - cur_base);
 778         if (kernel_size < 0) {
 779             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 780                     machine->kernel_filename);
 781             exit(1);
 782         }
 783
 784         cur_base += kernel_size;
 785     }
 786
 787     /* Load initrd. */
 788     if (machine->initrd_filename) {
 789         initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 790         initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
 791                                           ram_size - initrd_base);
 792
 793         if (initrd_size < 0) {
 794             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 795                     machine->initrd_filename);
 796             exit(1);
 797         }
 798
 799         cur_base = initrd_base + initrd_size;
 800     }
 801
 802     /*
 803      * Smart firmware defaults ahead!
 804      *
 805      * We follow the following table to select which payload we execute.
 806      *
 807      *  -kernel | -bios | payload
 808      * ---------+-------+---------
 809      *     N    |   Y   | u-boot
 810      *     N    |   N   | u-boot
 811      *     Y    |   Y   | u-boot
 812      *     Y    |   N   | kernel
 813      *
 814      * This ensures backwards compatibility with how we used to expose
 815      * -kernel to users but allows them to run through u-boot as well.
 816      */
 817     if (bios_name == NULL) {
 818         if (machine->kernel_filename) {
 819             bios_name = machine->kernel_filename;
 820         } else {
 821             bios_name = "u-boot.e500";
 822         }
 823     }
 824     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 825
 826     bios_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL,
 827                          1, ELF_MACHINE, 0);
 828     if (bios_size < 0) {
 829         /*
 830          * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
 831          * ePAPR compliant kernel
 832          */
 833         kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL);
 834         if (kernel_size < 0) {
 835             fprintf(stderr, "qemu: could not load firmware '%s'\n", filename);
 836             exit(1);
 837         }
 838     }
 839
 840     /* Reserve space for dtb */
 841     dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 842
 843     dt_size = ppce500_prep_device_tree(machine, params, dt_base,
 844                                        initrd_base, initrd_size,
 845                                        kernel_base, kernel_size);
 846     if (dt_size < 0) {
 847         fprintf(stderr, "couldn't load device tree\n");
 848         exit(1);
 849     }
 850     assert(dt_size < DTB_MAX_SIZE);
 851
 852     boot_info = env->load_info;
 853     boot_info->entry = bios_entry;
 854     boot_info->dt_base = dt_base;
 855     boot_info->dt_size = dt_size;
 856
 857     if (kvm_enabled()) {
 858         kvmppc_init();
 859     }
 860 }
 861
 862 static int e500_ccsr_initfn(SysBusDevice *dev)
 863 {
 864     PPCE500CCSRState *ccsr;
 865
 866     ccsr = CCSR(dev);
 867     memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr",
 868                        MPC8544_CCSRBAR_SIZE);
 869     return 0;
 870 }
 871
 872 static void e500_ccsr_class_init(ObjectClass *klass, void *data)
 873 {
 874     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 875     k->init = e500_ccsr_initfn;
 876 }
 877
 878 static const TypeInfo e500_ccsr_info = {
 879     .name          = TYPE_CCSR,
 880     .parent        = TYPE_SYS_BUS_DEVICE,
 881     .instance_size = sizeof(PPCE500CCSRState),
 882     .class_init    = e500_ccsr_class_init,
 883 };
 884
 885 static void e500_register_types(void)
 886 {
 887     type_register_static(&e500_ccsr_info);
 888 }
 889
 890 type_init(e500_register_types)