target/arm: Create gen_gvec_{uqadd, sqadd, uqsub, sqsub}
[qemu/ar7.git] / target / arm / translate-a64.c
blobea5f6ceadcb9610a0049113d843af3676c9fb942
1 /*
2 * AArch64 translation
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
25 #include "qemu/log.h"
26 #include "arm_ldst.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
36 #include "exec/log.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X[32];
43 static TCGv_i64 cpu_pc;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high;
48 static const char *regnames[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 enum a64_shift_type {
56 A64_SHIFT_TYPE_LSL = 0,
57 A64_SHIFT_TYPE_LSR = 1,
58 A64_SHIFT_TYPE_ASR = 2,
59 A64_SHIFT_TYPE_ROR = 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
67 typedef struct AArch64DecodeTable {
68 uint32_t pattern;
69 uint32_t mask;
70 AArch64DecodeFn *disas_fn;
71 } AArch64DecodeTable;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
76 int i;
78 cpu_pc = tcg_global_mem_new_i64(cpu_env,
79 offsetof(CPUARMState, pc),
80 "pc");
81 for (i = 0; i < 32; i++) {
82 cpu_X[i] = tcg_global_mem_new_i64(cpu_env,
83 offsetof(CPUARMState, xregs[i]),
84 regnames[i]);
87 cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env,
88 offsetof(CPUARMState, exclusive_high), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext *s)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx = s->mmu_idx;
102 if (s->unpriv) {
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
108 switch (useridx) {
109 case ARMMMUIdx_E10_1:
110 case ARMMMUIdx_E10_1_PAN:
111 useridx = ARMMMUIdx_E10_0;
112 break;
113 case ARMMMUIdx_E20_2:
114 case ARMMMUIdx_E20_2_PAN:
115 useridx = ARMMMUIdx_E20_0;
116 break;
117 case ARMMMUIdx_SE10_1:
118 case ARMMMUIdx_SE10_1_PAN:
119 useridx = ARMMMUIdx_SE10_0;
120 break;
121 default:
122 g_assert_not_reached();
125 return arm_to_core_mmu_idx(useridx);
128 static void reset_btype(DisasContext *s)
130 if (s->btype != 0) {
131 TCGv_i32 zero = tcg_const_i32(0);
132 tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype));
133 tcg_temp_free_i32(zero);
134 s->btype = 0;
138 static void set_btype(DisasContext *s, int val)
140 TCGv_i32 tcg_val;
142 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
143 tcg_debug_assert(val >= 1 && val <= 3);
145 tcg_val = tcg_const_i32(val);
146 tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype));
147 tcg_temp_free_i32(tcg_val);
148 s->btype = -1;
151 void gen_a64_set_pc_im(uint64_t val)
153 tcg_gen_movi_i64(cpu_pc, val);
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst,
170 TCGv_i64 src, int tbi)
172 if (tbi == 0) {
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst, src);
175 } else if (!regime_has_2_ranges(s->mmu_idx)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst, src, 0, 56);
178 } else {
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst, src, 0, 56);
182 if (tbi != 3) {
183 TCGv_i64 tcg_zero = tcg_const_i64(0);
186 * The two TBI bits differ.
187 * If tbi0, then !tbi1: only use the extension if positive.
188 * if !tbi0, then tbi1: only use the extension if negative.
190 tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT,
191 dst, dst, tcg_zero, dst, src);
192 tcg_temp_free_i64(tcg_zero);
197 static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
200 * If address tagging is enabled for instructions via the TCR TBI bits,
201 * then loading an address into the PC will clear out any tag.
203 gen_top_byte_ignore(s, cpu_pc, src, s->tbii);
207 * Return a "clean" address for ADDR according to TBID.
208 * This is always a fresh temporary, as we need to be able to
209 * increment this independently of a dirty write-back address.
211 static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
213 TCGv_i64 clean = new_tmp_a64(s);
215 * In order to get the correct value in the FAR_ELx register,
216 * we must present the memory subsystem with the "dirty" address
217 * including the TBI. In system mode we can make this work via
218 * the TLB, dropping the TBI during translation. But for user-only
219 * mode we don't have that option, and must remove the top byte now.
221 #ifdef CONFIG_USER_ONLY
222 gen_top_byte_ignore(s, clean, addr, s->tbid);
223 #else
224 tcg_gen_mov_i64(clean, addr);
225 #endif
226 return clean;
229 typedef struct DisasCompare64 {
230 TCGCond cond;
231 TCGv_i64 value;
232 } DisasCompare64;
234 static void a64_test_cc(DisasCompare64 *c64, int cc)
236 DisasCompare c32;
238 arm_test_cc(&c32, cc);
240 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
241 * properly. The NE/EQ comparisons are also fine with this choice. */
242 c64->cond = c32.cond;
243 c64->value = tcg_temp_new_i64();
244 tcg_gen_ext_i32_i64(c64->value, c32.value);
246 arm_free_cc(&c32);
249 static void a64_free_cc(DisasCompare64 *c64)
251 tcg_temp_free_i64(c64->value);
254 static void gen_exception_internal(int excp)
256 TCGv_i32 tcg_excp = tcg_const_i32(excp);
258 assert(excp_is_internal(excp));
259 gen_helper_exception_internal(cpu_env, tcg_excp);
260 tcg_temp_free_i32(tcg_excp);
263 static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
265 gen_a64_set_pc_im(pc);
266 gen_exception_internal(excp);
267 s->base.is_jmp = DISAS_NORETURN;
270 static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
271 uint32_t syndrome, uint32_t target_el)
273 gen_a64_set_pc_im(pc);
274 gen_exception(excp, syndrome, target_el);
275 s->base.is_jmp = DISAS_NORETURN;
278 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
280 TCGv_i32 tcg_syn;
282 gen_a64_set_pc_im(s->pc_curr);
283 tcg_syn = tcg_const_i32(syndrome);
284 gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
285 tcg_temp_free_i32(tcg_syn);
286 s->base.is_jmp = DISAS_NORETURN;
289 static void gen_step_complete_exception(DisasContext *s)
291 /* We just completed step of an insn. Move from Active-not-pending
292 * to Active-pending, and then also take the swstep exception.
293 * This corresponds to making the (IMPDEF) choice to prioritize
294 * swstep exceptions over asynchronous exceptions taken to an exception
295 * level where debug is disabled. This choice has the advantage that
296 * we do not need to maintain internal state corresponding to the
297 * ISV/EX syndrome bits between completion of the step and generation
298 * of the exception, and our syndrome information is always correct.
300 gen_ss_advance(s);
301 gen_swstep_exception(s, 1, s->is_ldex);
302 s->base.is_jmp = DISAS_NORETURN;
305 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
307 /* No direct tb linking with singlestep (either QEMU's or the ARM
308 * debug architecture kind) or deterministic io
310 if (s->base.singlestep_enabled || s->ss_active ||
311 (tb_cflags(s->base.tb) & CF_LAST_IO)) {
312 return false;
315 #ifndef CONFIG_USER_ONLY
316 /* Only link tbs from inside the same guest page */
317 if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
318 return false;
320 #endif
322 return true;
325 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
327 TranslationBlock *tb;
329 tb = s->base.tb;
330 if (use_goto_tb(s, n, dest)) {
331 tcg_gen_goto_tb(n);
332 gen_a64_set_pc_im(dest);
333 tcg_gen_exit_tb(tb, n);
334 s->base.is_jmp = DISAS_NORETURN;
335 } else {
336 gen_a64_set_pc_im(dest);
337 if (s->ss_active) {
338 gen_step_complete_exception(s);
339 } else if (s->base.singlestep_enabled) {
340 gen_exception_internal(EXCP_DEBUG);
341 } else {
342 tcg_gen_lookup_and_goto_ptr();
343 s->base.is_jmp = DISAS_NORETURN;
348 void unallocated_encoding(DisasContext *s)
350 /* Unallocated and reserved encodings are uncategorized */
351 gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
352 default_exception_el(s));
355 static void init_tmp_a64_array(DisasContext *s)
357 #ifdef CONFIG_DEBUG_TCG
358 memset(s->tmp_a64, 0, sizeof(s->tmp_a64));
359 #endif
360 s->tmp_a64_count = 0;
363 static void free_tmp_a64(DisasContext *s)
365 int i;
366 for (i = 0; i < s->tmp_a64_count; i++) {
367 tcg_temp_free_i64(s->tmp_a64[i]);
369 init_tmp_a64_array(s);
372 TCGv_i64 new_tmp_a64(DisasContext *s)
374 assert(s->tmp_a64_count < TMP_A64_MAX);
375 return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
378 TCGv_i64 new_tmp_a64_zero(DisasContext *s)
380 TCGv_i64 t = new_tmp_a64(s);
381 tcg_gen_movi_i64(t, 0);
382 return t;
386 * Register access functions
388 * These functions are used for directly accessing a register in where
389 * changes to the final register value are likely to be made. If you
390 * need to use a register for temporary calculation (e.g. index type
391 * operations) use the read_* form.
393 * B1.2.1 Register mappings
395 * In instruction register encoding 31 can refer to ZR (zero register) or
396 * the SP (stack pointer) depending on context. In QEMU's case we map SP
397 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
398 * This is the point of the _sp forms.
400 TCGv_i64 cpu_reg(DisasContext *s, int reg)
402 if (reg == 31) {
403 return new_tmp_a64_zero(s);
404 } else {
405 return cpu_X[reg];
409 /* register access for when 31 == SP */
410 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
412 return cpu_X[reg];
415 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
416 * representing the register contents. This TCGv is an auto-freed
417 * temporary so it need not be explicitly freed, and may be modified.
419 TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
421 TCGv_i64 v = new_tmp_a64(s);
422 if (reg != 31) {
423 if (sf) {
424 tcg_gen_mov_i64(v, cpu_X[reg]);
425 } else {
426 tcg_gen_ext32u_i64(v, cpu_X[reg]);
428 } else {
429 tcg_gen_movi_i64(v, 0);
431 return v;
434 TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
436 TCGv_i64 v = new_tmp_a64(s);
437 if (sf) {
438 tcg_gen_mov_i64(v, cpu_X[reg]);
439 } else {
440 tcg_gen_ext32u_i64(v, cpu_X[reg]);
442 return v;
445 /* Return the offset into CPUARMState of a slice (from
446 * the least significant end) of FP register Qn (ie
447 * Dn, Sn, Hn or Bn).
448 * (Note that this is not the same mapping as for A32; see cpu.h)
450 static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size)
452 return vec_reg_offset(s, regno, 0, size);
455 /* Offset of the high half of the 128 bit vector Qn */
456 static inline int fp_reg_hi_offset(DisasContext *s, int regno)
458 return vec_reg_offset(s, regno, 1, MO_64);
461 /* Convenience accessors for reading and writing single and double
462 * FP registers. Writing clears the upper parts of the associated
463 * 128 bit vector register, as required by the architecture.
464 * Note that unlike the GP register accessors, the values returned
465 * by the read functions must be manually freed.
467 static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
469 TCGv_i64 v = tcg_temp_new_i64();
471 tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));
472 return v;
475 static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
477 TCGv_i32 v = tcg_temp_new_i32();
479 tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32));
480 return v;
483 static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
485 TCGv_i32 v = tcg_temp_new_i32();
487 tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
488 return v;
491 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
492 * If SVE is not enabled, then there are only 128 bits in the vector.
494 static void clear_vec_high(DisasContext *s, bool is_q, int rd)
496 unsigned ofs = fp_reg_offset(s, rd, MO_64);
497 unsigned vsz = vec_full_reg_size(s);
499 if (!is_q) {
500 TCGv_i64 tcg_zero = tcg_const_i64(0);
501 tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
502 tcg_temp_free_i64(tcg_zero);
504 if (vsz > 16) {
505 tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
509 void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
511 unsigned ofs = fp_reg_offset(s, reg, MO_64);
513 tcg_gen_st_i64(v, cpu_env, ofs);
514 clear_vec_high(s, false, reg);
517 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
519 TCGv_i64 tmp = tcg_temp_new_i64();
521 tcg_gen_extu_i32_i64(tmp, v);
522 write_fp_dreg(s, reg, tmp);
523 tcg_temp_free_i64(tmp);
526 TCGv_ptr get_fpstatus_ptr(bool is_f16)
528 TCGv_ptr statusptr = tcg_temp_new_ptr();
529 int offset;
531 /* In A64 all instructions (both FP and Neon) use the FPCR; there
532 * is no equivalent of the A32 Neon "standard FPSCR value".
533 * However half-precision operations operate under a different
534 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
536 if (is_f16) {
537 offset = offsetof(CPUARMState, vfp.fp_status_f16);
538 } else {
539 offset = offsetof(CPUARMState, vfp.fp_status);
541 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
542 return statusptr;
545 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
546 static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn,
547 GVecGen2Fn *gvec_fn, int vece)
549 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
550 is_q ? 16 : 8, vec_full_reg_size(s));
553 /* Expand a 2-operand + immediate AdvSIMD vector operation using
554 * an expander function.
556 static void gen_gvec_fn2i(DisasContext *s, bool is_q, int rd, int rn,
557 int64_t imm, GVecGen2iFn *gvec_fn, int vece)
559 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
560 imm, is_q ? 16 : 8, vec_full_reg_size(s));
563 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
564 static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm,
565 GVecGen3Fn *gvec_fn, int vece)
567 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
568 vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s));
571 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
572 static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
573 int rx, GVecGen4Fn *gvec_fn, int vece)
575 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
576 vec_full_reg_offset(s, rm), vec_full_reg_offset(s, rx),
577 is_q ? 16 : 8, vec_full_reg_size(s));
580 /* Expand a 3-operand operation using an out-of-line helper. */
581 static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,
582 int rn, int rm, int data, gen_helper_gvec_3 *fn)
584 tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
585 vec_full_reg_offset(s, rn),
586 vec_full_reg_offset(s, rm),
587 is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
590 /* Expand a 3-operand + env pointer operation using
591 * an out-of-line helper.
593 static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd,
594 int rn, int rm, gen_helper_gvec_3_ptr *fn)
596 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
597 vec_full_reg_offset(s, rn),
598 vec_full_reg_offset(s, rm), cpu_env,
599 is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
602 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
603 * an out-of-line helper.
605 static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
606 int rm, bool is_fp16, int data,
607 gen_helper_gvec_3_ptr *fn)
609 TCGv_ptr fpst = get_fpstatus_ptr(is_fp16);
610 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
611 vec_full_reg_offset(s, rn),
612 vec_full_reg_offset(s, rm), fpst,
613 is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
614 tcg_temp_free_ptr(fpst);
617 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
618 * than the 32 bit equivalent.
620 static inline void gen_set_NZ64(TCGv_i64 result)
622 tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result);
623 tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF);
626 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
627 static inline void gen_logic_CC(int sf, TCGv_i64 result)
629 if (sf) {
630 gen_set_NZ64(result);
631 } else {
632 tcg_gen_extrl_i64_i32(cpu_ZF, result);
633 tcg_gen_mov_i32(cpu_NF, cpu_ZF);
635 tcg_gen_movi_i32(cpu_CF, 0);
636 tcg_gen_movi_i32(cpu_VF, 0);
639 /* dest = T0 + T1; compute C, N, V and Z flags */
640 static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
642 if (sf) {
643 TCGv_i64 result, flag, tmp;
644 result = tcg_temp_new_i64();
645 flag = tcg_temp_new_i64();
646 tmp = tcg_temp_new_i64();
648 tcg_gen_movi_i64(tmp, 0);
649 tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp);
651 tcg_gen_extrl_i64_i32(cpu_CF, flag);
653 gen_set_NZ64(result);
655 tcg_gen_xor_i64(flag, result, t0);
656 tcg_gen_xor_i64(tmp, t0, t1);
657 tcg_gen_andc_i64(flag, flag, tmp);
658 tcg_temp_free_i64(tmp);
659 tcg_gen_extrh_i64_i32(cpu_VF, flag);
661 tcg_gen_mov_i64(dest, result);
662 tcg_temp_free_i64(result);
663 tcg_temp_free_i64(flag);
664 } else {
665 /* 32 bit arithmetic */
666 TCGv_i32 t0_32 = tcg_temp_new_i32();
667 TCGv_i32 t1_32 = tcg_temp_new_i32();
668 TCGv_i32 tmp = tcg_temp_new_i32();
670 tcg_gen_movi_i32(tmp, 0);
671 tcg_gen_extrl_i64_i32(t0_32, t0);
672 tcg_gen_extrl_i64_i32(t1_32, t1);
673 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp);
674 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
675 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
676 tcg_gen_xor_i32(tmp, t0_32, t1_32);
677 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
678 tcg_gen_extu_i32_i64(dest, cpu_NF);
680 tcg_temp_free_i32(tmp);
681 tcg_temp_free_i32(t0_32);
682 tcg_temp_free_i32(t1_32);
686 /* dest = T0 - T1; compute C, N, V and Z flags */
687 static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
689 if (sf) {
690 /* 64 bit arithmetic */
691 TCGv_i64 result, flag, tmp;
693 result = tcg_temp_new_i64();
694 flag = tcg_temp_new_i64();
695 tcg_gen_sub_i64(result, t0, t1);
697 gen_set_NZ64(result);
699 tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1);
700 tcg_gen_extrl_i64_i32(cpu_CF, flag);
702 tcg_gen_xor_i64(flag, result, t0);
703 tmp = tcg_temp_new_i64();
704 tcg_gen_xor_i64(tmp, t0, t1);
705 tcg_gen_and_i64(flag, flag, tmp);
706 tcg_temp_free_i64(tmp);
707 tcg_gen_extrh_i64_i32(cpu_VF, flag);
708 tcg_gen_mov_i64(dest, result);
709 tcg_temp_free_i64(flag);
710 tcg_temp_free_i64(result);
711 } else {
712 /* 32 bit arithmetic */
713 TCGv_i32 t0_32 = tcg_temp_new_i32();
714 TCGv_i32 t1_32 = tcg_temp_new_i32();
715 TCGv_i32 tmp;
717 tcg_gen_extrl_i64_i32(t0_32, t0);
718 tcg_gen_extrl_i64_i32(t1_32, t1);
719 tcg_gen_sub_i32(cpu_NF, t0_32, t1_32);
720 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
721 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32);
722 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
723 tmp = tcg_temp_new_i32();
724 tcg_gen_xor_i32(tmp, t0_32, t1_32);
725 tcg_temp_free_i32(t0_32);
726 tcg_temp_free_i32(t1_32);
727 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
728 tcg_temp_free_i32(tmp);
729 tcg_gen_extu_i32_i64(dest, cpu_NF);
733 /* dest = T0 + T1 + CF; do not compute flags. */
734 static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
736 TCGv_i64 flag = tcg_temp_new_i64();
737 tcg_gen_extu_i32_i64(flag, cpu_CF);
738 tcg_gen_add_i64(dest, t0, t1);
739 tcg_gen_add_i64(dest, dest, flag);
740 tcg_temp_free_i64(flag);
742 if (!sf) {
743 tcg_gen_ext32u_i64(dest, dest);
747 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
748 static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
750 if (sf) {
751 TCGv_i64 result, cf_64, vf_64, tmp;
752 result = tcg_temp_new_i64();
753 cf_64 = tcg_temp_new_i64();
754 vf_64 = tcg_temp_new_i64();
755 tmp = tcg_const_i64(0);
757 tcg_gen_extu_i32_i64(cf_64, cpu_CF);
758 tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
759 tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
760 tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
761 gen_set_NZ64(result);
763 tcg_gen_xor_i64(vf_64, result, t0);
764 tcg_gen_xor_i64(tmp, t0, t1);
765 tcg_gen_andc_i64(vf_64, vf_64, tmp);
766 tcg_gen_extrh_i64_i32(cpu_VF, vf_64);
768 tcg_gen_mov_i64(dest, result);
770 tcg_temp_free_i64(tmp);
771 tcg_temp_free_i64(vf_64);
772 tcg_temp_free_i64(cf_64);
773 tcg_temp_free_i64(result);
774 } else {
775 TCGv_i32 t0_32, t1_32, tmp;
776 t0_32 = tcg_temp_new_i32();
777 t1_32 = tcg_temp_new_i32();
778 tmp = tcg_const_i32(0);
780 tcg_gen_extrl_i64_i32(t0_32, t0);
781 tcg_gen_extrl_i64_i32(t1_32, t1);
782 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
783 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
785 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
786 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
787 tcg_gen_xor_i32(tmp, t0_32, t1_32);
788 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
789 tcg_gen_extu_i32_i64(dest, cpu_NF);
791 tcg_temp_free_i32(tmp);
792 tcg_temp_free_i32(t1_32);
793 tcg_temp_free_i32(t0_32);
798 * Load/Store generators
802 * Store from GPR register to memory.
804 static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
805 TCGv_i64 tcg_addr, int size, int memidx,
806 bool iss_valid,
807 unsigned int iss_srt,
808 bool iss_sf, bool iss_ar)
810 g_assert(size <= 3);
811 tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size);
813 if (iss_valid) {
814 uint32_t syn;
816 syn = syn_data_abort_with_iss(0,
817 size,
818 false,
819 iss_srt,
820 iss_sf,
821 iss_ar,
822 0, 0, 0, 0, 0, false);
823 disas_set_insn_syndrome(s, syn);
827 static void do_gpr_st(DisasContext *s, TCGv_i64 source,
828 TCGv_i64 tcg_addr, int size,
829 bool iss_valid,
830 unsigned int iss_srt,
831 bool iss_sf, bool iss_ar)
833 do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s),
834 iss_valid, iss_srt, iss_sf, iss_ar);
838 * Load from memory to GPR register
840 static void do_gpr_ld_memidx(DisasContext *s,
841 TCGv_i64 dest, TCGv_i64 tcg_addr,
842 int size, bool is_signed,
843 bool extend, int memidx,
844 bool iss_valid, unsigned int iss_srt,
845 bool iss_sf, bool iss_ar)
847 MemOp memop = s->be_data + size;
849 g_assert(size <= 3);
851 if (is_signed) {
852 memop += MO_SIGN;
855 tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
857 if (extend && is_signed) {
858 g_assert(size < 3);
859 tcg_gen_ext32u_i64(dest, dest);
862 if (iss_valid) {
863 uint32_t syn;
865 syn = syn_data_abort_with_iss(0,
866 size,
867 is_signed,
868 iss_srt,
869 iss_sf,
870 iss_ar,
871 0, 0, 0, 0, 0, false);
872 disas_set_insn_syndrome(s, syn);
876 static void do_gpr_ld(DisasContext *s,
877 TCGv_i64 dest, TCGv_i64 tcg_addr,
878 int size, bool is_signed, bool extend,
879 bool iss_valid, unsigned int iss_srt,
880 bool iss_sf, bool iss_ar)
882 do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
883 get_mem_index(s),
884 iss_valid, iss_srt, iss_sf, iss_ar);
888 * Store from FP register to memory
890 static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
892 /* This writes the bottom N bits of a 128 bit wide vector to memory */
893 TCGv_i64 tmp = tcg_temp_new_i64();
894 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64));
895 if (size < 4) {
896 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s),
897 s->be_data + size);
898 } else {
899 bool be = s->be_data == MO_BE;
900 TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
902 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
903 tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
904 s->be_data | MO_Q);
905 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx));
906 tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
907 s->be_data | MO_Q);
908 tcg_temp_free_i64(tcg_hiaddr);
911 tcg_temp_free_i64(tmp);
915 * Load from memory to FP register
917 static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
919 /* This always zero-extends and writes to a full 128 bit wide vector */
920 TCGv_i64 tmplo = tcg_temp_new_i64();
921 TCGv_i64 tmphi;
923 if (size < 4) {
924 MemOp memop = s->be_data + size;
925 tmphi = tcg_const_i64(0);
926 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
927 } else {
928 bool be = s->be_data == MO_BE;
929 TCGv_i64 tcg_hiaddr;
931 tmphi = tcg_temp_new_i64();
932 tcg_hiaddr = tcg_temp_new_i64();
934 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
935 tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
936 s->be_data | MO_Q);
937 tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
938 s->be_data | MO_Q);
939 tcg_temp_free_i64(tcg_hiaddr);
942 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
943 tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
945 tcg_temp_free_i64(tmplo);
946 tcg_temp_free_i64(tmphi);
948 clear_vec_high(s, true, destidx);
952 * Vector load/store helpers.
954 * The principal difference between this and a FP load is that we don't
955 * zero extend as we are filling a partial chunk of the vector register.
956 * These functions don't support 128 bit loads/stores, which would be
957 * normal load/store operations.
959 * The _i32 versions are useful when operating on 32 bit quantities
960 * (eg for floating point single or using Neon helper functions).
963 /* Get value of an element within a vector register */
964 static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
965 int element, MemOp memop)
967 int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
968 switch (memop) {
969 case MO_8:
970 tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
971 break;
972 case MO_16:
973 tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
974 break;
975 case MO_32:
976 tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
977 break;
978 case MO_8|MO_SIGN:
979 tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
980 break;
981 case MO_16|MO_SIGN:
982 tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
983 break;
984 case MO_32|MO_SIGN:
985 tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
986 break;
987 case MO_64:
988 case MO_64|MO_SIGN:
989 tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
990 break;
991 default:
992 g_assert_not_reached();
996 static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
997 int element, MemOp memop)
999 int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
1000 switch (memop) {
1001 case MO_8:
1002 tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
1003 break;
1004 case MO_16:
1005 tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
1006 break;
1007 case MO_8|MO_SIGN:
1008 tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
1009 break;
1010 case MO_16|MO_SIGN:
1011 tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
1012 break;
1013 case MO_32:
1014 case MO_32|MO_SIGN:
1015 tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
1016 break;
1017 default:
1018 g_assert_not_reached();
1022 /* Set value of an element within a vector register */
1023 static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
1024 int element, MemOp memop)
1026 int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
1027 switch (memop) {
1028 case MO_8:
1029 tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
1030 break;
1031 case MO_16:
1032 tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
1033 break;
1034 case MO_32:
1035 tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
1036 break;
1037 case MO_64:
1038 tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
1039 break;
1040 default:
1041 g_assert_not_reached();
1045 static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
1046 int destidx, int element, MemOp memop)
1048 int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
1049 switch (memop) {
1050 case MO_8:
1051 tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
1052 break;
1053 case MO_16:
1054 tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
1055 break;
1056 case MO_32:
1057 tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
1058 break;
1059 default:
1060 g_assert_not_reached();
1064 /* Store from vector register to memory */
1065 static void do_vec_st(DisasContext *s, int srcidx, int element,
1066 TCGv_i64 tcg_addr, int size, MemOp endian)
1068 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
1070 read_vec_element(s, tcg_tmp, srcidx, element, size);
1071 tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size);
1073 tcg_temp_free_i64(tcg_tmp);
1076 /* Load from memory to vector register */
1077 static void do_vec_ld(DisasContext *s, int destidx, int element,
1078 TCGv_i64 tcg_addr, int size, MemOp endian)
1080 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
1082 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size);
1083 write_vec_element(s, tcg_tmp, destidx, element, size);
1085 tcg_temp_free_i64(tcg_tmp);
1088 /* Check that FP/Neon access is enabled. If it is, return
1089 * true. If not, emit code to generate an appropriate exception,
1090 * and return false; the caller should not emit any code for
1091 * the instruction. Note that this check must happen after all
1092 * unallocated-encoding checks (otherwise the syndrome information
1093 * for the resulting exception will be incorrect).
1095 static inline bool fp_access_check(DisasContext *s)
1097 assert(!s->fp_access_checked);
1098 s->fp_access_checked = true;
1100 if (!s->fp_excp_el) {
1101 return true;
1104 gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
1105 syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
1106 return false;
1109 /* Check that SVE access is enabled. If it is, return true.
1110 * If not, emit code to generate an appropriate exception and return false.
1112 bool sve_access_check(DisasContext *s)
1114 if (s->sve_excp_el) {
1115 gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
1116 s->sve_excp_el);
1117 return false;
1119 return fp_access_check(s);
1123 * This utility function is for doing register extension with an
1124 * optional shift. You will likely want to pass a temporary for the
1125 * destination register. See DecodeRegExtend() in the ARM ARM.
1127 static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in,
1128 int option, unsigned int shift)
1130 int extsize = extract32(option, 0, 2);
1131 bool is_signed = extract32(option, 2, 1);
1133 if (is_signed) {
1134 switch (extsize) {
1135 case 0:
1136 tcg_gen_ext8s_i64(tcg_out, tcg_in);
1137 break;
1138 case 1:
1139 tcg_gen_ext16s_i64(tcg_out, tcg_in);
1140 break;
1141 case 2:
1142 tcg_gen_ext32s_i64(tcg_out, tcg_in);
1143 break;
1144 case 3:
1145 tcg_gen_mov_i64(tcg_out, tcg_in);
1146 break;
1148 } else {
1149 switch (extsize) {
1150 case 0:
1151 tcg_gen_ext8u_i64(tcg_out, tcg_in);
1152 break;
1153 case 1:
1154 tcg_gen_ext16u_i64(tcg_out, tcg_in);
1155 break;
1156 case 2:
1157 tcg_gen_ext32u_i64(tcg_out, tcg_in);
1158 break;
1159 case 3:
1160 tcg_gen_mov_i64(tcg_out, tcg_in);
1161 break;
1165 if (shift) {
1166 tcg_gen_shli_i64(tcg_out, tcg_out, shift);
1170 static inline void gen_check_sp_alignment(DisasContext *s)
1172 /* The AArch64 architecture mandates that (if enabled via PSTATE
1173 * or SCTLR bits) there is a check that SP is 16-aligned on every
1174 * SP-relative load or store (with an exception generated if it is not).
1175 * In line with general QEMU practice regarding misaligned accesses,
1176 * we omit these checks for the sake of guest program performance.
1177 * This function is provided as a hook so we can more easily add these
1178 * checks in future (possibly as a "favour catching guest program bugs
1179 * over speed" user selectable option).
1184 * This provides a simple table based table lookup decoder. It is
1185 * intended to be used when the relevant bits for decode are too
1186 * awkwardly placed and switch/if based logic would be confusing and
1187 * deeply nested. Since it's a linear search through the table, tables
1188 * should be kept small.
1190 * It returns the first handler where insn & mask == pattern, or
1191 * NULL if there is no match.
1192 * The table is terminated by an empty mask (i.e. 0)
1194 static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
1195 uint32_t insn)
1197 const AArch64DecodeTable *tptr = table;
1199 while (tptr->mask) {
1200 if ((insn & tptr->mask) == tptr->pattern) {
1201 return tptr->disas_fn;
1203 tptr++;
1205 return NULL;
1209 * The instruction disassembly implemented here matches
1210 * the instruction encoding classifications in chapter C4
1211 * of the ARM Architecture Reference Manual (DDI0487B_a);
1212 * classification names and decode diagrams here should generally
1213 * match up with those in the manual.
1216 /* Unconditional branch (immediate)
1217 * 31 30 26 25 0
1218 * +----+-----------+-------------------------------------+
1219 * | op | 0 0 1 0 1 | imm26 |
1220 * +----+-----------+-------------------------------------+
1222 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
1224 uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4;
1226 if (insn & (1U << 31)) {
1227 /* BL Branch with link */
1228 tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
1231 /* B Branch / BL Branch with link */
1232 reset_btype(s);
1233 gen_goto_tb(s, 0, addr);
1236 /* Compare and branch (immediate)
1237 * 31 30 25 24 23 5 4 0
1238 * +----+-------------+----+---------------------+--------+
1239 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1240 * +----+-------------+----+---------------------+--------+
1242 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
1244 unsigned int sf, op, rt;
1245 uint64_t addr;
1246 TCGLabel *label_match;
1247 TCGv_i64 tcg_cmp;
1249 sf = extract32(insn, 31, 1);
1250 op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
1251 rt = extract32(insn, 0, 5);
1252 addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
1254 tcg_cmp = read_cpu_reg(s, rt, sf);
1255 label_match = gen_new_label();
1257 reset_btype(s);
1258 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1259 tcg_cmp, 0, label_match);
1261 gen_goto_tb(s, 0, s->base.pc_next);
1262 gen_set_label(label_match);
1263 gen_goto_tb(s, 1, addr);
1266 /* Test and branch (immediate)
1267 * 31 30 25 24 23 19 18 5 4 0
1268 * +----+-------------+----+-------+-------------+------+
1269 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1270 * +----+-------------+----+-------+-------------+------+
1272 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
1274 unsigned int bit_pos, op, rt;
1275 uint64_t addr;
1276 TCGLabel *label_match;
1277 TCGv_i64 tcg_cmp;
1279 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
1280 op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
1281 addr = s->pc_curr + sextract32(insn, 5, 14) * 4;
1282 rt = extract32(insn, 0, 5);
1284 tcg_cmp = tcg_temp_new_i64();
1285 tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
1286 label_match = gen_new_label();
1288 reset_btype(s);
1289 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1290 tcg_cmp, 0, label_match);
1291 tcg_temp_free_i64(tcg_cmp);
1292 gen_goto_tb(s, 0, s->base.pc_next);
1293 gen_set_label(label_match);
1294 gen_goto_tb(s, 1, addr);
1297 /* Conditional branch (immediate)
1298 * 31 25 24 23 5 4 3 0
1299 * +---------------+----+---------------------+----+------+
1300 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1301 * +---------------+----+---------------------+----+------+
1303 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
1305 unsigned int cond;
1306 uint64_t addr;
1308 if ((insn & (1 << 4)) || (insn & (1 << 24))) {
1309 unallocated_encoding(s);
1310 return;
1312 addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
1313 cond = extract32(insn, 0, 4);
1315 reset_btype(s);
1316 if (cond < 0x0e) {
1317 /* genuinely conditional branches */
1318 TCGLabel *label_match = gen_new_label();
1319 arm_gen_test_cc(cond, label_match);
1320 gen_goto_tb(s, 0, s->base.pc_next);
1321 gen_set_label(label_match);
1322 gen_goto_tb(s, 1, addr);
1323 } else {
1324 /* 0xe and 0xf are both "always" conditions */
1325 gen_goto_tb(s, 0, addr);
1329 /* HINT instruction group, including various allocated HINTs */
1330 static void handle_hint(DisasContext *s, uint32_t insn,
1331 unsigned int op1, unsigned int op2, unsigned int crm)
1333 unsigned int selector = crm << 3 | op2;
1335 if (op1 != 3) {
1336 unallocated_encoding(s);
1337 return;
1340 switch (selector) {
1341 case 0b00000: /* NOP */
1342 break;
1343 case 0b00011: /* WFI */
1344 s->base.is_jmp = DISAS_WFI;
1345 break;
1346 case 0b00001: /* YIELD */
1347 /* When running in MTTCG we don't generate jumps to the yield and
1348 * WFE helpers as it won't affect the scheduling of other vCPUs.
1349 * If we wanted to more completely model WFE/SEV so we don't busy
1350 * spin unnecessarily we would need to do something more involved.
1352 if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
1353 s->base.is_jmp = DISAS_YIELD;
1355 break;
1356 case 0b00010: /* WFE */
1357 if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
1358 s->base.is_jmp = DISAS_WFE;
1360 break;
1361 case 0b00100: /* SEV */
1362 case 0b00101: /* SEVL */
1363 /* we treat all as NOP at least for now */
1364 break;
1365 case 0b00111: /* XPACLRI */
1366 if (s->pauth_active) {
1367 gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]);
1369 break;
1370 case 0b01000: /* PACIA1716 */
1371 if (s->pauth_active) {
1372 gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
1374 break;
1375 case 0b01010: /* PACIB1716 */
1376 if (s->pauth_active) {
1377 gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
1379 break;
1380 case 0b01100: /* AUTIA1716 */
1381 if (s->pauth_active) {
1382 gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
1384 break;
1385 case 0b01110: /* AUTIB1716 */
1386 if (s->pauth_active) {
1387 gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
1389 break;
1390 case 0b11000: /* PACIAZ */
1391 if (s->pauth_active) {
1392 gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
1393 new_tmp_a64_zero(s));
1395 break;
1396 case 0b11001: /* PACIASP */
1397 if (s->pauth_active) {
1398 gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
1400 break;
1401 case 0b11010: /* PACIBZ */
1402 if (s->pauth_active) {
1403 gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30],
1404 new_tmp_a64_zero(s));
1406 break;
1407 case 0b11011: /* PACIBSP */
1408 if (s->pauth_active) {
1409 gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
1411 break;
1412 case 0b11100: /* AUTIAZ */
1413 if (s->pauth_active) {
1414 gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30],
1415 new_tmp_a64_zero(s));
1417 break;
1418 case 0b11101: /* AUTIASP */
1419 if (s->pauth_active) {
1420 gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
1422 break;
1423 case 0b11110: /* AUTIBZ */
1424 if (s->pauth_active) {
1425 gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30],
1426 new_tmp_a64_zero(s));
1428 break;
1429 case 0b11111: /* AUTIBSP */
1430 if (s->pauth_active) {
1431 gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
1433 break;
1434 default:
1435 /* default specified as NOP equivalent */
1436 break;
1440 static void gen_clrex(DisasContext *s, uint32_t insn)
1442 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1445 /* CLREX, DSB, DMB, ISB */
1446 static void handle_sync(DisasContext *s, uint32_t insn,
1447 unsigned int op1, unsigned int op2, unsigned int crm)
1449 TCGBar bar;
1451 if (op1 != 3) {
1452 unallocated_encoding(s);
1453 return;
1456 switch (op2) {
1457 case 2: /* CLREX */
1458 gen_clrex(s, insn);
1459 return;
1460 case 4: /* DSB */
1461 case 5: /* DMB */
1462 switch (crm & 3) {
1463 case 1: /* MBReqTypes_Reads */
1464 bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST;
1465 break;
1466 case 2: /* MBReqTypes_Writes */
1467 bar = TCG_BAR_SC | TCG_MO_ST_ST;
1468 break;
1469 default: /* MBReqTypes_All */
1470 bar = TCG_BAR_SC | TCG_MO_ALL;
1471 break;
1473 tcg_gen_mb(bar);
1474 return;
1475 case 6: /* ISB */
1476 /* We need to break the TB after this insn to execute
1477 * a self-modified code correctly and also to take
1478 * any pending interrupts immediately.
1480 reset_btype(s);
1481 gen_goto_tb(s, 0, s->base.pc_next);
1482 return;
1484 case 7: /* SB */
1485 if (crm != 0 || !dc_isar_feature(aa64_sb, s)) {
1486 goto do_unallocated;
1489 * TODO: There is no speculation barrier opcode for TCG;
1490 * MB and end the TB instead.
1492 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
1493 gen_goto_tb(s, 0, s->base.pc_next);
1494 return;
1496 default:
1497 do_unallocated:
1498 unallocated_encoding(s);
1499 return;
1503 static void gen_xaflag(void)
1505 TCGv_i32 z = tcg_temp_new_i32();
1507 tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0);
1510 * (!C & !Z) << 31
1511 * (!(C | Z)) << 31
1512 * ~((C | Z) << 31)
1513 * ~-(C | Z)
1514 * (C | Z) - 1
1516 tcg_gen_or_i32(cpu_NF, cpu_CF, z);
1517 tcg_gen_subi_i32(cpu_NF, cpu_NF, 1);
1519 /* !(Z & C) */
1520 tcg_gen_and_i32(cpu_ZF, z, cpu_CF);
1521 tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1);
1523 /* (!C & Z) << 31 -> -(Z & ~C) */
1524 tcg_gen_andc_i32(cpu_VF, z, cpu_CF);
1525 tcg_gen_neg_i32(cpu_VF, cpu_VF);
1527 /* C | Z */
1528 tcg_gen_or_i32(cpu_CF, cpu_CF, z);
1530 tcg_temp_free_i32(z);
1533 static void gen_axflag(void)
1535 tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */
1536 tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */
1538 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1539 tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF);
1541 tcg_gen_movi_i32(cpu_NF, 0);
1542 tcg_gen_movi_i32(cpu_VF, 0);
1545 /* MSR (immediate) - move immediate to processor state field */
1546 static void handle_msr_i(DisasContext *s, uint32_t insn,
1547 unsigned int op1, unsigned int op2, unsigned int crm)
1549 TCGv_i32 t1;
1550 int op = op1 << 3 | op2;
1552 /* End the TB by default, chaining is ok. */
1553 s->base.is_jmp = DISAS_TOO_MANY;
1555 switch (op) {
1556 case 0x00: /* CFINV */
1557 if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) {
1558 goto do_unallocated;
1560 tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
1561 s->base.is_jmp = DISAS_NEXT;
1562 break;
1564 case 0x01: /* XAFlag */
1565 if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
1566 goto do_unallocated;
1568 gen_xaflag();
1569 s->base.is_jmp = DISAS_NEXT;
1570 break;
1572 case 0x02: /* AXFlag */
1573 if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
1574 goto do_unallocated;
1576 gen_axflag();
1577 s->base.is_jmp = DISAS_NEXT;
1578 break;
1580 case 0x03: /* UAO */
1581 if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) {
1582 goto do_unallocated;
1584 if (crm & 1) {
1585 set_pstate_bits(PSTATE_UAO);
1586 } else {
1587 clear_pstate_bits(PSTATE_UAO);
1589 t1 = tcg_const_i32(s->current_el);
1590 gen_helper_rebuild_hflags_a64(cpu_env, t1);
1591 tcg_temp_free_i32(t1);
1592 break;
1594 case 0x04: /* PAN */
1595 if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) {
1596 goto do_unallocated;
1598 if (crm & 1) {
1599 set_pstate_bits(PSTATE_PAN);
1600 } else {
1601 clear_pstate_bits(PSTATE_PAN);
1603 t1 = tcg_const_i32(s->current_el);
1604 gen_helper_rebuild_hflags_a64(cpu_env, t1);
1605 tcg_temp_free_i32(t1);
1606 break;
1608 case 0x05: /* SPSel */
1609 if (s->current_el == 0) {
1610 goto do_unallocated;
1612 t1 = tcg_const_i32(crm & PSTATE_SP);
1613 gen_helper_msr_i_spsel(cpu_env, t1);
1614 tcg_temp_free_i32(t1);
1615 break;
1617 case 0x1e: /* DAIFSet */
1618 t1 = tcg_const_i32(crm);
1619 gen_helper_msr_i_daifset(cpu_env, t1);
1620 tcg_temp_free_i32(t1);
1621 break;
1623 case 0x1f: /* DAIFClear */
1624 t1 = tcg_const_i32(crm);
1625 gen_helper_msr_i_daifclear(cpu_env, t1);
1626 tcg_temp_free_i32(t1);
1627 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1628 s->base.is_jmp = DISAS_UPDATE;
1629 break;
1631 default:
1632 do_unallocated:
1633 unallocated_encoding(s);
1634 return;
1638 static void gen_get_nzcv(TCGv_i64 tcg_rt)
1640 TCGv_i32 tmp = tcg_temp_new_i32();
1641 TCGv_i32 nzcv = tcg_temp_new_i32();
1643 /* build bit 31, N */
1644 tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31));
1645 /* build bit 30, Z */
1646 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);
1647 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1);
1648 /* build bit 29, C */
1649 tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1);
1650 /* build bit 28, V */
1651 tcg_gen_shri_i32(tmp, cpu_VF, 31);
1652 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1);
1653 /* generate result */
1654 tcg_gen_extu_i32_i64(tcg_rt, nzcv);
1656 tcg_temp_free_i32(nzcv);
1657 tcg_temp_free_i32(tmp);
1660 static void gen_set_nzcv(TCGv_i64 tcg_rt)
1662 TCGv_i32 nzcv = tcg_temp_new_i32();
1664 /* take NZCV from R[t] */
1665 tcg_gen_extrl_i64_i32(nzcv, tcg_rt);
1667 /* bit 31, N */
1668 tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31));
1669 /* bit 30, Z */
1670 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30));
1671 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
1672 /* bit 29, C */
1673 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29));
1674 tcg_gen_shri_i32(cpu_CF, cpu_CF, 29);
1675 /* bit 28, V */
1676 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28));
1677 tcg_gen_shli_i32(cpu_VF, cpu_VF, 3);
1678 tcg_temp_free_i32(nzcv);
1681 /* MRS - move from system register
1682 * MSR (register) - move to system register
1683 * SYS
1684 * SYSL
1685 * These are all essentially the same insn in 'read' and 'write'
1686 * versions, with varying op0 fields.
1688 static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
1689 unsigned int op0, unsigned int op1, unsigned int op2,
1690 unsigned int crn, unsigned int crm, unsigned int rt)
1692 const ARMCPRegInfo *ri;
1693 TCGv_i64 tcg_rt;
1695 ri = get_arm_cp_reginfo(s->cp_regs,
1696 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
1697 crn, crm, op0, op1, op2));
1699 if (!ri) {
1700 /* Unknown register; this might be a guest error or a QEMU
1701 * unimplemented feature.
1703 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
1704 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1705 isread ? "read" : "write", op0, op1, crn, crm, op2);
1706 unallocated_encoding(s);
1707 return;
1710 /* Check access permissions */
1711 if (!cp_access_ok(s->current_el, ri, isread)) {
1712 unallocated_encoding(s);
1713 return;
1716 if (ri->accessfn) {
1717 /* Emit code to perform further access permissions checks at
1718 * runtime; this may result in an exception.
1720 TCGv_ptr tmpptr;
1721 TCGv_i32 tcg_syn, tcg_isread;
1722 uint32_t syndrome;
1724 gen_a64_set_pc_im(s->pc_curr);
1725 tmpptr = tcg_const_ptr(ri);
1726 syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
1727 tcg_syn = tcg_const_i32(syndrome);
1728 tcg_isread = tcg_const_i32(isread);
1729 gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
1730 tcg_temp_free_ptr(tmpptr);
1731 tcg_temp_free_i32(tcg_syn);
1732 tcg_temp_free_i32(tcg_isread);
1733 } else if (ri->type & ARM_CP_RAISES_EXC) {
1735 * The readfn or writefn might raise an exception;
1736 * synchronize the CPU state in case it does.
1738 gen_a64_set_pc_im(s->pc_curr);
1741 /* Handle special cases first */
1742 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
1743 case ARM_CP_NOP:
1744 return;
1745 case ARM_CP_NZCV:
1746 tcg_rt = cpu_reg(s, rt);
1747 if (isread) {
1748 gen_get_nzcv(tcg_rt);
1749 } else {
1750 gen_set_nzcv(tcg_rt);
1752 return;
1753 case ARM_CP_CURRENTEL:
1754 /* Reads as current EL value from pstate, which is
1755 * guaranteed to be constant by the tb flags.
1757 tcg_rt = cpu_reg(s, rt);
1758 tcg_gen_movi_i64(tcg_rt, s->current_el << 2);
1759 return;
1760 case ARM_CP_DC_ZVA:
1761 /* Writes clear the aligned block of memory which rt points into. */
1762 tcg_rt = clean_data_tbi(s, cpu_reg(s, rt));
1763 gen_helper_dc_zva(cpu_env, tcg_rt);
1764 return;
1765 default:
1766 break;
1768 if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
1769 return;
1770 } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
1771 return;
1774 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
1775 gen_io_start();
1778 tcg_rt = cpu_reg(s, rt);
1780 if (isread) {
1781 if (ri->type & ARM_CP_CONST) {
1782 tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
1783 } else if (ri->readfn) {
1784 TCGv_ptr tmpptr;
1785 tmpptr = tcg_const_ptr(ri);
1786 gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
1787 tcg_temp_free_ptr(tmpptr);
1788 } else {
1789 tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
1791 } else {
1792 if (ri->type & ARM_CP_CONST) {
1793 /* If not forbidden by access permissions, treat as WI */
1794 return;
1795 } else if (ri->writefn) {
1796 TCGv_ptr tmpptr;
1797 tmpptr = tcg_const_ptr(ri);
1798 gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
1799 tcg_temp_free_ptr(tmpptr);
1800 } else {
1801 tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
1805 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
1806 /* I/O operations must end the TB here (whether read or write) */
1807 s->base.is_jmp = DISAS_UPDATE;
1809 if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
1811 * A write to any coprocessor regiser that ends a TB
1812 * must rebuild the hflags for the next TB.
1814 TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
1815 gen_helper_rebuild_hflags_a64(cpu_env, tcg_el);
1816 tcg_temp_free_i32(tcg_el);
1818 * We default to ending the TB on a coprocessor register write,
1819 * but allow this to be suppressed by the register definition
1820 * (usually only necessary to work around guest bugs).
1822 s->base.is_jmp = DISAS_UPDATE;
1826 /* System
1827 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1828 * +---------------------+---+-----+-----+-------+-------+-----+------+
1829 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1830 * +---------------------+---+-----+-----+-------+-------+-----+------+
1832 static void disas_system(DisasContext *s, uint32_t insn)
1834 unsigned int l, op0, op1, crn, crm, op2, rt;
1835 l = extract32(insn, 21, 1);
1836 op0 = extract32(insn, 19, 2);
1837 op1 = extract32(insn, 16, 3);
1838 crn = extract32(insn, 12, 4);
1839 crm = extract32(insn, 8, 4);
1840 op2 = extract32(insn, 5, 3);
1841 rt = extract32(insn, 0, 5);
1843 if (op0 == 0) {
1844 if (l || rt != 31) {
1845 unallocated_encoding(s);
1846 return;
1848 switch (crn) {
1849 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1850 handle_hint(s, insn, op1, op2, crm);
1851 break;
1852 case 3: /* CLREX, DSB, DMB, ISB */
1853 handle_sync(s, insn, op1, op2, crm);
1854 break;
1855 case 4: /* MSR (immediate) */
1856 handle_msr_i(s, insn, op1, op2, crm);
1857 break;
1858 default:
1859 unallocated_encoding(s);
1860 break;
1862 return;
1864 handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
1867 /* Exception generation
1869 * 31 24 23 21 20 5 4 2 1 0
1870 * +-----------------+-----+------------------------+-----+----+
1871 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1872 * +-----------------------+------------------------+----------+
1874 static void disas_exc(DisasContext *s, uint32_t insn)
1876 int opc = extract32(insn, 21, 3);
1877 int op2_ll = extract32(insn, 0, 5);
1878 int imm16 = extract32(insn, 5, 16);
1879 TCGv_i32 tmp;
1881 switch (opc) {
1882 case 0:
1883 /* For SVC, HVC and SMC we advance the single-step state
1884 * machine before taking the exception. This is architecturally
1885 * mandated, to ensure that single-stepping a system call
1886 * instruction works properly.
1888 switch (op2_ll) {
1889 case 1: /* SVC */
1890 gen_ss_advance(s);
1891 gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
1892 syn_aa64_svc(imm16), default_exception_el(s));
1893 break;
1894 case 2: /* HVC */
1895 if (s->current_el == 0) {
1896 unallocated_encoding(s);
1897 break;
1899 /* The pre HVC helper handles cases when HVC gets trapped
1900 * as an undefined insn by runtime configuration.
1902 gen_a64_set_pc_im(s->pc_curr);
1903 gen_helper_pre_hvc(cpu_env);
1904 gen_ss_advance(s);
1905 gen_exception_insn(s, s->base.pc_next, EXCP_HVC,
1906 syn_aa64_hvc(imm16), 2);
1907 break;
1908 case 3: /* SMC */
1909 if (s->current_el == 0) {
1910 unallocated_encoding(s);
1911 break;
1913 gen_a64_set_pc_im(s->pc_curr);
1914 tmp = tcg_const_i32(syn_aa64_smc(imm16));
1915 gen_helper_pre_smc(cpu_env, tmp);
1916 tcg_temp_free_i32(tmp);
1917 gen_ss_advance(s);
1918 gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
1919 syn_aa64_smc(imm16), 3);
1920 break;
1921 default:
1922 unallocated_encoding(s);
1923 break;
1925 break;
1926 case 1:
1927 if (op2_ll != 0) {
1928 unallocated_encoding(s);
1929 break;
1931 /* BRK */
1932 gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16));
1933 break;
1934 case 2:
1935 if (op2_ll != 0) {
1936 unallocated_encoding(s);
1937 break;
1939 /* HLT. This has two purposes.
1940 * Architecturally, it is an external halting debug instruction.
1941 * Since QEMU doesn't implement external debug, we treat this as
1942 * it is required for halting debug disabled: it will UNDEF.
1943 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1945 if (semihosting_enabled() && imm16 == 0xf000) {
1946 #ifndef CONFIG_USER_ONLY
1947 /* In system mode, don't allow userspace access to semihosting,
1948 * to provide some semblance of security (and for consistency
1949 * with our 32-bit semihosting).
1951 if (s->current_el == 0) {
1952 unsupported_encoding(s, insn);
1953 break;
1955 #endif
1956 gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
1957 } else {
1958 unsupported_encoding(s, insn);
1960 break;
1961 case 5:
1962 if (op2_ll < 1 || op2_ll > 3) {
1963 unallocated_encoding(s);
1964 break;
1966 /* DCPS1, DCPS2, DCPS3 */
1967 unsupported_encoding(s, insn);
1968 break;
1969 default:
1970 unallocated_encoding(s);
1971 break;
1975 /* Unconditional branch (register)
1976 * 31 25 24 21 20 16 15 10 9 5 4 0
1977 * +---------------+-------+-------+-------+------+-------+
1978 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1979 * +---------------+-------+-------+-------+------+-------+
1981 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
1983 unsigned int opc, op2, op3, rn, op4;
1984 unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */
1985 TCGv_i64 dst;
1986 TCGv_i64 modifier;
1988 opc = extract32(insn, 21, 4);
1989 op2 = extract32(insn, 16, 5);
1990 op3 = extract32(insn, 10, 6);
1991 rn = extract32(insn, 5, 5);
1992 op4 = extract32(insn, 0, 5);
1994 if (op2 != 0x1f) {
1995 goto do_unallocated;
1998 switch (opc) {
1999 case 0: /* BR */
2000 case 1: /* BLR */
2001 case 2: /* RET */
2002 btype_mod = opc;
2003 switch (op3) {
2004 case 0:
2005 /* BR, BLR, RET */
2006 if (op4 != 0) {
2007 goto do_unallocated;
2009 dst = cpu_reg(s, rn);
2010 break;
2012 case 2:
2013 case 3:
2014 if (!dc_isar_feature(aa64_pauth, s)) {
2015 goto do_unallocated;
2017 if (opc == 2) {
2018 /* RETAA, RETAB */
2019 if (rn != 0x1f || op4 != 0x1f) {
2020 goto do_unallocated;
2022 rn = 30;
2023 modifier = cpu_X[31];
2024 } else {
2025 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2026 if (op4 != 0x1f) {
2027 goto do_unallocated;
2029 modifier = new_tmp_a64_zero(s);
2031 if (s->pauth_active) {
2032 dst = new_tmp_a64(s);
2033 if (op3 == 2) {
2034 gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
2035 } else {
2036 gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
2038 } else {
2039 dst = cpu_reg(s, rn);
2041 break;
2043 default:
2044 goto do_unallocated;
2046 gen_a64_set_pc(s, dst);
2047 /* BLR also needs to load return address */
2048 if (opc == 1) {
2049 tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
2051 break;
2053 case 8: /* BRAA */
2054 case 9: /* BLRAA */
2055 if (!dc_isar_feature(aa64_pauth, s)) {
2056 goto do_unallocated;
2058 if ((op3 & ~1) != 2) {
2059 goto do_unallocated;
2061 btype_mod = opc & 1;
2062 if (s->pauth_active) {
2063 dst = new_tmp_a64(s);
2064 modifier = cpu_reg_sp(s, op4);
2065 if (op3 == 2) {
2066 gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
2067 } else {
2068 gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
2070 } else {
2071 dst = cpu_reg(s, rn);
2073 gen_a64_set_pc(s, dst);
2074 /* BLRAA also needs to load return address */
2075 if (opc == 9) {
2076 tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
2078 break;
2080 case 4: /* ERET */
2081 if (s->current_el == 0) {
2082 goto do_unallocated;
2084 switch (op3) {
2085 case 0: /* ERET */
2086 if (op4 != 0) {
2087 goto do_unallocated;
2089 dst = tcg_temp_new_i64();
2090 tcg_gen_ld_i64(dst, cpu_env,
2091 offsetof(CPUARMState, elr_el[s->current_el]));
2092 break;
2094 case 2: /* ERETAA */
2095 case 3: /* ERETAB */
2096 if (!dc_isar_feature(aa64_pauth, s)) {
2097 goto do_unallocated;
2099 if (rn != 0x1f || op4 != 0x1f) {
2100 goto do_unallocated;
2102 dst = tcg_temp_new_i64();
2103 tcg_gen_ld_i64(dst, cpu_env,
2104 offsetof(CPUARMState, elr_el[s->current_el]));
2105 if (s->pauth_active) {
2106 modifier = cpu_X[31];
2107 if (op3 == 2) {
2108 gen_helper_autia(dst, cpu_env, dst, modifier);
2109 } else {
2110 gen_helper_autib(dst, cpu_env, dst, modifier);
2113 break;
2115 default:
2116 goto do_unallocated;
2118 if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
2119 gen_io_start();
2122 gen_helper_exception_return(cpu_env, dst);
2123 tcg_temp_free_i64(dst);
2124 /* Must exit loop to check un-masked IRQs */
2125 s->base.is_jmp = DISAS_EXIT;
2126 return;
2128 case 5: /* DRPS */
2129 if (op3 != 0 || op4 != 0 || rn != 0x1f) {
2130 goto do_unallocated;
2131 } else {
2132 unsupported_encoding(s, insn);
2134 return;
2136 default:
2137 do_unallocated:
2138 unallocated_encoding(s);
2139 return;
2142 switch (btype_mod) {
2143 case 0: /* BR */
2144 if (dc_isar_feature(aa64_bti, s)) {
2145 /* BR to {x16,x17} or !guard -> 1, else 3. */
2146 set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3);
2148 break;
2150 case 1: /* BLR */
2151 if (dc_isar_feature(aa64_bti, s)) {
2152 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2153 set_btype(s, 2);
2155 break;
2157 default: /* RET or none of the above. */
2158 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2159 break;
2162 s->base.is_jmp = DISAS_JUMP;
2165 /* Branches, exception generating and system instructions */
2166 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
2168 switch (extract32(insn, 25, 7)) {
2169 case 0x0a: case 0x0b:
2170 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2171 disas_uncond_b_imm(s, insn);
2172 break;
2173 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2174 disas_comp_b_imm(s, insn);
2175 break;
2176 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2177 disas_test_b_imm(s, insn);
2178 break;
2179 case 0x2a: /* Conditional branch (immediate) */
2180 disas_cond_b_imm(s, insn);
2181 break;
2182 case 0x6a: /* Exception generation / System */
2183 if (insn & (1 << 24)) {
2184 if (extract32(insn, 22, 2) == 0) {
2185 disas_system(s, insn);
2186 } else {
2187 unallocated_encoding(s);
2189 } else {
2190 disas_exc(s, insn);
2192 break;
2193 case 0x6b: /* Unconditional branch (register) */
2194 disas_uncond_b_reg(s, insn);
2195 break;
2196 default:
2197 unallocated_encoding(s);
2198 break;
2203 * Load/Store exclusive instructions are implemented by remembering
2204 * the value/address loaded, and seeing if these are the same
2205 * when the store is performed. This is not actually the architecturally
2206 * mandated semantics, but it works for typical guest code sequences
2207 * and avoids having to monitor regular stores.
2209 * The store exclusive uses the atomic cmpxchg primitives to avoid
2210 * races in multi-threaded linux-user and when MTTCG softmmu is
2211 * enabled.
2213 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
2214 TCGv_i64 addr, int size, bool is_pair)
2216 int idx = get_mem_index(s);
2217 MemOp memop = s->be_data;
2219 g_assert(size <= 3);
2220 if (is_pair) {
2221 g_assert(size >= 2);
2222 if (size == 2) {
2223 /* The pair must be single-copy atomic for the doubleword. */
2224 memop |= MO_64 | MO_ALIGN;
2225 tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);
2226 if (s->be_data == MO_LE) {
2227 tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32);
2228 tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32);
2229 } else {
2230 tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32);
2231 tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32);
2233 } else {
2234 /* The pair must be single-copy atomic for *each* doubleword, not
2235 the entire quadword, however it must be quadword aligned. */
2236 memop |= MO_64;
2237 tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx,
2238 memop | MO_ALIGN_16);
2240 TCGv_i64 addr2 = tcg_temp_new_i64();
2241 tcg_gen_addi_i64(addr2, addr, 8);
2242 tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop);
2243 tcg_temp_free_i64(addr2);
2245 tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
2246 tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high);
2248 } else {
2249 memop |= size | MO_ALIGN;
2250 tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);
2251 tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
2253 tcg_gen_mov_i64(cpu_exclusive_addr, addr);
2256 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
2257 TCGv_i64 addr, int size, int is_pair)
2259 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2260 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2261 * [addr] = {Rt};
2262 * if (is_pair) {
2263 * [addr + datasize] = {Rt2};
2265 * {Rd} = 0;
2266 * } else {
2267 * {Rd} = 1;
2269 * env->exclusive_addr = -1;
2271 TCGLabel *fail_label = gen_new_label();
2272 TCGLabel *done_label = gen_new_label();
2273 TCGv_i64 tmp;
2275 tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
2277 tmp = tcg_temp_new_i64();
2278 if (is_pair) {
2279 if (size == 2) {
2280 if (s->be_data == MO_LE) {
2281 tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2));
2282 } else {
2283 tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt));
2285 tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,
2286 cpu_exclusive_val, tmp,
2287 get_mem_index(s),
2288 MO_64 | MO_ALIGN | s->be_data);
2289 tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
2290 } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2291 if (!HAVE_CMPXCHG128) {
2292 gen_helper_exit_atomic(cpu_env);
2293 s->base.is_jmp = DISAS_NORETURN;
2294 } else if (s->be_data == MO_LE) {
2295 gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env,
2296 cpu_exclusive_addr,
2297 cpu_reg(s, rt),
2298 cpu_reg(s, rt2));
2299 } else {
2300 gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env,
2301 cpu_exclusive_addr,
2302 cpu_reg(s, rt),
2303 cpu_reg(s, rt2));
2305 } else if (s->be_data == MO_LE) {
2306 gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr,
2307 cpu_reg(s, rt), cpu_reg(s, rt2));
2308 } else {
2309 gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr,
2310 cpu_reg(s, rt), cpu_reg(s, rt2));
2312 } else {
2313 tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,
2314 cpu_reg(s, rt), get_mem_index(s),
2315 size | MO_ALIGN | s->be_data);
2316 tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
2318 tcg_gen_mov_i64(cpu_reg(s, rd), tmp);
2319 tcg_temp_free_i64(tmp);
2320 tcg_gen_br(done_label);
2322 gen_set_label(fail_label);
2323 tcg_gen_movi_i64(cpu_reg(s, rd), 1);
2324 gen_set_label(done_label);
2325 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
2328 static void gen_compare_and_swap(DisasContext *s, int rs, int rt,
2329 int rn, int size)
2331 TCGv_i64 tcg_rs = cpu_reg(s, rs);
2332 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2333 int memidx = get_mem_index(s);
2334 TCGv_i64 clean_addr;
2336 if (rn == 31) {
2337 gen_check_sp_alignment(s);
2339 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
2340 tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx,
2341 size | MO_ALIGN | s->be_data);
2344 static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
2345 int rn, int size)
2347 TCGv_i64 s1 = cpu_reg(s, rs);
2348 TCGv_i64 s2 = cpu_reg(s, rs + 1);
2349 TCGv_i64 t1 = cpu_reg(s, rt);
2350 TCGv_i64 t2 = cpu_reg(s, rt + 1);
2351 TCGv_i64 clean_addr;
2352 int memidx = get_mem_index(s);
2354 if (rn == 31) {
2355 gen_check_sp_alignment(s);
2357 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
2359 if (size == 2) {
2360 TCGv_i64 cmp = tcg_temp_new_i64();
2361 TCGv_i64 val = tcg_temp_new_i64();
2363 if (s->be_data == MO_LE) {
2364 tcg_gen_concat32_i64(val, t1, t2);
2365 tcg_gen_concat32_i64(cmp, s1, s2);
2366 } else {
2367 tcg_gen_concat32_i64(val, t2, t1);
2368 tcg_gen_concat32_i64(cmp, s2, s1);
2371 tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx,
2372 MO_64 | MO_ALIGN | s->be_data);
2373 tcg_temp_free_i64(val);
2375 if (s->be_data == MO_LE) {
2376 tcg_gen_extr32_i64(s1, s2, cmp);
2377 } else {
2378 tcg_gen_extr32_i64(s2, s1, cmp);
2380 tcg_temp_free_i64(cmp);
2381 } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2382 if (HAVE_CMPXCHG128) {
2383 TCGv_i32 tcg_rs = tcg_const_i32(rs);
2384 if (s->be_data == MO_LE) {
2385 gen_helper_casp_le_parallel(cpu_env, tcg_rs,
2386 clean_addr, t1, t2);
2387 } else {
2388 gen_helper_casp_be_parallel(cpu_env, tcg_rs,
2389 clean_addr, t1, t2);
2391 tcg_temp_free_i32(tcg_rs);
2392 } else {
2393 gen_helper_exit_atomic(cpu_env);
2394 s->base.is_jmp = DISAS_NORETURN;
2396 } else {
2397 TCGv_i64 d1 = tcg_temp_new_i64();
2398 TCGv_i64 d2 = tcg_temp_new_i64();
2399 TCGv_i64 a2 = tcg_temp_new_i64();
2400 TCGv_i64 c1 = tcg_temp_new_i64();
2401 TCGv_i64 c2 = tcg_temp_new_i64();
2402 TCGv_i64 zero = tcg_const_i64(0);
2404 /* Load the two words, in memory order. */
2405 tcg_gen_qemu_ld_i64(d1, clean_addr, memidx,
2406 MO_64 | MO_ALIGN_16 | s->be_data);
2407 tcg_gen_addi_i64(a2, clean_addr, 8);
2408 tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data);
2410 /* Compare the two words, also in memory order. */
2411 tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1);
2412 tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2);
2413 tcg_gen_and_i64(c2, c2, c1);
2415 /* If compare equal, write back new data, else write back old data. */
2416 tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1);
2417 tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2);
2418 tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data);
2419 tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data);
2420 tcg_temp_free_i64(a2);
2421 tcg_temp_free_i64(c1);
2422 tcg_temp_free_i64(c2);
2423 tcg_temp_free_i64(zero);
2425 /* Write back the data from memory to Rs. */
2426 tcg_gen_mov_i64(s1, d1);
2427 tcg_gen_mov_i64(s2, d2);
2428 tcg_temp_free_i64(d1);
2429 tcg_temp_free_i64(d2);
2433 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2434 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2436 static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
2438 int opc0 = extract32(opc, 0, 1);
2439 int regsize;
2441 if (is_signed) {
2442 regsize = opc0 ? 32 : 64;
2443 } else {
2444 regsize = size == 3 ? 64 : 32;
2446 return regsize == 64;
2449 /* Load/store exclusive
2451 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2452 * +-----+-------------+----+---+----+------+----+-------+------+------+
2453 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2454 * +-----+-------------+----+---+----+------+----+-------+------+------+
2456 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2457 * L: 0 -> store, 1 -> load
2458 * o2: 0 -> exclusive, 1 -> not
2459 * o1: 0 -> single register, 1 -> register pair
2460 * o0: 1 -> load-acquire/store-release, 0 -> not
2462 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
2464 int rt = extract32(insn, 0, 5);
2465 int rn = extract32(insn, 5, 5);
2466 int rt2 = extract32(insn, 10, 5);
2467 int rs = extract32(insn, 16, 5);
2468 int is_lasr = extract32(insn, 15, 1);
2469 int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr;
2470 int size = extract32(insn, 30, 2);
2471 TCGv_i64 clean_addr;
2473 switch (o2_L_o1_o0) {
2474 case 0x0: /* STXR */
2475 case 0x1: /* STLXR */
2476 if (rn == 31) {
2477 gen_check_sp_alignment(s);
2479 if (is_lasr) {
2480 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
2482 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
2483 gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false);
2484 return;
2486 case 0x4: /* LDXR */
2487 case 0x5: /* LDAXR */
2488 if (rn == 31) {
2489 gen_check_sp_alignment(s);
2491 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
2492 s->is_ldex = true;
2493 gen_load_exclusive(s, rt, rt2, clean_addr, size, false);
2494 if (is_lasr) {
2495 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
2497 return;
2499 case 0x8: /* STLLR */
2500 if (!dc_isar_feature(aa64_lor, s)) {
2501 break;
2503 /* StoreLORelease is the same as Store-Release for QEMU. */
2504 /* fall through */
2505 case 0x9: /* STLR */
2506 /* Generate ISS for non-exclusive accesses including LASR. */
2507 if (rn == 31) {
2508 gen_check_sp_alignment(s);
2510 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
2511 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
2512 do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt,
2513 disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
2514 return;
2516 case 0xc: /* LDLAR */
2517 if (!dc_isar_feature(aa64_lor, s)) {
2518 break;
2520 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2521 /* fall through */
2522 case 0xd: /* LDAR */
2523 /* Generate ISS for non-exclusive accesses including LASR. */
2524 if (rn == 31) {
2525 gen_check_sp_alignment(s);
2527 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
2528 do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt,
2529 disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
2530 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
2531 return;
2533 case 0x2: case 0x3: /* CASP / STXP */
2534 if (size & 2) { /* STXP / STLXP */
2535 if (rn == 31) {
2536 gen_check_sp_alignment(s);
2538 if (is_lasr) {
2539 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
2541 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
2542 gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true);
2543 return;
2545 if (rt2 == 31
2546 && ((rt | rs) & 1) == 0
2547 && dc_isar_feature(aa64_atomics, s)) {
2548 /* CASP / CASPL */
2549 gen_compare_and_swap_pair(s, rs, rt, rn, size | 2);
2550 return;
2552 break;
2554 case 0x6: case 0x7: /* CASPA / LDXP */
2555 if (size & 2) { /* LDXP / LDAXP */
2556 if (rn == 31) {
2557 gen_check_sp_alignment(s);
2559 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
2560 s->is_ldex = true;
2561 gen_load_exclusive(s, rt, rt2, clean_addr, size, true);
2562 if (is_lasr) {
2563 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
2565 return;
2567 if (rt2 == 31
2568 && ((rt | rs) & 1) == 0
2569 && dc_isar_feature(aa64_atomics, s)) {
2570 /* CASPA / CASPAL */
2571 gen_compare_and_swap_pair(s, rs, rt, rn, size | 2);
2572 return;
2574 break;
2576 case 0xa: /* CAS */
2577 case 0xb: /* CASL */
2578 case 0xe: /* CASA */
2579 case 0xf: /* CASAL */
2580 if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) {
2581 gen_compare_and_swap(s, rs, rt, rn, size);
2582 return;
2584 break;
2586 unallocated_encoding(s);
2590 * Load register (literal)
2592 * 31 30 29 27 26 25 24 23 5 4 0
2593 * +-----+-------+---+-----+-------------------+-------+
2594 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2595 * +-----+-------+---+-----+-------------------+-------+
2597 * V: 1 -> vector (simd/fp)
2598 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2599 * 10-> 32 bit signed, 11 -> prefetch
2600 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2602 static void disas_ld_lit(DisasContext *s, uint32_t insn)
2604 int rt = extract32(insn, 0, 5);
2605 int64_t imm = sextract32(insn, 5, 19) << 2;
2606 bool is_vector = extract32(insn, 26, 1);
2607 int opc = extract32(insn, 30, 2);
2608 bool is_signed = false;
2609 int size = 2;
2610 TCGv_i64 tcg_rt, clean_addr;
2612 if (is_vector) {
2613 if (opc == 3) {
2614 unallocated_encoding(s);
2615 return;
2617 size = 2 + opc;
2618 if (!fp_access_check(s)) {
2619 return;
2621 } else {
2622 if (opc == 3) {
2623 /* PRFM (literal) : prefetch */
2624 return;
2626 size = 2 + extract32(opc, 0, 1);
2627 is_signed = extract32(opc, 1, 1);
2630 tcg_rt = cpu_reg(s, rt);
2632 clean_addr = tcg_const_i64(s->pc_curr + imm);
2633 if (is_vector) {
2634 do_fp_ld(s, rt, clean_addr, size);
2635 } else {
2636 /* Only unsigned 32bit loads target 32bit registers. */
2637 bool iss_sf = opc != 0;
2639 do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false,
2640 true, rt, iss_sf, false);
2642 tcg_temp_free_i64(clean_addr);
2646 * LDNP (Load Pair - non-temporal hint)
2647 * LDP (Load Pair - non vector)
2648 * LDPSW (Load Pair Signed Word - non vector)
2649 * STNP (Store Pair - non-temporal hint)
2650 * STP (Store Pair - non vector)
2651 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2652 * LDP (Load Pair of SIMD&FP)
2653 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2654 * STP (Store Pair of SIMD&FP)
2656 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2657 * +-----+-------+---+---+-------+---+-----------------------------+
2658 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2659 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2661 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2662 * LDPSW 01
2663 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2664 * V: 0 -> GPR, 1 -> Vector
2665 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2666 * 10 -> signed offset, 11 -> pre-index
2667 * L: 0 -> Store 1 -> Load
2669 * Rt, Rt2 = GPR or SIMD registers to be stored
2670 * Rn = general purpose register containing address
2671 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2673 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
2675 int rt = extract32(insn, 0, 5);
2676 int rn = extract32(insn, 5, 5);
2677 int rt2 = extract32(insn, 10, 5);
2678 uint64_t offset = sextract64(insn, 15, 7);
2679 int index = extract32(insn, 23, 2);
2680 bool is_vector = extract32(insn, 26, 1);
2681 bool is_load = extract32(insn, 22, 1);
2682 int opc = extract32(insn, 30, 2);
2684 bool is_signed = false;
2685 bool postindex = false;
2686 bool wback = false;
2688 TCGv_i64 clean_addr, dirty_addr;
2690 int size;
2692 if (opc == 3) {
2693 unallocated_encoding(s);
2694 return;
2697 if (is_vector) {
2698 size = 2 + opc;
2699 } else {
2700 size = 2 + extract32(opc, 1, 1);
2701 is_signed = extract32(opc, 0, 1);
2702 if (!is_load && is_signed) {
2703 unallocated_encoding(s);
2704 return;
2708 switch (index) {
2709 case 1: /* post-index */
2710 postindex = true;
2711 wback = true;
2712 break;
2713 case 0:
2714 /* signed offset with "non-temporal" hint. Since we don't emulate
2715 * caches we don't care about hints to the cache system about
2716 * data access patterns, and handle this identically to plain
2717 * signed offset.
2719 if (is_signed) {
2720 /* There is no non-temporal-hint version of LDPSW */
2721 unallocated_encoding(s);
2722 return;
2724 postindex = false;
2725 break;
2726 case 2: /* signed offset, rn not updated */
2727 postindex = false;
2728 break;
2729 case 3: /* pre-index */
2730 postindex = false;
2731 wback = true;
2732 break;
2735 if (is_vector && !fp_access_check(s)) {
2736 return;
2739 offset <<= size;
2741 if (rn == 31) {
2742 gen_check_sp_alignment(s);
2745 dirty_addr = read_cpu_reg_sp(s, rn, 1);
2746 if (!postindex) {
2747 tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
2749 clean_addr = clean_data_tbi(s, dirty_addr);
2751 if (is_vector) {
2752 if (is_load) {
2753 do_fp_ld(s, rt, clean_addr, size);
2754 } else {
2755 do_fp_st(s, rt, clean_addr, size);
2757 tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size);
2758 if (is_load) {
2759 do_fp_ld(s, rt2, clean_addr, size);
2760 } else {
2761 do_fp_st(s, rt2, clean_addr, size);
2763 } else {
2764 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2765 TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
2767 if (is_load) {
2768 TCGv_i64 tmp = tcg_temp_new_i64();
2770 /* Do not modify tcg_rt before recognizing any exception
2771 * from the second load.
2773 do_gpr_ld(s, tmp, clean_addr, size, is_signed, false,
2774 false, 0, false, false);
2775 tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size);
2776 do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false,
2777 false, 0, false, false);
2779 tcg_gen_mov_i64(tcg_rt, tmp);
2780 tcg_temp_free_i64(tmp);
2781 } else {
2782 do_gpr_st(s, tcg_rt, clean_addr, size,
2783 false, 0, false, false);
2784 tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size);
2785 do_gpr_st(s, tcg_rt2, clean_addr, size,
2786 false, 0, false, false);
2790 if (wback) {
2791 if (postindex) {
2792 tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
2794 tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr);
2799 * Load/store (immediate post-indexed)
2800 * Load/store (immediate pre-indexed)
2801 * Load/store (unscaled immediate)
2803 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2804 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2805 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2806 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2808 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2809 10 -> unprivileged
2810 * V = 0 -> non-vector
2811 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2812 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2814 static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
2815 int opc,
2816 int size,
2817 int rt,
2818 bool is_vector)
2820 int rn = extract32(insn, 5, 5);
2821 int imm9 = sextract32(insn, 12, 9);
2822 int idx = extract32(insn, 10, 2);
2823 bool is_signed = false;
2824 bool is_store = false;
2825 bool is_extended = false;
2826 bool is_unpriv = (idx == 2);
2827 bool iss_valid = !is_vector;
2828 bool post_index;
2829 bool writeback;
2831 TCGv_i64 clean_addr, dirty_addr;
2833 if (is_vector) {
2834 size |= (opc & 2) << 1;
2835 if (size > 4 || is_unpriv) {
2836 unallocated_encoding(s);
2837 return;
2839 is_store = ((opc & 1) == 0);
2840 if (!fp_access_check(s)) {
2841 return;
2843 } else {
2844 if (size == 3 && opc == 2) {
2845 /* PRFM - prefetch */
2846 if (idx != 0) {
2847 unallocated_encoding(s);
2848 return;
2850 return;
2852 if (opc == 3 && size > 1) {
2853 unallocated_encoding(s);
2854 return;
2856 is_store = (opc == 0);
2857 is_signed = extract32(opc, 1, 1);
2858 is_extended = (size < 3) && extract32(opc, 0, 1);
2861 switch (idx) {
2862 case 0:
2863 case 2:
2864 post_index = false;
2865 writeback = false;
2866 break;
2867 case 1:
2868 post_index = true;
2869 writeback = true;
2870 break;
2871 case 3:
2872 post_index = false;
2873 writeback = true;
2874 break;
2875 default:
2876 g_assert_not_reached();
2879 if (rn == 31) {
2880 gen_check_sp_alignment(s);
2883 dirty_addr = read_cpu_reg_sp(s, rn, 1);
2884 if (!post_index) {
2885 tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9);
2887 clean_addr = clean_data_tbi(s, dirty_addr);
2889 if (is_vector) {
2890 if (is_store) {
2891 do_fp_st(s, rt, clean_addr, size);
2892 } else {
2893 do_fp_ld(s, rt, clean_addr, size);
2895 } else {
2896 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2897 int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
2898 bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
2900 if (is_store) {
2901 do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx,
2902 iss_valid, rt, iss_sf, false);
2903 } else {
2904 do_gpr_ld_memidx(s, tcg_rt, clean_addr, size,
2905 is_signed, is_extended, memidx,
2906 iss_valid, rt, iss_sf, false);
2910 if (writeback) {
2911 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2912 if (post_index) {
2913 tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9);
2915 tcg_gen_mov_i64(tcg_rn, dirty_addr);
2920 * Load/store (register offset)
2922 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2923 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2924 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2925 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2927 * For non-vector:
2928 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2929 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2930 * For vector:
2931 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2932 * opc<0>: 0 -> store, 1 -> load
2933 * V: 1 -> vector/simd
2934 * opt: extend encoding (see DecodeRegExtend)
2935 * S: if S=1 then scale (essentially index by sizeof(size))
2936 * Rt: register to transfer into/out of
2937 * Rn: address register or SP for base
2938 * Rm: offset register or ZR for offset
2940 static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
2941 int opc,
2942 int size,
2943 int rt,
2944 bool is_vector)
2946 int rn = extract32(insn, 5, 5);
2947 int shift = extract32(insn, 12, 1);
2948 int rm = extract32(insn, 16, 5);
2949 int opt = extract32(insn, 13, 3);
2950 bool is_signed = false;
2951 bool is_store = false;
2952 bool is_extended = false;
2954 TCGv_i64 tcg_rm, clean_addr, dirty_addr;
2956 if (extract32(opt, 1, 1) == 0) {
2957 unallocated_encoding(s);
2958 return;
2961 if (is_vector) {
2962 size |= (opc & 2) << 1;
2963 if (size > 4) {
2964 unallocated_encoding(s);
2965 return;
2967 is_store = !extract32(opc, 0, 1);
2968 if (!fp_access_check(s)) {
2969 return;
2971 } else {
2972 if (size == 3 && opc == 2) {
2973 /* PRFM - prefetch */
2974 return;
2976 if (opc == 3 && size > 1) {
2977 unallocated_encoding(s);
2978 return;
2980 is_store = (opc == 0);
2981 is_signed = extract32(opc, 1, 1);
2982 is_extended = (size < 3) && extract32(opc, 0, 1);
2985 if (rn == 31) {
2986 gen_check_sp_alignment(s);
2988 dirty_addr = read_cpu_reg_sp(s, rn, 1);
2990 tcg_rm = read_cpu_reg(s, rm, 1);
2991 ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
2993 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
2994 clean_addr = clean_data_tbi(s, dirty_addr);
2996 if (is_vector) {
2997 if (is_store) {
2998 do_fp_st(s, rt, clean_addr, size);
2999 } else {
3000 do_fp_ld(s, rt, clean_addr, size);
3002 } else {
3003 TCGv_i64 tcg_rt = cpu_reg(s, rt);
3004 bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
3005 if (is_store) {
3006 do_gpr_st(s, tcg_rt, clean_addr, size,
3007 true, rt, iss_sf, false);
3008 } else {
3009 do_gpr_ld(s, tcg_rt, clean_addr, size,
3010 is_signed, is_extended,
3011 true, rt, iss_sf, false);
3017 * Load/store (unsigned immediate)
3019 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3020 * +----+-------+---+-----+-----+------------+-------+------+
3021 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3022 * +----+-------+---+-----+-----+------------+-------+------+
3024 * For non-vector:
3025 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3026 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3027 * For vector:
3028 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3029 * opc<0>: 0 -> store, 1 -> load
3030 * Rn: base address register (inc SP)
3031 * Rt: target register
3033 static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
3034 int opc,
3035 int size,
3036 int rt,
3037 bool is_vector)
3039 int rn = extract32(insn, 5, 5);
3040 unsigned int imm12 = extract32(insn, 10, 12);
3041 unsigned int offset;
3043 TCGv_i64 clean_addr, dirty_addr;
3045 bool is_store;
3046 bool is_signed = false;
3047 bool is_extended = false;
3049 if (is_vector) {
3050 size |= (opc & 2) << 1;
3051 if (size > 4) {
3052 unallocated_encoding(s);
3053 return;
3055 is_store = !extract32(opc, 0, 1);
3056 if (!fp_access_check(s)) {
3057 return;
3059 } else {
3060 if (size == 3 && opc == 2) {
3061 /* PRFM - prefetch */
3062 return;
3064 if (opc == 3 && size > 1) {
3065 unallocated_encoding(s);
3066 return;
3068 is_store = (opc == 0);
3069 is_signed = extract32(opc, 1, 1);
3070 is_extended = (size < 3) && extract32(opc, 0, 1);
3073 if (rn == 31) {
3074 gen_check_sp_alignment(s);
3076 dirty_addr = read_cpu_reg_sp(s, rn, 1);
3077 offset = imm12 << size;
3078 tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
3079 clean_addr = clean_data_tbi(s, dirty_addr);
3081 if (is_vector) {
3082 if (is_store) {
3083 do_fp_st(s, rt, clean_addr, size);
3084 } else {
3085 do_fp_ld(s, rt, clean_addr, size);
3087 } else {
3088 TCGv_i64 tcg_rt = cpu_reg(s, rt);
3089 bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
3090 if (is_store) {
3091 do_gpr_st(s, tcg_rt, clean_addr, size,
3092 true, rt, iss_sf, false);
3093 } else {
3094 do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended,
3095 true, rt, iss_sf, false);
3100 /* Atomic memory operations
3102 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3103 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3104 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3105 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3107 * Rt: the result register
3108 * Rn: base address or SP
3109 * Rs: the source register for the operation
3110 * V: vector flag (always 0 as of v8.3)
3111 * A: acquire flag
3112 * R: release flag
3114 static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
3115 int size, int rt, bool is_vector)
3117 int rs = extract32(insn, 16, 5);
3118 int rn = extract32(insn, 5, 5);
3119 int o3_opc = extract32(insn, 12, 4);
3120 bool r = extract32(insn, 22, 1);
3121 bool a = extract32(insn, 23, 1);
3122 TCGv_i64 tcg_rs, clean_addr;
3123 AtomicThreeOpFn *fn;
3125 if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
3126 unallocated_encoding(s);
3127 return;
3129 switch (o3_opc) {
3130 case 000: /* LDADD */
3131 fn = tcg_gen_atomic_fetch_add_i64;
3132 break;
3133 case 001: /* LDCLR */
3134 fn = tcg_gen_atomic_fetch_and_i64;
3135 break;
3136 case 002: /* LDEOR */
3137 fn = tcg_gen_atomic_fetch_xor_i64;
3138 break;
3139 case 003: /* LDSET */
3140 fn = tcg_gen_atomic_fetch_or_i64;
3141 break;
3142 case 004: /* LDSMAX */
3143 fn = tcg_gen_atomic_fetch_smax_i64;
3144 break;
3145 case 005: /* LDSMIN */
3146 fn = tcg_gen_atomic_fetch_smin_i64;
3147 break;
3148 case 006: /* LDUMAX */
3149 fn = tcg_gen_atomic_fetch_umax_i64;
3150 break;
3151 case 007: /* LDUMIN */
3152 fn = tcg_gen_atomic_fetch_umin_i64;
3153 break;
3154 case 010: /* SWP */
3155 fn = tcg_gen_atomic_xchg_i64;
3156 break;
3157 case 014: /* LDAPR, LDAPRH, LDAPRB */
3158 if (!dc_isar_feature(aa64_rcpc_8_3, s) ||
3159 rs != 31 || a != 1 || r != 0) {
3160 unallocated_encoding(s);
3161 return;
3163 break;
3164 default:
3165 unallocated_encoding(s);
3166 return;
3169 if (rn == 31) {
3170 gen_check_sp_alignment(s);
3172 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
3174 if (o3_opc == 014) {
3176 * LDAPR* are a special case because they are a simple load, not a
3177 * fetch-and-do-something op.
3178 * The architectural consistency requirements here are weaker than
3179 * full load-acquire (we only need "load-acquire processor consistent"),
3180 * but we choose to implement them as full LDAQ.
3182 do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false,
3183 true, rt, disas_ldst_compute_iss_sf(size, false, 0), true);
3184 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3185 return;
3188 tcg_rs = read_cpu_reg(s, rs, true);
3190 if (o3_opc == 1) { /* LDCLR */
3191 tcg_gen_not_i64(tcg_rs, tcg_rs);
3194 /* The tcg atomic primitives are all full barriers. Therefore we
3195 * can ignore the Acquire and Release bits of this instruction.
3197 fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
3198 s->be_data | size | MO_ALIGN);
3202 * PAC memory operations
3204 * 31 30 27 26 24 22 21 12 11 10 5 0
3205 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3206 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3207 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3209 * Rt: the result register
3210 * Rn: base address or SP
3211 * V: vector flag (always 0 as of v8.3)
3212 * M: clear for key DA, set for key DB
3213 * W: pre-indexing flag
3214 * S: sign for imm9.
3216 static void disas_ldst_pac(DisasContext *s, uint32_t insn,
3217 int size, int rt, bool is_vector)
3219 int rn = extract32(insn, 5, 5);
3220 bool is_wback = extract32(insn, 11, 1);
3221 bool use_key_a = !extract32(insn, 23, 1);
3222 int offset;
3223 TCGv_i64 clean_addr, dirty_addr, tcg_rt;
3225 if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) {
3226 unallocated_encoding(s);
3227 return;
3230 if (rn == 31) {
3231 gen_check_sp_alignment(s);
3233 dirty_addr = read_cpu_reg_sp(s, rn, 1);
3235 if (s->pauth_active) {
3236 if (use_key_a) {
3237 gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
3238 } else {
3239 gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
3243 /* Form the 10-bit signed, scaled offset. */
3244 offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9);
3245 offset = sextract32(offset << size, 0, 10 + size);
3246 tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
3248 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3249 clean_addr = clean_data_tbi(s, dirty_addr);
3251 tcg_rt = cpu_reg(s, rt);
3252 do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false,
3253 /* extend */ false, /* iss_valid */ !is_wback,
3254 /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);
3256 if (is_wback) {
3257 tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr);
3262 * LDAPR/STLR (unscaled immediate)
3264 * 31 30 24 22 21 12 10 5 0
3265 * +------+-------------+-----+---+--------+-----+----+-----+
3266 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3267 * +------+-------------+-----+---+--------+-----+----+-----+
3269 * Rt: source or destination register
3270 * Rn: base register
3271 * imm9: unscaled immediate offset
3272 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3273 * size: size of load/store
3275 static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
3277 int rt = extract32(insn, 0, 5);
3278 int rn = extract32(insn, 5, 5);
3279 int offset = sextract32(insn, 12, 9);
3280 int opc = extract32(insn, 22, 2);
3281 int size = extract32(insn, 30, 2);
3282 TCGv_i64 clean_addr, dirty_addr;
3283 bool is_store = false;
3284 bool is_signed = false;
3285 bool extend = false;
3286 bool iss_sf;
3288 if (!dc_isar_feature(aa64_rcpc_8_4, s)) {
3289 unallocated_encoding(s);
3290 return;
3293 switch (opc) {
3294 case 0: /* STLURB */
3295 is_store = true;
3296 break;
3297 case 1: /* LDAPUR* */
3298 break;
3299 case 2: /* LDAPURS* 64-bit variant */
3300 if (size == 3) {
3301 unallocated_encoding(s);
3302 return;
3304 is_signed = true;
3305 break;
3306 case 3: /* LDAPURS* 32-bit variant */
3307 if (size > 1) {
3308 unallocated_encoding(s);
3309 return;
3311 is_signed = true;
3312 extend = true; /* zero-extend 32->64 after signed load */
3313 break;
3314 default:
3315 g_assert_not_reached();
3318 iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
3320 if (rn == 31) {
3321 gen_check_sp_alignment(s);
3324 dirty_addr = read_cpu_reg_sp(s, rn, 1);
3325 tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
3326 clean_addr = clean_data_tbi(s, dirty_addr);
3328 if (is_store) {
3329 /* Store-Release semantics */
3330 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3331 do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true);
3332 } else {
3334 * Load-AcquirePC semantics; we implement as the slightly more
3335 * restrictive Load-Acquire.
3337 do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend,
3338 true, rt, iss_sf, true);
3339 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3343 /* Load/store register (all forms) */
3344 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
3346 int rt = extract32(insn, 0, 5);
3347 int opc = extract32(insn, 22, 2);
3348 bool is_vector = extract32(insn, 26, 1);
3349 int size = extract32(insn, 30, 2);
3351 switch (extract32(insn, 24, 2)) {
3352 case 0:
3353 if (extract32(insn, 21, 1) == 0) {
3354 /* Load/store register (unscaled immediate)
3355 * Load/store immediate pre/post-indexed
3356 * Load/store register unprivileged
3358 disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector);
3359 return;
3361 switch (extract32(insn, 10, 2)) {
3362 case 0:
3363 disas_ldst_atomic(s, insn, size, rt, is_vector);
3364 return;
3365 case 2:
3366 disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector);
3367 return;
3368 default:
3369 disas_ldst_pac(s, insn, size, rt, is_vector);
3370 return;
3372 break;
3373 case 1:
3374 disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector);
3375 return;
3377 unallocated_encoding(s);
3380 /* AdvSIMD load/store multiple structures
3382 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3383 * +---+---+---------------+---+-------------+--------+------+------+------+
3384 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3385 * +---+---+---------------+---+-------------+--------+------+------+------+
3387 * AdvSIMD load/store multiple structures (post-indexed)
3389 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3390 * +---+---+---------------+---+---+---------+--------+------+------+------+
3391 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3392 * +---+---+---------------+---+---+---------+--------+------+------+------+
3394 * Rt: first (or only) SIMD&FP register to be transferred
3395 * Rn: base address or SP
3396 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3398 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
3400 int rt = extract32(insn, 0, 5);
3401 int rn = extract32(insn, 5, 5);
3402 int rm = extract32(insn, 16, 5);
3403 int size = extract32(insn, 10, 2);
3404 int opcode = extract32(insn, 12, 4);
3405 bool is_store = !extract32(insn, 22, 1);
3406 bool is_postidx = extract32(insn, 23, 1);
3407 bool is_q = extract32(insn, 30, 1);
3408 TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
3409 MemOp endian = s->be_data;
3411 int ebytes; /* bytes per element */
3412 int elements; /* elements per vector */
3413 int rpt; /* num iterations */
3414 int selem; /* structure elements */
3415 int r;
3417 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) {
3418 unallocated_encoding(s);
3419 return;
3422 if (!is_postidx && rm != 0) {
3423 unallocated_encoding(s);
3424 return;
3427 /* From the shared decode logic */
3428 switch (opcode) {
3429 case 0x0:
3430 rpt = 1;
3431 selem = 4;
3432 break;
3433 case 0x2:
3434 rpt = 4;
3435 selem = 1;
3436 break;
3437 case 0x4:
3438 rpt = 1;
3439 selem = 3;
3440 break;
3441 case 0x6:
3442 rpt = 3;
3443 selem = 1;
3444 break;
3445 case 0x7:
3446 rpt = 1;
3447 selem = 1;
3448 break;
3449 case 0x8:
3450 rpt = 1;
3451 selem = 2;
3452 break;
3453 case 0xa:
3454 rpt = 2;
3455 selem = 1;
3456 break;
3457 default:
3458 unallocated_encoding(s);
3459 return;
3462 if (size == 3 && !is_q && selem != 1) {
3463 /* reserved */
3464 unallocated_encoding(s);
3465 return;
3468 if (!fp_access_check(s)) {
3469 return;
3472 if (rn == 31) {
3473 gen_check_sp_alignment(s);
3476 /* For our purposes, bytes are always little-endian. */
3477 if (size == 0) {
3478 endian = MO_LE;
3481 /* Consecutive little-endian elements from a single register
3482 * can be promoted to a larger little-endian operation.
3484 if (selem == 1 && endian == MO_LE) {
3485 size = 3;
3487 ebytes = 1 << size;
3488 elements = (is_q ? 16 : 8) / ebytes;
3490 tcg_rn = cpu_reg_sp(s, rn);
3491 clean_addr = clean_data_tbi(s, tcg_rn);
3492 tcg_ebytes = tcg_const_i64(ebytes);
3494 for (r = 0; r < rpt; r++) {
3495 int e;
3496 for (e = 0; e < elements; e++) {
3497 int xs;
3498 for (xs = 0; xs < selem; xs++) {
3499 int tt = (rt + r + xs) % 32;
3500 if (is_store) {
3501 do_vec_st(s, tt, e, clean_addr, size, endian);
3502 } else {
3503 do_vec_ld(s, tt, e, clean_addr, size, endian);
3505 tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
3509 tcg_temp_free_i64(tcg_ebytes);
3511 if (!is_store) {
3512 /* For non-quad operations, setting a slice of the low
3513 * 64 bits of the register clears the high 64 bits (in
3514 * the ARM ARM pseudocode this is implicit in the fact
3515 * that 'rval' is a 64 bit wide variable).
3516 * For quad operations, we might still need to zero the
3517 * high bits of SVE.
3519 for (r = 0; r < rpt * selem; r++) {
3520 int tt = (rt + r) % 32;
3521 clear_vec_high(s, is_q, tt);
3525 if (is_postidx) {
3526 if (rm == 31) {
3527 tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebytes);
3528 } else {
3529 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
3534 /* AdvSIMD load/store single structure
3536 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3537 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3538 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3539 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3541 * AdvSIMD load/store single structure (post-indexed)
3543 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3544 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3545 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3546 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3548 * Rt: first (or only) SIMD&FP register to be transferred
3549 * Rn: base address or SP
3550 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3551 * index = encoded in Q:S:size dependent on size
3553 * lane_size = encoded in R, opc
3554 * transfer width = encoded in opc, S, size
3556 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
3558 int rt = extract32(insn, 0, 5);
3559 int rn = extract32(insn, 5, 5);
3560 int rm = extract32(insn, 16, 5);
3561 int size = extract32(insn, 10, 2);
3562 int S = extract32(insn, 12, 1);
3563 int opc = extract32(insn, 13, 3);
3564 int R = extract32(insn, 21, 1);
3565 int is_load = extract32(insn, 22, 1);
3566 int is_postidx = extract32(insn, 23, 1);
3567 int is_q = extract32(insn, 30, 1);
3569 int scale = extract32(opc, 1, 2);
3570 int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
3571 bool replicate = false;
3572 int index = is_q << 3 | S << 2 | size;
3573 int ebytes, xs;
3574 TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
3576 if (extract32(insn, 31, 1)) {
3577 unallocated_encoding(s);
3578 return;
3580 if (!is_postidx && rm != 0) {
3581 unallocated_encoding(s);
3582 return;
3585 switch (scale) {
3586 case 3:
3587 if (!is_load || S) {
3588 unallocated_encoding(s);
3589 return;
3591 scale = size;
3592 replicate = true;
3593 break;
3594 case 0:
3595 break;
3596 case 1:
3597 if (extract32(size, 0, 1)) {
3598 unallocated_encoding(s);
3599 return;
3601 index >>= 1;
3602 break;
3603 case 2:
3604 if (extract32(size, 1, 1)) {
3605 unallocated_encoding(s);
3606 return;
3608 if (!extract32(size, 0, 1)) {
3609 index >>= 2;
3610 } else {
3611 if (S) {
3612 unallocated_encoding(s);
3613 return;
3615 index >>= 3;
3616 scale = 3;
3618 break;
3619 default:
3620 g_assert_not_reached();
3623 if (!fp_access_check(s)) {
3624 return;
3627 ebytes = 1 << scale;
3629 if (rn == 31) {
3630 gen_check_sp_alignment(s);
3633 tcg_rn = cpu_reg_sp(s, rn);
3634 clean_addr = clean_data_tbi(s, tcg_rn);
3635 tcg_ebytes = tcg_const_i64(ebytes);
3637 for (xs = 0; xs < selem; xs++) {
3638 if (replicate) {
3639 /* Load and replicate to all elements */
3640 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
3642 tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr,
3643 get_mem_index(s), s->be_data + scale);
3644 tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
3645 (is_q + 1) * 8, vec_full_reg_size(s),
3646 tcg_tmp);
3647 tcg_temp_free_i64(tcg_tmp);
3648 } else {
3649 /* Load/store one element per register */
3650 if (is_load) {
3651 do_vec_ld(s, rt, index, clean_addr, scale, s->be_data);
3652 } else {
3653 do_vec_st(s, rt, index, clean_addr, scale, s->be_data);
3656 tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
3657 rt = (rt + 1) % 32;
3659 tcg_temp_free_i64(tcg_ebytes);
3661 if (is_postidx) {
3662 if (rm == 31) {
3663 tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes);
3664 } else {
3665 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
3670 /* Loads and stores */
3671 static void disas_ldst(DisasContext *s, uint32_t insn)
3673 switch (extract32(insn, 24, 6)) {
3674 case 0x08: /* Load/store exclusive */
3675 disas_ldst_excl(s, insn);
3676 break;
3677 case 0x18: case 0x1c: /* Load register (literal) */
3678 disas_ld_lit(s, insn);
3679 break;
3680 case 0x28: case 0x29:
3681 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3682 disas_ldst_pair(s, insn);
3683 break;
3684 case 0x38: case 0x39:
3685 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3686 disas_ldst_reg(s, insn);
3687 break;
3688 case 0x0c: /* AdvSIMD load/store multiple structures */
3689 disas_ldst_multiple_struct(s, insn);
3690 break;
3691 case 0x0d: /* AdvSIMD load/store single structure */
3692 disas_ldst_single_struct(s, insn);
3693 break;
3694 case 0x19: /* LDAPR/STLR (unscaled immediate) */
3695 if (extract32(insn, 10, 2) != 0 ||
3696 extract32(insn, 21, 1) != 0) {
3697 unallocated_encoding(s);
3698 break;
3700 disas_ldst_ldapr_stlr(s, insn);
3701 break;
3702 default:
3703 unallocated_encoding(s);
3704 break;
3708 /* PC-rel. addressing
3709 * 31 30 29 28 24 23 5 4 0
3710 * +----+-------+-----------+-------------------+------+
3711 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3712 * +----+-------+-----------+-------------------+------+
3714 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
3716 unsigned int page, rd;
3717 uint64_t base;
3718 uint64_t offset;
3720 page = extract32(insn, 31, 1);
3721 /* SignExtend(immhi:immlo) -> offset */
3722 offset = sextract64(insn, 5, 19);
3723 offset = offset << 2 | extract32(insn, 29, 2);
3724 rd = extract32(insn, 0, 5);
3725 base = s->pc_curr;
3727 if (page) {
3728 /* ADRP (page based) */
3729 base &= ~0xfff;
3730 offset <<= 12;
3733 tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
3737 * Add/subtract (immediate)
3739 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3740 * +--+--+--+-----------+-----+-------------+-----+-----+
3741 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3742 * +--+--+--+-----------+-----+-------------+-----+-----+
3744 * sf: 0 -> 32bit, 1 -> 64bit
3745 * op: 0 -> add , 1 -> sub
3746 * S: 1 -> set flags
3747 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3749 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
3751 int rd = extract32(insn, 0, 5);
3752 int rn = extract32(insn, 5, 5);
3753 uint64_t imm = extract32(insn, 10, 12);
3754 int shift = extract32(insn, 22, 2);
3755 bool setflags = extract32(insn, 29, 1);
3756 bool sub_op = extract32(insn, 30, 1);
3757 bool is_64bit = extract32(insn, 31, 1);
3759 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
3760 TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
3761 TCGv_i64 tcg_result;
3763 switch (shift) {
3764 case 0x0:
3765 break;
3766 case 0x1:
3767 imm <<= 12;
3768 break;
3769 default:
3770 unallocated_encoding(s);
3771 return;
3774 tcg_result = tcg_temp_new_i64();
3775 if (!setflags) {
3776 if (sub_op) {
3777 tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
3778 } else {
3779 tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
3781 } else {
3782 TCGv_i64 tcg_imm = tcg_const_i64(imm);
3783 if (sub_op) {
3784 gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
3785 } else {
3786 gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
3788 tcg_temp_free_i64(tcg_imm);
3791 if (is_64bit) {
3792 tcg_gen_mov_i64(tcg_rd, tcg_result);
3793 } else {
3794 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3797 tcg_temp_free_i64(tcg_result);
3800 /* The input should be a value in the bottom e bits (with higher
3801 * bits zero); returns that value replicated into every element
3802 * of size e in a 64 bit integer.
3804 static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
3806 assert(e != 0);
3807 while (e < 64) {
3808 mask |= mask << e;
3809 e *= 2;
3811 return mask;
3814 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3815 static inline uint64_t bitmask64(unsigned int length)
3817 assert(length > 0 && length <= 64);
3818 return ~0ULL >> (64 - length);
3821 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3822 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3823 * value (ie should cause a guest UNDEF exception), and true if they are
3824 * valid, in which case the decoded bit pattern is written to result.
3826 bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
3827 unsigned int imms, unsigned int immr)
3829 uint64_t mask;
3830 unsigned e, levels, s, r;
3831 int len;
3833 assert(immn < 2 && imms < 64 && immr < 64);
3835 /* The bit patterns we create here are 64 bit patterns which
3836 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3837 * 64 bits each. Each element contains the same value: a run
3838 * of between 1 and e-1 non-zero bits, rotated within the
3839 * element by between 0 and e-1 bits.
3841 * The element size and run length are encoded into immn (1 bit)
3842 * and imms (6 bits) as follows:
3843 * 64 bit elements: immn = 1, imms = <length of run - 1>
3844 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3845 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3846 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3847 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3848 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3849 * Notice that immn = 0, imms = 11111x is the only combination
3850 * not covered by one of the above options; this is reserved.
3851 * Further, <length of run - 1> all-ones is a reserved pattern.
3853 * In all cases the rotation is by immr % e (and immr is 6 bits).
3856 /* First determine the element size */
3857 len = 31 - clz32((immn << 6) | (~imms & 0x3f));
3858 if (len < 1) {
3859 /* This is the immn == 0, imms == 0x11111x case */
3860 return false;
3862 e = 1 << len;
3864 levels = e - 1;
3865 s = imms & levels;
3866 r = immr & levels;
3868 if (s == levels) {
3869 /* <length of run - 1> mustn't be all-ones. */
3870 return false;
3873 /* Create the value of one element: s+1 set bits rotated
3874 * by r within the element (which is e bits wide)...
3876 mask = bitmask64(s + 1);
3877 if (r) {
3878 mask = (mask >> r) | (mask << (e - r));
3879 mask &= bitmask64(e);
3881 /* ...then replicate the element over the whole 64 bit value */
3882 mask = bitfield_replicate(mask, e);
3883 *result = mask;
3884 return true;
3887 /* Logical (immediate)
3888 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3889 * +----+-----+-------------+---+------+------+------+------+
3890 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3891 * +----+-----+-------------+---+------+------+------+------+
3893 static void disas_logic_imm(DisasContext *s, uint32_t insn)
3895 unsigned int sf, opc, is_n, immr, imms, rn, rd;
3896 TCGv_i64 tcg_rd, tcg_rn;
3897 uint64_t wmask;
3898 bool is_and = false;
3900 sf = extract32(insn, 31, 1);
3901 opc = extract32(insn, 29, 2);
3902 is_n = extract32(insn, 22, 1);
3903 immr = extract32(insn, 16, 6);
3904 imms = extract32(insn, 10, 6);
3905 rn = extract32(insn, 5, 5);
3906 rd = extract32(insn, 0, 5);
3908 if (!sf && is_n) {
3909 unallocated_encoding(s);
3910 return;
3913 if (opc == 0x3) { /* ANDS */
3914 tcg_rd = cpu_reg(s, rd);
3915 } else {
3916 tcg_rd = cpu_reg_sp(s, rd);
3918 tcg_rn = cpu_reg(s, rn);
3920 if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
3921 /* some immediate field values are reserved */
3922 unallocated_encoding(s);
3923 return;
3926 if (!sf) {
3927 wmask &= 0xffffffff;
3930 switch (opc) {
3931 case 0x3: /* ANDS */
3932 case 0x0: /* AND */
3933 tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
3934 is_and = true;
3935 break;
3936 case 0x1: /* ORR */
3937 tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
3938 break;
3939 case 0x2: /* EOR */
3940 tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
3941 break;
3942 default:
3943 assert(FALSE); /* must handle all above */
3944 break;
3947 if (!sf && !is_and) {
3948 /* zero extend final result; we know we can skip this for AND
3949 * since the immediate had the high 32 bits clear.
3951 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3954 if (opc == 3) { /* ANDS */
3955 gen_logic_CC(sf, tcg_rd);
3960 * Move wide (immediate)
3962 * 31 30 29 28 23 22 21 20 5 4 0
3963 * +--+-----+-------------+-----+----------------+------+
3964 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3965 * +--+-----+-------------+-----+----------------+------+
3967 * sf: 0 -> 32 bit, 1 -> 64 bit
3968 * opc: 00 -> N, 10 -> Z, 11 -> K
3969 * hw: shift/16 (0,16, and sf only 32, 48)
3971 static void disas_movw_imm(DisasContext *s, uint32_t insn)
3973 int rd = extract32(insn, 0, 5);
3974 uint64_t imm = extract32(insn, 5, 16);
3975 int sf = extract32(insn, 31, 1);
3976 int opc = extract32(insn, 29, 2);
3977 int pos = extract32(insn, 21, 2) << 4;
3978 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3979 TCGv_i64 tcg_imm;
3981 if (!sf && (pos >= 32)) {
3982 unallocated_encoding(s);
3983 return;
3986 switch (opc) {
3987 case 0: /* MOVN */
3988 case 2: /* MOVZ */
3989 imm <<= pos;
3990 if (opc == 0) {
3991 imm = ~imm;
3993 if (!sf) {
3994 imm &= 0xffffffffu;
3996 tcg_gen_movi_i64(tcg_rd, imm);
3997 break;
3998 case 3: /* MOVK */
3999 tcg_imm = tcg_const_i64(imm);
4000 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
4001 tcg_temp_free_i64(tcg_imm);
4002 if (!sf) {
4003 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
4005 break;
4006 default:
4007 unallocated_encoding(s);
4008 break;
4012 /* Bitfield
4013 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4014 * +----+-----+-------------+---+------+------+------+------+
4015 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4016 * +----+-----+-------------+---+------+------+------+------+
4018 static void disas_bitfield(DisasContext *s, uint32_t insn)
4020 unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
4021 TCGv_i64 tcg_rd, tcg_tmp;
4023 sf = extract32(insn, 31, 1);
4024 opc = extract32(insn, 29, 2);
4025 n = extract32(insn, 22, 1);
4026 ri = extract32(insn, 16, 6);
4027 si = extract32(insn, 10, 6);
4028 rn = extract32(insn, 5, 5);
4029 rd = extract32(insn, 0, 5);
4030 bitsize = sf ? 64 : 32;
4032 if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
4033 unallocated_encoding(s);
4034 return;
4037 tcg_rd = cpu_reg(s, rd);
4039 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4040 to be smaller than bitsize, we'll never reference data outside the
4041 low 32-bits anyway. */
4042 tcg_tmp = read_cpu_reg(s, rn, 1);
4044 /* Recognize simple(r) extractions. */
4045 if (si >= ri) {
4046 /* Wd<s-r:0> = Wn<s:r> */
4047 len = (si - ri) + 1;
4048 if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4049 tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len);
4050 goto done;
4051 } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4052 tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
4053 return;
4055 /* opc == 1, BFXIL fall through to deposit */
4056 tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
4057 pos = 0;
4058 } else {
4059 /* Handle the ri > si case with a deposit
4060 * Wd<32+s-r,32-r> = Wn<s:0>
4062 len = si + 1;
4063 pos = (bitsize - ri) & (bitsize - 1);
4066 if (opc == 0 && len < ri) {
4067 /* SBFM: sign extend the destination field from len to fill
4068 the balance of the word. Let the deposit below insert all
4069 of those sign bits. */
4070 tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len);
4071 len = ri;
4074 if (opc == 1) { /* BFM, BFXIL */
4075 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
4076 } else {
4077 /* SBFM or UBFM: We start with zero, and we haven't modified
4078 any bits outside bitsize, therefore the zero-extension
4079 below is unneeded. */
4080 tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len);
4081 return;
4084 done:
4085 if (!sf) { /* zero extend final result */
4086 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
4090 /* Extract
4091 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4092 * +----+------+-------------+---+----+------+--------+------+------+
4093 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4094 * +----+------+-------------+---+----+------+--------+------+------+
4096 static void disas_extract(DisasContext *s, uint32_t insn)
4098 unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
4100 sf = extract32(insn, 31, 1);
4101 n = extract32(insn, 22, 1);
4102 rm = extract32(insn, 16, 5);
4103 imm = extract32(insn, 10, 6);
4104 rn = extract32(insn, 5, 5);
4105 rd = extract32(insn, 0, 5);
4106 op21 = extract32(insn, 29, 2);
4107 op0 = extract32(insn, 21, 1);
4108 bitsize = sf ? 64 : 32;
4110 if (sf != n || op21 || op0 || imm >= bitsize) {
4111 unallocated_encoding(s);
4112 } else {
4113 TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
4115 tcg_rd = cpu_reg(s, rd);
4117 if (unlikely(imm == 0)) {
4118 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4119 * so an extract from bit 0 is a special case.
4121 if (sf) {
4122 tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
4123 } else {
4124 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
4126 } else {
4127 tcg_rm = cpu_reg(s, rm);
4128 tcg_rn = cpu_reg(s, rn);
4130 if (sf) {
4131 /* Specialization to ROR happens in EXTRACT2. */
4132 tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
4133 } else {
4134 TCGv_i32 t0 = tcg_temp_new_i32();
4136 tcg_gen_extrl_i64_i32(t0, tcg_rm);
4137 if (rm == rn) {
4138 tcg_gen_rotri_i32(t0, t0, imm);
4139 } else {
4140 TCGv_i32 t1 = tcg_temp_new_i32();
4141 tcg_gen_extrl_i64_i32(t1, tcg_rn);
4142 tcg_gen_extract2_i32(t0, t0, t1, imm);
4143 tcg_temp_free_i32(t1);
4145 tcg_gen_extu_i32_i64(tcg_rd, t0);
4146 tcg_temp_free_i32(t0);
4152 /* Data processing - immediate */
4153 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
4155 switch (extract32(insn, 23, 6)) {
4156 case 0x20: case 0x21: /* PC-rel. addressing */
4157 disas_pc_rel_adr(s, insn);
4158 break;
4159 case 0x22: case 0x23: /* Add/subtract (immediate) */
4160 disas_add_sub_imm(s, insn);
4161 break;
4162 case 0x24: /* Logical (immediate) */
4163 disas_logic_imm(s, insn);
4164 break;
4165 case 0x25: /* Move wide (immediate) */
4166 disas_movw_imm(s, insn);
4167 break;
4168 case 0x26: /* Bitfield */
4169 disas_bitfield(s, insn);
4170 break;
4171 case 0x27: /* Extract */
4172 disas_extract(s, insn);
4173 break;
4174 default:
4175 unallocated_encoding(s);
4176 break;
4180 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4181 * Note that it is the caller's responsibility to ensure that the
4182 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4183 * mandated semantics for out of range shifts.
4185 static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,
4186 enum a64_shift_type shift_type, TCGv_i64 shift_amount)
4188 switch (shift_type) {
4189 case A64_SHIFT_TYPE_LSL:
4190 tcg_gen_shl_i64(dst, src, shift_amount);
4191 break;
4192 case A64_SHIFT_TYPE_LSR:
4193 tcg_gen_shr_i64(dst, src, shift_amount);
4194 break;
4195 case A64_SHIFT_TYPE_ASR:
4196 if (!sf) {
4197 tcg_gen_ext32s_i64(dst, src);
4199 tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);
4200 break;
4201 case A64_SHIFT_TYPE_ROR:
4202 if (sf) {
4203 tcg_gen_rotr_i64(dst, src, shift_amount);
4204 } else {
4205 TCGv_i32 t0, t1;
4206 t0 = tcg_temp_new_i32();
4207 t1 = tcg_temp_new_i32();
4208 tcg_gen_extrl_i64_i32(t0, src);
4209 tcg_gen_extrl_i64_i32(t1, shift_amount);
4210 tcg_gen_rotr_i32(t0, t0, t1);
4211 tcg_gen_extu_i32_i64(dst, t0);
4212 tcg_temp_free_i32(t0);
4213 tcg_temp_free_i32(t1);
4215 break;
4216 default:
4217 assert(FALSE); /* all shift types should be handled */
4218 break;
4221 if (!sf) { /* zero extend final result */
4222 tcg_gen_ext32u_i64(dst, dst);
4226 /* Shift a TCGv src by immediate, put result in dst.
4227 * The shift amount must be in range (this should always be true as the
4228 * relevant instructions will UNDEF on bad shift immediates).
4230 static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
4231 enum a64_shift_type shift_type, unsigned int shift_i)
4233 assert(shift_i < (sf ? 64 : 32));
4235 if (shift_i == 0) {
4236 tcg_gen_mov_i64(dst, src);
4237 } else {
4238 TCGv_i64 shift_const;
4240 shift_const = tcg_const_i64(shift_i);
4241 shift_reg(dst, src, sf, shift_type, shift_const);
4242 tcg_temp_free_i64(shift_const);
4246 /* Logical (shifted register)
4247 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4248 * +----+-----+-----------+-------+---+------+--------+------+------+
4249 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4250 * +----+-----+-----------+-------+---+------+--------+------+------+
4252 static void disas_logic_reg(DisasContext *s, uint32_t insn)
4254 TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
4255 unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
4257 sf = extract32(insn, 31, 1);
4258 opc = extract32(insn, 29, 2);
4259 shift_type = extract32(insn, 22, 2);
4260 invert = extract32(insn, 21, 1);
4261 rm = extract32(insn, 16, 5);
4262 shift_amount = extract32(insn, 10, 6);
4263 rn = extract32(insn, 5, 5);
4264 rd = extract32(insn, 0, 5);
4266 if (!sf && (shift_amount & (1 << 5))) {
4267 unallocated_encoding(s);
4268 return;
4271 tcg_rd = cpu_reg(s, rd);
4273 if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
4274 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4275 * register-register MOV and MVN, so it is worth special casing.
4277 tcg_rm = cpu_reg(s, rm);
4278 if (invert) {
4279 tcg_gen_not_i64(tcg_rd, tcg_rm);
4280 if (!sf) {
4281 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
4283 } else {
4284 if (sf) {
4285 tcg_gen_mov_i64(tcg_rd, tcg_rm);
4286 } else {
4287 tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
4290 return;
4293 tcg_rm = read_cpu_reg(s, rm, sf);
4295 if (shift_amount) {
4296 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
4299 tcg_rn = cpu_reg(s, rn);
4301 switch (opc | (invert << 2)) {
4302 case 0: /* AND */
4303 case 3: /* ANDS */
4304 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
4305 break;
4306 case 1: /* ORR */
4307 tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
4308 break;
4309 case 2: /* EOR */
4310 tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
4311 break;
4312 case 4: /* BIC */
4313 case 7: /* BICS */
4314 tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
4315 break;
4316 case 5: /* ORN */
4317 tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
4318 break;
4319 case 6: /* EON */
4320 tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
4321 break;
4322 default:
4323 assert(FALSE);
4324 break;
4327 if (!sf) {
4328 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
4331 if (opc == 3) {
4332 gen_logic_CC(sf, tcg_rd);
4337 * Add/subtract (extended register)
4339 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4340 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4341 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4342 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4344 * sf: 0 -> 32bit, 1 -> 64bit
4345 * op: 0 -> add , 1 -> sub
4346 * S: 1 -> set flags
4347 * opt: 00
4348 * option: extension type (see DecodeRegExtend)
4349 * imm3: optional shift to Rm
4351 * Rd = Rn + LSL(extend(Rm), amount)
4353 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
4355 int rd = extract32(insn, 0, 5);
4356 int rn = extract32(insn, 5, 5);
4357 int imm3 = extract32(insn, 10, 3);
4358 int option = extract32(insn, 13, 3);
4359 int rm = extract32(insn, 16, 5);
4360 int opt = extract32(insn, 22, 2);
4361 bool setflags = extract32(insn, 29, 1);
4362 bool sub_op = extract32(insn, 30, 1);
4363 bool sf = extract32(insn, 31, 1);
4365 TCGv_i64 tcg_rm, tcg_rn; /* temps */
4366 TCGv_i64 tcg_rd;
4367 TCGv_i64 tcg_result;
4369 if (imm3 > 4 || opt != 0) {
4370 unallocated_encoding(s);
4371 return;
4374 /* non-flag setting ops may use SP */
4375 if (!setflags) {
4376 tcg_rd = cpu_reg_sp(s, rd);
4377 } else {
4378 tcg_rd = cpu_reg(s, rd);
4380 tcg_rn = read_cpu_reg_sp(s, rn, sf);
4382 tcg_rm = read_cpu_reg(s, rm, sf);
4383 ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
4385 tcg_result = tcg_temp_new_i64();
4387 if (!setflags) {
4388 if (sub_op) {
4389 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
4390 } else {
4391 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
4393 } else {
4394 if (sub_op) {
4395 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
4396 } else {
4397 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
4401 if (sf) {
4402 tcg_gen_mov_i64(tcg_rd, tcg_result);
4403 } else {
4404 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
4407 tcg_temp_free_i64(tcg_result);
4411 * Add/subtract (shifted register)
4413 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4414 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4415 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4416 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4418 * sf: 0 -> 32bit, 1 -> 64bit
4419 * op: 0 -> add , 1 -> sub
4420 * S: 1 -> set flags
4421 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4422 * imm6: Shift amount to apply to Rm before the add/sub
4424 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
4426 int rd = extract32(insn, 0, 5);
4427 int rn = extract32(insn, 5, 5);
4428 int imm6 = extract32(insn, 10, 6);
4429 int rm = extract32(insn, 16, 5);
4430 int shift_type = extract32(insn, 22, 2);
4431 bool setflags = extract32(insn, 29, 1);
4432 bool sub_op = extract32(insn, 30, 1);
4433 bool sf = extract32(insn, 31, 1);
4435 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4436 TCGv_i64 tcg_rn, tcg_rm;
4437 TCGv_i64 tcg_result;
4439 if ((shift_type == 3) || (!sf && (imm6 > 31))) {
4440 unallocated_encoding(s);
4441 return;
4444 tcg_rn = read_cpu_reg(s, rn, sf);
4445 tcg_rm = read_cpu_reg(s, rm, sf);
4447 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
4449 tcg_result = tcg_temp_new_i64();
4451 if (!setflags) {
4452 if (sub_op) {
4453 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
4454 } else {
4455 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
4457 } else {
4458 if (sub_op) {
4459 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
4460 } else {
4461 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
4465 if (sf) {
4466 tcg_gen_mov_i64(tcg_rd, tcg_result);
4467 } else {
4468 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
4471 tcg_temp_free_i64(tcg_result);
4474 /* Data-processing (3 source)
4476 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4477 * +--+------+-----------+------+------+----+------+------+------+
4478 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4479 * +--+------+-----------+------+------+----+------+------+------+
4481 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
4483 int rd = extract32(insn, 0, 5);
4484 int rn = extract32(insn, 5, 5);
4485 int ra = extract32(insn, 10, 5);
4486 int rm = extract32(insn, 16, 5);
4487 int op_id = (extract32(insn, 29, 3) << 4) |
4488 (extract32(insn, 21, 3) << 1) |
4489 extract32(insn, 15, 1);
4490 bool sf = extract32(insn, 31, 1);
4491 bool is_sub = extract32(op_id, 0, 1);
4492 bool is_high = extract32(op_id, 2, 1);
4493 bool is_signed = false;
4494 TCGv_i64 tcg_op1;
4495 TCGv_i64 tcg_op2;
4496 TCGv_i64 tcg_tmp;
4498 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4499 switch (op_id) {
4500 case 0x42: /* SMADDL */
4501 case 0x43: /* SMSUBL */
4502 case 0x44: /* SMULH */
4503 is_signed = true;
4504 break;
4505 case 0x0: /* MADD (32bit) */
4506 case 0x1: /* MSUB (32bit) */
4507 case 0x40: /* MADD (64bit) */
4508 case 0x41: /* MSUB (64bit) */
4509 case 0x4a: /* UMADDL */
4510 case 0x4b: /* UMSUBL */
4511 case 0x4c: /* UMULH */
4512 break;
4513 default:
4514 unallocated_encoding(s);
4515 return;
4518 if (is_high) {
4519 TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
4520 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4521 TCGv_i64 tcg_rn = cpu_reg(s, rn);
4522 TCGv_i64 tcg_rm = cpu_reg(s, rm);
4524 if (is_signed) {
4525 tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
4526 } else {
4527 tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
4530 tcg_temp_free_i64(low_bits);
4531 return;
4534 tcg_op1 = tcg_temp_new_i64();
4535 tcg_op2 = tcg_temp_new_i64();
4536 tcg_tmp = tcg_temp_new_i64();
4538 if (op_id < 0x42) {
4539 tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn));
4540 tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm));
4541 } else {
4542 if (is_signed) {
4543 tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn));
4544 tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm));
4545 } else {
4546 tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn));
4547 tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm));
4551 if (ra == 31 && !is_sub) {
4552 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4553 tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2);
4554 } else {
4555 tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
4556 if (is_sub) {
4557 tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
4558 } else {
4559 tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
4563 if (!sf) {
4564 tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd));
4567 tcg_temp_free_i64(tcg_op1);
4568 tcg_temp_free_i64(tcg_op2);
4569 tcg_temp_free_i64(tcg_tmp);
4572 /* Add/subtract (with carry)
4573 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4574 * +--+--+--+------------------------+------+-------------+------+-----+
4575 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4576 * +--+--+--+------------------------+------+-------------+------+-----+
4579 static void disas_adc_sbc(DisasContext *s, uint32_t insn)
4581 unsigned int sf, op, setflags, rm, rn, rd;
4582 TCGv_i64 tcg_y, tcg_rn, tcg_rd;
4584 sf = extract32(insn, 31, 1);
4585 op = extract32(insn, 30, 1);
4586 setflags = extract32(insn, 29, 1);
4587 rm = extract32(insn, 16, 5);
4588 rn = extract32(insn, 5, 5);
4589 rd = extract32(insn, 0, 5);
4591 tcg_rd = cpu_reg(s, rd);
4592 tcg_rn = cpu_reg(s, rn);
4594 if (op) {
4595 tcg_y = new_tmp_a64(s);
4596 tcg_gen_not_i64(tcg_y, cpu_reg(s, rm));
4597 } else {
4598 tcg_y = cpu_reg(s, rm);
4601 if (setflags) {
4602 gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y);
4603 } else {
4604 gen_adc(sf, tcg_rd, tcg_rn, tcg_y);
4609 * Rotate right into flags
4610 * 31 30 29 21 15 10 5 4 0
4611 * +--+--+--+-----------------+--------+-----------+------+--+------+
4612 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4613 * +--+--+--+-----------------+--------+-----------+------+--+------+
4615 static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn)
4617 int mask = extract32(insn, 0, 4);
4618 int o2 = extract32(insn, 4, 1);
4619 int rn = extract32(insn, 5, 5);
4620 int imm6 = extract32(insn, 15, 6);
4621 int sf_op_s = extract32(insn, 29, 3);
4622 TCGv_i64 tcg_rn;
4623 TCGv_i32 nzcv;
4625 if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) {
4626 unallocated_encoding(s);
4627 return;
4630 tcg_rn = read_cpu_reg(s, rn, 1);
4631 tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6);
4633 nzcv = tcg_temp_new_i32();
4634 tcg_gen_extrl_i64_i32(nzcv, tcg_rn);
4636 if (mask & 8) { /* N */
4637 tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3);
4639 if (mask & 4) { /* Z */
4640 tcg_gen_not_i32(cpu_ZF, nzcv);
4641 tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4);
4643 if (mask & 2) { /* C */
4644 tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1);
4646 if (mask & 1) { /* V */
4647 tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0);
4650 tcg_temp_free_i32(nzcv);
4654 * Evaluate into flags
4655 * 31 30 29 21 15 14 10 5 4 0
4656 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4657 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4658 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4660 static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn)
4662 int o3_mask = extract32(insn, 0, 5);
4663 int rn = extract32(insn, 5, 5);
4664 int o2 = extract32(insn, 15, 6);
4665 int sz = extract32(insn, 14, 1);
4666 int sf_op_s = extract32(insn, 29, 3);
4667 TCGv_i32 tmp;
4668 int shift;
4670 if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd ||
4671 !dc_isar_feature(aa64_condm_4, s)) {
4672 unallocated_encoding(s);
4673 return;
4675 shift = sz ? 16 : 24; /* SETF16 or SETF8 */
4677 tmp = tcg_temp_new_i32();
4678 tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn));
4679 tcg_gen_shli_i32(cpu_NF, tmp, shift);
4680 tcg_gen_shli_i32(cpu_VF, tmp, shift - 1);
4681 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
4682 tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF);
4683 tcg_temp_free_i32(tmp);
4686 /* Conditional compare (immediate / register)
4687 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4688 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4689 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4690 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4691 * [1] y [0] [0]
4693 static void disas_cc(DisasContext *s, uint32_t insn)
4695 unsigned int sf, op, y, cond, rn, nzcv, is_imm;
4696 TCGv_i32 tcg_t0, tcg_t1, tcg_t2;
4697 TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
4698 DisasCompare c;
4700 if (!extract32(insn, 29, 1)) {
4701 unallocated_encoding(s);
4702 return;
4704 if (insn & (1 << 10 | 1 << 4)) {
4705 unallocated_encoding(s);
4706 return;
4708 sf = extract32(insn, 31, 1);
4709 op = extract32(insn, 30, 1);
4710 is_imm = extract32(insn, 11, 1);
4711 y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
4712 cond = extract32(insn, 12, 4);
4713 rn = extract32(insn, 5, 5);
4714 nzcv = extract32(insn, 0, 4);
4716 /* Set T0 = !COND. */
4717 tcg_t0 = tcg_temp_new_i32();
4718 arm_test_cc(&c, cond);
4719 tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0);
4720 arm_free_cc(&c);
4722 /* Load the arguments for the new comparison. */
4723 if (is_imm) {
4724 tcg_y = new_tmp_a64(s);
4725 tcg_gen_movi_i64(tcg_y, y);
4726 } else {
4727 tcg_y = cpu_reg(s, y);
4729 tcg_rn = cpu_reg(s, rn);
4731 /* Set the flags for the new comparison. */
4732 tcg_tmp = tcg_temp_new_i64();
4733 if (op) {
4734 gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
4735 } else {
4736 gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
4738 tcg_temp_free_i64(tcg_tmp);
4740 /* If COND was false, force the flags to #nzcv. Compute two masks
4741 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4742 * For tcg hosts that support ANDC, we can make do with just T1.
4743 * In either case, allow the tcg optimizer to delete any unused mask.
4745 tcg_t1 = tcg_temp_new_i32();
4746 tcg_t2 = tcg_temp_new_i32();
4747 tcg_gen_neg_i32(tcg_t1, tcg_t0);
4748 tcg_gen_subi_i32(tcg_t2, tcg_t0, 1);
4750 if (nzcv & 8) { /* N */
4751 tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1);
4752 } else {
4753 if (TCG_TARGET_HAS_andc_i32) {
4754 tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1);
4755 } else {
4756 tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2);
4759 if (nzcv & 4) { /* Z */
4760 if (TCG_TARGET_HAS_andc_i32) {
4761 tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1);
4762 } else {
4763 tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2);
4765 } else {
4766 tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0);
4768 if (nzcv & 2) { /* C */
4769 tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0);
4770 } else {
4771 if (TCG_TARGET_HAS_andc_i32) {
4772 tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1);
4773 } else {
4774 tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2);
4777 if (nzcv & 1) { /* V */
4778 tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1);
4779 } else {
4780 if (TCG_TARGET_HAS_andc_i32) {
4781 tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1);
4782 } else {
4783 tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2);
4786 tcg_temp_free_i32(tcg_t0);
4787 tcg_temp_free_i32(tcg_t1);
4788 tcg_temp_free_i32(tcg_t2);
4791 /* Conditional select
4792 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4793 * +----+----+---+-----------------+------+------+-----+------+------+
4794 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4795 * +----+----+---+-----------------+------+------+-----+------+------+
4797 static void disas_cond_select(DisasContext *s, uint32_t insn)
4799 unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
4800 TCGv_i64 tcg_rd, zero;
4801 DisasCompare64 c;
4803 if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
4804 /* S == 1 or op2<1> == 1 */
4805 unallocated_encoding(s);
4806 return;
4808 sf = extract32(insn, 31, 1);
4809 else_inv = extract32(insn, 30, 1);
4810 rm = extract32(insn, 16, 5);
4811 cond = extract32(insn, 12, 4);
4812 else_inc = extract32(insn, 10, 1);
4813 rn = extract32(insn, 5, 5);
4814 rd = extract32(insn, 0, 5);
4816 tcg_rd = cpu_reg(s, rd);
4818 a64_test_cc(&c, cond);
4819 zero = tcg_const_i64(0);
4821 if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
4822 /* CSET & CSETM. */
4823 tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero);
4824 if (else_inv) {
4825 tcg_gen_neg_i64(tcg_rd, tcg_rd);
4827 } else {
4828 TCGv_i64 t_true = cpu_reg(s, rn);
4829 TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
4830 if (else_inv && else_inc) {
4831 tcg_gen_neg_i64(t_false, t_false);
4832 } else if (else_inv) {
4833 tcg_gen_not_i64(t_false, t_false);
4834 } else if (else_inc) {
4835 tcg_gen_addi_i64(t_false, t_false, 1);
4837 tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
4840 tcg_temp_free_i64(zero);
4841 a64_free_cc(&c);
4843 if (!sf) {
4844 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
4848 static void handle_clz(DisasContext *s, unsigned int sf,
4849 unsigned int rn, unsigned int rd)
4851 TCGv_i64 tcg_rd, tcg_rn;
4852 tcg_rd = cpu_reg(s, rd);
4853 tcg_rn = cpu_reg(s, rn);
4855 if (sf) {
4856 tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
4857 } else {
4858 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
4859 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
4860 tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32);
4861 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
4862 tcg_temp_free_i32(tcg_tmp32);
4866 static void handle_cls(DisasContext *s, unsigned int sf,
4867 unsigned int rn, unsigned int rd)
4869 TCGv_i64 tcg_rd, tcg_rn;
4870 tcg_rd = cpu_reg(s, rd);
4871 tcg_rn = cpu_reg(s, rn);
4873 if (sf) {
4874 tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
4875 } else {
4876 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
4877 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
4878 tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32);
4879 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
4880 tcg_temp_free_i32(tcg_tmp32);
4884 static void handle_rbit(DisasContext *s, unsigned int sf,
4885 unsigned int rn, unsigned int rd)
4887 TCGv_i64 tcg_rd, tcg_rn;
4888 tcg_rd = cpu_reg(s, rd);
4889 tcg_rn = cpu_reg(s, rn);
4891 if (sf) {
4892 gen_helper_rbit64(tcg_rd, tcg_rn);
4893 } else {
4894 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
4895 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
4896 gen_helper_rbit(tcg_tmp32, tcg_tmp32);
4897 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
4898 tcg_temp_free_i32(tcg_tmp32);
4902 /* REV with sf==1, opcode==3 ("REV64") */
4903 static void handle_rev64(DisasContext *s, unsigned int sf,
4904 unsigned int rn, unsigned int rd)
4906 if (!sf) {
4907 unallocated_encoding(s);
4908 return;
4910 tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
4913 /* REV with sf==0, opcode==2
4914 * REV32 (sf==1, opcode==2)
4916 static void handle_rev32(DisasContext *s, unsigned int sf,
4917 unsigned int rn, unsigned int rd)
4919 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4921 if (sf) {
4922 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
4923 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
4925 /* bswap32_i64 requires zero high word */
4926 tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
4927 tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
4928 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
4929 tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
4930 tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
4932 tcg_temp_free_i64(tcg_tmp);
4933 } else {
4934 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
4935 tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
4939 /* REV16 (opcode==1) */
4940 static void handle_rev16(DisasContext *s, unsigned int sf,
4941 unsigned int rn, unsigned int rd)
4943 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4944 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
4945 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
4946 TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
4948 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
4949 tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
4950 tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
4951 tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
4952 tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
4954 tcg_temp_free_i64(mask);
4955 tcg_temp_free_i64(tcg_tmp);
4958 /* Data-processing (1 source)
4959 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4960 * +----+---+---+-----------------+---------+--------+------+------+
4961 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4962 * +----+---+---+-----------------+---------+--------+------+------+
4964 static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
4966 unsigned int sf, opcode, opcode2, rn, rd;
4967 TCGv_i64 tcg_rd;
4969 if (extract32(insn, 29, 1)) {
4970 unallocated_encoding(s);
4971 return;
4974 sf = extract32(insn, 31, 1);
4975 opcode = extract32(insn, 10, 6);
4976 opcode2 = extract32(insn, 16, 5);
4977 rn = extract32(insn, 5, 5);
4978 rd = extract32(insn, 0, 5);
4980 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4982 switch (MAP(sf, opcode2, opcode)) {
4983 case MAP(0, 0x00, 0x00): /* RBIT */
4984 case MAP(1, 0x00, 0x00):
4985 handle_rbit(s, sf, rn, rd);
4986 break;
4987 case MAP(0, 0x00, 0x01): /* REV16 */
4988 case MAP(1, 0x00, 0x01):
4989 handle_rev16(s, sf, rn, rd);
4990 break;
4991 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4992 case MAP(1, 0x00, 0x02):
4993 handle_rev32(s, sf, rn, rd);
4994 break;
4995 case MAP(1, 0x00, 0x03): /* REV64 */
4996 handle_rev64(s, sf, rn, rd);
4997 break;
4998 case MAP(0, 0x00, 0x04): /* CLZ */
4999 case MAP(1, 0x00, 0x04):
5000 handle_clz(s, sf, rn, rd);
5001 break;
5002 case MAP(0, 0x00, 0x05): /* CLS */
5003 case MAP(1, 0x00, 0x05):
5004 handle_cls(s, sf, rn, rd);
5005 break;
5006 case MAP(1, 0x01, 0x00): /* PACIA */
5007 if (s->pauth_active) {
5008 tcg_rd = cpu_reg(s, rd);
5009 gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
5010 } else if (!dc_isar_feature(aa64_pauth, s)) {
5011 goto do_unallocated;
5013 break;
5014 case MAP(1, 0x01, 0x01): /* PACIB */
5015 if (s->pauth_active) {
5016 tcg_rd = cpu_reg(s, rd);
5017 gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
5018 } else if (!dc_isar_feature(aa64_pauth, s)) {
5019 goto do_unallocated;
5021 break;
5022 case MAP(1, 0x01, 0x02): /* PACDA */
5023 if (s->pauth_active) {
5024 tcg_rd = cpu_reg(s, rd);
5025 gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
5026 } else if (!dc_isar_feature(aa64_pauth, s)) {
5027 goto do_unallocated;
5029 break;
5030 case MAP(1, 0x01, 0x03): /* PACDB */
5031 if (s->pauth_active) {
5032 tcg_rd = cpu_reg(s, rd);
5033 gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
5034 } else if (!dc_isar_feature(aa64_pauth, s)) {
5035 goto do_unallocated;
5037 break;
5038 case MAP(1, 0x01, 0x04): /* AUTIA */
5039 if (s->pauth_active) {
5040 tcg_rd = cpu_reg(s, rd);
5041 gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
5042 } else if (!dc_isar_feature(aa64_pauth, s)) {
5043 goto do_unallocated;
5045 break;
5046 case MAP(1, 0x01, 0x05): /* AUTIB */
5047 if (s->pauth_active) {
5048 tcg_rd = cpu_reg(s, rd);
5049 gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
5050 } else if (!dc_isar_feature(aa64_pauth, s)) {
5051 goto do_unallocated;
5053 break;
5054 case MAP(1, 0x01, 0x06): /* AUTDA */
5055 if (s->pauth_active) {
5056 tcg_rd = cpu_reg(s, rd);
5057 gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
5058 } else if (!dc_isar_feature(aa64_pauth, s)) {
5059 goto do_unallocated;
5061 break;
5062 case MAP(1, 0x01, 0x07): /* AUTDB */
5063 if (s->pauth_active) {
5064 tcg_rd = cpu_reg(s, rd);
5065 gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
5066 } else if (!dc_isar_feature(aa64_pauth, s)) {
5067 goto do_unallocated;
5069 break;
5070 case MAP(1, 0x01, 0x08): /* PACIZA */
5071 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5072 goto do_unallocated;
5073 } else if (s->pauth_active) {
5074 tcg_rd = cpu_reg(s, rd);
5075 gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
5077 break;
5078 case MAP(1, 0x01, 0x09): /* PACIZB */
5079 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5080 goto do_unallocated;
5081 } else if (s->pauth_active) {
5082 tcg_rd = cpu_reg(s, rd);
5083 gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
5085 break;
5086 case MAP(1, 0x01, 0x0a): /* PACDZA */
5087 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5088 goto do_unallocated;
5089 } else if (s->pauth_active) {
5090 tcg_rd = cpu_reg(s, rd);
5091 gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
5093 break;
5094 case MAP(1, 0x01, 0x0b): /* PACDZB */
5095 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5096 goto do_unallocated;
5097 } else if (s->pauth_active) {
5098 tcg_rd = cpu_reg(s, rd);
5099 gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
5101 break;
5102 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5103 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5104 goto do_unallocated;
5105 } else if (s->pauth_active) {
5106 tcg_rd = cpu_reg(s, rd);
5107 gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
5109 break;
5110 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5111 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5112 goto do_unallocated;
5113 } else if (s->pauth_active) {
5114 tcg_rd = cpu_reg(s, rd);
5115 gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
5117 break;
5118 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5119 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5120 goto do_unallocated;
5121 } else if (s->pauth_active) {
5122 tcg_rd = cpu_reg(s, rd);
5123 gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
5125 break;
5126 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5127 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5128 goto do_unallocated;
5129 } else if (s->pauth_active) {
5130 tcg_rd = cpu_reg(s, rd);
5131 gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
5133 break;
5134 case MAP(1, 0x01, 0x10): /* XPACI */
5135 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5136 goto do_unallocated;
5137 } else if (s->pauth_active) {
5138 tcg_rd = cpu_reg(s, rd);
5139 gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd);
5141 break;
5142 case MAP(1, 0x01, 0x11): /* XPACD */
5143 if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
5144 goto do_unallocated;
5145 } else if (s->pauth_active) {
5146 tcg_rd = cpu_reg(s, rd);
5147 gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd);
5149 break;
5150 default:
5151 do_unallocated:
5152 unallocated_encoding(s);
5153 break;
5156 #undef MAP
5159 static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
5160 unsigned int rm, unsigned int rn, unsigned int rd)
5162 TCGv_i64 tcg_n, tcg_m, tcg_rd;
5163 tcg_rd = cpu_reg(s, rd);
5165 if (!sf && is_signed) {
5166 tcg_n = new_tmp_a64(s);
5167 tcg_m = new_tmp_a64(s);
5168 tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
5169 tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
5170 } else {
5171 tcg_n = read_cpu_reg(s, rn, sf);
5172 tcg_m = read_cpu_reg(s, rm, sf);
5175 if (is_signed) {
5176 gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
5177 } else {
5178 gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
5181 if (!sf) { /* zero extend final result */
5182 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
5186 /* LSLV, LSRV, ASRV, RORV */
5187 static void handle_shift_reg(DisasContext *s,
5188 enum a64_shift_type shift_type, unsigned int sf,
5189 unsigned int rm, unsigned int rn, unsigned int rd)
5191 TCGv_i64 tcg_shift = tcg_temp_new_i64();
5192 TCGv_i64 tcg_rd = cpu_reg(s, rd);
5193 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
5195 tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31);
5196 shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift);
5197 tcg_temp_free_i64(tcg_shift);
5200 /* CRC32[BHWX], CRC32C[BHWX] */
5201 static void handle_crc32(DisasContext *s,
5202 unsigned int sf, unsigned int sz, bool crc32c,
5203 unsigned int rm, unsigned int rn, unsigned int rd)
5205 TCGv_i64 tcg_acc, tcg_val;
5206 TCGv_i32 tcg_bytes;
5208 if (!dc_isar_feature(aa64_crc32, s)
5209 || (sf == 1 && sz != 3)
5210 || (sf == 0 && sz == 3)) {
5211 unallocated_encoding(s);
5212 return;
5215 if (sz == 3) {
5216 tcg_val = cpu_reg(s, rm);
5217 } else {
5218 uint64_t mask;
5219 switch (sz) {
5220 case 0:
5221 mask = 0xFF;
5222 break;
5223 case 1:
5224 mask = 0xFFFF;
5225 break;
5226 case 2:
5227 mask = 0xFFFFFFFF;
5228 break;
5229 default:
5230 g_assert_not_reached();
5232 tcg_val = new_tmp_a64(s);
5233 tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask);
5236 tcg_acc = cpu_reg(s, rn);
5237 tcg_bytes = tcg_const_i32(1 << sz);
5239 if (crc32c) {
5240 gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
5241 } else {
5242 gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
5245 tcg_temp_free_i32(tcg_bytes);
5248 /* Data-processing (2 source)
5249 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5250 * +----+---+---+-----------------+------+--------+------+------+
5251 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5252 * +----+---+---+-----------------+------+--------+------+------+
5254 static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
5256 unsigned int sf, rm, opcode, rn, rd;
5257 sf = extract32(insn, 31, 1);
5258 rm = extract32(insn, 16, 5);
5259 opcode = extract32(insn, 10, 6);
5260 rn = extract32(insn, 5, 5);
5261 rd = extract32(insn, 0, 5);
5263 if (extract32(insn, 29, 1)) {
5264 unallocated_encoding(s);
5265 return;
5268 switch (opcode) {
5269 case 2: /* UDIV */
5270 handle_div(s, false, sf, rm, rn, rd);
5271 break;
5272 case 3: /* SDIV */
5273 handle_div(s, true, sf, rm, rn, rd);
5274 break;
5275 case 8: /* LSLV */
5276 handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
5277 break;
5278 case 9: /* LSRV */
5279 handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd);
5280 break;
5281 case 10: /* ASRV */
5282 handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd);
5283 break;
5284 case 11: /* RORV */
5285 handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
5286 break;
5287 case 12: /* PACGA */
5288 if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) {
5289 goto do_unallocated;
5291 gen_helper_pacga(cpu_reg(s, rd), cpu_env,
5292 cpu_reg(s, rn), cpu_reg_sp(s, rm));
5293 break;
5294 case 16:
5295 case 17:
5296 case 18:
5297 case 19:
5298 case 20:
5299 case 21:
5300 case 22:
5301 case 23: /* CRC32 */
5303 int sz = extract32(opcode, 0, 2);
5304 bool crc32c = extract32(opcode, 2, 1);
5305 handle_crc32(s, sf, sz, crc32c, rm, rn, rd);
5306 break;
5308 default:
5309 do_unallocated:
5310 unallocated_encoding(s);
5311 break;
5316 * Data processing - register
5317 * 31 30 29 28 25 21 20 16 10 0
5318 * +--+---+--+---+-------+-----+-------+-------+---------+
5319 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5320 * +--+---+--+---+-------+-----+-------+-------+---------+
5322 static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
5324 int op0 = extract32(insn, 30, 1);
5325 int op1 = extract32(insn, 28, 1);
5326 int op2 = extract32(insn, 21, 4);
5327 int op3 = extract32(insn, 10, 6);
5329 if (!op1) {
5330 if (op2 & 8) {
5331 if (op2 & 1) {
5332 /* Add/sub (extended register) */
5333 disas_add_sub_ext_reg(s, insn);
5334 } else {
5335 /* Add/sub (shifted register) */
5336 disas_add_sub_reg(s, insn);
5338 } else {
5339 /* Logical (shifted register) */
5340 disas_logic_reg(s, insn);
5342 return;
5345 switch (op2) {
5346 case 0x0:
5347 switch (op3) {
5348 case 0x00: /* Add/subtract (with carry) */
5349 disas_adc_sbc(s, insn);
5350 break;
5352 case 0x01: /* Rotate right into flags */
5353 case 0x21:
5354 disas_rotate_right_into_flags(s, insn);
5355 break;
5357 case 0x02: /* Evaluate into flags */
5358 case 0x12:
5359 case 0x22:
5360 case 0x32:
5361 disas_evaluate_into_flags(s, insn);
5362 break;
5364 default:
5365 goto do_unallocated;
5367 break;
5369 case 0x2: /* Conditional compare */
5370 disas_cc(s, insn); /* both imm and reg forms */
5371 break;
5373 case 0x4: /* Conditional select */
5374 disas_cond_select(s, insn);
5375 break;
5377 case 0x6: /* Data-processing */
5378 if (op0) { /* (1 source) */
5379 disas_data_proc_1src(s, insn);
5380 } else { /* (2 source) */
5381 disas_data_proc_2src(s, insn);
5383 break;
5384 case 0x8 ... 0xf: /* (3 source) */
5385 disas_data_proc_3src(s, insn);
5386 break;
5388 default:
5389 do_unallocated:
5390 unallocated_encoding(s);
5391 break;
5395 static void handle_fp_compare(DisasContext *s, int size,
5396 unsigned int rn, unsigned int rm,
5397 bool cmp_with_zero, bool signal_all_nans)
5399 TCGv_i64 tcg_flags = tcg_temp_new_i64();
5400 TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
5402 if (size == MO_64) {
5403 TCGv_i64 tcg_vn, tcg_vm;
5405 tcg_vn = read_fp_dreg(s, rn);
5406 if (cmp_with_zero) {
5407 tcg_vm = tcg_const_i64(0);
5408 } else {
5409 tcg_vm = read_fp_dreg(s, rm);
5411 if (signal_all_nans) {
5412 gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
5413 } else {
5414 gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
5416 tcg_temp_free_i64(tcg_vn);
5417 tcg_temp_free_i64(tcg_vm);
5418 } else {
5419 TCGv_i32 tcg_vn = tcg_temp_new_i32();
5420 TCGv_i32 tcg_vm = tcg_temp_new_i32();
5422 read_vec_element_i32(s, tcg_vn, rn, 0, size);
5423 if (cmp_with_zero) {
5424 tcg_gen_movi_i32(tcg_vm, 0);
5425 } else {
5426 read_vec_element_i32(s, tcg_vm, rm, 0, size);
5429 switch (size) {
5430 case MO_32:
5431 if (signal_all_nans) {
5432 gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
5433 } else {
5434 gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
5436 break;
5437 case MO_16:
5438 if (signal_all_nans) {
5439 gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
5440 } else {
5441 gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
5443 break;
5444 default:
5445 g_assert_not_reached();
5448 tcg_temp_free_i32(tcg_vn);
5449 tcg_temp_free_i32(tcg_vm);
5452 tcg_temp_free_ptr(fpst);
5454 gen_set_nzcv(tcg_flags);
5456 tcg_temp_free_i64(tcg_flags);
5459 /* Floating point compare
5460 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5461 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5462 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5463 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5465 static void disas_fp_compare(DisasContext *s, uint32_t insn)
5467 unsigned int mos, type, rm, op, rn, opc, op2r;
5468 int size;
5470 mos = extract32(insn, 29, 3);
5471 type = extract32(insn, 22, 2);
5472 rm = extract32(insn, 16, 5);
5473 op = extract32(insn, 14, 2);
5474 rn = extract32(insn, 5, 5);
5475 opc = extract32(insn, 3, 2);
5476 op2r = extract32(insn, 0, 3);
5478 if (mos || op || op2r) {
5479 unallocated_encoding(s);
5480 return;
5483 switch (type) {
5484 case 0:
5485 size = MO_32;
5486 break;
5487 case 1:
5488 size = MO_64;
5489 break;
5490 case 3:
5491 size = MO_16;
5492 if (dc_isar_feature(aa64_fp16, s)) {
5493 break;
5495 /* fallthru */
5496 default:
5497 unallocated_encoding(s);
5498 return;
5501 if (!fp_access_check(s)) {
5502 return;
5505 handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
5508 /* Floating point conditional compare
5509 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5510 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5511 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5512 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5514 static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
5516 unsigned int mos, type, rm, cond, rn, op, nzcv;
5517 TCGv_i64 tcg_flags;
5518 TCGLabel *label_continue = NULL;
5519 int size;
5521 mos = extract32(insn, 29, 3);
5522 type = extract32(insn, 22, 2);
5523 rm = extract32(insn, 16, 5);
5524 cond = extract32(insn, 12, 4);
5525 rn = extract32(insn, 5, 5);
5526 op = extract32(insn, 4, 1);
5527 nzcv = extract32(insn, 0, 4);
5529 if (mos) {
5530 unallocated_encoding(s);
5531 return;
5534 switch (type) {
5535 case 0:
5536 size = MO_32;
5537 break;
5538 case 1:
5539 size = MO_64;
5540 break;
5541 case 3:
5542 size = MO_16;
5543 if (dc_isar_feature(aa64_fp16, s)) {
5544 break;
5546 /* fallthru */
5547 default:
5548 unallocated_encoding(s);
5549 return;
5552 if (!fp_access_check(s)) {
5553 return;
5556 if (cond < 0x0e) { /* not always */
5557 TCGLabel *label_match = gen_new_label();
5558 label_continue = gen_new_label();
5559 arm_gen_test_cc(cond, label_match);
5560 /* nomatch: */
5561 tcg_flags = tcg_const_i64(nzcv << 28);
5562 gen_set_nzcv(tcg_flags);
5563 tcg_temp_free_i64(tcg_flags);
5564 tcg_gen_br(label_continue);
5565 gen_set_label(label_match);
5568 handle_fp_compare(s, size, rn, rm, false, op);
5570 if (cond < 0x0e) {
5571 gen_set_label(label_continue);
5575 /* Floating point conditional select
5576 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5577 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5578 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5579 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5581 static void disas_fp_csel(DisasContext *s, uint32_t insn)
5583 unsigned int mos, type, rm, cond, rn, rd;
5584 TCGv_i64 t_true, t_false, t_zero;
5585 DisasCompare64 c;
5586 MemOp sz;
5588 mos = extract32(insn, 29, 3);
5589 type = extract32(insn, 22, 2);
5590 rm = extract32(insn, 16, 5);
5591 cond = extract32(insn, 12, 4);
5592 rn = extract32(insn, 5, 5);
5593 rd = extract32(insn, 0, 5);
5595 if (mos) {
5596 unallocated_encoding(s);
5597 return;
5600 switch (type) {
5601 case 0:
5602 sz = MO_32;
5603 break;
5604 case 1:
5605 sz = MO_64;
5606 break;
5607 case 3:
5608 sz = MO_16;
5609 if (dc_isar_feature(aa64_fp16, s)) {
5610 break;
5612 /* fallthru */
5613 default:
5614 unallocated_encoding(s);
5615 return;
5618 if (!fp_access_check(s)) {
5619 return;
5622 /* Zero extend sreg & hreg inputs to 64 bits now. */
5623 t_true = tcg_temp_new_i64();
5624 t_false = tcg_temp_new_i64();
5625 read_vec_element(s, t_true, rn, 0, sz);
5626 read_vec_element(s, t_false, rm, 0, sz);
5628 a64_test_cc(&c, cond);
5629 t_zero = tcg_const_i64(0);
5630 tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false);
5631 tcg_temp_free_i64(t_zero);
5632 tcg_temp_free_i64(t_false);
5633 a64_free_cc(&c);
5635 /* Note that sregs & hregs write back zeros to the high bits,
5636 and we've already done the zero-extension. */
5637 write_fp_dreg(s, rd, t_true);
5638 tcg_temp_free_i64(t_true);
5641 /* Floating-point data-processing (1 source) - half precision */
5642 static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
5644 TCGv_ptr fpst = NULL;
5645 TCGv_i32 tcg_op = read_fp_hreg(s, rn);
5646 TCGv_i32 tcg_res = tcg_temp_new_i32();
5648 switch (opcode) {
5649 case 0x0: /* FMOV */
5650 tcg_gen_mov_i32(tcg_res, tcg_op);
5651 break;
5652 case 0x1: /* FABS */
5653 tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
5654 break;
5655 case 0x2: /* FNEG */
5656 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
5657 break;
5658 case 0x3: /* FSQRT */
5659 fpst = get_fpstatus_ptr(true);
5660 gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
5661 break;
5662 case 0x8: /* FRINTN */
5663 case 0x9: /* FRINTP */
5664 case 0xa: /* FRINTM */
5665 case 0xb: /* FRINTZ */
5666 case 0xc: /* FRINTA */
5668 TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
5669 fpst = get_fpstatus_ptr(true);
5671 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
5672 gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
5674 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
5675 tcg_temp_free_i32(tcg_rmode);
5676 break;
5678 case 0xe: /* FRINTX */
5679 fpst = get_fpstatus_ptr(true);
5680 gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
5681 break;
5682 case 0xf: /* FRINTI */
5683 fpst = get_fpstatus_ptr(true);
5684 gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
5685 break;
5686 default:
5687 abort();
5690 write_fp_sreg(s, rd, tcg_res);
5692 if (fpst) {
5693 tcg_temp_free_ptr(fpst);
5695 tcg_temp_free_i32(tcg_op);
5696 tcg_temp_free_i32(tcg_res);
5699 /* Floating-point data-processing (1 source) - single precision */
5700 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
5702 void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr);
5703 TCGv_i32 tcg_op, tcg_res;
5704 TCGv_ptr fpst;
5705 int rmode = -1;
5707 tcg_op = read_fp_sreg(s, rn);
5708 tcg_res = tcg_temp_new_i32();
5710 switch (opcode) {
5711 case 0x0: /* FMOV */
5712 tcg_gen_mov_i32(tcg_res, tcg_op);
5713 goto done;
5714 case 0x1: /* FABS */
5715 gen_helper_vfp_abss(tcg_res, tcg_op);
5716 goto done;
5717 case 0x2: /* FNEG */
5718 gen_helper_vfp_negs(tcg_res, tcg_op);
5719 goto done;
5720 case 0x3: /* FSQRT */
5721 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
5722 goto done;
5723 case 0x8: /* FRINTN */
5724 case 0x9: /* FRINTP */
5725 case 0xa: /* FRINTM */
5726 case 0xb: /* FRINTZ */
5727 case 0xc: /* FRINTA */
5728 rmode = arm_rmode_to_sf(opcode & 7);
5729 gen_fpst = gen_helper_rints;
5730 break;
5731 case 0xe: /* FRINTX */
5732 gen_fpst = gen_helper_rints_exact;
5733 break;
5734 case 0xf: /* FRINTI */
5735 gen_fpst = gen_helper_rints;
5736 break;
5737 case 0x10: /* FRINT32Z */
5738 rmode = float_round_to_zero;
5739 gen_fpst = gen_helper_frint32_s;
5740 break;
5741 case 0x11: /* FRINT32X */
5742 gen_fpst = gen_helper_frint32_s;
5743 break;
5744 case 0x12: /* FRINT64Z */
5745 rmode = float_round_to_zero;
5746 gen_fpst = gen_helper_frint64_s;
5747 break;
5748 case 0x13: /* FRINT64X */
5749 gen_fpst = gen_helper_frint64_s;
5750 break;
5751 default:
5752 g_assert_not_reached();
5755 fpst = get_fpstatus_ptr(false);
5756 if (rmode >= 0) {
5757 TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
5758 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
5759 gen_fpst(tcg_res, tcg_op, fpst);
5760 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
5761 tcg_temp_free_i32(tcg_rmode);
5762 } else {
5763 gen_fpst(tcg_res, tcg_op, fpst);
5765 tcg_temp_free_ptr(fpst);
5767 done:
5768 write_fp_sreg(s, rd, tcg_res);
5769 tcg_temp_free_i32(tcg_op);
5770 tcg_temp_free_i32(tcg_res);
5773 /* Floating-point data-processing (1 source) - double precision */
5774 static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
5776 void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr);
5777 TCGv_i64 tcg_op, tcg_res;
5778 TCGv_ptr fpst;
5779 int rmode = -1;
5781 switch (opcode) {
5782 case 0x0: /* FMOV */
5783 gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0);
5784 return;
5787 tcg_op = read_fp_dreg(s, rn);
5788 tcg_res = tcg_temp_new_i64();
5790 switch (opcode) {
5791 case 0x1: /* FABS */
5792 gen_helper_vfp_absd(tcg_res, tcg_op);
5793 goto done;
5794 case 0x2: /* FNEG */
5795 gen_helper_vfp_negd(tcg_res, tcg_op);
5796 goto done;
5797 case 0x3: /* FSQRT */
5798 gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
5799 goto done;
5800 case 0x8: /* FRINTN */
5801 case 0x9: /* FRINTP */
5802 case 0xa: /* FRINTM */
5803 case 0xb: /* FRINTZ */
5804 case 0xc: /* FRINTA */
5805 rmode = arm_rmode_to_sf(opcode & 7);
5806 gen_fpst = gen_helper_rintd;
5807 break;
5808 case 0xe: /* FRINTX */
5809 gen_fpst = gen_helper_rintd_exact;
5810 break;
5811 case 0xf: /* FRINTI */
5812 gen_fpst = gen_helper_rintd;
5813 break;
5814 case 0x10: /* FRINT32Z */
5815 rmode = float_round_to_zero;
5816 gen_fpst = gen_helper_frint32_d;
5817 break;
5818 case 0x11: /* FRINT32X */
5819 gen_fpst = gen_helper_frint32_d;
5820 break;
5821 case 0x12: /* FRINT64Z */
5822 rmode = float_round_to_zero;
5823 gen_fpst = gen_helper_frint64_d;
5824 break;
5825 case 0x13: /* FRINT64X */
5826 gen_fpst = gen_helper_frint64_d;
5827 break;
5828 default:
5829 g_assert_not_reached();
5832 fpst = get_fpstatus_ptr(false);
5833 if (rmode >= 0) {
5834 TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
5835 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
5836 gen_fpst(tcg_res, tcg_op, fpst);
5837 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
5838 tcg_temp_free_i32(tcg_rmode);
5839 } else {
5840 gen_fpst(tcg_res, tcg_op, fpst);
5842 tcg_temp_free_ptr(fpst);
5844 done:
5845 write_fp_dreg(s, rd, tcg_res);
5846 tcg_temp_free_i64(tcg_op);
5847 tcg_temp_free_i64(tcg_res);
5850 static void handle_fp_fcvt(DisasContext *s, int opcode,
5851 int rd, int rn, int dtype, int ntype)
5853 switch (ntype) {
5854 case 0x0:
5856 TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
5857 if (dtype == 1) {
5858 /* Single to double */
5859 TCGv_i64 tcg_rd = tcg_temp_new_i64();
5860 gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env);
5861 write_fp_dreg(s, rd, tcg_rd);
5862 tcg_temp_free_i64(tcg_rd);
5863 } else {
5864 /* Single to half */
5865 TCGv_i32 tcg_rd = tcg_temp_new_i32();
5866 TCGv_i32 ahp = get_ahp_flag();
5867 TCGv_ptr fpst = get_fpstatus_ptr(false);
5869 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp);
5870 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5871 write_fp_sreg(s, rd, tcg_rd);
5872 tcg_temp_free_i32(tcg_rd);
5873 tcg_temp_free_i32(ahp);
5874 tcg_temp_free_ptr(fpst);
5876 tcg_temp_free_i32(tcg_rn);
5877 break;
5879 case 0x1:
5881 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
5882 TCGv_i32 tcg_rd = tcg_temp_new_i32();
5883 if (dtype == 0) {
5884 /* Double to single */
5885 gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env);
5886 } else {
5887 TCGv_ptr fpst = get_fpstatus_ptr(false);
5888 TCGv_i32 ahp = get_ahp_flag();
5889 /* Double to half */
5890 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp);
5891 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5892 tcg_temp_free_ptr(fpst);
5893 tcg_temp_free_i32(ahp);
5895 write_fp_sreg(s, rd, tcg_rd);
5896 tcg_temp_free_i32(tcg_rd);
5897 tcg_temp_free_i64(tcg_rn);
5898 break;
5900 case 0x3:
5902 TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
5903 TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
5904 TCGv_i32 tcg_ahp = get_ahp_flag();
5905 tcg_gen_ext16u_i32(tcg_rn, tcg_rn);
5906 if (dtype == 0) {
5907 /* Half to single */
5908 TCGv_i32 tcg_rd = tcg_temp_new_i32();
5909 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
5910 write_fp_sreg(s, rd, tcg_rd);
5911 tcg_temp_free_i32(tcg_rd);
5912 } else {
5913 /* Half to double */
5914 TCGv_i64 tcg_rd = tcg_temp_new_i64();
5915 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
5916 write_fp_dreg(s, rd, tcg_rd);
5917 tcg_temp_free_i64(tcg_rd);
5919 tcg_temp_free_i32(tcg_rn);
5920 tcg_temp_free_ptr(tcg_fpst);
5921 tcg_temp_free_i32(tcg_ahp);
5922 break;
5924 default:
5925 abort();
5929 /* Floating point data-processing (1 source)
5930 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5931 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5932 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5933 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5935 static void disas_fp_1src(DisasContext *s, uint32_t insn)
5937 int mos = extract32(insn, 29, 3);
5938 int type = extract32(insn, 22, 2);
5939 int opcode = extract32(insn, 15, 6);
5940 int rn = extract32(insn, 5, 5);
5941 int rd = extract32(insn, 0, 5);
5943 if (mos) {
5944 unallocated_encoding(s);
5945 return;
5948 switch (opcode) {
5949 case 0x4: case 0x5: case 0x7:
5951 /* FCVT between half, single and double precision */
5952 int dtype = extract32(opcode, 0, 2);
5953 if (type == 2 || dtype == type) {
5954 unallocated_encoding(s);
5955 return;
5957 if (!fp_access_check(s)) {
5958 return;
5961 handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
5962 break;
5965 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5966 if (type > 1 || !dc_isar_feature(aa64_frint, s)) {
5967 unallocated_encoding(s);
5968 return;
5970 /* fall through */
5971 case 0x0 ... 0x3:
5972 case 0x8 ... 0xc:
5973 case 0xe ... 0xf:
5974 /* 32-to-32 and 64-to-64 ops */
5975 switch (type) {
5976 case 0:
5977 if (!fp_access_check(s)) {
5978 return;
5980 handle_fp_1src_single(s, opcode, rd, rn);
5981 break;
5982 case 1:
5983 if (!fp_access_check(s)) {
5984 return;
5986 handle_fp_1src_double(s, opcode, rd, rn);
5987 break;
5988 case 3:
5989 if (!dc_isar_feature(aa64_fp16, s)) {
5990 unallocated_encoding(s);
5991 return;
5994 if (!fp_access_check(s)) {
5995 return;
5997 handle_fp_1src_half(s, opcode, rd, rn);
5998 break;
5999 default:
6000 unallocated_encoding(s);
6002 break;
6004 default:
6005 unallocated_encoding(s);
6006 break;
6010 /* Floating-point data-processing (2 source) - single precision */
6011 static void handle_fp_2src_single(DisasContext *s, int opcode,
6012 int rd, int rn, int rm)
6014 TCGv_i32 tcg_op1;
6015 TCGv_i32 tcg_op2;
6016 TCGv_i32 tcg_res;
6017 TCGv_ptr fpst;
6019 tcg_res = tcg_temp_new_i32();
6020 fpst = get_fpstatus_ptr(false);
6021 tcg_op1 = read_fp_sreg(s, rn);
6022 tcg_op2 = read_fp_sreg(s, rm);
6024 switch (opcode) {
6025 case 0x0: /* FMUL */
6026 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
6027 break;
6028 case 0x1: /* FDIV */
6029 gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
6030 break;
6031 case 0x2: /* FADD */
6032 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
6033 break;
6034 case 0x3: /* FSUB */
6035 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
6036 break;
6037 case 0x4: /* FMAX */
6038 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
6039 break;
6040 case 0x5: /* FMIN */
6041 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
6042 break;
6043 case 0x6: /* FMAXNM */
6044 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
6045 break;
6046 case 0x7: /* FMINNM */
6047 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
6048 break;
6049 case 0x8: /* FNMUL */
6050 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
6051 gen_helper_vfp_negs(tcg_res, tcg_res);
6052 break;
6055 write_fp_sreg(s, rd, tcg_res);
6057 tcg_temp_free_ptr(fpst);
6058 tcg_temp_free_i32(tcg_op1);
6059 tcg_temp_free_i32(tcg_op2);
6060 tcg_temp_free_i32(tcg_res);
6063 /* Floating-point data-processing (2 source) - double precision */
6064 static void handle_fp_2src_double(DisasContext *s, int opcode,
6065 int rd, int rn, int rm)
6067 TCGv_i64 tcg_op1;
6068 TCGv_i64 tcg_op2;
6069 TCGv_i64 tcg_res;
6070 TCGv_ptr fpst;
6072 tcg_res = tcg_temp_new_i64();
6073 fpst = get_fpstatus_ptr(false);
6074 tcg_op1 = read_fp_dreg(s, rn);
6075 tcg_op2 = read_fp_dreg(s, rm);
6077 switch (opcode) {
6078 case 0x0: /* FMUL */
6079 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
6080 break;
6081 case 0x1: /* FDIV */
6082 gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
6083 break;
6084 case 0x2: /* FADD */
6085 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
6086 break;
6087 case 0x3: /* FSUB */
6088 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
6089 break;
6090 case 0x4: /* FMAX */
6091 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
6092 break;
6093 case 0x5: /* FMIN */
6094 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
6095 break;
6096 case 0x6: /* FMAXNM */
6097 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
6098 break;
6099 case 0x7: /* FMINNM */
6100 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
6101 break;
6102 case 0x8: /* FNMUL */
6103 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
6104 gen_helper_vfp_negd(tcg_res, tcg_res);
6105 break;
6108 write_fp_dreg(s, rd, tcg_res);
6110 tcg_temp_free_ptr(fpst);
6111 tcg_temp_free_i64(tcg_op1);
6112 tcg_temp_free_i64(tcg_op2);
6113 tcg_temp_free_i64(tcg_res);
6116 /* Floating-point data-processing (2 source) - half precision */
6117 static void handle_fp_2src_half(DisasContext *s, int opcode,
6118 int rd, int rn, int rm)
6120 TCGv_i32 tcg_op1;
6121 TCGv_i32 tcg_op2;
6122 TCGv_i32 tcg_res;
6123 TCGv_ptr fpst;
6125 tcg_res = tcg_temp_new_i32();
6126 fpst = get_fpstatus_ptr(true);
6127 tcg_op1 = read_fp_hreg(s, rn);
6128 tcg_op2 = read_fp_hreg(s, rm);
6130 switch (opcode) {
6131 case 0x0: /* FMUL */
6132 gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
6133 break;
6134 case 0x1: /* FDIV */
6135 gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
6136 break;
6137 case 0x2: /* FADD */
6138 gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
6139 break;
6140 case 0x3: /* FSUB */
6141 gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
6142 break;
6143 case 0x4: /* FMAX */
6144 gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
6145 break;
6146 case 0x5: /* FMIN */
6147 gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
6148 break;
6149 case 0x6: /* FMAXNM */
6150 gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
6151 break;
6152 case 0x7: /* FMINNM */
6153 gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
6154 break;
6155 case 0x8: /* FNMUL */
6156 gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
6157 tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
6158 break;
6159 default:
6160 g_assert_not_reached();
6163 write_fp_sreg(s, rd, tcg_res);
6165 tcg_temp_free_ptr(fpst);
6166 tcg_temp_free_i32(tcg_op1);
6167 tcg_temp_free_i32(tcg_op2);
6168 tcg_temp_free_i32(tcg_res);
6171 /* Floating point data-processing (2 source)
6172 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6173 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6174 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6175 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6177 static void disas_fp_2src(DisasContext *s, uint32_t insn)
6179 int mos = extract32(insn, 29, 3);
6180 int type = extract32(insn, 22, 2);
6181 int rd = extract32(insn, 0, 5);
6182 int rn = extract32(insn, 5, 5);
6183 int rm = extract32(insn, 16, 5);
6184 int opcode = extract32(insn, 12, 4);
6186 if (opcode > 8 || mos) {
6187 unallocated_encoding(s);
6188 return;
6191 switch (type) {
6192 case 0:
6193 if (!fp_access_check(s)) {
6194 return;
6196 handle_fp_2src_single(s, opcode, rd, rn, rm);
6197 break;
6198 case 1:
6199 if (!fp_access_check(s)) {
6200 return;
6202 handle_fp_2src_double(s, opcode, rd, rn, rm);
6203 break;
6204 case 3:
6205 if (!dc_isar_feature(aa64_fp16, s)) {
6206 unallocated_encoding(s);
6207 return;
6209 if (!fp_access_check(s)) {
6210 return;
6212 handle_fp_2src_half(s, opcode, rd, rn, rm);
6213 break;
6214 default:
6215 unallocated_encoding(s);
6219 /* Floating-point data-processing (3 source) - single precision */
6220 static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
6221 int rd, int rn, int rm, int ra)
6223 TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
6224 TCGv_i32 tcg_res = tcg_temp_new_i32();
6225 TCGv_ptr fpst = get_fpstatus_ptr(false);
6227 tcg_op1 = read_fp_sreg(s, rn);
6228 tcg_op2 = read_fp_sreg(s, rm);
6229 tcg_op3 = read_fp_sreg(s, ra);
6231 /* These are fused multiply-add, and must be done as one
6232 * floating point operation with no rounding between the
6233 * multiplication and addition steps.
6234 * NB that doing the negations here as separate steps is
6235 * correct : an input NaN should come out with its sign bit
6236 * flipped if it is a negated-input.
6238 if (o1 == true) {
6239 gen_helper_vfp_negs(tcg_op3, tcg_op3);
6242 if (o0 != o1) {
6243 gen_helper_vfp_negs(tcg_op1, tcg_op1);
6246 gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
6248 write_fp_sreg(s, rd, tcg_res);
6250 tcg_temp_free_ptr(fpst);
6251 tcg_temp_free_i32(tcg_op1);
6252 tcg_temp_free_i32(tcg_op2);
6253 tcg_temp_free_i32(tcg_op3);
6254 tcg_temp_free_i32(tcg_res);
6257 /* Floating-point data-processing (3 source) - double precision */
6258 static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
6259 int rd, int rn, int rm, int ra)
6261 TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
6262 TCGv_i64 tcg_res = tcg_temp_new_i64();
6263 TCGv_ptr fpst = get_fpstatus_ptr(false);
6265 tcg_op1 = read_fp_dreg(s, rn);
6266 tcg_op2 = read_fp_dreg(s, rm);
6267 tcg_op3 = read_fp_dreg(s, ra);
6269 /* These are fused multiply-add, and must be done as one
6270 * floating point operation with no rounding between the
6271 * multiplication and addition steps.
6272 * NB that doing the negations here as separate steps is
6273 * correct : an input NaN should come out with its sign bit
6274 * flipped if it is a negated-input.
6276 if (o1 == true) {
6277 gen_helper_vfp_negd(tcg_op3, tcg_op3);
6280 if (o0 != o1) {
6281 gen_helper_vfp_negd(tcg_op1, tcg_op1);
6284 gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
6286 write_fp_dreg(s, rd, tcg_res);
6288 tcg_temp_free_ptr(fpst);
6289 tcg_temp_free_i64(tcg_op1);
6290 tcg_temp_free_i64(tcg_op2);
6291 tcg_temp_free_i64(tcg_op3);
6292 tcg_temp_free_i64(tcg_res);
6295 /* Floating-point data-processing (3 source) - half precision */
6296 static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
6297 int rd, int rn, int rm, int ra)
6299 TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
6300 TCGv_i32 tcg_res = tcg_temp_new_i32();
6301 TCGv_ptr fpst = get_fpstatus_ptr(true);
6303 tcg_op1 = read_fp_hreg(s, rn);
6304 tcg_op2 = read_fp_hreg(s, rm);
6305 tcg_op3 = read_fp_hreg(s, ra);
6307 /* These are fused multiply-add, and must be done as one
6308 * floating point operation with no rounding between the
6309 * multiplication and addition steps.
6310 * NB that doing the negations here as separate steps is
6311 * correct : an input NaN should come out with its sign bit
6312 * flipped if it is a negated-input.
6314 if (o1 == true) {
6315 tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
6318 if (o0 != o1) {
6319 tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
6322 gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
6324 write_fp_sreg(s, rd, tcg_res);
6326 tcg_temp_free_ptr(fpst);
6327 tcg_temp_free_i32(tcg_op1);
6328 tcg_temp_free_i32(tcg_op2);
6329 tcg_temp_free_i32(tcg_op3);
6330 tcg_temp_free_i32(tcg_res);
6333 /* Floating point data-processing (3 source)
6334 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6335 * +---+---+---+-----------+------+----+------+----+------+------+------+
6336 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6337 * +---+---+---+-----------+------+----+------+----+------+------+------+
6339 static void disas_fp_3src(DisasContext *s, uint32_t insn)
6341 int mos = extract32(insn, 29, 3);
6342 int type = extract32(insn, 22, 2);
6343 int rd = extract32(insn, 0, 5);
6344 int rn = extract32(insn, 5, 5);
6345 int ra = extract32(insn, 10, 5);
6346 int rm = extract32(insn, 16, 5);
6347 bool o0 = extract32(insn, 15, 1);
6348 bool o1 = extract32(insn, 21, 1);
6350 if (mos) {
6351 unallocated_encoding(s);
6352 return;
6355 switch (type) {
6356 case 0:
6357 if (!fp_access_check(s)) {
6358 return;
6360 handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra);
6361 break;
6362 case 1:
6363 if (!fp_access_check(s)) {
6364 return;
6366 handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
6367 break;
6368 case 3:
6369 if (!dc_isar_feature(aa64_fp16, s)) {
6370 unallocated_encoding(s);
6371 return;
6373 if (!fp_access_check(s)) {
6374 return;
6376 handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
6377 break;
6378 default:
6379 unallocated_encoding(s);
6383 /* Floating point immediate
6384 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6385 * +---+---+---+-----------+------+---+------------+-------+------+------+
6386 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6387 * +---+---+---+-----------+------+---+------------+-------+------+------+
6389 static void disas_fp_imm(DisasContext *s, uint32_t insn)
6391 int rd = extract32(insn, 0, 5);
6392 int imm5 = extract32(insn, 5, 5);
6393 int imm8 = extract32(insn, 13, 8);
6394 int type = extract32(insn, 22, 2);
6395 int mos = extract32(insn, 29, 3);
6396 uint64_t imm;
6397 TCGv_i64 tcg_res;
6398 MemOp sz;
6400 if (mos || imm5) {
6401 unallocated_encoding(s);
6402 return;
6405 switch (type) {
6406 case 0:
6407 sz = MO_32;
6408 break;
6409 case 1:
6410 sz = MO_64;
6411 break;
6412 case 3:
6413 sz = MO_16;
6414 if (dc_isar_feature(aa64_fp16, s)) {
6415 break;
6417 /* fallthru */
6418 default:
6419 unallocated_encoding(s);
6420 return;
6423 if (!fp_access_check(s)) {
6424 return;
6427 imm = vfp_expand_imm(sz, imm8);
6429 tcg_res = tcg_const_i64(imm);
6430 write_fp_dreg(s, rd, tcg_res);
6431 tcg_temp_free_i64(tcg_res);
6434 /* Handle floating point <=> fixed point conversions. Note that we can
6435 * also deal with fp <=> integer conversions as a special case (scale == 64)
6436 * OPTME: consider handling that special case specially or at least skipping
6437 * the call to scalbn in the helpers for zero shifts.
6439 static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
6440 bool itof, int rmode, int scale, int sf, int type)
6442 bool is_signed = !(opcode & 1);
6443 TCGv_ptr tcg_fpstatus;
6444 TCGv_i32 tcg_shift, tcg_single;
6445 TCGv_i64 tcg_double;
6447 tcg_fpstatus = get_fpstatus_ptr(type == 3);
6449 tcg_shift = tcg_const_i32(64 - scale);
6451 if (itof) {
6452 TCGv_i64 tcg_int = cpu_reg(s, rn);
6453 if (!sf) {
6454 TCGv_i64 tcg_extend = new_tmp_a64(s);
6456 if (is_signed) {
6457 tcg_gen_ext32s_i64(tcg_extend, tcg_int);
6458 } else {
6459 tcg_gen_ext32u_i64(tcg_extend, tcg_int);
6462 tcg_int = tcg_extend;
6465 switch (type) {
6466 case 1: /* float64 */
6467 tcg_double = tcg_temp_new_i64();
6468 if (is_signed) {
6469 gen_helper_vfp_sqtod(tcg_double, tcg_int,
6470 tcg_shift, tcg_fpstatus);
6471 } else {
6472 gen_helper_vfp_uqtod(tcg_double, tcg_int,
6473 tcg_shift, tcg_fpstatus);
6475 write_fp_dreg(s, rd, tcg_double);
6476 tcg_temp_free_i64(tcg_double);
6477 break;
6479 case 0: /* float32 */
6480 tcg_single = tcg_temp_new_i32();
6481 if (is_signed) {
6482 gen_helper_vfp_sqtos(tcg_single, tcg_int,
6483 tcg_shift, tcg_fpstatus);
6484 } else {
6485 gen_helper_vfp_uqtos(tcg_single, tcg_int,
6486 tcg_shift, tcg_fpstatus);
6488 write_fp_sreg(s, rd, tcg_single);
6489 tcg_temp_free_i32(tcg_single);
6490 break;
6492 case 3: /* float16 */
6493 tcg_single = tcg_temp_new_i32();
6494 if (is_signed) {
6495 gen_helper_vfp_sqtoh(tcg_single, tcg_int,
6496 tcg_shift, tcg_fpstatus);
6497 } else {
6498 gen_helper_vfp_uqtoh(tcg_single, tcg_int,
6499 tcg_shift, tcg_fpstatus);
6501 write_fp_sreg(s, rd, tcg_single);
6502 tcg_temp_free_i32(tcg_single);
6503 break;
6505 default:
6506 g_assert_not_reached();
6508 } else {
6509 TCGv_i64 tcg_int = cpu_reg(s, rd);
6510 TCGv_i32 tcg_rmode;
6512 if (extract32(opcode, 2, 1)) {
6513 /* There are too many rounding modes to all fit into rmode,
6514 * so FCVTA[US] is a special case.
6516 rmode = FPROUNDING_TIEAWAY;
6519 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
6521 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
6523 switch (type) {
6524 case 1: /* float64 */
6525 tcg_double = read_fp_dreg(s, rn);
6526 if (is_signed) {
6527 if (!sf) {
6528 gen_helper_vfp_tosld(tcg_int, tcg_double,
6529 tcg_shift, tcg_fpstatus);
6530 } else {
6531 gen_helper_vfp_tosqd(tcg_int, tcg_double,
6532 tcg_shift, tcg_fpstatus);
6534 } else {
6535 if (!sf) {
6536 gen_helper_vfp_tould(tcg_int, tcg_double,
6537 tcg_shift, tcg_fpstatus);
6538 } else {
6539 gen_helper_vfp_touqd(tcg_int, tcg_double,
6540 tcg_shift, tcg_fpstatus);
6543 if (!sf) {
6544 tcg_gen_ext32u_i64(tcg_int, tcg_int);
6546 tcg_temp_free_i64(tcg_double);
6547 break;
6549 case 0: /* float32 */
6550 tcg_single = read_fp_sreg(s, rn);
6551 if (sf) {
6552 if (is_signed) {
6553 gen_helper_vfp_tosqs(tcg_int, tcg_single,
6554 tcg_shift, tcg_fpstatus);
6555 } else {
6556 gen_helper_vfp_touqs(tcg_int, tcg_single,
6557 tcg_shift, tcg_fpstatus);
6559 } else {
6560 TCGv_i32 tcg_dest = tcg_temp_new_i32();
6561 if (is_signed) {
6562 gen_helper_vfp_tosls(tcg_dest, tcg_single,
6563 tcg_shift, tcg_fpstatus);
6564 } else {
6565 gen_helper_vfp_touls(tcg_dest, tcg_single,
6566 tcg_shift, tcg_fpstatus);
6568 tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
6569 tcg_temp_free_i32(tcg_dest);
6571 tcg_temp_free_i32(tcg_single);
6572 break;
6574 case 3: /* float16 */
6575 tcg_single = read_fp_sreg(s, rn);
6576 if (sf) {
6577 if (is_signed) {
6578 gen_helper_vfp_tosqh(tcg_int, tcg_single,
6579 tcg_shift, tcg_fpstatus);
6580 } else {
6581 gen_helper_vfp_touqh(tcg_int, tcg_single,
6582 tcg_shift, tcg_fpstatus);
6584 } else {
6585 TCGv_i32 tcg_dest = tcg_temp_new_i32();
6586 if (is_signed) {
6587 gen_helper_vfp_toslh(tcg_dest, tcg_single,
6588 tcg_shift, tcg_fpstatus);
6589 } else {
6590 gen_helper_vfp_toulh(tcg_dest, tcg_single,
6591 tcg_shift, tcg_fpstatus);
6593 tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
6594 tcg_temp_free_i32(tcg_dest);
6596 tcg_temp_free_i32(tcg_single);
6597 break;
6599 default:
6600 g_assert_not_reached();
6603 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
6604 tcg_temp_free_i32(tcg_rmode);
6607 tcg_temp_free_ptr(tcg_fpstatus);
6608 tcg_temp_free_i32(tcg_shift);
6611 /* Floating point <-> fixed point conversions
6612 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6613 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6614 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6615 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6617 static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
6619 int rd = extract32(insn, 0, 5);
6620 int rn = extract32(insn, 5, 5);
6621 int scale = extract32(insn, 10, 6);
6622 int opcode = extract32(insn, 16, 3);
6623 int rmode = extract32(insn, 19, 2);
6624 int type = extract32(insn, 22, 2);
6625 bool sbit = extract32(insn, 29, 1);
6626 bool sf = extract32(insn, 31, 1);
6627 bool itof;
6629 if (sbit || (!sf && scale < 32)) {
6630 unallocated_encoding(s);
6631 return;
6634 switch (type) {
6635 case 0: /* float32 */
6636 case 1: /* float64 */
6637 break;
6638 case 3: /* float16 */
6639 if (dc_isar_feature(aa64_fp16, s)) {
6640 break;
6642 /* fallthru */
6643 default:
6644 unallocated_encoding(s);
6645 return;
6648 switch ((rmode << 3) | opcode) {
6649 case 0x2: /* SCVTF */
6650 case 0x3: /* UCVTF */
6651 itof = true;
6652 break;
6653 case 0x18: /* FCVTZS */
6654 case 0x19: /* FCVTZU */
6655 itof = false;
6656 break;
6657 default:
6658 unallocated_encoding(s);
6659 return;
6662 if (!fp_access_check(s)) {
6663 return;
6666 handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type);
6669 static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
6671 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6672 * without conversion.
6675 if (itof) {
6676 TCGv_i64 tcg_rn = cpu_reg(s, rn);
6677 TCGv_i64 tmp;
6679 switch (type) {
6680 case 0:
6681 /* 32 bit */
6682 tmp = tcg_temp_new_i64();
6683 tcg_gen_ext32u_i64(tmp, tcg_rn);
6684 write_fp_dreg(s, rd, tmp);
6685 tcg_temp_free_i64(tmp);
6686 break;
6687 case 1:
6688 /* 64 bit */
6689 write_fp_dreg(s, rd, tcg_rn);
6690 break;
6691 case 2:
6692 /* 64 bit to top half. */
6693 tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
6694 clear_vec_high(s, true, rd);
6695 break;
6696 case 3:
6697 /* 16 bit */
6698 tmp = tcg_temp_new_i64();
6699 tcg_gen_ext16u_i64(tmp, tcg_rn);
6700 write_fp_dreg(s, rd, tmp);
6701 tcg_temp_free_i64(tmp);
6702 break;
6703 default:
6704 g_assert_not_reached();
6706 } else {
6707 TCGv_i64 tcg_rd = cpu_reg(s, rd);
6709 switch (type) {
6710 case 0:
6711 /* 32 bit */
6712 tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32));
6713 break;
6714 case 1:
6715 /* 64 bit */
6716 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64));
6717 break;
6718 case 2:
6719 /* 64 bits from top half */
6720 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
6721 break;
6722 case 3:
6723 /* 16 bit */
6724 tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
6725 break;
6726 default:
6727 g_assert_not_reached();
6732 static void handle_fjcvtzs(DisasContext *s, int rd, int rn)
6734 TCGv_i64 t = read_fp_dreg(s, rn);
6735 TCGv_ptr fpstatus = get_fpstatus_ptr(false);
6737 gen_helper_fjcvtzs(t, t, fpstatus);
6739 tcg_temp_free_ptr(fpstatus);
6741 tcg_gen_ext32u_i64(cpu_reg(s, rd), t);
6742 tcg_gen_extrh_i64_i32(cpu_ZF, t);
6743 tcg_gen_movi_i32(cpu_CF, 0);
6744 tcg_gen_movi_i32(cpu_NF, 0);
6745 tcg_gen_movi_i32(cpu_VF, 0);
6747 tcg_temp_free_i64(t);
6750 /* Floating point <-> integer conversions
6751 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6752 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6753 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6754 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6756 static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
6758 int rd = extract32(insn, 0, 5);
6759 int rn = extract32(insn, 5, 5);
6760 int opcode = extract32(insn, 16, 3);
6761 int rmode = extract32(insn, 19, 2);
6762 int type = extract32(insn, 22, 2);
6763 bool sbit = extract32(insn, 29, 1);
6764 bool sf = extract32(insn, 31, 1);
6765 bool itof = false;
6767 if (sbit) {
6768 goto do_unallocated;
6771 switch (opcode) {
6772 case 2: /* SCVTF */
6773 case 3: /* UCVTF */
6774 itof = true;
6775 /* fallthru */
6776 case 4: /* FCVTAS */
6777 case 5: /* FCVTAU */
6778 if (rmode != 0) {
6779 goto do_unallocated;
6781 /* fallthru */
6782 case 0: /* FCVT[NPMZ]S */
6783 case 1: /* FCVT[NPMZ]U */
6784 switch (type) {
6785 case 0: /* float32 */
6786 case 1: /* float64 */
6787 break;
6788 case 3: /* float16 */
6789 if (!dc_isar_feature(aa64_fp16, s)) {
6790 goto do_unallocated;
6792 break;
6793 default:
6794 goto do_unallocated;
6796 if (!fp_access_check(s)) {
6797 return;
6799 handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
6800 break;
6802 default:
6803 switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
6804 case 0b01100110: /* FMOV half <-> 32-bit int */
6805 case 0b01100111:
6806 case 0b11100110: /* FMOV half <-> 64-bit int */
6807 case 0b11100111:
6808 if (!dc_isar_feature(aa64_fp16, s)) {
6809 goto do_unallocated;
6811 /* fallthru */
6812 case 0b00000110: /* FMOV 32-bit */
6813 case 0b00000111:
6814 case 0b10100110: /* FMOV 64-bit */
6815 case 0b10100111:
6816 case 0b11001110: /* FMOV top half of 128-bit */
6817 case 0b11001111:
6818 if (!fp_access_check(s)) {
6819 return;
6821 itof = opcode & 1;
6822 handle_fmov(s, rd, rn, type, itof);
6823 break;
6825 case 0b00111110: /* FJCVTZS */
6826 if (!dc_isar_feature(aa64_jscvt, s)) {
6827 goto do_unallocated;
6828 } else if (fp_access_check(s)) {
6829 handle_fjcvtzs(s, rd, rn);
6831 break;
6833 default:
6834 do_unallocated:
6835 unallocated_encoding(s);
6836 return;
6838 break;
6842 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6843 * 31 30 29 28 25 24 0
6844 * +---+---+---+---------+-----------------------------+
6845 * | | 0 | | 1 1 1 1 | |
6846 * +---+---+---+---------+-----------------------------+
6848 static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
6850 if (extract32(insn, 24, 1)) {
6851 /* Floating point data-processing (3 source) */
6852 disas_fp_3src(s, insn);
6853 } else if (extract32(insn, 21, 1) == 0) {
6854 /* Floating point to fixed point conversions */
6855 disas_fp_fixed_conv(s, insn);
6856 } else {
6857 switch (extract32(insn, 10, 2)) {
6858 case 1:
6859 /* Floating point conditional compare */
6860 disas_fp_ccomp(s, insn);
6861 break;
6862 case 2:
6863 /* Floating point data-processing (2 source) */
6864 disas_fp_2src(s, insn);
6865 break;
6866 case 3:
6867 /* Floating point conditional select */
6868 disas_fp_csel(s, insn);
6869 break;
6870 case 0:
6871 switch (ctz32(extract32(insn, 12, 4))) {
6872 case 0: /* [15:12] == xxx1 */
6873 /* Floating point immediate */
6874 disas_fp_imm(s, insn);
6875 break;
6876 case 1: /* [15:12] == xx10 */
6877 /* Floating point compare */
6878 disas_fp_compare(s, insn);
6879 break;
6880 case 2: /* [15:12] == x100 */
6881 /* Floating point data-processing (1 source) */
6882 disas_fp_1src(s, insn);
6883 break;
6884 case 3: /* [15:12] == 1000 */
6885 unallocated_encoding(s);
6886 break;
6887 default: /* [15:12] == 0000 */
6888 /* Floating point <-> integer conversions */
6889 disas_fp_int_conv(s, insn);
6890 break;
6892 break;
6897 static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
6898 int pos)
6900 /* Extract 64 bits from the middle of two concatenated 64 bit
6901 * vector register slices left:right. The extracted bits start
6902 * at 'pos' bits into the right (least significant) side.
6903 * We return the result in tcg_right, and guarantee not to
6904 * trash tcg_left.
6906 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
6907 assert(pos > 0 && pos < 64);
6909 tcg_gen_shri_i64(tcg_right, tcg_right, pos);
6910 tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos);
6911 tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp);
6913 tcg_temp_free_i64(tcg_tmp);
6916 /* EXT
6917 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6918 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6919 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6920 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6922 static void disas_simd_ext(DisasContext *s, uint32_t insn)
6924 int is_q = extract32(insn, 30, 1);
6925 int op2 = extract32(insn, 22, 2);
6926 int imm4 = extract32(insn, 11, 4);
6927 int rm = extract32(insn, 16, 5);
6928 int rn = extract32(insn, 5, 5);
6929 int rd = extract32(insn, 0, 5);
6930 int pos = imm4 << 3;
6931 TCGv_i64 tcg_resl, tcg_resh;
6933 if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) {
6934 unallocated_encoding(s);
6935 return;
6938 if (!fp_access_check(s)) {
6939 return;
6942 tcg_resh = tcg_temp_new_i64();
6943 tcg_resl = tcg_temp_new_i64();
6945 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6946 * either extracting 128 bits from a 128:128 concatenation, or
6947 * extracting 64 bits from a 64:64 concatenation.
6949 if (!is_q) {
6950 read_vec_element(s, tcg_resl, rn, 0, MO_64);
6951 if (pos != 0) {
6952 read_vec_element(s, tcg_resh, rm, 0, MO_64);
6953 do_ext64(s, tcg_resh, tcg_resl, pos);
6955 tcg_gen_movi_i64(tcg_resh, 0);
6956 } else {
6957 TCGv_i64 tcg_hh;
6958 typedef struct {
6959 int reg;
6960 int elt;
6961 } EltPosns;
6962 EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} };
6963 EltPosns *elt = eltposns;
6965 if (pos >= 64) {
6966 elt++;
6967 pos -= 64;
6970 read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64);
6971 elt++;
6972 read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64);
6973 elt++;
6974 if (pos != 0) {
6975 do_ext64(s, tcg_resh, tcg_resl, pos);
6976 tcg_hh = tcg_temp_new_i64();
6977 read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64);
6978 do_ext64(s, tcg_hh, tcg_resh, pos);
6979 tcg_temp_free_i64(tcg_hh);
6983 write_vec_element(s, tcg_resl, rd, 0, MO_64);
6984 tcg_temp_free_i64(tcg_resl);
6985 write_vec_element(s, tcg_resh, rd, 1, MO_64);
6986 tcg_temp_free_i64(tcg_resh);
6987 clear_vec_high(s, true, rd);
6990 /* TBL/TBX
6991 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6992 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6993 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6994 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6996 static void disas_simd_tb(DisasContext *s, uint32_t insn)
6998 int op2 = extract32(insn, 22, 2);
6999 int is_q = extract32(insn, 30, 1);
7000 int rm = extract32(insn, 16, 5);
7001 int rn = extract32(insn, 5, 5);
7002 int rd = extract32(insn, 0, 5);
7003 int is_tblx = extract32(insn, 12, 1);
7004 int len = extract32(insn, 13, 2);
7005 TCGv_i64 tcg_resl, tcg_resh, tcg_idx;
7006 TCGv_i32 tcg_regno, tcg_numregs;
7008 if (op2 != 0) {
7009 unallocated_encoding(s);
7010 return;
7013 if (!fp_access_check(s)) {
7014 return;
7017 /* This does a table lookup: for every byte element in the input
7018 * we index into a table formed from up to four vector registers,
7019 * and then the output is the result of the lookups. Our helper
7020 * function does the lookup operation for a single 64 bit part of
7021 * the input.
7023 tcg_resl = tcg_temp_new_i64();
7024 tcg_resh = tcg_temp_new_i64();
7026 if (is_tblx) {
7027 read_vec_element(s, tcg_resl, rd, 0, MO_64);
7028 } else {
7029 tcg_gen_movi_i64(tcg_resl, 0);
7031 if (is_tblx && is_q) {
7032 read_vec_element(s, tcg_resh, rd, 1, MO_64);
7033 } else {
7034 tcg_gen_movi_i64(tcg_resh, 0);
7037 tcg_idx = tcg_temp_new_i64();
7038 tcg_regno = tcg_const_i32(rn);
7039 tcg_numregs = tcg_const_i32(len + 1);
7040 read_vec_element(s, tcg_idx, rm, 0, MO_64);
7041 gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,
7042 tcg_regno, tcg_numregs);
7043 if (is_q) {
7044 read_vec_element(s, tcg_idx, rm, 1, MO_64);
7045 gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,
7046 tcg_regno, tcg_numregs);
7048 tcg_temp_free_i64(tcg_idx);
7049 tcg_temp_free_i32(tcg_regno);
7050 tcg_temp_free_i32(tcg_numregs);
7052 write_vec_element(s, tcg_resl, rd, 0, MO_64);
7053 tcg_temp_free_i64(tcg_resl);
7054 write_vec_element(s, tcg_resh, rd, 1, MO_64);
7055 tcg_temp_free_i64(tcg_resh);
7056 clear_vec_high(s, true, rd);
7059 /* ZIP/UZP/TRN
7060 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7061 * +---+---+-------------+------+---+------+---+------------------+------+
7062 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7063 * +---+---+-------------+------+---+------+---+------------------+------+
7065 static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
7067 int rd = extract32(insn, 0, 5);
7068 int rn = extract32(insn, 5, 5);
7069 int rm = extract32(insn, 16, 5);
7070 int size = extract32(insn, 22, 2);
7071 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7072 * bit 2 indicates 1 vs 2 variant of the insn.
7074 int opcode = extract32(insn, 12, 2);
7075 bool part = extract32(insn, 14, 1);
7076 bool is_q = extract32(insn, 30, 1);
7077 int esize = 8 << size;
7078 int i, ofs;
7079 int datasize = is_q ? 128 : 64;
7080 int elements = datasize / esize;
7081 TCGv_i64 tcg_res, tcg_resl, tcg_resh;
7083 if (opcode == 0 || (size == 3 && !is_q)) {
7084 unallocated_encoding(s);
7085 return;
7088 if (!fp_access_check(s)) {
7089 return;
7092 tcg_resl = tcg_const_i64(0);
7093 tcg_resh = tcg_const_i64(0);
7094 tcg_res = tcg_temp_new_i64();
7096 for (i = 0; i < elements; i++) {
7097 switch (opcode) {
7098 case 1: /* UZP1/2 */
7100 int midpoint = elements / 2;
7101 if (i < midpoint) {
7102 read_vec_element(s, tcg_res, rn, 2 * i + part, size);
7103 } else {
7104 read_vec_element(s, tcg_res, rm,
7105 2 * (i - midpoint) + part, size);
7107 break;
7109 case 2: /* TRN1/2 */
7110 if (i & 1) {
7111 read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
7112 } else {
7113 read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
7115 break;
7116 case 3: /* ZIP1/2 */
7118 int base = part * elements / 2;
7119 if (i & 1) {
7120 read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
7121 } else {
7122 read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
7124 break;
7126 default:
7127 g_assert_not_reached();
7130 ofs = i * esize;
7131 if (ofs < 64) {
7132 tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
7133 tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
7134 } else {
7135 tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
7136 tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
7140 tcg_temp_free_i64(tcg_res);
7142 write_vec_element(s, tcg_resl, rd, 0, MO_64);
7143 tcg_temp_free_i64(tcg_resl);
7144 write_vec_element(s, tcg_resh, rd, 1, MO_64);
7145 tcg_temp_free_i64(tcg_resh);
7146 clear_vec_high(s, true, rd);
7150 * do_reduction_op helper
7152 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7153 * important for correct NaN propagation that we do these
7154 * operations in exactly the order specified by the pseudocode.
7156 * This is a recursive function, TCG temps should be freed by the
7157 * calling function once it is done with the values.
7159 static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
7160 int esize, int size, int vmap, TCGv_ptr fpst)
7162 if (esize == size) {
7163 int element;
7164 MemOp msize = esize == 16 ? MO_16 : MO_32;
7165 TCGv_i32 tcg_elem;
7167 /* We should have one register left here */
7168 assert(ctpop8(vmap) == 1);
7169 element = ctz32(vmap);
7170 assert(element < 8);
7172 tcg_elem = tcg_temp_new_i32();
7173 read_vec_element_i32(s, tcg_elem, rn, element, msize);
7174 return tcg_elem;
7175 } else {
7176 int bits = size / 2;
7177 int shift = ctpop8(vmap) / 2;
7178 int vmap_lo = (vmap >> shift) & vmap;
7179 int vmap_hi = (vmap & ~vmap_lo);
7180 TCGv_i32 tcg_hi, tcg_lo, tcg_res;
7182 tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
7183 tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
7184 tcg_res = tcg_temp_new_i32();
7186 switch (fpopcode) {
7187 case 0x0c: /* fmaxnmv half-precision */
7188 gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
7189 break;
7190 case 0x0f: /* fmaxv half-precision */
7191 gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
7192 break;
7193 case 0x1c: /* fminnmv half-precision */
7194 gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
7195 break;
7196 case 0x1f: /* fminv half-precision */
7197 gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
7198 break;
7199 case 0x2c: /* fmaxnmv */
7200 gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
7201 break;
7202 case 0x2f: /* fmaxv */
7203 gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
7204 break;
7205 case 0x3c: /* fminnmv */
7206 gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
7207 break;
7208 case 0x3f: /* fminv */
7209 gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
7210 break;
7211 default:
7212 g_assert_not_reached();
7215 tcg_temp_free_i32(tcg_hi);
7216 tcg_temp_free_i32(tcg_lo);
7217 return tcg_res;
7221 /* AdvSIMD across lanes
7222 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7223 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7224 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7225 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7227 static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
7229 int rd = extract32(insn, 0, 5);
7230 int rn = extract32(insn, 5, 5);
7231 int size = extract32(insn, 22, 2);
7232 int opcode = extract32(insn, 12, 5);
7233 bool is_q = extract32(insn, 30, 1);
7234 bool is_u = extract32(insn, 29, 1);
7235 bool is_fp = false;
7236 bool is_min = false;
7237 int esize;
7238 int elements;
7239 int i;
7240 TCGv_i64 tcg_res, tcg_elt;
7242 switch (opcode) {
7243 case 0x1b: /* ADDV */
7244 if (is_u) {
7245 unallocated_encoding(s);
7246 return;
7248 /* fall through */
7249 case 0x3: /* SADDLV, UADDLV */
7250 case 0xa: /* SMAXV, UMAXV */
7251 case 0x1a: /* SMINV, UMINV */
7252 if (size == 3 || (size == 2 && !is_q)) {
7253 unallocated_encoding(s);
7254 return;
7256 break;
7257 case 0xc: /* FMAXNMV, FMINNMV */
7258 case 0xf: /* FMAXV, FMINV */
7259 /* Bit 1 of size field encodes min vs max and the actual size
7260 * depends on the encoding of the U bit. If not set (and FP16
7261 * enabled) then we do half-precision float instead of single
7262 * precision.
7264 is_min = extract32(size, 1, 1);
7265 is_fp = true;
7266 if (!is_u && dc_isar_feature(aa64_fp16, s)) {
7267 size = 1;
7268 } else if (!is_u || !is_q || extract32(size, 0, 1)) {
7269 unallocated_encoding(s);
7270 return;
7271 } else {
7272 size = 2;
7274 break;
7275 default:
7276 unallocated_encoding(s);
7277 return;
7280 if (!fp_access_check(s)) {
7281 return;
7284 esize = 8 << size;
7285 elements = (is_q ? 128 : 64) / esize;
7287 tcg_res = tcg_temp_new_i64();
7288 tcg_elt = tcg_temp_new_i64();
7290 /* These instructions operate across all lanes of a vector
7291 * to produce a single result. We can guarantee that a 64
7292 * bit intermediate is sufficient:
7293 * + for [US]ADDLV the maximum element size is 32 bits, and
7294 * the result type is 64 bits
7295 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7296 * same as the element size, which is 32 bits at most
7297 * For the integer operations we can choose to work at 64
7298 * or 32 bits and truncate at the end; for simplicity
7299 * we use 64 bits always. The floating point
7300 * ops do require 32 bit intermediates, though.
7302 if (!is_fp) {
7303 read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN));
7305 for (i = 1; i < elements; i++) {
7306 read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN));
7308 switch (opcode) {
7309 case 0x03: /* SADDLV / UADDLV */
7310 case 0x1b: /* ADDV */
7311 tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt);
7312 break;
7313 case 0x0a: /* SMAXV / UMAXV */
7314 if (is_u) {
7315 tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt);
7316 } else {
7317 tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt);
7319 break;
7320 case 0x1a: /* SMINV / UMINV */
7321 if (is_u) {
7322 tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt);
7323 } else {
7324 tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt);
7326 break;
7327 default:
7328 g_assert_not_reached();
7332 } else {
7333 /* Floating point vector reduction ops which work across 32
7334 * bit (single) or 16 bit (half-precision) intermediates.
7335 * Note that correct NaN propagation requires that we do these
7336 * operations in exactly the order specified by the pseudocode.
7338 TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
7339 int fpopcode = opcode | is_min << 4 | is_u << 5;
7340 int vmap = (1 << elements) - 1;
7341 TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
7342 (is_q ? 128 : 64), vmap, fpst);
7343 tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
7344 tcg_temp_free_i32(tcg_res32);
7345 tcg_temp_free_ptr(fpst);
7348 tcg_temp_free_i64(tcg_elt);
7350 /* Now truncate the result to the width required for the final output */
7351 if (opcode == 0x03) {
7352 /* SADDLV, UADDLV: result is 2*esize */
7353 size++;
7356 switch (size) {
7357 case 0:
7358 tcg_gen_ext8u_i64(tcg_res, tcg_res);
7359 break;
7360 case 1:
7361 tcg_gen_ext16u_i64(tcg_res, tcg_res);
7362 break;
7363 case 2:
7364 tcg_gen_ext32u_i64(tcg_res, tcg_res);
7365 break;
7366 case 3:
7367 break;
7368 default:
7369 g_assert_not_reached();
7372 write_fp_dreg(s, rd, tcg_res);
7373 tcg_temp_free_i64(tcg_res);
7376 /* DUP (Element, Vector)
7378 * 31 30 29 21 20 16 15 10 9 5 4 0
7379 * +---+---+-------------------+--------+-------------+------+------+
7380 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7381 * +---+---+-------------------+--------+-------------+------+------+
7383 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7385 static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
7386 int imm5)
7388 int size = ctz32(imm5);
7389 int index;
7391 if (size > 3 || (size == 3 && !is_q)) {
7392 unallocated_encoding(s);
7393 return;
7396 if (!fp_access_check(s)) {
7397 return;
7400 index = imm5 >> (size + 1);
7401 tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd),
7402 vec_reg_offset(s, rn, index, size),
7403 is_q ? 16 : 8, vec_full_reg_size(s));
7406 /* DUP (element, scalar)
7407 * 31 21 20 16 15 10 9 5 4 0
7408 * +-----------------------+--------+-------------+------+------+
7409 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7410 * +-----------------------+--------+-------------+------+------+
7412 static void handle_simd_dupes(DisasContext *s, int rd, int rn,
7413 int imm5)
7415 int size = ctz32(imm5);
7416 int index;
7417 TCGv_i64 tmp;
7419 if (size > 3) {
7420 unallocated_encoding(s);
7421 return;
7424 if (!fp_access_check(s)) {
7425 return;
7428 index = imm5 >> (size + 1);
7430 /* This instruction just extracts the specified element and
7431 * zero-extends it into the bottom of the destination register.
7433 tmp = tcg_temp_new_i64();
7434 read_vec_element(s, tmp, rn, index, size);
7435 write_fp_dreg(s, rd, tmp);
7436 tcg_temp_free_i64(tmp);
7439 /* DUP (General)
7441 * 31 30 29 21 20 16 15 10 9 5 4 0
7442 * +---+---+-------------------+--------+-------------+------+------+
7443 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7444 * +---+---+-------------------+--------+-------------+------+------+
7446 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7448 static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
7449 int imm5)
7451 int size = ctz32(imm5);
7452 uint32_t dofs, oprsz, maxsz;
7454 if (size > 3 || ((size == 3) && !is_q)) {
7455 unallocated_encoding(s);
7456 return;
7459 if (!fp_access_check(s)) {
7460 return;
7463 dofs = vec_full_reg_offset(s, rd);
7464 oprsz = is_q ? 16 : 8;
7465 maxsz = vec_full_reg_size(s);
7467 tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn));
7470 /* INS (Element)
7472 * 31 21 20 16 15 14 11 10 9 5 4 0
7473 * +-----------------------+--------+------------+---+------+------+
7474 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7475 * +-----------------------+--------+------------+---+------+------+
7477 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7478 * index: encoded in imm5<4:size+1>
7480 static void handle_simd_inse(DisasContext *s, int rd, int rn,
7481 int imm4, int imm5)
7483 int size = ctz32(imm5);
7484 int src_index, dst_index;
7485 TCGv_i64 tmp;
7487 if (size > 3) {
7488 unallocated_encoding(s);
7489 return;
7492 if (!fp_access_check(s)) {
7493 return;
7496 dst_index = extract32(imm5, 1+size, 5);
7497 src_index = extract32(imm4, size, 4);
7499 tmp = tcg_temp_new_i64();
7501 read_vec_element(s, tmp, rn, src_index, size);
7502 write_vec_element(s, tmp, rd, dst_index, size);
7504 tcg_temp_free_i64(tmp);
7506 /* INS is considered a 128-bit write for SVE. */
7507 clear_vec_high(s, true, rd);
7511 /* INS (General)
7513 * 31 21 20 16 15 10 9 5 4 0
7514 * +-----------------------+--------+-------------+------+------+
7515 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7516 * +-----------------------+--------+-------------+------+------+
7518 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7519 * index: encoded in imm5<4:size+1>
7521 static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
7523 int size = ctz32(imm5);
7524 int idx;
7526 if (size > 3) {
7527 unallocated_encoding(s);
7528 return;
7531 if (!fp_access_check(s)) {
7532 return;
7535 idx = extract32(imm5, 1 + size, 4 - size);
7536 write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
7538 /* INS is considered a 128-bit write for SVE. */
7539 clear_vec_high(s, true, rd);
7543 * UMOV (General)
7544 * SMOV (General)
7546 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7547 * +---+---+-------------------+--------+-------------+------+------+
7548 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7549 * +---+---+-------------------+--------+-------------+------+------+
7551 * U: unsigned when set
7552 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7554 static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
7555 int rn, int rd, int imm5)
7557 int size = ctz32(imm5);
7558 int element;
7559 TCGv_i64 tcg_rd;
7561 /* Check for UnallocatedEncodings */
7562 if (is_signed) {
7563 if (size > 2 || (size == 2 && !is_q)) {
7564 unallocated_encoding(s);
7565 return;
7567 } else {
7568 if (size > 3
7569 || (size < 3 && is_q)
7570 || (size == 3 && !is_q)) {
7571 unallocated_encoding(s);
7572 return;
7576 if (!fp_access_check(s)) {
7577 return;
7580 element = extract32(imm5, 1+size, 4);
7582 tcg_rd = cpu_reg(s, rd);
7583 read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0));
7584 if (is_signed && !is_q) {
7585 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
7589 /* AdvSIMD copy
7590 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7591 * +---+---+----+-----------------+------+---+------+---+------+------+
7592 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7593 * +---+---+----+-----------------+------+---+------+---+------+------+
7595 static void disas_simd_copy(DisasContext *s, uint32_t insn)
7597 int rd = extract32(insn, 0, 5);
7598 int rn = extract32(insn, 5, 5);
7599 int imm4 = extract32(insn, 11, 4);
7600 int op = extract32(insn, 29, 1);
7601 int is_q = extract32(insn, 30, 1);
7602 int imm5 = extract32(insn, 16, 5);
7604 if (op) {
7605 if (is_q) {
7606 /* INS (element) */
7607 handle_simd_inse(s, rd, rn, imm4, imm5);
7608 } else {
7609 unallocated_encoding(s);
7611 } else {
7612 switch (imm4) {
7613 case 0:
7614 /* DUP (element - vector) */
7615 handle_simd_dupe(s, is_q, rd, rn, imm5);
7616 break;
7617 case 1:
7618 /* DUP (general) */
7619 handle_simd_dupg(s, is_q, rd, rn, imm5);
7620 break;
7621 case 3:
7622 if (is_q) {
7623 /* INS (general) */
7624 handle_simd_insg(s, rd, rn, imm5);
7625 } else {
7626 unallocated_encoding(s);
7628 break;
7629 case 5:
7630 case 7:
7631 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7632 handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5);
7633 break;
7634 default:
7635 unallocated_encoding(s);
7636 break;
7641 /* AdvSIMD modified immediate
7642 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7643 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7644 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7645 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7647 * There are a number of operations that can be carried out here:
7648 * MOVI - move (shifted) imm into register
7649 * MVNI - move inverted (shifted) imm into register
7650 * ORR - bitwise OR of (shifted) imm with register
7651 * BIC - bitwise clear of (shifted) imm with register
7652 * With ARMv8.2 we also have:
7653 * FMOV half-precision
7655 static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
7657 int rd = extract32(insn, 0, 5);
7658 int cmode = extract32(insn, 12, 4);
7659 int cmode_3_1 = extract32(cmode, 1, 3);
7660 int cmode_0 = extract32(cmode, 0, 1);
7661 int o2 = extract32(insn, 11, 1);
7662 uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
7663 bool is_neg = extract32(insn, 29, 1);
7664 bool is_q = extract32(insn, 30, 1);
7665 uint64_t imm = 0;
7667 if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
7668 /* Check for FMOV (vector, immediate) - half-precision */
7669 if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) {
7670 unallocated_encoding(s);
7671 return;
7675 if (!fp_access_check(s)) {
7676 return;
7679 /* See AdvSIMDExpandImm() in ARM ARM */
7680 switch (cmode_3_1) {
7681 case 0: /* Replicate(Zeros(24):imm8, 2) */
7682 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7683 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7684 case 3: /* Replicate(imm8:Zeros(24), 2) */
7686 int shift = cmode_3_1 * 8;
7687 imm = bitfield_replicate(abcdefgh << shift, 32);
7688 break;
7690 case 4: /* Replicate(Zeros(8):imm8, 4) */
7691 case 5: /* Replicate(imm8:Zeros(8), 4) */
7693 int shift = (cmode_3_1 & 0x1) * 8;
7694 imm = bitfield_replicate(abcdefgh << shift, 16);
7695 break;
7697 case 6:
7698 if (cmode_0) {
7699 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7700 imm = (abcdefgh << 16) | 0xffff;
7701 } else {
7702 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7703 imm = (abcdefgh << 8) | 0xff;
7705 imm = bitfield_replicate(imm, 32);
7706 break;
7707 case 7:
7708 if (!cmode_0 && !is_neg) {
7709 imm = bitfield_replicate(abcdefgh, 8);
7710 } else if (!cmode_0 && is_neg) {
7711 int i;
7712 imm = 0;
7713 for (i = 0; i < 8; i++) {
7714 if ((abcdefgh) & (1 << i)) {
7715 imm |= 0xffULL << (i * 8);
7718 } else if (cmode_0) {
7719 if (is_neg) {
7720 imm = (abcdefgh & 0x3f) << 48;
7721 if (abcdefgh & 0x80) {
7722 imm |= 0x8000000000000000ULL;
7724 if (abcdefgh & 0x40) {
7725 imm |= 0x3fc0000000000000ULL;
7726 } else {
7727 imm |= 0x4000000000000000ULL;
7729 } else {
7730 if (o2) {
7731 /* FMOV (vector, immediate) - half-precision */
7732 imm = vfp_expand_imm(MO_16, abcdefgh);
7733 /* now duplicate across the lanes */
7734 imm = bitfield_replicate(imm, 16);
7735 } else {
7736 imm = (abcdefgh & 0x3f) << 19;
7737 if (abcdefgh & 0x80) {
7738 imm |= 0x80000000;
7740 if (abcdefgh & 0x40) {
7741 imm |= 0x3e000000;
7742 } else {
7743 imm |= 0x40000000;
7745 imm |= (imm << 32);
7749 break;
7750 default:
7751 fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
7752 g_assert_not_reached();
7755 if (cmode_3_1 != 7 && is_neg) {
7756 imm = ~imm;
7759 if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
7760 /* MOVI or MVNI, with MVNI negation handled above. */
7761 tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8,
7762 vec_full_reg_size(s), imm);
7763 } else {
7764 /* ORR or BIC, with BIC negation to AND handled above. */
7765 if (is_neg) {
7766 gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64);
7767 } else {
7768 gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64);
7773 /* AdvSIMD scalar copy
7774 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7775 * +-----+----+-----------------+------+---+------+---+------+------+
7776 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7777 * +-----+----+-----------------+------+---+------+---+------+------+
7779 static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
7781 int rd = extract32(insn, 0, 5);
7782 int rn = extract32(insn, 5, 5);
7783 int imm4 = extract32(insn, 11, 4);
7784 int imm5 = extract32(insn, 16, 5);
7785 int op = extract32(insn, 29, 1);
7787 if (op != 0 || imm4 != 0) {
7788 unallocated_encoding(s);
7789 return;
7792 /* DUP (element, scalar) */
7793 handle_simd_dupes(s, rd, rn, imm5);
7796 /* AdvSIMD scalar pairwise
7797 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7798 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7799 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7800 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7802 static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
7804 int u = extract32(insn, 29, 1);
7805 int size = extract32(insn, 22, 2);
7806 int opcode = extract32(insn, 12, 5);
7807 int rn = extract32(insn, 5, 5);
7808 int rd = extract32(insn, 0, 5);
7809 TCGv_ptr fpst;
7811 /* For some ops (the FP ones), size[1] is part of the encoding.
7812 * For ADDP strictly it is not but size[1] is always 1 for valid
7813 * encodings.
7815 opcode |= (extract32(size, 1, 1) << 5);
7817 switch (opcode) {
7818 case 0x3b: /* ADDP */
7819 if (u || size != 3) {
7820 unallocated_encoding(s);
7821 return;
7823 if (!fp_access_check(s)) {
7824 return;
7827 fpst = NULL;
7828 break;
7829 case 0xc: /* FMAXNMP */
7830 case 0xd: /* FADDP */
7831 case 0xf: /* FMAXP */
7832 case 0x2c: /* FMINNMP */
7833 case 0x2f: /* FMINP */
7834 /* FP op, size[0] is 32 or 64 bit*/
7835 if (!u) {
7836 if (!dc_isar_feature(aa64_fp16, s)) {
7837 unallocated_encoding(s);
7838 return;
7839 } else {
7840 size = MO_16;
7842 } else {
7843 size = extract32(size, 0, 1) ? MO_64 : MO_32;
7846 if (!fp_access_check(s)) {
7847 return;
7850 fpst = get_fpstatus_ptr(size == MO_16);
7851 break;
7852 default:
7853 unallocated_encoding(s);
7854 return;
7857 if (size == MO_64) {
7858 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
7859 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
7860 TCGv_i64 tcg_res = tcg_temp_new_i64();
7862 read_vec_element(s, tcg_op1, rn, 0, MO_64);
7863 read_vec_element(s, tcg_op2, rn, 1, MO_64);
7865 switch (opcode) {
7866 case 0x3b: /* ADDP */
7867 tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2);
7868 break;
7869 case 0xc: /* FMAXNMP */
7870 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
7871 break;
7872 case 0xd: /* FADDP */
7873 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
7874 break;
7875 case 0xf: /* FMAXP */
7876 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
7877 break;
7878 case 0x2c: /* FMINNMP */
7879 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
7880 break;
7881 case 0x2f: /* FMINP */
7882 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
7883 break;
7884 default:
7885 g_assert_not_reached();
7888 write_fp_dreg(s, rd, tcg_res);
7890 tcg_temp_free_i64(tcg_op1);
7891 tcg_temp_free_i64(tcg_op2);
7892 tcg_temp_free_i64(tcg_res);
7893 } else {
7894 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
7895 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
7896 TCGv_i32 tcg_res = tcg_temp_new_i32();
7898 read_vec_element_i32(s, tcg_op1, rn, 0, size);
7899 read_vec_element_i32(s, tcg_op2, rn, 1, size);
7901 if (size == MO_16) {
7902 switch (opcode) {
7903 case 0xc: /* FMAXNMP */
7904 gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
7905 break;
7906 case 0xd: /* FADDP */
7907 gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
7908 break;
7909 case 0xf: /* FMAXP */
7910 gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
7911 break;
7912 case 0x2c: /* FMINNMP */
7913 gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
7914 break;
7915 case 0x2f: /* FMINP */
7916 gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
7917 break;
7918 default:
7919 g_assert_not_reached();
7921 } else {
7922 switch (opcode) {
7923 case 0xc: /* FMAXNMP */
7924 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
7925 break;
7926 case 0xd: /* FADDP */
7927 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
7928 break;
7929 case 0xf: /* FMAXP */
7930 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
7931 break;
7932 case 0x2c: /* FMINNMP */
7933 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
7934 break;
7935 case 0x2f: /* FMINP */
7936 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
7937 break;
7938 default:
7939 g_assert_not_reached();
7943 write_fp_sreg(s, rd, tcg_res);
7945 tcg_temp_free_i32(tcg_op1);
7946 tcg_temp_free_i32(tcg_op2);
7947 tcg_temp_free_i32(tcg_res);
7950 if (fpst) {
7951 tcg_temp_free_ptr(fpst);
7956 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7958 * This code is handles the common shifting code and is used by both
7959 * the vector and scalar code.
7961 static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
7962 TCGv_i64 tcg_rnd, bool accumulate,
7963 bool is_u, int size, int shift)
7965 bool extended_result = false;
7966 bool round = tcg_rnd != NULL;
7967 int ext_lshift = 0;
7968 TCGv_i64 tcg_src_hi;
7970 if (round && size == 3) {
7971 extended_result = true;
7972 ext_lshift = 64 - shift;
7973 tcg_src_hi = tcg_temp_new_i64();
7974 } else if (shift == 64) {
7975 if (!accumulate && is_u) {
7976 /* result is zero */
7977 tcg_gen_movi_i64(tcg_res, 0);
7978 return;
7982 /* Deal with the rounding step */
7983 if (round) {
7984 if (extended_result) {
7985 TCGv_i64 tcg_zero = tcg_const_i64(0);
7986 if (!is_u) {
7987 /* take care of sign extending tcg_res */
7988 tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
7989 tcg_gen_add2_i64(tcg_src, tcg_src_hi,
7990 tcg_src, tcg_src_hi,
7991 tcg_rnd, tcg_zero);
7992 } else {
7993 tcg_gen_add2_i64(tcg_src, tcg_src_hi,
7994 tcg_src, tcg_zero,
7995 tcg_rnd, tcg_zero);
7997 tcg_temp_free_i64(tcg_zero);
7998 } else {
7999 tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
8003 /* Now do the shift right */
8004 if (round && extended_result) {
8005 /* extended case, >64 bit precision required */
8006 if (ext_lshift == 0) {
8007 /* special case, only high bits matter */
8008 tcg_gen_mov_i64(tcg_src, tcg_src_hi);
8009 } else {
8010 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
8011 tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift);
8012 tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi);
8014 } else {
8015 if (is_u) {
8016 if (shift == 64) {
8017 /* essentially shifting in 64 zeros */
8018 tcg_gen_movi_i64(tcg_src, 0);
8019 } else {
8020 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
8022 } else {
8023 if (shift == 64) {
8024 /* effectively extending the sign-bit */
8025 tcg_gen_sari_i64(tcg_src, tcg_src, 63);
8026 } else {
8027 tcg_gen_sari_i64(tcg_src, tcg_src, shift);
8032 if (accumulate) {
8033 tcg_gen_add_i64(tcg_res, tcg_res, tcg_src);
8034 } else {
8035 tcg_gen_mov_i64(tcg_res, tcg_src);
8038 if (extended_result) {
8039 tcg_temp_free_i64(tcg_src_hi);
8043 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8044 static void handle_scalar_simd_shri(DisasContext *s,
8045 bool is_u, int immh, int immb,
8046 int opcode, int rn, int rd)
8048 const int size = 3;
8049 int immhb = immh << 3 | immb;
8050 int shift = 2 * (8 << size) - immhb;
8051 bool accumulate = false;
8052 bool round = false;
8053 bool insert = false;
8054 TCGv_i64 tcg_rn;
8055 TCGv_i64 tcg_rd;
8056 TCGv_i64 tcg_round;
8058 if (!extract32(immh, 3, 1)) {
8059 unallocated_encoding(s);
8060 return;
8063 if (!fp_access_check(s)) {
8064 return;
8067 switch (opcode) {
8068 case 0x02: /* SSRA / USRA (accumulate) */
8069 accumulate = true;
8070 break;
8071 case 0x04: /* SRSHR / URSHR (rounding) */
8072 round = true;
8073 break;
8074 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8075 accumulate = round = true;
8076 break;
8077 case 0x08: /* SRI */
8078 insert = true;
8079 break;
8082 if (round) {
8083 uint64_t round_const = 1ULL << (shift - 1);
8084 tcg_round = tcg_const_i64(round_const);
8085 } else {
8086 tcg_round = NULL;
8089 tcg_rn = read_fp_dreg(s, rn);
8090 tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
8092 if (insert) {
8093 /* shift count same as element size is valid but does nothing;
8094 * special case to avoid potential shift by 64.
8096 int esize = 8 << size;
8097 if (shift != esize) {
8098 tcg_gen_shri_i64(tcg_rn, tcg_rn, shift);
8099 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift);
8101 } else {
8102 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
8103 accumulate, is_u, size, shift);
8106 write_fp_dreg(s, rd, tcg_rd);
8108 tcg_temp_free_i64(tcg_rn);
8109 tcg_temp_free_i64(tcg_rd);
8110 if (round) {
8111 tcg_temp_free_i64(tcg_round);
8115 /* SHL/SLI - Scalar shift left */
8116 static void handle_scalar_simd_shli(DisasContext *s, bool insert,
8117 int immh, int immb, int opcode,
8118 int rn, int rd)
8120 int size = 32 - clz32(immh) - 1;
8121 int immhb = immh << 3 | immb;
8122 int shift = immhb - (8 << size);
8123 TCGv_i64 tcg_rn = new_tmp_a64(s);
8124 TCGv_i64 tcg_rd = new_tmp_a64(s);
8126 if (!extract32(immh, 3, 1)) {
8127 unallocated_encoding(s);
8128 return;
8131 if (!fp_access_check(s)) {
8132 return;
8135 tcg_rn = read_fp_dreg(s, rn);
8136 tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
8138 if (insert) {
8139 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift);
8140 } else {
8141 tcg_gen_shli_i64(tcg_rd, tcg_rn, shift);
8144 write_fp_dreg(s, rd, tcg_rd);
8146 tcg_temp_free_i64(tcg_rn);
8147 tcg_temp_free_i64(tcg_rd);
8150 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8151 * (signed/unsigned) narrowing */
8152 static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
8153 bool is_u_shift, bool is_u_narrow,
8154 int immh, int immb, int opcode,
8155 int rn, int rd)
8157 int immhb = immh << 3 | immb;
8158 int size = 32 - clz32(immh) - 1;
8159 int esize = 8 << size;
8160 int shift = (2 * esize) - immhb;
8161 int elements = is_scalar ? 1 : (64 / esize);
8162 bool round = extract32(opcode, 0, 1);
8163 MemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);
8164 TCGv_i64 tcg_rn, tcg_rd, tcg_round;
8165 TCGv_i32 tcg_rd_narrowed;
8166 TCGv_i64 tcg_final;
8168 static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = {
8169 { gen_helper_neon_narrow_sat_s8,
8170 gen_helper_neon_unarrow_sat8 },
8171 { gen_helper_neon_narrow_sat_s16,
8172 gen_helper_neon_unarrow_sat16 },
8173 { gen_helper_neon_narrow_sat_s32,
8174 gen_helper_neon_unarrow_sat32 },
8175 { NULL, NULL },
8177 static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = {
8178 gen_helper_neon_narrow_sat_u8,
8179 gen_helper_neon_narrow_sat_u16,
8180 gen_helper_neon_narrow_sat_u32,
8181 NULL
8183 NeonGenNarrowEnvFn *narrowfn;
8185 int i;
8187 assert(size < 4);
8189 if (extract32(immh, 3, 1)) {
8190 unallocated_encoding(s);
8191 return;
8194 if (!fp_access_check(s)) {
8195 return;
8198 if (is_u_shift) {
8199 narrowfn = unsigned_narrow_fns[size];
8200 } else {
8201 narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0];
8204 tcg_rn = tcg_temp_new_i64();
8205 tcg_rd = tcg_temp_new_i64();
8206 tcg_rd_narrowed = tcg_temp_new_i32();
8207 tcg_final = tcg_const_i64(0);
8209 if (round) {
8210 uint64_t round_const = 1ULL << (shift - 1);
8211 tcg_round = tcg_const_i64(round_const);
8212 } else {
8213 tcg_round = NULL;
8216 for (i = 0; i < elements; i++) {
8217 read_vec_element(s, tcg_rn, rn, i, ldop);
8218 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
8219 false, is_u_shift, size+1, shift);
8220 narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
8221 tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
8222 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
8225 if (!is_q) {
8226 write_vec_element(s, tcg_final, rd, 0, MO_64);
8227 } else {
8228 write_vec_element(s, tcg_final, rd, 1, MO_64);
8231 if (round) {
8232 tcg_temp_free_i64(tcg_round);
8234 tcg_temp_free_i64(tcg_rn);
8235 tcg_temp_free_i64(tcg_rd);
8236 tcg_temp_free_i32(tcg_rd_narrowed);
8237 tcg_temp_free_i64(tcg_final);
8239 clear_vec_high(s, is_q, rd);
8242 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8243 static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
8244 bool src_unsigned, bool dst_unsigned,
8245 int immh, int immb, int rn, int rd)
8247 int immhb = immh << 3 | immb;
8248 int size = 32 - clz32(immh) - 1;
8249 int shift = immhb - (8 << size);
8250 int pass;
8252 assert(immh != 0);
8253 assert(!(scalar && is_q));
8255 if (!scalar) {
8256 if (!is_q && extract32(immh, 3, 1)) {
8257 unallocated_encoding(s);
8258 return;
8261 /* Since we use the variable-shift helpers we must
8262 * replicate the shift count into each element of
8263 * the tcg_shift value.
8265 switch (size) {
8266 case 0:
8267 shift |= shift << 8;
8268 /* fall through */
8269 case 1:
8270 shift |= shift << 16;
8271 break;
8272 case 2:
8273 case 3:
8274 break;
8275 default:
8276 g_assert_not_reached();
8280 if (!fp_access_check(s)) {
8281 return;
8284 if (size == 3) {
8285 TCGv_i64 tcg_shift = tcg_const_i64(shift);
8286 static NeonGenTwo64OpEnvFn * const fns[2][2] = {
8287 { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
8288 { NULL, gen_helper_neon_qshl_u64 },
8290 NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned];
8291 int maxpass = is_q ? 2 : 1;
8293 for (pass = 0; pass < maxpass; pass++) {
8294 TCGv_i64 tcg_op = tcg_temp_new_i64();
8296 read_vec_element(s, tcg_op, rn, pass, MO_64);
8297 genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
8298 write_vec_element(s, tcg_op, rd, pass, MO_64);
8300 tcg_temp_free_i64(tcg_op);
8302 tcg_temp_free_i64(tcg_shift);
8303 clear_vec_high(s, is_q, rd);
8304 } else {
8305 TCGv_i32 tcg_shift = tcg_const_i32(shift);
8306 static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
8308 { gen_helper_neon_qshl_s8,
8309 gen_helper_neon_qshl_s16,
8310 gen_helper_neon_qshl_s32 },
8311 { gen_helper_neon_qshlu_s8,
8312 gen_helper_neon_qshlu_s16,
8313 gen_helper_neon_qshlu_s32 }
8314 }, {
8315 { NULL, NULL, NULL },
8316 { gen_helper_neon_qshl_u8,
8317 gen_helper_neon_qshl_u16,
8318 gen_helper_neon_qshl_u32 }
8321 NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];
8322 MemOp memop = scalar ? size : MO_32;
8323 int maxpass = scalar ? 1 : is_q ? 4 : 2;
8325 for (pass = 0; pass < maxpass; pass++) {
8326 TCGv_i32 tcg_op = tcg_temp_new_i32();
8328 read_vec_element_i32(s, tcg_op, rn, pass, memop);
8329 genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
8330 if (scalar) {
8331 switch (size) {
8332 case 0:
8333 tcg_gen_ext8u_i32(tcg_op, tcg_op);
8334 break;
8335 case 1:
8336 tcg_gen_ext16u_i32(tcg_op, tcg_op);
8337 break;
8338 case 2:
8339 break;
8340 default:
8341 g_assert_not_reached();
8343 write_fp_sreg(s, rd, tcg_op);
8344 } else {
8345 write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
8348 tcg_temp_free_i32(tcg_op);
8350 tcg_temp_free_i32(tcg_shift);
8352 if (!scalar) {
8353 clear_vec_high(s, is_q, rd);
8358 /* Common vector code for handling integer to FP conversion */
8359 static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
8360 int elements, int is_signed,
8361 int fracbits, int size)
8363 TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
8364 TCGv_i32 tcg_shift = NULL;
8366 MemOp mop = size | (is_signed ? MO_SIGN : 0);
8367 int pass;
8369 if (fracbits || size == MO_64) {
8370 tcg_shift = tcg_const_i32(fracbits);
8373 if (size == MO_64) {
8374 TCGv_i64 tcg_int64 = tcg_temp_new_i64();
8375 TCGv_i64 tcg_double = tcg_temp_new_i64();
8377 for (pass = 0; pass < elements; pass++) {
8378 read_vec_element(s, tcg_int64, rn, pass, mop);
8380 if (is_signed) {
8381 gen_helper_vfp_sqtod(tcg_double, tcg_int64,
8382 tcg_shift, tcg_fpst);
8383 } else {
8384 gen_helper_vfp_uqtod(tcg_double, tcg_int64,
8385 tcg_shift, tcg_fpst);
8387 if (elements == 1) {
8388 write_fp_dreg(s, rd, tcg_double);
8389 } else {
8390 write_vec_element(s, tcg_double, rd, pass, MO_64);
8394 tcg_temp_free_i64(tcg_int64);
8395 tcg_temp_free_i64(tcg_double);
8397 } else {
8398 TCGv_i32 tcg_int32 = tcg_temp_new_i32();
8399 TCGv_i32 tcg_float = tcg_temp_new_i32();
8401 for (pass = 0; pass < elements; pass++) {
8402 read_vec_element_i32(s, tcg_int32, rn, pass, mop);
8404 switch (size) {
8405 case MO_32:
8406 if (fracbits) {
8407 if (is_signed) {
8408 gen_helper_vfp_sltos(tcg_float, tcg_int32,
8409 tcg_shift, tcg_fpst);
8410 } else {
8411 gen_helper_vfp_ultos(tcg_float, tcg_int32,
8412 tcg_shift, tcg_fpst);
8414 } else {
8415 if (is_signed) {
8416 gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
8417 } else {
8418 gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
8421 break;
8422 case MO_16:
8423 if (fracbits) {
8424 if (is_signed) {
8425 gen_helper_vfp_sltoh(tcg_float, tcg_int32,
8426 tcg_shift, tcg_fpst);
8427 } else {
8428 gen_helper_vfp_ultoh(tcg_float, tcg_int32,
8429 tcg_shift, tcg_fpst);
8431 } else {
8432 if (is_signed) {
8433 gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
8434 } else {
8435 gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
8438 break;
8439 default:
8440 g_assert_not_reached();
8443 if (elements == 1) {
8444 write_fp_sreg(s, rd, tcg_float);
8445 } else {
8446 write_vec_element_i32(s, tcg_float, rd, pass, size);
8450 tcg_temp_free_i32(tcg_int32);
8451 tcg_temp_free_i32(tcg_float);
8454 tcg_temp_free_ptr(tcg_fpst);
8455 if (tcg_shift) {
8456 tcg_temp_free_i32(tcg_shift);
8459 clear_vec_high(s, elements << size == 16, rd);
8462 /* UCVTF/SCVTF - Integer to FP conversion */
8463 static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
8464 bool is_q, bool is_u,
8465 int immh, int immb, int opcode,
8466 int rn, int rd)
8468 int size, elements, fracbits;
8469 int immhb = immh << 3 | immb;
8471 if (immh & 8) {
8472 size = MO_64;
8473 if (!is_scalar && !is_q) {
8474 unallocated_encoding(s);
8475 return;
8477 } else if (immh & 4) {
8478 size = MO_32;
8479 } else if (immh & 2) {
8480 size = MO_16;
8481 if (!dc_isar_feature(aa64_fp16, s)) {
8482 unallocated_encoding(s);
8483 return;
8485 } else {
8486 /* immh == 0 would be a failure of the decode logic */
8487 g_assert(immh == 1);
8488 unallocated_encoding(s);
8489 return;
8492 if (is_scalar) {
8493 elements = 1;
8494 } else {
8495 elements = (8 << is_q) >> size;
8497 fracbits = (16 << size) - immhb;
8499 if (!fp_access_check(s)) {
8500 return;
8503 handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
8506 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8507 static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
8508 bool is_q, bool is_u,
8509 int immh, int immb, int rn, int rd)
8511 int immhb = immh << 3 | immb;
8512 int pass, size, fracbits;
8513 TCGv_ptr tcg_fpstatus;
8514 TCGv_i32 tcg_rmode, tcg_shift;
8516 if (immh & 0x8) {
8517 size = MO_64;
8518 if (!is_scalar && !is_q) {
8519 unallocated_encoding(s);
8520 return;
8522 } else if (immh & 0x4) {
8523 size = MO_32;
8524 } else if (immh & 0x2) {
8525 size = MO_16;
8526 if (!dc_isar_feature(aa64_fp16, s)) {
8527 unallocated_encoding(s);
8528 return;
8530 } else {
8531 /* Should have split out AdvSIMD modified immediate earlier. */
8532 assert(immh == 1);
8533 unallocated_encoding(s);
8534 return;
8537 if (!fp_access_check(s)) {
8538 return;
8541 assert(!(is_scalar && is_q));
8543 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
8544 tcg_fpstatus = get_fpstatus_ptr(size == MO_16);
8545 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
8546 fracbits = (16 << size) - immhb;
8547 tcg_shift = tcg_const_i32(fracbits);
8549 if (size == MO_64) {
8550 int maxpass = is_scalar ? 1 : 2;
8552 for (pass = 0; pass < maxpass; pass++) {
8553 TCGv_i64 tcg_op = tcg_temp_new_i64();
8555 read_vec_element(s, tcg_op, rn, pass, MO_64);
8556 if (is_u) {
8557 gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
8558 } else {
8559 gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
8561 write_vec_element(s, tcg_op, rd, pass, MO_64);
8562 tcg_temp_free_i64(tcg_op);
8564 clear_vec_high(s, is_q, rd);
8565 } else {
8566 void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
8567 int maxpass = is_scalar ? 1 : ((8 << is_q) >> size);
8569 switch (size) {
8570 case MO_16:
8571 if (is_u) {
8572 fn = gen_helper_vfp_touhh;
8573 } else {
8574 fn = gen_helper_vfp_toshh;
8576 break;
8577 case MO_32:
8578 if (is_u) {
8579 fn = gen_helper_vfp_touls;
8580 } else {
8581 fn = gen_helper_vfp_tosls;
8583 break;
8584 default:
8585 g_assert_not_reached();
8588 for (pass = 0; pass < maxpass; pass++) {
8589 TCGv_i32 tcg_op = tcg_temp_new_i32();
8591 read_vec_element_i32(s, tcg_op, rn, pass, size);
8592 fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
8593 if (is_scalar) {
8594 write_fp_sreg(s, rd, tcg_op);
8595 } else {
8596 write_vec_element_i32(s, tcg_op, rd, pass, size);
8598 tcg_temp_free_i32(tcg_op);
8600 if (!is_scalar) {
8601 clear_vec_high(s, is_q, rd);
8605 tcg_temp_free_ptr(tcg_fpstatus);
8606 tcg_temp_free_i32(tcg_shift);
8607 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
8608 tcg_temp_free_i32(tcg_rmode);
8611 /* AdvSIMD scalar shift by immediate
8612 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8613 * +-----+---+-------------+------+------+--------+---+------+------+
8614 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8615 * +-----+---+-------------+------+------+--------+---+------+------+
8617 * This is the scalar version so it works on a fixed sized registers
8619 static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
8621 int rd = extract32(insn, 0, 5);
8622 int rn = extract32(insn, 5, 5);
8623 int opcode = extract32(insn, 11, 5);
8624 int immb = extract32(insn, 16, 3);
8625 int immh = extract32(insn, 19, 4);
8626 bool is_u = extract32(insn, 29, 1);
8628 if (immh == 0) {
8629 unallocated_encoding(s);
8630 return;
8633 switch (opcode) {
8634 case 0x08: /* SRI */
8635 if (!is_u) {
8636 unallocated_encoding(s);
8637 return;
8639 /* fall through */
8640 case 0x00: /* SSHR / USHR */
8641 case 0x02: /* SSRA / USRA */
8642 case 0x04: /* SRSHR / URSHR */
8643 case 0x06: /* SRSRA / URSRA */
8644 handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd);
8645 break;
8646 case 0x0a: /* SHL / SLI */
8647 handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd);
8648 break;
8649 case 0x1c: /* SCVTF, UCVTF */
8650 handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
8651 opcode, rn, rd);
8652 break;
8653 case 0x10: /* SQSHRUN, SQSHRUN2 */
8654 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8655 if (!is_u) {
8656 unallocated_encoding(s);
8657 return;
8659 handle_vec_simd_sqshrn(s, true, false, false, true,
8660 immh, immb, opcode, rn, rd);
8661 break;
8662 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8663 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8664 handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
8665 immh, immb, opcode, rn, rd);
8666 break;
8667 case 0xc: /* SQSHLU */
8668 if (!is_u) {
8669 unallocated_encoding(s);
8670 return;
8672 handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd);
8673 break;
8674 case 0xe: /* SQSHL, UQSHL */
8675 handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd);
8676 break;
8677 case 0x1f: /* FCVTZS, FCVTZU */
8678 handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
8679 break;
8680 default:
8681 unallocated_encoding(s);
8682 break;
8686 /* AdvSIMD scalar three different
8687 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8688 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8689 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8690 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8692 static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
8694 bool is_u = extract32(insn, 29, 1);
8695 int size = extract32(insn, 22, 2);
8696 int opcode = extract32(insn, 12, 4);
8697 int rm = extract32(insn, 16, 5);
8698 int rn = extract32(insn, 5, 5);
8699 int rd = extract32(insn, 0, 5);
8701 if (is_u) {
8702 unallocated_encoding(s);
8703 return;
8706 switch (opcode) {
8707 case 0x9: /* SQDMLAL, SQDMLAL2 */
8708 case 0xb: /* SQDMLSL, SQDMLSL2 */
8709 case 0xd: /* SQDMULL, SQDMULL2 */
8710 if (size == 0 || size == 3) {
8711 unallocated_encoding(s);
8712 return;
8714 break;
8715 default:
8716 unallocated_encoding(s);
8717 return;
8720 if (!fp_access_check(s)) {
8721 return;
8724 if (size == 2) {
8725 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8726 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8727 TCGv_i64 tcg_res = tcg_temp_new_i64();
8729 read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);
8730 read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
8732 tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);
8733 gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res);
8735 switch (opcode) {
8736 case 0xd: /* SQDMULL, SQDMULL2 */
8737 break;
8738 case 0xb: /* SQDMLSL, SQDMLSL2 */
8739 tcg_gen_neg_i64(tcg_res, tcg_res);
8740 /* fall through */
8741 case 0x9: /* SQDMLAL, SQDMLAL2 */
8742 read_vec_element(s, tcg_op1, rd, 0, MO_64);
8743 gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env,
8744 tcg_res, tcg_op1);
8745 break;
8746 default:
8747 g_assert_not_reached();
8750 write_fp_dreg(s, rd, tcg_res);
8752 tcg_temp_free_i64(tcg_op1);
8753 tcg_temp_free_i64(tcg_op2);
8754 tcg_temp_free_i64(tcg_res);
8755 } else {
8756 TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
8757 TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
8758 TCGv_i64 tcg_res = tcg_temp_new_i64();
8760 gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
8761 gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
8763 switch (opcode) {
8764 case 0xd: /* SQDMULL, SQDMULL2 */
8765 break;
8766 case 0xb: /* SQDMLSL, SQDMLSL2 */
8767 gen_helper_neon_negl_u32(tcg_res, tcg_res);
8768 /* fall through */
8769 case 0x9: /* SQDMLAL, SQDMLAL2 */
8771 TCGv_i64 tcg_op3 = tcg_temp_new_i64();
8772 read_vec_element(s, tcg_op3, rd, 0, MO_32);
8773 gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env,
8774 tcg_res, tcg_op3);
8775 tcg_temp_free_i64(tcg_op3);
8776 break;
8778 default:
8779 g_assert_not_reached();
8782 tcg_gen_ext32u_i64(tcg_res, tcg_res);
8783 write_fp_dreg(s, rd, tcg_res);
8785 tcg_temp_free_i32(tcg_op1);
8786 tcg_temp_free_i32(tcg_op2);
8787 tcg_temp_free_i64(tcg_res);
8791 static void handle_3same_64(DisasContext *s, int opcode, bool u,
8792 TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
8794 /* Handle 64x64->64 opcodes which are shared between the scalar
8795 * and vector 3-same groups. We cover every opcode where size == 3
8796 * is valid in either the three-reg-same (integer, not pairwise)
8797 * or scalar-three-reg-same groups.
8799 TCGCond cond;
8801 switch (opcode) {
8802 case 0x1: /* SQADD */
8803 if (u) {
8804 gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8805 } else {
8806 gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8808 break;
8809 case 0x5: /* SQSUB */
8810 if (u) {
8811 gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8812 } else {
8813 gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8815 break;
8816 case 0x6: /* CMGT, CMHI */
8817 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8818 * We implement this using setcond (test) and then negating.
8820 cond = u ? TCG_COND_GTU : TCG_COND_GT;
8821 do_cmop:
8822 tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm);
8823 tcg_gen_neg_i64(tcg_rd, tcg_rd);
8824 break;
8825 case 0x7: /* CMGE, CMHS */
8826 cond = u ? TCG_COND_GEU : TCG_COND_GE;
8827 goto do_cmop;
8828 case 0x11: /* CMTST, CMEQ */
8829 if (u) {
8830 cond = TCG_COND_EQ;
8831 goto do_cmop;
8833 gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm);
8834 break;
8835 case 0x8: /* SSHL, USHL */
8836 if (u) {
8837 gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm);
8838 } else {
8839 gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm);
8841 break;
8842 case 0x9: /* SQSHL, UQSHL */
8843 if (u) {
8844 gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8845 } else {
8846 gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8848 break;
8849 case 0xa: /* SRSHL, URSHL */
8850 if (u) {
8851 gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm);
8852 } else {
8853 gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm);
8855 break;
8856 case 0xb: /* SQRSHL, UQRSHL */
8857 if (u) {
8858 gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8859 } else {
8860 gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8862 break;
8863 case 0x10: /* ADD, SUB */
8864 if (u) {
8865 tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm);
8866 } else {
8867 tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm);
8869 break;
8870 default:
8871 g_assert_not_reached();
8875 /* Handle the 3-same-operands float operations; shared by the scalar
8876 * and vector encodings. The caller must filter out any encodings
8877 * not allocated for the encoding it is dealing with.
8879 static void handle_3same_float(DisasContext *s, int size, int elements,
8880 int fpopcode, int rd, int rn, int rm)
8882 int pass;
8883 TCGv_ptr fpst = get_fpstatus_ptr(false);
8885 for (pass = 0; pass < elements; pass++) {
8886 if (size) {
8887 /* Double */
8888 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8889 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8890 TCGv_i64 tcg_res = tcg_temp_new_i64();
8892 read_vec_element(s, tcg_op1, rn, pass, MO_64);
8893 read_vec_element(s, tcg_op2, rm, pass, MO_64);
8895 switch (fpopcode) {
8896 case 0x39: /* FMLS */
8897 /* As usual for ARM, separate negation for fused multiply-add */
8898 gen_helper_vfp_negd(tcg_op1, tcg_op1);
8899 /* fall through */
8900 case 0x19: /* FMLA */
8901 read_vec_element(s, tcg_res, rd, pass, MO_64);
8902 gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2,
8903 tcg_res, fpst);
8904 break;
8905 case 0x18: /* FMAXNM */
8906 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
8907 break;
8908 case 0x1a: /* FADD */
8909 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
8910 break;
8911 case 0x1b: /* FMULX */
8912 gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst);
8913 break;
8914 case 0x1c: /* FCMEQ */
8915 gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8916 break;
8917 case 0x1e: /* FMAX */
8918 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
8919 break;
8920 case 0x1f: /* FRECPS */
8921 gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8922 break;
8923 case 0x38: /* FMINNM */
8924 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
8925 break;
8926 case 0x3a: /* FSUB */
8927 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
8928 break;
8929 case 0x3e: /* FMIN */
8930 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
8931 break;
8932 case 0x3f: /* FRSQRTS */
8933 gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8934 break;
8935 case 0x5b: /* FMUL */
8936 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
8937 break;
8938 case 0x5c: /* FCMGE */
8939 gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8940 break;
8941 case 0x5d: /* FACGE */
8942 gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8943 break;
8944 case 0x5f: /* FDIV */
8945 gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
8946 break;
8947 case 0x7a: /* FABD */
8948 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
8949 gen_helper_vfp_absd(tcg_res, tcg_res);
8950 break;
8951 case 0x7c: /* FCMGT */
8952 gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8953 break;
8954 case 0x7d: /* FACGT */
8955 gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8956 break;
8957 default:
8958 g_assert_not_reached();
8961 write_vec_element(s, tcg_res, rd, pass, MO_64);
8963 tcg_temp_free_i64(tcg_res);
8964 tcg_temp_free_i64(tcg_op1);
8965 tcg_temp_free_i64(tcg_op2);
8966 } else {
8967 /* Single */
8968 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
8969 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
8970 TCGv_i32 tcg_res = tcg_temp_new_i32();
8972 read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
8973 read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
8975 switch (fpopcode) {
8976 case 0x39: /* FMLS */
8977 /* As usual for ARM, separate negation for fused multiply-add */
8978 gen_helper_vfp_negs(tcg_op1, tcg_op1);
8979 /* fall through */
8980 case 0x19: /* FMLA */
8981 read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
8982 gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2,
8983 tcg_res, fpst);
8984 break;
8985 case 0x1a: /* FADD */
8986 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
8987 break;
8988 case 0x1b: /* FMULX */
8989 gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst);
8990 break;
8991 case 0x1c: /* FCMEQ */
8992 gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8993 break;
8994 case 0x1e: /* FMAX */
8995 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
8996 break;
8997 case 0x1f: /* FRECPS */
8998 gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8999 break;
9000 case 0x18: /* FMAXNM */
9001 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
9002 break;
9003 case 0x38: /* FMINNM */
9004 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
9005 break;
9006 case 0x3a: /* FSUB */
9007 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
9008 break;
9009 case 0x3e: /* FMIN */
9010 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
9011 break;
9012 case 0x3f: /* FRSQRTS */
9013 gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
9014 break;
9015 case 0x5b: /* FMUL */
9016 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
9017 break;
9018 case 0x5c: /* FCMGE */
9019 gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
9020 break;
9021 case 0x5d: /* FACGE */
9022 gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
9023 break;
9024 case 0x5f: /* FDIV */
9025 gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
9026 break;
9027 case 0x7a: /* FABD */
9028 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
9029 gen_helper_vfp_abss(tcg_res, tcg_res);
9030 break;
9031 case 0x7c: /* FCMGT */
9032 gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
9033 break;
9034 case 0x7d: /* FACGT */
9035 gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
9036 break;
9037 default:
9038 g_assert_not_reached();
9041 if (elements == 1) {
9042 /* scalar single so clear high part */
9043 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
9045 tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);
9046 write_vec_element(s, tcg_tmp, rd, pass, MO_64);
9047 tcg_temp_free_i64(tcg_tmp);
9048 } else {
9049 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
9052 tcg_temp_free_i32(tcg_res);
9053 tcg_temp_free_i32(tcg_op1);
9054 tcg_temp_free_i32(tcg_op2);
9058 tcg_temp_free_ptr(fpst);
9060 clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd);
9063 /* AdvSIMD scalar three same
9064 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9065 * +-----+---+-----------+------+---+------+--------+---+------+------+
9066 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9067 * +-----+---+-----------+------+---+------+--------+---+------+------+
9069 static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
9071 int rd = extract32(insn, 0, 5);
9072 int rn = extract32(insn, 5, 5);
9073 int opcode = extract32(insn, 11, 5);
9074 int rm = extract32(insn, 16, 5);
9075 int size = extract32(insn, 22, 2);
9076 bool u = extract32(insn, 29, 1);
9077 TCGv_i64 tcg_rd;
9079 if (opcode >= 0x18) {
9080 /* Floating point: U, size[1] and opcode indicate operation */
9081 int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6);
9082 switch (fpopcode) {
9083 case 0x1b: /* FMULX */
9084 case 0x1f: /* FRECPS */
9085 case 0x3f: /* FRSQRTS */
9086 case 0x5d: /* FACGE */
9087 case 0x7d: /* FACGT */
9088 case 0x1c: /* FCMEQ */
9089 case 0x5c: /* FCMGE */
9090 case 0x7c: /* FCMGT */
9091 case 0x7a: /* FABD */
9092 break;
9093 default:
9094 unallocated_encoding(s);
9095 return;
9098 if (!fp_access_check(s)) {
9099 return;
9102 handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm);
9103 return;
9106 switch (opcode) {
9107 case 0x1: /* SQADD, UQADD */
9108 case 0x5: /* SQSUB, UQSUB */
9109 case 0x9: /* SQSHL, UQSHL */
9110 case 0xb: /* SQRSHL, UQRSHL */
9111 break;
9112 case 0x8: /* SSHL, USHL */
9113 case 0xa: /* SRSHL, URSHL */
9114 case 0x6: /* CMGT, CMHI */
9115 case 0x7: /* CMGE, CMHS */
9116 case 0x11: /* CMTST, CMEQ */
9117 case 0x10: /* ADD, SUB (vector) */
9118 if (size != 3) {
9119 unallocated_encoding(s);
9120 return;
9122 break;
9123 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9124 if (size != 1 && size != 2) {
9125 unallocated_encoding(s);
9126 return;
9128 break;
9129 default:
9130 unallocated_encoding(s);
9131 return;
9134 if (!fp_access_check(s)) {
9135 return;
9138 tcg_rd = tcg_temp_new_i64();
9140 if (size == 3) {
9141 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
9142 TCGv_i64 tcg_rm = read_fp_dreg(s, rm);
9144 handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm);
9145 tcg_temp_free_i64(tcg_rn);
9146 tcg_temp_free_i64(tcg_rm);
9147 } else {
9148 /* Do a single operation on the lowest element in the vector.
9149 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9150 * no side effects for all these operations.
9151 * OPTME: special-purpose helpers would avoid doing some
9152 * unnecessary work in the helper for the 8 and 16 bit cases.
9154 NeonGenTwoOpEnvFn *genenvfn;
9155 TCGv_i32 tcg_rn = tcg_temp_new_i32();
9156 TCGv_i32 tcg_rm = tcg_temp_new_i32();
9157 TCGv_i32 tcg_rd32 = tcg_temp_new_i32();
9159 read_vec_element_i32(s, tcg_rn, rn, 0, size);
9160 read_vec_element_i32(s, tcg_rm, rm, 0, size);
9162 switch (opcode) {
9163 case 0x1: /* SQADD, UQADD */
9165 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9166 { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
9167 { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
9168 { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
9170 genenvfn = fns[size][u];
9171 break;
9173 case 0x5: /* SQSUB, UQSUB */
9175 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9176 { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
9177 { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
9178 { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
9180 genenvfn = fns[size][u];
9181 break;
9183 case 0x9: /* SQSHL, UQSHL */
9185 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9186 { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
9187 { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
9188 { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
9190 genenvfn = fns[size][u];
9191 break;
9193 case 0xb: /* SQRSHL, UQRSHL */
9195 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9196 { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
9197 { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
9198 { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
9200 genenvfn = fns[size][u];
9201 break;
9203 case 0x16: /* SQDMULH, SQRDMULH */
9205 static NeonGenTwoOpEnvFn * const fns[2][2] = {
9206 { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
9207 { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
9209 assert(size == 1 || size == 2);
9210 genenvfn = fns[size - 1][u];
9211 break;
9213 default:
9214 g_assert_not_reached();
9217 genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm);
9218 tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32);
9219 tcg_temp_free_i32(tcg_rd32);
9220 tcg_temp_free_i32(tcg_rn);
9221 tcg_temp_free_i32(tcg_rm);
9224 write_fp_dreg(s, rd, tcg_rd);
9226 tcg_temp_free_i64(tcg_rd);
9229 /* AdvSIMD scalar three same FP16
9230 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9231 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9232 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9233 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9234 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9235 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9237 static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
9238 uint32_t insn)
9240 int rd = extract32(insn, 0, 5);
9241 int rn = extract32(insn, 5, 5);
9242 int opcode = extract32(insn, 11, 3);
9243 int rm = extract32(insn, 16, 5);
9244 bool u = extract32(insn, 29, 1);
9245 bool a = extract32(insn, 23, 1);
9246 int fpopcode = opcode | (a << 3) | (u << 4);
9247 TCGv_ptr fpst;
9248 TCGv_i32 tcg_op1;
9249 TCGv_i32 tcg_op2;
9250 TCGv_i32 tcg_res;
9252 switch (fpopcode) {
9253 case 0x03: /* FMULX */
9254 case 0x04: /* FCMEQ (reg) */
9255 case 0x07: /* FRECPS */
9256 case 0x0f: /* FRSQRTS */
9257 case 0x14: /* FCMGE (reg) */
9258 case 0x15: /* FACGE */
9259 case 0x1a: /* FABD */
9260 case 0x1c: /* FCMGT (reg) */
9261 case 0x1d: /* FACGT */
9262 break;
9263 default:
9264 unallocated_encoding(s);
9265 return;
9268 if (!dc_isar_feature(aa64_fp16, s)) {
9269 unallocated_encoding(s);
9272 if (!fp_access_check(s)) {
9273 return;
9276 fpst = get_fpstatus_ptr(true);
9278 tcg_op1 = read_fp_hreg(s, rn);
9279 tcg_op2 = read_fp_hreg(s, rm);
9280 tcg_res = tcg_temp_new_i32();
9282 switch (fpopcode) {
9283 case 0x03: /* FMULX */
9284 gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
9285 break;
9286 case 0x04: /* FCMEQ (reg) */
9287 gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
9288 break;
9289 case 0x07: /* FRECPS */
9290 gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
9291 break;
9292 case 0x0f: /* FRSQRTS */
9293 gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
9294 break;
9295 case 0x14: /* FCMGE (reg) */
9296 gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
9297 break;
9298 case 0x15: /* FACGE */
9299 gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
9300 break;
9301 case 0x1a: /* FABD */
9302 gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
9303 tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
9304 break;
9305 case 0x1c: /* FCMGT (reg) */
9306 gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
9307 break;
9308 case 0x1d: /* FACGT */
9309 gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
9310 break;
9311 default:
9312 g_assert_not_reached();
9315 write_fp_sreg(s, rd, tcg_res);
9318 tcg_temp_free_i32(tcg_res);
9319 tcg_temp_free_i32(tcg_op1);
9320 tcg_temp_free_i32(tcg_op2);
9321 tcg_temp_free_ptr(fpst);
9324 /* AdvSIMD scalar three same extra
9325 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9326 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9327 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9328 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9330 static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
9331 uint32_t insn)
9333 int rd = extract32(insn, 0, 5);
9334 int rn = extract32(insn, 5, 5);
9335 int opcode = extract32(insn, 11, 4);
9336 int rm = extract32(insn, 16, 5);
9337 int size = extract32(insn, 22, 2);
9338 bool u = extract32(insn, 29, 1);
9339 TCGv_i32 ele1, ele2, ele3;
9340 TCGv_i64 res;
9341 bool feature;
9343 switch (u * 16 + opcode) {
9344 case 0x10: /* SQRDMLAH (vector) */
9345 case 0x11: /* SQRDMLSH (vector) */
9346 if (size != 1 && size != 2) {
9347 unallocated_encoding(s);
9348 return;
9350 feature = dc_isar_feature(aa64_rdm, s);
9351 break;
9352 default:
9353 unallocated_encoding(s);
9354 return;
9356 if (!feature) {
9357 unallocated_encoding(s);
9358 return;
9360 if (!fp_access_check(s)) {
9361 return;
9364 /* Do a single operation on the lowest element in the vector.
9365 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9366 * with no side effects for all these operations.
9367 * OPTME: special-purpose helpers would avoid doing some
9368 * unnecessary work in the helper for the 16 bit cases.
9370 ele1 = tcg_temp_new_i32();
9371 ele2 = tcg_temp_new_i32();
9372 ele3 = tcg_temp_new_i32();
9374 read_vec_element_i32(s, ele1, rn, 0, size);
9375 read_vec_element_i32(s, ele2, rm, 0, size);
9376 read_vec_element_i32(s, ele3, rd, 0, size);
9378 switch (opcode) {
9379 case 0x0: /* SQRDMLAH */
9380 if (size == 1) {
9381 gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3);
9382 } else {
9383 gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3);
9385 break;
9386 case 0x1: /* SQRDMLSH */
9387 if (size == 1) {
9388 gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3);
9389 } else {
9390 gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3);
9392 break;
9393 default:
9394 g_assert_not_reached();
9396 tcg_temp_free_i32(ele1);
9397 tcg_temp_free_i32(ele2);
9399 res = tcg_temp_new_i64();
9400 tcg_gen_extu_i32_i64(res, ele3);
9401 tcg_temp_free_i32(ele3);
9403 write_fp_dreg(s, rd, res);
9404 tcg_temp_free_i64(res);
9407 static void handle_2misc_64(DisasContext *s, int opcode, bool u,
9408 TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
9409 TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
9411 /* Handle 64->64 opcodes which are shared between the scalar and
9412 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9413 * is valid in either group and also the double-precision fp ops.
9414 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9415 * requires them.
9417 TCGCond cond;
9419 switch (opcode) {
9420 case 0x4: /* CLS, CLZ */
9421 if (u) {
9422 tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
9423 } else {
9424 tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
9426 break;
9427 case 0x5: /* NOT */
9428 /* This opcode is shared with CNT and RBIT but we have earlier
9429 * enforced that size == 3 if and only if this is the NOT insn.
9431 tcg_gen_not_i64(tcg_rd, tcg_rn);
9432 break;
9433 case 0x7: /* SQABS, SQNEG */
9434 if (u) {
9435 gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn);
9436 } else {
9437 gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn);
9439 break;
9440 case 0xa: /* CMLT */
9441 /* 64 bit integer comparison against zero, result is
9442 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9443 * subtracting 1.
9445 cond = TCG_COND_LT;
9446 do_cmop:
9447 tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0);
9448 tcg_gen_neg_i64(tcg_rd, tcg_rd);
9449 break;
9450 case 0x8: /* CMGT, CMGE */
9451 cond = u ? TCG_COND_GE : TCG_COND_GT;
9452 goto do_cmop;
9453 case 0x9: /* CMEQ, CMLE */
9454 cond = u ? TCG_COND_LE : TCG_COND_EQ;
9455 goto do_cmop;
9456 case 0xb: /* ABS, NEG */
9457 if (u) {
9458 tcg_gen_neg_i64(tcg_rd, tcg_rn);
9459 } else {
9460 tcg_gen_abs_i64(tcg_rd, tcg_rn);
9462 break;
9463 case 0x2f: /* FABS */
9464 gen_helper_vfp_absd(tcg_rd, tcg_rn);
9465 break;
9466 case 0x6f: /* FNEG */
9467 gen_helper_vfp_negd(tcg_rd, tcg_rn);
9468 break;
9469 case 0x7f: /* FSQRT */
9470 gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env);
9471 break;
9472 case 0x1a: /* FCVTNS */
9473 case 0x1b: /* FCVTMS */
9474 case 0x1c: /* FCVTAS */
9475 case 0x3a: /* FCVTPS */
9476 case 0x3b: /* FCVTZS */
9478 TCGv_i32 tcg_shift = tcg_const_i32(0);
9479 gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
9480 tcg_temp_free_i32(tcg_shift);
9481 break;
9483 case 0x5a: /* FCVTNU */
9484 case 0x5b: /* FCVTMU */
9485 case 0x5c: /* FCVTAU */
9486 case 0x7a: /* FCVTPU */
9487 case 0x7b: /* FCVTZU */
9489 TCGv_i32 tcg_shift = tcg_const_i32(0);
9490 gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
9491 tcg_temp_free_i32(tcg_shift);
9492 break;
9494 case 0x18: /* FRINTN */
9495 case 0x19: /* FRINTM */
9496 case 0x38: /* FRINTP */
9497 case 0x39: /* FRINTZ */
9498 case 0x58: /* FRINTA */
9499 case 0x79: /* FRINTI */
9500 gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus);
9501 break;
9502 case 0x59: /* FRINTX */
9503 gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus);
9504 break;
9505 case 0x1e: /* FRINT32Z */
9506 case 0x5e: /* FRINT32X */
9507 gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus);
9508 break;
9509 case 0x1f: /* FRINT64Z */
9510 case 0x5f: /* FRINT64X */
9511 gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus);
9512 break;
9513 default:
9514 g_assert_not_reached();
9518 static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
9519 bool is_scalar, bool is_u, bool is_q,
9520 int size, int rn, int rd)
9522 bool is_double = (size == MO_64);
9523 TCGv_ptr fpst;
9525 if (!fp_access_check(s)) {
9526 return;
9529 fpst = get_fpstatus_ptr(size == MO_16);
9531 if (is_double) {
9532 TCGv_i64 tcg_op = tcg_temp_new_i64();
9533 TCGv_i64 tcg_zero = tcg_const_i64(0);
9534 TCGv_i64 tcg_res = tcg_temp_new_i64();
9535 NeonGenTwoDoubleOPFn *genfn;
9536 bool swap = false;
9537 int pass;
9539 switch (opcode) {
9540 case 0x2e: /* FCMLT (zero) */
9541 swap = true;
9542 /* fallthrough */
9543 case 0x2c: /* FCMGT (zero) */
9544 genfn = gen_helper_neon_cgt_f64;
9545 break;
9546 case 0x2d: /* FCMEQ (zero) */
9547 genfn = gen_helper_neon_ceq_f64;
9548 break;
9549 case 0x6d: /* FCMLE (zero) */
9550 swap = true;
9551 /* fall through */
9552 case 0x6c: /* FCMGE (zero) */
9553 genfn = gen_helper_neon_cge_f64;
9554 break;
9555 default:
9556 g_assert_not_reached();
9559 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
9560 read_vec_element(s, tcg_op, rn, pass, MO_64);
9561 if (swap) {
9562 genfn(tcg_res, tcg_zero, tcg_op, fpst);
9563 } else {
9564 genfn(tcg_res, tcg_op, tcg_zero, fpst);
9566 write_vec_element(s, tcg_res, rd, pass, MO_64);
9568 tcg_temp_free_i64(tcg_res);
9569 tcg_temp_free_i64(tcg_zero);
9570 tcg_temp_free_i64(tcg_op);
9572 clear_vec_high(s, !is_scalar, rd);
9573 } else {
9574 TCGv_i32 tcg_op = tcg_temp_new_i32();
9575 TCGv_i32 tcg_zero = tcg_const_i32(0);
9576 TCGv_i32 tcg_res = tcg_temp_new_i32();
9577 NeonGenTwoSingleOPFn *genfn;
9578 bool swap = false;
9579 int pass, maxpasses;
9581 if (size == MO_16) {
9582 switch (opcode) {
9583 case 0x2e: /* FCMLT (zero) */
9584 swap = true;
9585 /* fall through */
9586 case 0x2c: /* FCMGT (zero) */
9587 genfn = gen_helper_advsimd_cgt_f16;
9588 break;
9589 case 0x2d: /* FCMEQ (zero) */
9590 genfn = gen_helper_advsimd_ceq_f16;
9591 break;
9592 case 0x6d: /* FCMLE (zero) */
9593 swap = true;
9594 /* fall through */
9595 case 0x6c: /* FCMGE (zero) */
9596 genfn = gen_helper_advsimd_cge_f16;
9597 break;
9598 default:
9599 g_assert_not_reached();
9601 } else {
9602 switch (opcode) {
9603 case 0x2e: /* FCMLT (zero) */
9604 swap = true;
9605 /* fall through */
9606 case 0x2c: /* FCMGT (zero) */
9607 genfn = gen_helper_neon_cgt_f32;
9608 break;
9609 case 0x2d: /* FCMEQ (zero) */
9610 genfn = gen_helper_neon_ceq_f32;
9611 break;
9612 case 0x6d: /* FCMLE (zero) */
9613 swap = true;
9614 /* fall through */
9615 case 0x6c: /* FCMGE (zero) */
9616 genfn = gen_helper_neon_cge_f32;
9617 break;
9618 default:
9619 g_assert_not_reached();
9623 if (is_scalar) {
9624 maxpasses = 1;
9625 } else {
9626 int vector_size = 8 << is_q;
9627 maxpasses = vector_size >> size;
9630 for (pass = 0; pass < maxpasses; pass++) {
9631 read_vec_element_i32(s, tcg_op, rn, pass, size);
9632 if (swap) {
9633 genfn(tcg_res, tcg_zero, tcg_op, fpst);
9634 } else {
9635 genfn(tcg_res, tcg_op, tcg_zero, fpst);
9637 if (is_scalar) {
9638 write_fp_sreg(s, rd, tcg_res);
9639 } else {
9640 write_vec_element_i32(s, tcg_res, rd, pass, size);
9643 tcg_temp_free_i32(tcg_res);
9644 tcg_temp_free_i32(tcg_zero);
9645 tcg_temp_free_i32(tcg_op);
9646 if (!is_scalar) {
9647 clear_vec_high(s, is_q, rd);
9651 tcg_temp_free_ptr(fpst);
9654 static void handle_2misc_reciprocal(DisasContext *s, int opcode,
9655 bool is_scalar, bool is_u, bool is_q,
9656 int size, int rn, int rd)
9658 bool is_double = (size == 3);
9659 TCGv_ptr fpst = get_fpstatus_ptr(false);
9661 if (is_double) {
9662 TCGv_i64 tcg_op = tcg_temp_new_i64();
9663 TCGv_i64 tcg_res = tcg_temp_new_i64();
9664 int pass;
9666 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
9667 read_vec_element(s, tcg_op, rn, pass, MO_64);
9668 switch (opcode) {
9669 case 0x3d: /* FRECPE */
9670 gen_helper_recpe_f64(tcg_res, tcg_op, fpst);
9671 break;
9672 case 0x3f: /* FRECPX */
9673 gen_helper_frecpx_f64(tcg_res, tcg_op, fpst);
9674 break;
9675 case 0x7d: /* FRSQRTE */
9676 gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst);
9677 break;
9678 default:
9679 g_assert_not_reached();
9681 write_vec_element(s, tcg_res, rd, pass, MO_64);
9683 tcg_temp_free_i64(tcg_res);
9684 tcg_temp_free_i64(tcg_op);
9685 clear_vec_high(s, !is_scalar, rd);
9686 } else {
9687 TCGv_i32 tcg_op = tcg_temp_new_i32();
9688 TCGv_i32 tcg_res = tcg_temp_new_i32();
9689 int pass, maxpasses;
9691 if (is_scalar) {
9692 maxpasses = 1;
9693 } else {
9694 maxpasses = is_q ? 4 : 2;
9697 for (pass = 0; pass < maxpasses; pass++) {
9698 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
9700 switch (opcode) {
9701 case 0x3c: /* URECPE */
9702 gen_helper_recpe_u32(tcg_res, tcg_op, fpst);
9703 break;
9704 case 0x3d: /* FRECPE */
9705 gen_helper_recpe_f32(tcg_res, tcg_op, fpst);
9706 break;
9707 case 0x3f: /* FRECPX */
9708 gen_helper_frecpx_f32(tcg_res, tcg_op, fpst);
9709 break;
9710 case 0x7d: /* FRSQRTE */
9711 gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst);
9712 break;
9713 default:
9714 g_assert_not_reached();
9717 if (is_scalar) {
9718 write_fp_sreg(s, rd, tcg_res);
9719 } else {
9720 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
9723 tcg_temp_free_i32(tcg_res);
9724 tcg_temp_free_i32(tcg_op);
9725 if (!is_scalar) {
9726 clear_vec_high(s, is_q, rd);
9729 tcg_temp_free_ptr(fpst);
9732 static void handle_2misc_narrow(DisasContext *s, bool scalar,
9733 int opcode, bool u, bool is_q,
9734 int size, int rn, int rd)
9736 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9737 * in the source becomes a size element in the destination).
9739 int pass;
9740 TCGv_i32 tcg_res[2];
9741 int destelt = is_q ? 2 : 0;
9742 int passes = scalar ? 1 : 2;
9744 if (scalar) {
9745 tcg_res[1] = tcg_const_i32(0);
9748 for (pass = 0; pass < passes; pass++) {
9749 TCGv_i64 tcg_op = tcg_temp_new_i64();
9750 NeonGenNarrowFn *genfn = NULL;
9751 NeonGenNarrowEnvFn *genenvfn = NULL;
9753 if (scalar) {
9754 read_vec_element(s, tcg_op, rn, pass, size + 1);
9755 } else {
9756 read_vec_element(s, tcg_op, rn, pass, MO_64);
9758 tcg_res[pass] = tcg_temp_new_i32();
9760 switch (opcode) {
9761 case 0x12: /* XTN, SQXTUN */
9763 static NeonGenNarrowFn * const xtnfns[3] = {
9764 gen_helper_neon_narrow_u8,
9765 gen_helper_neon_narrow_u16,
9766 tcg_gen_extrl_i64_i32,
9768 static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
9769 gen_helper_neon_unarrow_sat8,
9770 gen_helper_neon_unarrow_sat16,
9771 gen_helper_neon_unarrow_sat32,
9773 if (u) {
9774 genenvfn = sqxtunfns[size];
9775 } else {
9776 genfn = xtnfns[size];
9778 break;
9780 case 0x14: /* SQXTN, UQXTN */
9782 static NeonGenNarrowEnvFn * const fns[3][2] = {
9783 { gen_helper_neon_narrow_sat_s8,
9784 gen_helper_neon_narrow_sat_u8 },
9785 { gen_helper_neon_narrow_sat_s16,
9786 gen_helper_neon_narrow_sat_u16 },
9787 { gen_helper_neon_narrow_sat_s32,
9788 gen_helper_neon_narrow_sat_u32 },
9790 genenvfn = fns[size][u];
9791 break;
9793 case 0x16: /* FCVTN, FCVTN2 */
9794 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9795 if (size == 2) {
9796 gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
9797 } else {
9798 TCGv_i32 tcg_lo = tcg_temp_new_i32();
9799 TCGv_i32 tcg_hi = tcg_temp_new_i32();
9800 TCGv_ptr fpst = get_fpstatus_ptr(false);
9801 TCGv_i32 ahp = get_ahp_flag();
9803 tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op);
9804 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp);
9805 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp);
9806 tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
9807 tcg_temp_free_i32(tcg_lo);
9808 tcg_temp_free_i32(tcg_hi);
9809 tcg_temp_free_ptr(fpst);
9810 tcg_temp_free_i32(ahp);
9812 break;
9813 case 0x56: /* FCVTXN, FCVTXN2 */
9814 /* 64 bit to 32 bit float conversion
9815 * with von Neumann rounding (round to odd)
9817 assert(size == 2);
9818 gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env);
9819 break;
9820 default:
9821 g_assert_not_reached();
9824 if (genfn) {
9825 genfn(tcg_res[pass], tcg_op);
9826 } else if (genenvfn) {
9827 genenvfn(tcg_res[pass], cpu_env, tcg_op);
9830 tcg_temp_free_i64(tcg_op);
9833 for (pass = 0; pass < 2; pass++) {
9834 write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);
9835 tcg_temp_free_i32(tcg_res[pass]);
9837 clear_vec_high(s, is_q, rd);
9840 /* Remaining saturating accumulating ops */
9841 static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
9842 bool is_q, int size, int rn, int rd)
9844 bool is_double = (size == 3);
9846 if (is_double) {
9847 TCGv_i64 tcg_rn = tcg_temp_new_i64();
9848 TCGv_i64 tcg_rd = tcg_temp_new_i64();
9849 int pass;
9851 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
9852 read_vec_element(s, tcg_rn, rn, pass, MO_64);
9853 read_vec_element(s, tcg_rd, rd, pass, MO_64);
9855 if (is_u) { /* USQADD */
9856 gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9857 } else { /* SUQADD */
9858 gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9860 write_vec_element(s, tcg_rd, rd, pass, MO_64);
9862 tcg_temp_free_i64(tcg_rd);
9863 tcg_temp_free_i64(tcg_rn);
9864 clear_vec_high(s, !is_scalar, rd);
9865 } else {
9866 TCGv_i32 tcg_rn = tcg_temp_new_i32();
9867 TCGv_i32 tcg_rd = tcg_temp_new_i32();
9868 int pass, maxpasses;
9870 if (is_scalar) {
9871 maxpasses = 1;
9872 } else {
9873 maxpasses = is_q ? 4 : 2;
9876 for (pass = 0; pass < maxpasses; pass++) {
9877 if (is_scalar) {
9878 read_vec_element_i32(s, tcg_rn, rn, pass, size);
9879 read_vec_element_i32(s, tcg_rd, rd, pass, size);
9880 } else {
9881 read_vec_element_i32(s, tcg_rn, rn, pass, MO_32);
9882 read_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
9885 if (is_u) { /* USQADD */
9886 switch (size) {
9887 case 0:
9888 gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9889 break;
9890 case 1:
9891 gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9892 break;
9893 case 2:
9894 gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9895 break;
9896 default:
9897 g_assert_not_reached();
9899 } else { /* SUQADD */
9900 switch (size) {
9901 case 0:
9902 gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9903 break;
9904 case 1:
9905 gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9906 break;
9907 case 2:
9908 gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9909 break;
9910 default:
9911 g_assert_not_reached();
9915 if (is_scalar) {
9916 TCGv_i64 tcg_zero = tcg_const_i64(0);
9917 write_vec_element(s, tcg_zero, rd, 0, MO_64);
9918 tcg_temp_free_i64(tcg_zero);
9920 write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
9922 tcg_temp_free_i32(tcg_rd);
9923 tcg_temp_free_i32(tcg_rn);
9924 clear_vec_high(s, is_q, rd);
9928 /* AdvSIMD scalar two reg misc
9929 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9930 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9931 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9932 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9934 static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
9936 int rd = extract32(insn, 0, 5);
9937 int rn = extract32(insn, 5, 5);
9938 int opcode = extract32(insn, 12, 5);
9939 int size = extract32(insn, 22, 2);
9940 bool u = extract32(insn, 29, 1);
9941 bool is_fcvt = false;
9942 int rmode;
9943 TCGv_i32 tcg_rmode;
9944 TCGv_ptr tcg_fpstatus;
9946 switch (opcode) {
9947 case 0x3: /* USQADD / SUQADD*/
9948 if (!fp_access_check(s)) {
9949 return;
9951 handle_2misc_satacc(s, true, u, false, size, rn, rd);
9952 return;
9953 case 0x7: /* SQABS / SQNEG */
9954 break;
9955 case 0xa: /* CMLT */
9956 if (u) {
9957 unallocated_encoding(s);
9958 return;
9960 /* fall through */
9961 case 0x8: /* CMGT, CMGE */
9962 case 0x9: /* CMEQ, CMLE */
9963 case 0xb: /* ABS, NEG */
9964 if (size != 3) {
9965 unallocated_encoding(s);
9966 return;
9968 break;
9969 case 0x12: /* SQXTUN */
9970 if (!u) {
9971 unallocated_encoding(s);
9972 return;
9974 /* fall through */
9975 case 0x14: /* SQXTN, UQXTN */
9976 if (size == 3) {
9977 unallocated_encoding(s);
9978 return;
9980 if (!fp_access_check(s)) {
9981 return;
9983 handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
9984 return;
9985 case 0xc ... 0xf:
9986 case 0x16 ... 0x1d:
9987 case 0x1f:
9988 /* Floating point: U, size[1] and opcode indicate operation;
9989 * size[0] indicates single or double precision.
9991 opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
9992 size = extract32(size, 0, 1) ? 3 : 2;
9993 switch (opcode) {
9994 case 0x2c: /* FCMGT (zero) */
9995 case 0x2d: /* FCMEQ (zero) */
9996 case 0x2e: /* FCMLT (zero) */
9997 case 0x6c: /* FCMGE (zero) */
9998 case 0x6d: /* FCMLE (zero) */
9999 handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
10000 return;
10001 case 0x1d: /* SCVTF */
10002 case 0x5d: /* UCVTF */
10004 bool is_signed = (opcode == 0x1d);
10005 if (!fp_access_check(s)) {
10006 return;
10008 handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size);
10009 return;
10011 case 0x3d: /* FRECPE */
10012 case 0x3f: /* FRECPX */
10013 case 0x7d: /* FRSQRTE */
10014 if (!fp_access_check(s)) {
10015 return;
10017 handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd);
10018 return;
10019 case 0x1a: /* FCVTNS */
10020 case 0x1b: /* FCVTMS */
10021 case 0x3a: /* FCVTPS */
10022 case 0x3b: /* FCVTZS */
10023 case 0x5a: /* FCVTNU */
10024 case 0x5b: /* FCVTMU */
10025 case 0x7a: /* FCVTPU */
10026 case 0x7b: /* FCVTZU */
10027 is_fcvt = true;
10028 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
10029 break;
10030 case 0x1c: /* FCVTAS */
10031 case 0x5c: /* FCVTAU */
10032 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10033 is_fcvt = true;
10034 rmode = FPROUNDING_TIEAWAY;
10035 break;
10036 case 0x56: /* FCVTXN, FCVTXN2 */
10037 if (size == 2) {
10038 unallocated_encoding(s);
10039 return;
10041 if (!fp_access_check(s)) {
10042 return;
10044 handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd);
10045 return;
10046 default:
10047 unallocated_encoding(s);
10048 return;
10050 break;
10051 default:
10052 unallocated_encoding(s);
10053 return;
10056 if (!fp_access_check(s)) {
10057 return;
10060 if (is_fcvt) {
10061 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
10062 tcg_fpstatus = get_fpstatus_ptr(false);
10063 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
10064 } else {
10065 tcg_rmode = NULL;
10066 tcg_fpstatus = NULL;
10069 if (size == 3) {
10070 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
10071 TCGv_i64 tcg_rd = tcg_temp_new_i64();
10073 handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
10074 write_fp_dreg(s, rd, tcg_rd);
10075 tcg_temp_free_i64(tcg_rd);
10076 tcg_temp_free_i64(tcg_rn);
10077 } else {
10078 TCGv_i32 tcg_rn = tcg_temp_new_i32();
10079 TCGv_i32 tcg_rd = tcg_temp_new_i32();
10081 read_vec_element_i32(s, tcg_rn, rn, 0, size);
10083 switch (opcode) {
10084 case 0x7: /* SQABS, SQNEG */
10086 NeonGenOneOpEnvFn *genfn;
10087 static NeonGenOneOpEnvFn * const fns[3][2] = {
10088 { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
10089 { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
10090 { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
10092 genfn = fns[size][u];
10093 genfn(tcg_rd, cpu_env, tcg_rn);
10094 break;
10096 case 0x1a: /* FCVTNS */
10097 case 0x1b: /* FCVTMS */
10098 case 0x1c: /* FCVTAS */
10099 case 0x3a: /* FCVTPS */
10100 case 0x3b: /* FCVTZS */
10102 TCGv_i32 tcg_shift = tcg_const_i32(0);
10103 gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
10104 tcg_temp_free_i32(tcg_shift);
10105 break;
10107 case 0x5a: /* FCVTNU */
10108 case 0x5b: /* FCVTMU */
10109 case 0x5c: /* FCVTAU */
10110 case 0x7a: /* FCVTPU */
10111 case 0x7b: /* FCVTZU */
10113 TCGv_i32 tcg_shift = tcg_const_i32(0);
10114 gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
10115 tcg_temp_free_i32(tcg_shift);
10116 break;
10118 default:
10119 g_assert_not_reached();
10122 write_fp_sreg(s, rd, tcg_rd);
10123 tcg_temp_free_i32(tcg_rd);
10124 tcg_temp_free_i32(tcg_rn);
10127 if (is_fcvt) {
10128 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
10129 tcg_temp_free_i32(tcg_rmode);
10130 tcg_temp_free_ptr(tcg_fpstatus);
10134 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10135 static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
10136 int immh, int immb, int opcode, int rn, int rd)
10138 int size = 32 - clz32(immh) - 1;
10139 int immhb = immh << 3 | immb;
10140 int shift = 2 * (8 << size) - immhb;
10141 GVecGen2iFn *gvec_fn;
10143 if (extract32(immh, 3, 1) && !is_q) {
10144 unallocated_encoding(s);
10145 return;
10147 tcg_debug_assert(size <= 3);
10149 if (!fp_access_check(s)) {
10150 return;
10153 switch (opcode) {
10154 case 0x02: /* SSRA / USRA (accumulate) */
10155 gvec_fn = is_u ? gen_gvec_usra : gen_gvec_ssra;
10156 break;
10158 case 0x08: /* SRI */
10159 gvec_fn = gen_gvec_sri;
10160 break;
10162 case 0x00: /* SSHR / USHR */
10163 if (is_u) {
10164 if (shift == 8 << size) {
10165 /* Shift count the same size as element size produces zero. */
10166 tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd),
10167 is_q ? 16 : 8, vec_full_reg_size(s), 0);
10168 return;
10170 gvec_fn = tcg_gen_gvec_shri;
10171 } else {
10172 /* Shift count the same size as element size produces all sign. */
10173 if (shift == 8 << size) {
10174 shift -= 1;
10176 gvec_fn = tcg_gen_gvec_sari;
10178 break;
10180 case 0x04: /* SRSHR / URSHR (rounding) */
10181 gvec_fn = is_u ? gen_gvec_urshr : gen_gvec_srshr;
10182 break;
10184 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10185 gvec_fn = is_u ? gen_gvec_ursra : gen_gvec_srsra;
10186 break;
10188 default:
10189 g_assert_not_reached();
10192 gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn, size);
10195 /* SHL/SLI - Vector shift left */
10196 static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
10197 int immh, int immb, int opcode, int rn, int rd)
10199 int size = 32 - clz32(immh) - 1;
10200 int immhb = immh << 3 | immb;
10201 int shift = immhb - (8 << size);
10203 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10204 assert(size >= 0 && size <= 3);
10206 if (extract32(immh, 3, 1) && !is_q) {
10207 unallocated_encoding(s);
10208 return;
10211 if (!fp_access_check(s)) {
10212 return;
10215 if (insert) {
10216 gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sli, size);
10217 } else {
10218 gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size);
10222 /* USHLL/SHLL - Vector shift left with widening */
10223 static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
10224 int immh, int immb, int opcode, int rn, int rd)
10226 int size = 32 - clz32(immh) - 1;
10227 int immhb = immh << 3 | immb;
10228 int shift = immhb - (8 << size);
10229 int dsize = 64;
10230 int esize = 8 << size;
10231 int elements = dsize/esize;
10232 TCGv_i64 tcg_rn = new_tmp_a64(s);
10233 TCGv_i64 tcg_rd = new_tmp_a64(s);
10234 int i;
10236 if (size >= 3) {
10237 unallocated_encoding(s);
10238 return;
10241 if (!fp_access_check(s)) {
10242 return;
10245 /* For the LL variants the store is larger than the load,
10246 * so if rd == rn we would overwrite parts of our input.
10247 * So load everything right now and use shifts in the main loop.
10249 read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);
10251 for (i = 0; i < elements; i++) {
10252 tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);
10253 ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0);
10254 tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
10255 write_vec_element(s, tcg_rd, rd, i, size + 1);
10259 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10260 static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
10261 int immh, int immb, int opcode, int rn, int rd)
10263 int immhb = immh << 3 | immb;
10264 int size = 32 - clz32(immh) - 1;
10265 int dsize = 64;
10266 int esize = 8 << size;
10267 int elements = dsize/esize;
10268 int shift = (2 * esize) - immhb;
10269 bool round = extract32(opcode, 0, 1);
10270 TCGv_i64 tcg_rn, tcg_rd, tcg_final;
10271 TCGv_i64 tcg_round;
10272 int i;
10274 if (extract32(immh, 3, 1)) {
10275 unallocated_encoding(s);
10276 return;
10279 if (!fp_access_check(s)) {
10280 return;
10283 tcg_rn = tcg_temp_new_i64();
10284 tcg_rd = tcg_temp_new_i64();
10285 tcg_final = tcg_temp_new_i64();
10286 read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
10288 if (round) {
10289 uint64_t round_const = 1ULL << (shift - 1);
10290 tcg_round = tcg_const_i64(round_const);
10291 } else {
10292 tcg_round = NULL;
10295 for (i = 0; i < elements; i++) {
10296 read_vec_element(s, tcg_rn, rn, i, size+1);
10297 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
10298 false, true, size+1, shift);
10300 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
10303 if (!is_q) {
10304 write_vec_element(s, tcg_final, rd, 0, MO_64);
10305 } else {
10306 write_vec_element(s, tcg_final, rd, 1, MO_64);
10308 if (round) {
10309 tcg_temp_free_i64(tcg_round);
10311 tcg_temp_free_i64(tcg_rn);
10312 tcg_temp_free_i64(tcg_rd);
10313 tcg_temp_free_i64(tcg_final);
10315 clear_vec_high(s, is_q, rd);
10319 /* AdvSIMD shift by immediate
10320 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10321 * +---+---+---+-------------+------+------+--------+---+------+------+
10322 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10323 * +---+---+---+-------------+------+------+--------+---+------+------+
10325 static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
10327 int rd = extract32(insn, 0, 5);
10328 int rn = extract32(insn, 5, 5);
10329 int opcode = extract32(insn, 11, 5);
10330 int immb = extract32(insn, 16, 3);
10331 int immh = extract32(insn, 19, 4);
10332 bool is_u = extract32(insn, 29, 1);
10333 bool is_q = extract32(insn, 30, 1);
10335 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10336 assert(immh != 0);
10338 switch (opcode) {
10339 case 0x08: /* SRI */
10340 if (!is_u) {
10341 unallocated_encoding(s);
10342 return;
10344 /* fall through */
10345 case 0x00: /* SSHR / USHR */
10346 case 0x02: /* SSRA / USRA (accumulate) */
10347 case 0x04: /* SRSHR / URSHR (rounding) */
10348 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10349 handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd);
10350 break;
10351 case 0x0a: /* SHL / SLI */
10352 handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd);
10353 break;
10354 case 0x10: /* SHRN */
10355 case 0x11: /* RSHRN / SQRSHRUN */
10356 if (is_u) {
10357 handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb,
10358 opcode, rn, rd);
10359 } else {
10360 handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd);
10362 break;
10363 case 0x12: /* SQSHRN / UQSHRN */
10364 case 0x13: /* SQRSHRN / UQRSHRN */
10365 handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb,
10366 opcode, rn, rd);
10367 break;
10368 case 0x14: /* SSHLL / USHLL */
10369 handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd);
10370 break;
10371 case 0x1c: /* SCVTF / UCVTF */
10372 handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
10373 opcode, rn, rd);
10374 break;
10375 case 0xc: /* SQSHLU */
10376 if (!is_u) {
10377 unallocated_encoding(s);
10378 return;
10380 handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd);
10381 break;
10382 case 0xe: /* SQSHL, UQSHL */
10383 handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd);
10384 break;
10385 case 0x1f: /* FCVTZS/ FCVTZU */
10386 handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd);
10387 return;
10388 default:
10389 unallocated_encoding(s);
10390 return;
10394 /* Generate code to do a "long" addition or subtraction, ie one done in
10395 * TCGv_i64 on vector lanes twice the width specified by size.
10397 static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res,
10398 TCGv_i64 tcg_op1, TCGv_i64 tcg_op2)
10400 static NeonGenTwo64OpFn * const fns[3][2] = {
10401 { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 },
10402 { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 },
10403 { tcg_gen_add_i64, tcg_gen_sub_i64 },
10405 NeonGenTwo64OpFn *genfn;
10406 assert(size < 3);
10408 genfn = fns[size][is_sub];
10409 genfn(tcg_res, tcg_op1, tcg_op2);
10412 static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
10413 int opcode, int rd, int rn, int rm)
10415 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10416 TCGv_i64 tcg_res[2];
10417 int pass, accop;
10419 tcg_res[0] = tcg_temp_new_i64();
10420 tcg_res[1] = tcg_temp_new_i64();
10422 /* Does this op do an adding accumulate, a subtracting accumulate,
10423 * or no accumulate at all?
10425 switch (opcode) {
10426 case 5:
10427 case 8:
10428 case 9:
10429 accop = 1;
10430 break;
10431 case 10:
10432 case 11:
10433 accop = -1;
10434 break;
10435 default:
10436 accop = 0;
10437 break;
10440 if (accop != 0) {
10441 read_vec_element(s, tcg_res[0], rd, 0, MO_64);
10442 read_vec_element(s, tcg_res[1], rd, 1, MO_64);
10445 /* size == 2 means two 32x32->64 operations; this is worth special
10446 * casing because we can generally handle it inline.
10448 if (size == 2) {
10449 for (pass = 0; pass < 2; pass++) {
10450 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10451 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
10452 TCGv_i64 tcg_passres;
10453 MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
10455 int elt = pass + is_q * 2;
10457 read_vec_element(s, tcg_op1, rn, elt, memop);
10458 read_vec_element(s, tcg_op2, rm, elt, memop);
10460 if (accop == 0) {
10461 tcg_passres = tcg_res[pass];
10462 } else {
10463 tcg_passres = tcg_temp_new_i64();
10466 switch (opcode) {
10467 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10468 tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2);
10469 break;
10470 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10471 tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2);
10472 break;
10473 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10474 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10476 TCGv_i64 tcg_tmp1 = tcg_temp_new_i64();
10477 TCGv_i64 tcg_tmp2 = tcg_temp_new_i64();
10479 tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2);
10480 tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1);
10481 tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
10482 tcg_passres,
10483 tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
10484 tcg_temp_free_i64(tcg_tmp1);
10485 tcg_temp_free_i64(tcg_tmp2);
10486 break;
10488 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10489 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10490 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10491 tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
10492 break;
10493 case 9: /* SQDMLAL, SQDMLAL2 */
10494 case 11: /* SQDMLSL, SQDMLSL2 */
10495 case 13: /* SQDMULL, SQDMULL2 */
10496 tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
10497 gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
10498 tcg_passres, tcg_passres);
10499 break;
10500 default:
10501 g_assert_not_reached();
10504 if (opcode == 9 || opcode == 11) {
10505 /* saturating accumulate ops */
10506 if (accop < 0) {
10507 tcg_gen_neg_i64(tcg_passres, tcg_passres);
10509 gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
10510 tcg_res[pass], tcg_passres);
10511 } else if (accop > 0) {
10512 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
10513 } else if (accop < 0) {
10514 tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
10517 if (accop != 0) {
10518 tcg_temp_free_i64(tcg_passres);
10521 tcg_temp_free_i64(tcg_op1);
10522 tcg_temp_free_i64(tcg_op2);
10524 } else {
10525 /* size 0 or 1, generally helper functions */
10526 for (pass = 0; pass < 2; pass++) {
10527 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
10528 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
10529 TCGv_i64 tcg_passres;
10530 int elt = pass + is_q * 2;
10532 read_vec_element_i32(s, tcg_op1, rn, elt, MO_32);
10533 read_vec_element_i32(s, tcg_op2, rm, elt, MO_32);
10535 if (accop == 0) {
10536 tcg_passres = tcg_res[pass];
10537 } else {
10538 tcg_passres = tcg_temp_new_i64();
10541 switch (opcode) {
10542 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10543 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10545 TCGv_i64 tcg_op2_64 = tcg_temp_new_i64();
10546 static NeonGenWidenFn * const widenfns[2][2] = {
10547 { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
10548 { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
10550 NeonGenWidenFn *widenfn = widenfns[size][is_u];
10552 widenfn(tcg_op2_64, tcg_op2);
10553 widenfn(tcg_passres, tcg_op1);
10554 gen_neon_addl(size, (opcode == 2), tcg_passres,
10555 tcg_passres, tcg_op2_64);
10556 tcg_temp_free_i64(tcg_op2_64);
10557 break;
10559 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10560 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10561 if (size == 0) {
10562 if (is_u) {
10563 gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2);
10564 } else {
10565 gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2);
10567 } else {
10568 if (is_u) {
10569 gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2);
10570 } else {
10571 gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2);
10574 break;
10575 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10576 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10577 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10578 if (size == 0) {
10579 if (is_u) {
10580 gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2);
10581 } else {
10582 gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2);
10584 } else {
10585 if (is_u) {
10586 gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2);
10587 } else {
10588 gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
10591 break;
10592 case 9: /* SQDMLAL, SQDMLAL2 */
10593 case 11: /* SQDMLSL, SQDMLSL2 */
10594 case 13: /* SQDMULL, SQDMULL2 */
10595 assert(size == 1);
10596 gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
10597 gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
10598 tcg_passres, tcg_passres);
10599 break;
10600 default:
10601 g_assert_not_reached();
10603 tcg_temp_free_i32(tcg_op1);
10604 tcg_temp_free_i32(tcg_op2);
10606 if (accop != 0) {
10607 if (opcode == 9 || opcode == 11) {
10608 /* saturating accumulate ops */
10609 if (accop < 0) {
10610 gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
10612 gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
10613 tcg_res[pass],
10614 tcg_passres);
10615 } else {
10616 gen_neon_addl(size, (accop < 0), tcg_res[pass],
10617 tcg_res[pass], tcg_passres);
10619 tcg_temp_free_i64(tcg_passres);
10624 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
10625 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
10626 tcg_temp_free_i64(tcg_res[0]);
10627 tcg_temp_free_i64(tcg_res[1]);
10630 static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
10631 int opcode, int rd, int rn, int rm)
10633 TCGv_i64 tcg_res[2];
10634 int part = is_q ? 2 : 0;
10635 int pass;
10637 for (pass = 0; pass < 2; pass++) {
10638 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10639 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
10640 TCGv_i64 tcg_op2_wide = tcg_temp_new_i64();
10641 static NeonGenWidenFn * const widenfns[3][2] = {
10642 { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
10643 { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
10644 { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 },
10646 NeonGenWidenFn *widenfn = widenfns[size][is_u];
10648 read_vec_element(s, tcg_op1, rn, pass, MO_64);
10649 read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32);
10650 widenfn(tcg_op2_wide, tcg_op2);
10651 tcg_temp_free_i32(tcg_op2);
10652 tcg_res[pass] = tcg_temp_new_i64();
10653 gen_neon_addl(size, (opcode == 3),
10654 tcg_res[pass], tcg_op1, tcg_op2_wide);
10655 tcg_temp_free_i64(tcg_op1);
10656 tcg_temp_free_i64(tcg_op2_wide);
10659 for (pass = 0; pass < 2; pass++) {
10660 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10661 tcg_temp_free_i64(tcg_res[pass]);
10665 static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in)
10667 tcg_gen_addi_i64(in, in, 1U << 31);
10668 tcg_gen_extrh_i64_i32(res, in);
10671 static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
10672 int opcode, int rd, int rn, int rm)
10674 TCGv_i32 tcg_res[2];
10675 int part = is_q ? 2 : 0;
10676 int pass;
10678 for (pass = 0; pass < 2; pass++) {
10679 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10680 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
10681 TCGv_i64 tcg_wideres = tcg_temp_new_i64();
10682 static NeonGenNarrowFn * const narrowfns[3][2] = {
10683 { gen_helper_neon_narrow_high_u8,
10684 gen_helper_neon_narrow_round_high_u8 },
10685 { gen_helper_neon_narrow_high_u16,
10686 gen_helper_neon_narrow_round_high_u16 },
10687 { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 },
10689 NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];
10691 read_vec_element(s, tcg_op1, rn, pass, MO_64);
10692 read_vec_element(s, tcg_op2, rm, pass, MO_64);
10694 gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2);
10696 tcg_temp_free_i64(tcg_op1);
10697 tcg_temp_free_i64(tcg_op2);
10699 tcg_res[pass] = tcg_temp_new_i32();
10700 gennarrow(tcg_res[pass], tcg_wideres);
10701 tcg_temp_free_i64(tcg_wideres);
10704 for (pass = 0; pass < 2; pass++) {
10705 write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);
10706 tcg_temp_free_i32(tcg_res[pass]);
10708 clear_vec_high(s, is_q, rd);
10711 /* AdvSIMD three different
10712 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10713 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10714 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10715 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10717 static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
10719 /* Instructions in this group fall into three basic classes
10720 * (in each case with the operation working on each element in
10721 * the input vectors):
10722 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10723 * 128 bit input)
10724 * (2) wide 64 x 128 -> 128
10725 * (3) narrowing 128 x 128 -> 64
10726 * Here we do initial decode, catch unallocated cases and
10727 * dispatch to separate functions for each class.
10729 int is_q = extract32(insn, 30, 1);
10730 int is_u = extract32(insn, 29, 1);
10731 int size = extract32(insn, 22, 2);
10732 int opcode = extract32(insn, 12, 4);
10733 int rm = extract32(insn, 16, 5);
10734 int rn = extract32(insn, 5, 5);
10735 int rd = extract32(insn, 0, 5);
10737 switch (opcode) {
10738 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10739 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10740 /* 64 x 128 -> 128 */
10741 if (size == 3) {
10742 unallocated_encoding(s);
10743 return;
10745 if (!fp_access_check(s)) {
10746 return;
10748 handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm);
10749 break;
10750 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10751 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10752 /* 128 x 128 -> 64 */
10753 if (size == 3) {
10754 unallocated_encoding(s);
10755 return;
10757 if (!fp_access_check(s)) {
10758 return;
10760 handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm);
10761 break;
10762 case 14: /* PMULL, PMULL2 */
10763 if (is_u) {
10764 unallocated_encoding(s);
10765 return;
10767 switch (size) {
10768 case 0: /* PMULL.P8 */
10769 if (!fp_access_check(s)) {
10770 return;
10772 /* The Q field specifies lo/hi half input for this insn. */
10773 gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
10774 gen_helper_neon_pmull_h);
10775 break;
10777 case 3: /* PMULL.P64 */
10778 if (!dc_isar_feature(aa64_pmull, s)) {
10779 unallocated_encoding(s);
10780 return;
10782 if (!fp_access_check(s)) {
10783 return;
10785 /* The Q field specifies lo/hi half input for this insn. */
10786 gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
10787 gen_helper_gvec_pmull_q);
10788 break;
10790 default:
10791 unallocated_encoding(s);
10792 break;
10794 return;
10795 case 9: /* SQDMLAL, SQDMLAL2 */
10796 case 11: /* SQDMLSL, SQDMLSL2 */
10797 case 13: /* SQDMULL, SQDMULL2 */
10798 if (is_u || size == 0) {
10799 unallocated_encoding(s);
10800 return;
10802 /* fall through */
10803 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10804 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10805 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10806 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10807 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10808 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10809 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10810 /* 64 x 64 -> 128 */
10811 if (size == 3) {
10812 unallocated_encoding(s);
10813 return;
10815 if (!fp_access_check(s)) {
10816 return;
10819 handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
10820 break;
10821 default:
10822 /* opcode 15 not allocated */
10823 unallocated_encoding(s);
10824 break;
10828 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10829 static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
10831 int rd = extract32(insn, 0, 5);
10832 int rn = extract32(insn, 5, 5);
10833 int rm = extract32(insn, 16, 5);
10834 int size = extract32(insn, 22, 2);
10835 bool is_u = extract32(insn, 29, 1);
10836 bool is_q = extract32(insn, 30, 1);
10838 if (!fp_access_check(s)) {
10839 return;
10842 switch (size + 4 * is_u) {
10843 case 0: /* AND */
10844 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_and, 0);
10845 return;
10846 case 1: /* BIC */
10847 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
10848 return;
10849 case 2: /* ORR */
10850 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
10851 return;
10852 case 3: /* ORN */
10853 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);
10854 return;
10855 case 4: /* EOR */
10856 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0);
10857 return;
10859 case 5: /* BSL bitwise select */
10860 gen_gvec_fn4(s, is_q, rd, rd, rn, rm, tcg_gen_gvec_bitsel, 0);
10861 return;
10862 case 6: /* BIT, bitwise insert if true */
10863 gen_gvec_fn4(s, is_q, rd, rm, rn, rd, tcg_gen_gvec_bitsel, 0);
10864 return;
10865 case 7: /* BIF, bitwise insert if false */
10866 gen_gvec_fn4(s, is_q, rd, rm, rd, rn, tcg_gen_gvec_bitsel, 0);
10867 return;
10869 default:
10870 g_assert_not_reached();
10874 /* Pairwise op subgroup of C3.6.16.
10876 * This is called directly or via the handle_3same_float for float pairwise
10877 * operations where the opcode and size are calculated differently.
10879 static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
10880 int size, int rn, int rm, int rd)
10882 TCGv_ptr fpst;
10883 int pass;
10885 /* Floating point operations need fpst */
10886 if (opcode >= 0x58) {
10887 fpst = get_fpstatus_ptr(false);
10888 } else {
10889 fpst = NULL;
10892 if (!fp_access_check(s)) {
10893 return;
10896 /* These operations work on the concatenated rm:rn, with each pair of
10897 * adjacent elements being operated on to produce an element in the result.
10899 if (size == 3) {
10900 TCGv_i64 tcg_res[2];
10902 for (pass = 0; pass < 2; pass++) {
10903 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10904 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
10905 int passreg = (pass == 0) ? rn : rm;
10907 read_vec_element(s, tcg_op1, passreg, 0, MO_64);
10908 read_vec_element(s, tcg_op2, passreg, 1, MO_64);
10909 tcg_res[pass] = tcg_temp_new_i64();
10911 switch (opcode) {
10912 case 0x17: /* ADDP */
10913 tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
10914 break;
10915 case 0x58: /* FMAXNMP */
10916 gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10917 break;
10918 case 0x5a: /* FADDP */
10919 gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10920 break;
10921 case 0x5e: /* FMAXP */
10922 gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10923 break;
10924 case 0x78: /* FMINNMP */
10925 gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10926 break;
10927 case 0x7e: /* FMINP */
10928 gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10929 break;
10930 default:
10931 g_assert_not_reached();
10934 tcg_temp_free_i64(tcg_op1);
10935 tcg_temp_free_i64(tcg_op2);
10938 for (pass = 0; pass < 2; pass++) {
10939 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10940 tcg_temp_free_i64(tcg_res[pass]);
10942 } else {
10943 int maxpass = is_q ? 4 : 2;
10944 TCGv_i32 tcg_res[4];
10946 for (pass = 0; pass < maxpass; pass++) {
10947 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
10948 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
10949 NeonGenTwoOpFn *genfn = NULL;
10950 int passreg = pass < (maxpass / 2) ? rn : rm;
10951 int passelt = (is_q && (pass & 1)) ? 2 : 0;
10953 read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32);
10954 read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32);
10955 tcg_res[pass] = tcg_temp_new_i32();
10957 switch (opcode) {
10958 case 0x17: /* ADDP */
10960 static NeonGenTwoOpFn * const fns[3] = {
10961 gen_helper_neon_padd_u8,
10962 gen_helper_neon_padd_u16,
10963 tcg_gen_add_i32,
10965 genfn = fns[size];
10966 break;
10968 case 0x14: /* SMAXP, UMAXP */
10970 static NeonGenTwoOpFn * const fns[3][2] = {
10971 { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 },
10972 { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 },
10973 { tcg_gen_smax_i32, tcg_gen_umax_i32 },
10975 genfn = fns[size][u];
10976 break;
10978 case 0x15: /* SMINP, UMINP */
10980 static NeonGenTwoOpFn * const fns[3][2] = {
10981 { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 },
10982 { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 },
10983 { tcg_gen_smin_i32, tcg_gen_umin_i32 },
10985 genfn = fns[size][u];
10986 break;
10988 /* The FP operations are all on single floats (32 bit) */
10989 case 0x58: /* FMAXNMP */
10990 gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10991 break;
10992 case 0x5a: /* FADDP */
10993 gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10994 break;
10995 case 0x5e: /* FMAXP */
10996 gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10997 break;
10998 case 0x78: /* FMINNMP */
10999 gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
11000 break;
11001 case 0x7e: /* FMINP */
11002 gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst);
11003 break;
11004 default:
11005 g_assert_not_reached();
11008 /* FP ops called directly, otherwise call now */
11009 if (genfn) {
11010 genfn(tcg_res[pass], tcg_op1, tcg_op2);
11013 tcg_temp_free_i32(tcg_op1);
11014 tcg_temp_free_i32(tcg_op2);
11017 for (pass = 0; pass < maxpass; pass++) {
11018 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
11019 tcg_temp_free_i32(tcg_res[pass]);
11021 clear_vec_high(s, is_q, rd);
11024 if (fpst) {
11025 tcg_temp_free_ptr(fpst);
11029 /* Floating point op subgroup of C3.6.16. */
11030 static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
11032 /* For floating point ops, the U, size[1] and opcode bits
11033 * together indicate the operation. size[0] indicates single
11034 * or double.
11036 int fpopcode = extract32(insn, 11, 5)
11037 | (extract32(insn, 23, 1) << 5)
11038 | (extract32(insn, 29, 1) << 6);
11039 int is_q = extract32(insn, 30, 1);
11040 int size = extract32(insn, 22, 1);
11041 int rm = extract32(insn, 16, 5);
11042 int rn = extract32(insn, 5, 5);
11043 int rd = extract32(insn, 0, 5);
11045 int datasize = is_q ? 128 : 64;
11046 int esize = 32 << size;
11047 int elements = datasize / esize;
11049 if (size == 1 && !is_q) {
11050 unallocated_encoding(s);
11051 return;
11054 switch (fpopcode) {
11055 case 0x58: /* FMAXNMP */
11056 case 0x5a: /* FADDP */
11057 case 0x5e: /* FMAXP */
11058 case 0x78: /* FMINNMP */
11059 case 0x7e: /* FMINP */
11060 if (size && !is_q) {
11061 unallocated_encoding(s);
11062 return;
11064 handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32,
11065 rn, rm, rd);
11066 return;
11067 case 0x1b: /* FMULX */
11068 case 0x1f: /* FRECPS */
11069 case 0x3f: /* FRSQRTS */
11070 case 0x5d: /* FACGE */
11071 case 0x7d: /* FACGT */
11072 case 0x19: /* FMLA */
11073 case 0x39: /* FMLS */
11074 case 0x18: /* FMAXNM */
11075 case 0x1a: /* FADD */
11076 case 0x1c: /* FCMEQ */
11077 case 0x1e: /* FMAX */
11078 case 0x38: /* FMINNM */
11079 case 0x3a: /* FSUB */
11080 case 0x3e: /* FMIN */
11081 case 0x5b: /* FMUL */
11082 case 0x5c: /* FCMGE */
11083 case 0x5f: /* FDIV */
11084 case 0x7a: /* FABD */
11085 case 0x7c: /* FCMGT */
11086 if (!fp_access_check(s)) {
11087 return;
11089 handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
11090 return;
11092 case 0x1d: /* FMLAL */
11093 case 0x3d: /* FMLSL */
11094 case 0x59: /* FMLAL2 */
11095 case 0x79: /* FMLSL2 */
11096 if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
11097 unallocated_encoding(s);
11098 return;
11100 if (fp_access_check(s)) {
11101 int is_s = extract32(insn, 23, 1);
11102 int is_2 = extract32(insn, 29, 1);
11103 int data = (is_2 << 1) | is_s;
11104 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
11105 vec_full_reg_offset(s, rn),
11106 vec_full_reg_offset(s, rm), cpu_env,
11107 is_q ? 16 : 8, vec_full_reg_size(s),
11108 data, gen_helper_gvec_fmlal_a64);
11110 return;
11112 default:
11113 unallocated_encoding(s);
11114 return;
11118 /* Integer op subgroup of C3.6.16. */
11119 static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
11121 int is_q = extract32(insn, 30, 1);
11122 int u = extract32(insn, 29, 1);
11123 int size = extract32(insn, 22, 2);
11124 int opcode = extract32(insn, 11, 5);
11125 int rm = extract32(insn, 16, 5);
11126 int rn = extract32(insn, 5, 5);
11127 int rd = extract32(insn, 0, 5);
11128 int pass;
11129 TCGCond cond;
11131 switch (opcode) {
11132 case 0x13: /* MUL, PMUL */
11133 if (u && size != 0) {
11134 unallocated_encoding(s);
11135 return;
11137 /* fall through */
11138 case 0x0: /* SHADD, UHADD */
11139 case 0x2: /* SRHADD, URHADD */
11140 case 0x4: /* SHSUB, UHSUB */
11141 case 0xc: /* SMAX, UMAX */
11142 case 0xd: /* SMIN, UMIN */
11143 case 0xe: /* SABD, UABD */
11144 case 0xf: /* SABA, UABA */
11145 case 0x12: /* MLA, MLS */
11146 if (size == 3) {
11147 unallocated_encoding(s);
11148 return;
11150 break;
11151 case 0x16: /* SQDMULH, SQRDMULH */
11152 if (size == 0 || size == 3) {
11153 unallocated_encoding(s);
11154 return;
11156 break;
11157 default:
11158 if (size == 3 && !is_q) {
11159 unallocated_encoding(s);
11160 return;
11162 break;
11165 if (!fp_access_check(s)) {
11166 return;
11169 switch (opcode) {
11170 case 0x01: /* SQADD, UQADD */
11171 if (u) {
11172 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqadd_qc, size);
11173 } else {
11174 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqadd_qc, size);
11176 return;
11177 case 0x05: /* SQSUB, UQSUB */
11178 if (u) {
11179 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqsub_qc, size);
11180 } else {
11181 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqsub_qc, size);
11183 return;
11184 case 0x08: /* SSHL, USHL */
11185 if (u) {
11186 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_ushl, size);
11187 } else {
11188 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sshl, size);
11190 return;
11191 case 0x0c: /* SMAX, UMAX */
11192 if (u) {
11193 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);
11194 } else {
11195 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size);
11197 return;
11198 case 0x0d: /* SMIN, UMIN */
11199 if (u) {
11200 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size);
11201 } else {
11202 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size);
11204 return;
11205 case 0x10: /* ADD, SUB */
11206 if (u) {
11207 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size);
11208 } else {
11209 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size);
11211 return;
11212 case 0x13: /* MUL, PMUL */
11213 if (!u) { /* MUL */
11214 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size);
11215 } else { /* PMUL */
11216 gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b);
11218 return;
11219 case 0x12: /* MLA, MLS */
11220 if (u) {
11221 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size);
11222 } else {
11223 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size);
11225 return;
11226 case 0x11:
11227 if (!u) { /* CMTST */
11228 gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size);
11229 return;
11231 /* else CMEQ */
11232 cond = TCG_COND_EQ;
11233 goto do_gvec_cmp;
11234 case 0x06: /* CMGT, CMHI */
11235 cond = u ? TCG_COND_GTU : TCG_COND_GT;
11236 goto do_gvec_cmp;
11237 case 0x07: /* CMGE, CMHS */
11238 cond = u ? TCG_COND_GEU : TCG_COND_GE;
11239 do_gvec_cmp:
11240 tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd),
11241 vec_full_reg_offset(s, rn),
11242 vec_full_reg_offset(s, rm),
11243 is_q ? 16 : 8, vec_full_reg_size(s));
11244 return;
11247 if (size == 3) {
11248 assert(is_q);
11249 for (pass = 0; pass < 2; pass++) {
11250 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
11251 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
11252 TCGv_i64 tcg_res = tcg_temp_new_i64();
11254 read_vec_element(s, tcg_op1, rn, pass, MO_64);
11255 read_vec_element(s, tcg_op2, rm, pass, MO_64);
11257 handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2);
11259 write_vec_element(s, tcg_res, rd, pass, MO_64);
11261 tcg_temp_free_i64(tcg_res);
11262 tcg_temp_free_i64(tcg_op1);
11263 tcg_temp_free_i64(tcg_op2);
11265 } else {
11266 for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
11267 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
11268 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
11269 TCGv_i32 tcg_res = tcg_temp_new_i32();
11270 NeonGenTwoOpFn *genfn = NULL;
11271 NeonGenTwoOpEnvFn *genenvfn = NULL;
11273 read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
11274 read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
11276 switch (opcode) {
11277 case 0x0: /* SHADD, UHADD */
11279 static NeonGenTwoOpFn * const fns[3][2] = {
11280 { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 },
11281 { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 },
11282 { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 },
11284 genfn = fns[size][u];
11285 break;
11287 case 0x2: /* SRHADD, URHADD */
11289 static NeonGenTwoOpFn * const fns[3][2] = {
11290 { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 },
11291 { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 },
11292 { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 },
11294 genfn = fns[size][u];
11295 break;
11297 case 0x4: /* SHSUB, UHSUB */
11299 static NeonGenTwoOpFn * const fns[3][2] = {
11300 { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 },
11301 { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 },
11302 { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 },
11304 genfn = fns[size][u];
11305 break;
11307 case 0x9: /* SQSHL, UQSHL */
11309 static NeonGenTwoOpEnvFn * const fns[3][2] = {
11310 { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
11311 { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
11312 { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
11314 genenvfn = fns[size][u];
11315 break;
11317 case 0xa: /* SRSHL, URSHL */
11319 static NeonGenTwoOpFn * const fns[3][2] = {
11320 { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 },
11321 { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 },
11322 { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 },
11324 genfn = fns[size][u];
11325 break;
11327 case 0xb: /* SQRSHL, UQRSHL */
11329 static NeonGenTwoOpEnvFn * const fns[3][2] = {
11330 { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
11331 { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
11332 { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
11334 genenvfn = fns[size][u];
11335 break;
11337 case 0xe: /* SABD, UABD */
11338 case 0xf: /* SABA, UABA */
11340 static NeonGenTwoOpFn * const fns[3][2] = {
11341 { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 },
11342 { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 },
11343 { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 },
11345 genfn = fns[size][u];
11346 break;
11348 case 0x16: /* SQDMULH, SQRDMULH */
11350 static NeonGenTwoOpEnvFn * const fns[2][2] = {
11351 { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
11352 { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
11354 assert(size == 1 || size == 2);
11355 genenvfn = fns[size - 1][u];
11356 break;
11358 default:
11359 g_assert_not_reached();
11362 if (genenvfn) {
11363 genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2);
11364 } else {
11365 genfn(tcg_res, tcg_op1, tcg_op2);
11368 if (opcode == 0xf) {
11369 /* SABA, UABA: accumulating ops */
11370 static NeonGenTwoOpFn * const fns[3] = {
11371 gen_helper_neon_add_u8,
11372 gen_helper_neon_add_u16,
11373 tcg_gen_add_i32,
11376 read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
11377 fns[size](tcg_res, tcg_op1, tcg_res);
11380 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
11382 tcg_temp_free_i32(tcg_res);
11383 tcg_temp_free_i32(tcg_op1);
11384 tcg_temp_free_i32(tcg_op2);
11387 clear_vec_high(s, is_q, rd);
11390 /* AdvSIMD three same
11391 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11392 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11393 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11394 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11396 static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
11398 int opcode = extract32(insn, 11, 5);
11400 switch (opcode) {
11401 case 0x3: /* logic ops */
11402 disas_simd_3same_logic(s, insn);
11403 break;
11404 case 0x17: /* ADDP */
11405 case 0x14: /* SMAXP, UMAXP */
11406 case 0x15: /* SMINP, UMINP */
11408 /* Pairwise operations */
11409 int is_q = extract32(insn, 30, 1);
11410 int u = extract32(insn, 29, 1);
11411 int size = extract32(insn, 22, 2);
11412 int rm = extract32(insn, 16, 5);
11413 int rn = extract32(insn, 5, 5);
11414 int rd = extract32(insn, 0, 5);
11415 if (opcode == 0x17) {
11416 if (u || (size == 3 && !is_q)) {
11417 unallocated_encoding(s);
11418 return;
11420 } else {
11421 if (size == 3) {
11422 unallocated_encoding(s);
11423 return;
11426 handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd);
11427 break;
11429 case 0x18 ... 0x31:
11430 /* floating point ops, sz[1] and U are part of opcode */
11431 disas_simd_3same_float(s, insn);
11432 break;
11433 default:
11434 disas_simd_3same_int(s, insn);
11435 break;
11440 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11442 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11443 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11444 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11445 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11447 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11448 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11451 static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
11453 int opcode, fpopcode;
11454 int is_q, u, a, rm, rn, rd;
11455 int datasize, elements;
11456 int pass;
11457 TCGv_ptr fpst;
11458 bool pairwise = false;
11460 if (!dc_isar_feature(aa64_fp16, s)) {
11461 unallocated_encoding(s);
11462 return;
11465 if (!fp_access_check(s)) {
11466 return;
11469 /* For these floating point ops, the U, a and opcode bits
11470 * together indicate the operation.
11472 opcode = extract32(insn, 11, 3);
11473 u = extract32(insn, 29, 1);
11474 a = extract32(insn, 23, 1);
11475 is_q = extract32(insn, 30, 1);
11476 rm = extract32(insn, 16, 5);
11477 rn = extract32(insn, 5, 5);
11478 rd = extract32(insn, 0, 5);
11480 fpopcode = opcode | (a << 3) | (u << 4);
11481 datasize = is_q ? 128 : 64;
11482 elements = datasize / 16;
11484 switch (fpopcode) {
11485 case 0x10: /* FMAXNMP */
11486 case 0x12: /* FADDP */
11487 case 0x16: /* FMAXP */
11488 case 0x18: /* FMINNMP */
11489 case 0x1e: /* FMINP */
11490 pairwise = true;
11491 break;
11494 fpst = get_fpstatus_ptr(true);
11496 if (pairwise) {
11497 int maxpass = is_q ? 8 : 4;
11498 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
11499 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
11500 TCGv_i32 tcg_res[8];
11502 for (pass = 0; pass < maxpass; pass++) {
11503 int passreg = pass < (maxpass / 2) ? rn : rm;
11504 int passelt = (pass << 1) & (maxpass - 1);
11506 read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
11507 read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
11508 tcg_res[pass] = tcg_temp_new_i32();
11510 switch (fpopcode) {
11511 case 0x10: /* FMAXNMP */
11512 gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
11513 fpst);
11514 break;
11515 case 0x12: /* FADDP */
11516 gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
11517 break;
11518 case 0x16: /* FMAXP */
11519 gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
11520 break;
11521 case 0x18: /* FMINNMP */
11522 gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
11523 fpst);
11524 break;
11525 case 0x1e: /* FMINP */
11526 gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
11527 break;
11528 default:
11529 g_assert_not_reached();
11533 for (pass = 0; pass < maxpass; pass++) {
11534 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
11535 tcg_temp_free_i32(tcg_res[pass]);
11538 tcg_temp_free_i32(tcg_op1);
11539 tcg_temp_free_i32(tcg_op2);
11541 } else {
11542 for (pass = 0; pass < elements; pass++) {
11543 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
11544 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
11545 TCGv_i32 tcg_res = tcg_temp_new_i32();
11547 read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
11548 read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
11550 switch (fpopcode) {
11551 case 0x0: /* FMAXNM */
11552 gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
11553 break;
11554 case 0x1: /* FMLA */
11555 read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
11556 gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
11557 fpst);
11558 break;
11559 case 0x2: /* FADD */
11560 gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
11561 break;
11562 case 0x3: /* FMULX */
11563 gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
11564 break;
11565 case 0x4: /* FCMEQ */
11566 gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11567 break;
11568 case 0x6: /* FMAX */
11569 gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
11570 break;
11571 case 0x7: /* FRECPS */
11572 gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11573 break;
11574 case 0x8: /* FMINNM */
11575 gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
11576 break;
11577 case 0x9: /* FMLS */
11578 /* As usual for ARM, separate negation for fused multiply-add */
11579 tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
11580 read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
11581 gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
11582 fpst);
11583 break;
11584 case 0xa: /* FSUB */
11585 gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
11586 break;
11587 case 0xe: /* FMIN */
11588 gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
11589 break;
11590 case 0xf: /* FRSQRTS */
11591 gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11592 break;
11593 case 0x13: /* FMUL */
11594 gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
11595 break;
11596 case 0x14: /* FCMGE */
11597 gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11598 break;
11599 case 0x15: /* FACGE */
11600 gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11601 break;
11602 case 0x17: /* FDIV */
11603 gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
11604 break;
11605 case 0x1a: /* FABD */
11606 gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
11607 tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
11608 break;
11609 case 0x1c: /* FCMGT */
11610 gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11611 break;
11612 case 0x1d: /* FACGT */
11613 gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11614 break;
11615 default:
11616 fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
11617 __func__, insn, fpopcode, s->pc_curr);
11618 g_assert_not_reached();
11621 write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
11622 tcg_temp_free_i32(tcg_res);
11623 tcg_temp_free_i32(tcg_op1);
11624 tcg_temp_free_i32(tcg_op2);
11628 tcg_temp_free_ptr(fpst);
11630 clear_vec_high(s, is_q, rd);
11633 /* AdvSIMD three same extra
11634 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11635 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11636 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11637 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11639 static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
11641 int rd = extract32(insn, 0, 5);
11642 int rn = extract32(insn, 5, 5);
11643 int opcode = extract32(insn, 11, 4);
11644 int rm = extract32(insn, 16, 5);
11645 int size = extract32(insn, 22, 2);
11646 bool u = extract32(insn, 29, 1);
11647 bool is_q = extract32(insn, 30, 1);
11648 bool feature;
11649 int rot;
11651 switch (u * 16 + opcode) {
11652 case 0x10: /* SQRDMLAH (vector) */
11653 case 0x11: /* SQRDMLSH (vector) */
11654 if (size != 1 && size != 2) {
11655 unallocated_encoding(s);
11656 return;
11658 feature = dc_isar_feature(aa64_rdm, s);
11659 break;
11660 case 0x02: /* SDOT (vector) */
11661 case 0x12: /* UDOT (vector) */
11662 if (size != MO_32) {
11663 unallocated_encoding(s);
11664 return;
11666 feature = dc_isar_feature(aa64_dp, s);
11667 break;
11668 case 0x18: /* FCMLA, #0 */
11669 case 0x19: /* FCMLA, #90 */
11670 case 0x1a: /* FCMLA, #180 */
11671 case 0x1b: /* FCMLA, #270 */
11672 case 0x1c: /* FCADD, #90 */
11673 case 0x1e: /* FCADD, #270 */
11674 if (size == 0
11675 || (size == 1 && !dc_isar_feature(aa64_fp16, s))
11676 || (size == 3 && !is_q)) {
11677 unallocated_encoding(s);
11678 return;
11680 feature = dc_isar_feature(aa64_fcma, s);
11681 break;
11682 default:
11683 unallocated_encoding(s);
11684 return;
11686 if (!feature) {
11687 unallocated_encoding(s);
11688 return;
11690 if (!fp_access_check(s)) {
11691 return;
11694 switch (opcode) {
11695 case 0x0: /* SQRDMLAH (vector) */
11696 switch (size) {
11697 case 1:
11698 gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16);
11699 break;
11700 case 2:
11701 gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32);
11702 break;
11703 default:
11704 g_assert_not_reached();
11706 return;
11708 case 0x1: /* SQRDMLSH (vector) */
11709 switch (size) {
11710 case 1:
11711 gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16);
11712 break;
11713 case 2:
11714 gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32);
11715 break;
11716 default:
11717 g_assert_not_reached();
11719 return;
11721 case 0x2: /* SDOT / UDOT */
11722 gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0,
11723 u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b);
11724 return;
11726 case 0x8: /* FCMLA, #0 */
11727 case 0x9: /* FCMLA, #90 */
11728 case 0xa: /* FCMLA, #180 */
11729 case 0xb: /* FCMLA, #270 */
11730 rot = extract32(opcode, 0, 2);
11731 switch (size) {
11732 case 1:
11733 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot,
11734 gen_helper_gvec_fcmlah);
11735 break;
11736 case 2:
11737 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
11738 gen_helper_gvec_fcmlas);
11739 break;
11740 case 3:
11741 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
11742 gen_helper_gvec_fcmlad);
11743 break;
11744 default:
11745 g_assert_not_reached();
11747 return;
11749 case 0xc: /* FCADD, #90 */
11750 case 0xe: /* FCADD, #270 */
11751 rot = extract32(opcode, 1, 1);
11752 switch (size) {
11753 case 1:
11754 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
11755 gen_helper_gvec_fcaddh);
11756 break;
11757 case 2:
11758 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
11759 gen_helper_gvec_fcadds);
11760 break;
11761 case 3:
11762 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
11763 gen_helper_gvec_fcaddd);
11764 break;
11765 default:
11766 g_assert_not_reached();
11768 return;
11770 default:
11771 g_assert_not_reached();
11775 static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
11776 int size, int rn, int rd)
11778 /* Handle 2-reg-misc ops which are widening (so each size element
11779 * in the source becomes a 2*size element in the destination.
11780 * The only instruction like this is FCVTL.
11782 int pass;
11784 if (size == 3) {
11785 /* 32 -> 64 bit fp conversion */
11786 TCGv_i64 tcg_res[2];
11787 int srcelt = is_q ? 2 : 0;
11789 for (pass = 0; pass < 2; pass++) {
11790 TCGv_i32 tcg_op = tcg_temp_new_i32();
11791 tcg_res[pass] = tcg_temp_new_i64();
11793 read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);
11794 gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env);
11795 tcg_temp_free_i32(tcg_op);
11797 for (pass = 0; pass < 2; pass++) {
11798 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
11799 tcg_temp_free_i64(tcg_res[pass]);
11801 } else {
11802 /* 16 -> 32 bit fp conversion */
11803 int srcelt = is_q ? 4 : 0;
11804 TCGv_i32 tcg_res[4];
11805 TCGv_ptr fpst = get_fpstatus_ptr(false);
11806 TCGv_i32 ahp = get_ahp_flag();
11808 for (pass = 0; pass < 4; pass++) {
11809 tcg_res[pass] = tcg_temp_new_i32();
11811 read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);
11812 gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass],
11813 fpst, ahp);
11815 for (pass = 0; pass < 4; pass++) {
11816 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
11817 tcg_temp_free_i32(tcg_res[pass]);
11820 tcg_temp_free_ptr(fpst);
11821 tcg_temp_free_i32(ahp);
11825 static void handle_rev(DisasContext *s, int opcode, bool u,
11826 bool is_q, int size, int rn, int rd)
11828 int op = (opcode << 1) | u;
11829 int opsz = op + size;
11830 int grp_size = 3 - opsz;
11831 int dsize = is_q ? 128 : 64;
11832 int i;
11834 if (opsz >= 3) {
11835 unallocated_encoding(s);
11836 return;
11839 if (!fp_access_check(s)) {
11840 return;
11843 if (size == 0) {
11844 /* Special case bytes, use bswap op on each group of elements */
11845 int groups = dsize / (8 << grp_size);
11847 for (i = 0; i < groups; i++) {
11848 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
11850 read_vec_element(s, tcg_tmp, rn, i, grp_size);
11851 switch (grp_size) {
11852 case MO_16:
11853 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
11854 break;
11855 case MO_32:
11856 tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
11857 break;
11858 case MO_64:
11859 tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
11860 break;
11861 default:
11862 g_assert_not_reached();
11864 write_vec_element(s, tcg_tmp, rd, i, grp_size);
11865 tcg_temp_free_i64(tcg_tmp);
11867 clear_vec_high(s, is_q, rd);
11868 } else {
11869 int revmask = (1 << grp_size) - 1;
11870 int esize = 8 << size;
11871 int elements = dsize / esize;
11872 TCGv_i64 tcg_rn = tcg_temp_new_i64();
11873 TCGv_i64 tcg_rd = tcg_const_i64(0);
11874 TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
11876 for (i = 0; i < elements; i++) {
11877 int e_rev = (i & 0xf) ^ revmask;
11878 int off = e_rev * esize;
11879 read_vec_element(s, tcg_rn, rn, i, size);
11880 if (off >= 64) {
11881 tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
11882 tcg_rn, off - 64, esize);
11883 } else {
11884 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
11887 write_vec_element(s, tcg_rd, rd, 0, MO_64);
11888 write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
11890 tcg_temp_free_i64(tcg_rd_hi);
11891 tcg_temp_free_i64(tcg_rd);
11892 tcg_temp_free_i64(tcg_rn);
11896 static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
11897 bool is_q, int size, int rn, int rd)
11899 /* Implement the pairwise operations from 2-misc:
11900 * SADDLP, UADDLP, SADALP, UADALP.
11901 * These all add pairs of elements in the input to produce a
11902 * double-width result element in the output (possibly accumulating).
11904 bool accum = (opcode == 0x6);
11905 int maxpass = is_q ? 2 : 1;
11906 int pass;
11907 TCGv_i64 tcg_res[2];
11909 if (size == 2) {
11910 /* 32 + 32 -> 64 op */
11911 MemOp memop = size + (u ? 0 : MO_SIGN);
11913 for (pass = 0; pass < maxpass; pass++) {
11914 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
11915 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
11917 tcg_res[pass] = tcg_temp_new_i64();
11919 read_vec_element(s, tcg_op1, rn, pass * 2, memop);
11920 read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop);
11921 tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
11922 if (accum) {
11923 read_vec_element(s, tcg_op1, rd, pass, MO_64);
11924 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
11927 tcg_temp_free_i64(tcg_op1);
11928 tcg_temp_free_i64(tcg_op2);
11930 } else {
11931 for (pass = 0; pass < maxpass; pass++) {
11932 TCGv_i64 tcg_op = tcg_temp_new_i64();
11933 NeonGenOneOpFn *genfn;
11934 static NeonGenOneOpFn * const fns[2][2] = {
11935 { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 },
11936 { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 },
11939 genfn = fns[size][u];
11941 tcg_res[pass] = tcg_temp_new_i64();
11943 read_vec_element(s, tcg_op, rn, pass, MO_64);
11944 genfn(tcg_res[pass], tcg_op);
11946 if (accum) {
11947 read_vec_element(s, tcg_op, rd, pass, MO_64);
11948 if (size == 0) {
11949 gen_helper_neon_addl_u16(tcg_res[pass],
11950 tcg_res[pass], tcg_op);
11951 } else {
11952 gen_helper_neon_addl_u32(tcg_res[pass],
11953 tcg_res[pass], tcg_op);
11956 tcg_temp_free_i64(tcg_op);
11959 if (!is_q) {
11960 tcg_res[1] = tcg_const_i64(0);
11962 for (pass = 0; pass < 2; pass++) {
11963 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
11964 tcg_temp_free_i64(tcg_res[pass]);
11968 static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
11970 /* Implement SHLL and SHLL2 */
11971 int pass;
11972 int part = is_q ? 2 : 0;
11973 TCGv_i64 tcg_res[2];
11975 for (pass = 0; pass < 2; pass++) {
11976 static NeonGenWidenFn * const widenfns[3] = {
11977 gen_helper_neon_widen_u8,
11978 gen_helper_neon_widen_u16,
11979 tcg_gen_extu_i32_i64,
11981 NeonGenWidenFn *widenfn = widenfns[size];
11982 TCGv_i32 tcg_op = tcg_temp_new_i32();
11984 read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);
11985 tcg_res[pass] = tcg_temp_new_i64();
11986 widenfn(tcg_res[pass], tcg_op);
11987 tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);
11989 tcg_temp_free_i32(tcg_op);
11992 for (pass = 0; pass < 2; pass++) {
11993 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
11994 tcg_temp_free_i64(tcg_res[pass]);
11998 /* AdvSIMD two reg misc
11999 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12000 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12001 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12002 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12004 static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
12006 int size = extract32(insn, 22, 2);
12007 int opcode = extract32(insn, 12, 5);
12008 bool u = extract32(insn, 29, 1);
12009 bool is_q = extract32(insn, 30, 1);
12010 int rn = extract32(insn, 5, 5);
12011 int rd = extract32(insn, 0, 5);
12012 bool need_fpstatus = false;
12013 bool need_rmode = false;
12014 int rmode = -1;
12015 TCGv_i32 tcg_rmode;
12016 TCGv_ptr tcg_fpstatus;
12018 switch (opcode) {
12019 case 0x0: /* REV64, REV32 */
12020 case 0x1: /* REV16 */
12021 handle_rev(s, opcode, u, is_q, size, rn, rd);
12022 return;
12023 case 0x5: /* CNT, NOT, RBIT */
12024 if (u && size == 0) {
12025 /* NOT */
12026 break;
12027 } else if (u && size == 1) {
12028 /* RBIT */
12029 break;
12030 } else if (!u && size == 0) {
12031 /* CNT */
12032 break;
12034 unallocated_encoding(s);
12035 return;
12036 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12037 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12038 if (size == 3) {
12039 unallocated_encoding(s);
12040 return;
12042 if (!fp_access_check(s)) {
12043 return;
12046 handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
12047 return;
12048 case 0x4: /* CLS, CLZ */
12049 if (size == 3) {
12050 unallocated_encoding(s);
12051 return;
12053 break;
12054 case 0x2: /* SADDLP, UADDLP */
12055 case 0x6: /* SADALP, UADALP */
12056 if (size == 3) {
12057 unallocated_encoding(s);
12058 return;
12060 if (!fp_access_check(s)) {
12061 return;
12063 handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd);
12064 return;
12065 case 0x13: /* SHLL, SHLL2 */
12066 if (u == 0 || size == 3) {
12067 unallocated_encoding(s);
12068 return;
12070 if (!fp_access_check(s)) {
12071 return;
12073 handle_shll(s, is_q, size, rn, rd);
12074 return;
12075 case 0xa: /* CMLT */
12076 if (u == 1) {
12077 unallocated_encoding(s);
12078 return;
12080 /* fall through */
12081 case 0x8: /* CMGT, CMGE */
12082 case 0x9: /* CMEQ, CMLE */
12083 case 0xb: /* ABS, NEG */
12084 if (size == 3 && !is_q) {
12085 unallocated_encoding(s);
12086 return;
12088 break;
12089 case 0x3: /* SUQADD, USQADD */
12090 if (size == 3 && !is_q) {
12091 unallocated_encoding(s);
12092 return;
12094 if (!fp_access_check(s)) {
12095 return;
12097 handle_2misc_satacc(s, false, u, is_q, size, rn, rd);
12098 return;
12099 case 0x7: /* SQABS, SQNEG */
12100 if (size == 3 && !is_q) {
12101 unallocated_encoding(s);
12102 return;
12104 break;
12105 case 0xc ... 0xf:
12106 case 0x16 ... 0x1f:
12108 /* Floating point: U, size[1] and opcode indicate operation;
12109 * size[0] indicates single or double precision.
12111 int is_double = extract32(size, 0, 1);
12112 opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
12113 size = is_double ? 3 : 2;
12114 switch (opcode) {
12115 case 0x2f: /* FABS */
12116 case 0x6f: /* FNEG */
12117 if (size == 3 && !is_q) {
12118 unallocated_encoding(s);
12119 return;
12121 break;
12122 case 0x1d: /* SCVTF */
12123 case 0x5d: /* UCVTF */
12125 bool is_signed = (opcode == 0x1d) ? true : false;
12126 int elements = is_double ? 2 : is_q ? 4 : 2;
12127 if (is_double && !is_q) {
12128 unallocated_encoding(s);
12129 return;
12131 if (!fp_access_check(s)) {
12132 return;
12134 handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size);
12135 return;
12137 case 0x2c: /* FCMGT (zero) */
12138 case 0x2d: /* FCMEQ (zero) */
12139 case 0x2e: /* FCMLT (zero) */
12140 case 0x6c: /* FCMGE (zero) */
12141 case 0x6d: /* FCMLE (zero) */
12142 if (size == 3 && !is_q) {
12143 unallocated_encoding(s);
12144 return;
12146 handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
12147 return;
12148 case 0x7f: /* FSQRT */
12149 if (size == 3 && !is_q) {
12150 unallocated_encoding(s);
12151 return;
12153 break;
12154 case 0x1a: /* FCVTNS */
12155 case 0x1b: /* FCVTMS */
12156 case 0x3a: /* FCVTPS */
12157 case 0x3b: /* FCVTZS */
12158 case 0x5a: /* FCVTNU */
12159 case 0x5b: /* FCVTMU */
12160 case 0x7a: /* FCVTPU */
12161 case 0x7b: /* FCVTZU */
12162 need_fpstatus = true;
12163 need_rmode = true;
12164 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
12165 if (size == 3 && !is_q) {
12166 unallocated_encoding(s);
12167 return;
12169 break;
12170 case 0x5c: /* FCVTAU */
12171 case 0x1c: /* FCVTAS */
12172 need_fpstatus = true;
12173 need_rmode = true;
12174 rmode = FPROUNDING_TIEAWAY;
12175 if (size == 3 && !is_q) {
12176 unallocated_encoding(s);
12177 return;
12179 break;
12180 case 0x3c: /* URECPE */
12181 if (size == 3) {
12182 unallocated_encoding(s);
12183 return;
12185 /* fall through */
12186 case 0x3d: /* FRECPE */
12187 case 0x7d: /* FRSQRTE */
12188 if (size == 3 && !is_q) {
12189 unallocated_encoding(s);
12190 return;
12192 if (!fp_access_check(s)) {
12193 return;
12195 handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd);
12196 return;
12197 case 0x56: /* FCVTXN, FCVTXN2 */
12198 if (size == 2) {
12199 unallocated_encoding(s);
12200 return;
12202 /* fall through */
12203 case 0x16: /* FCVTN, FCVTN2 */
12204 /* handle_2misc_narrow does a 2*size -> size operation, but these
12205 * instructions encode the source size rather than dest size.
12207 if (!fp_access_check(s)) {
12208 return;
12210 handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
12211 return;
12212 case 0x17: /* FCVTL, FCVTL2 */
12213 if (!fp_access_check(s)) {
12214 return;
12216 handle_2misc_widening(s, opcode, is_q, size, rn, rd);
12217 return;
12218 case 0x18: /* FRINTN */
12219 case 0x19: /* FRINTM */
12220 case 0x38: /* FRINTP */
12221 case 0x39: /* FRINTZ */
12222 need_rmode = true;
12223 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
12224 /* fall through */
12225 case 0x59: /* FRINTX */
12226 case 0x79: /* FRINTI */
12227 need_fpstatus = true;
12228 if (size == 3 && !is_q) {
12229 unallocated_encoding(s);
12230 return;
12232 break;
12233 case 0x58: /* FRINTA */
12234 need_rmode = true;
12235 rmode = FPROUNDING_TIEAWAY;
12236 need_fpstatus = true;
12237 if (size == 3 && !is_q) {
12238 unallocated_encoding(s);
12239 return;
12241 break;
12242 case 0x7c: /* URSQRTE */
12243 if (size == 3) {
12244 unallocated_encoding(s);
12245 return;
12247 need_fpstatus = true;
12248 break;
12249 case 0x1e: /* FRINT32Z */
12250 case 0x1f: /* FRINT64Z */
12251 need_rmode = true;
12252 rmode = FPROUNDING_ZERO;
12253 /* fall through */
12254 case 0x5e: /* FRINT32X */
12255 case 0x5f: /* FRINT64X */
12256 need_fpstatus = true;
12257 if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) {
12258 unallocated_encoding(s);
12259 return;
12261 break;
12262 default:
12263 unallocated_encoding(s);
12264 return;
12266 break;
12268 default:
12269 unallocated_encoding(s);
12270 return;
12273 if (!fp_access_check(s)) {
12274 return;
12277 if (need_fpstatus || need_rmode) {
12278 tcg_fpstatus = get_fpstatus_ptr(false);
12279 } else {
12280 tcg_fpstatus = NULL;
12282 if (need_rmode) {
12283 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
12284 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
12285 } else {
12286 tcg_rmode = NULL;
12289 switch (opcode) {
12290 case 0x5:
12291 if (u && size == 0) { /* NOT */
12292 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
12293 return;
12295 break;
12296 case 0x8: /* CMGT, CMGE */
12297 if (u) {
12298 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size);
12299 } else {
12300 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size);
12302 return;
12303 case 0x9: /* CMEQ, CMLE */
12304 if (u) {
12305 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size);
12306 } else {
12307 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size);
12309 return;
12310 case 0xa: /* CMLT */
12311 gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
12312 return;
12313 case 0xb:
12314 if (u) { /* ABS, NEG */
12315 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
12316 } else {
12317 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size);
12319 return;
12322 if (size == 3) {
12323 /* All 64-bit element operations can be shared with scalar 2misc */
12324 int pass;
12326 /* Coverity claims (size == 3 && !is_q) has been eliminated
12327 * from all paths leading to here.
12329 tcg_debug_assert(is_q);
12330 for (pass = 0; pass < 2; pass++) {
12331 TCGv_i64 tcg_op = tcg_temp_new_i64();
12332 TCGv_i64 tcg_res = tcg_temp_new_i64();
12334 read_vec_element(s, tcg_op, rn, pass, MO_64);
12336 handle_2misc_64(s, opcode, u, tcg_res, tcg_op,
12337 tcg_rmode, tcg_fpstatus);
12339 write_vec_element(s, tcg_res, rd, pass, MO_64);
12341 tcg_temp_free_i64(tcg_res);
12342 tcg_temp_free_i64(tcg_op);
12344 } else {
12345 int pass;
12347 for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
12348 TCGv_i32 tcg_op = tcg_temp_new_i32();
12349 TCGv_i32 tcg_res = tcg_temp_new_i32();
12351 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
12353 if (size == 2) {
12354 /* Special cases for 32 bit elements */
12355 switch (opcode) {
12356 case 0x4: /* CLS */
12357 if (u) {
12358 tcg_gen_clzi_i32(tcg_res, tcg_op, 32);
12359 } else {
12360 tcg_gen_clrsb_i32(tcg_res, tcg_op);
12362 break;
12363 case 0x7: /* SQABS, SQNEG */
12364 if (u) {
12365 gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op);
12366 } else {
12367 gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
12369 break;
12370 case 0x2f: /* FABS */
12371 gen_helper_vfp_abss(tcg_res, tcg_op);
12372 break;
12373 case 0x6f: /* FNEG */
12374 gen_helper_vfp_negs(tcg_res, tcg_op);
12375 break;
12376 case 0x7f: /* FSQRT */
12377 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
12378 break;
12379 case 0x1a: /* FCVTNS */
12380 case 0x1b: /* FCVTMS */
12381 case 0x1c: /* FCVTAS */
12382 case 0x3a: /* FCVTPS */
12383 case 0x3b: /* FCVTZS */
12385 TCGv_i32 tcg_shift = tcg_const_i32(0);
12386 gen_helper_vfp_tosls(tcg_res, tcg_op,
12387 tcg_shift, tcg_fpstatus);
12388 tcg_temp_free_i32(tcg_shift);
12389 break;
12391 case 0x5a: /* FCVTNU */
12392 case 0x5b: /* FCVTMU */
12393 case 0x5c: /* FCVTAU */
12394 case 0x7a: /* FCVTPU */
12395 case 0x7b: /* FCVTZU */
12397 TCGv_i32 tcg_shift = tcg_const_i32(0);
12398 gen_helper_vfp_touls(tcg_res, tcg_op,
12399 tcg_shift, tcg_fpstatus);
12400 tcg_temp_free_i32(tcg_shift);
12401 break;
12403 case 0x18: /* FRINTN */
12404 case 0x19: /* FRINTM */
12405 case 0x38: /* FRINTP */
12406 case 0x39: /* FRINTZ */
12407 case 0x58: /* FRINTA */
12408 case 0x79: /* FRINTI */
12409 gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus);
12410 break;
12411 case 0x59: /* FRINTX */
12412 gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus);
12413 break;
12414 case 0x7c: /* URSQRTE */
12415 gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus);
12416 break;
12417 case 0x1e: /* FRINT32Z */
12418 case 0x5e: /* FRINT32X */
12419 gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus);
12420 break;
12421 case 0x1f: /* FRINT64Z */
12422 case 0x5f: /* FRINT64X */
12423 gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus);
12424 break;
12425 default:
12426 g_assert_not_reached();
12428 } else {
12429 /* Use helpers for 8 and 16 bit elements */
12430 switch (opcode) {
12431 case 0x5: /* CNT, RBIT */
12432 /* For these two insns size is part of the opcode specifier
12433 * (handled earlier); they always operate on byte elements.
12435 if (u) {
12436 gen_helper_neon_rbit_u8(tcg_res, tcg_op);
12437 } else {
12438 gen_helper_neon_cnt_u8(tcg_res, tcg_op);
12440 break;
12441 case 0x7: /* SQABS, SQNEG */
12443 NeonGenOneOpEnvFn *genfn;
12444 static NeonGenOneOpEnvFn * const fns[2][2] = {
12445 { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
12446 { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
12448 genfn = fns[size][u];
12449 genfn(tcg_res, cpu_env, tcg_op);
12450 break;
12452 case 0x4: /* CLS, CLZ */
12453 if (u) {
12454 if (size == 0) {
12455 gen_helper_neon_clz_u8(tcg_res, tcg_op);
12456 } else {
12457 gen_helper_neon_clz_u16(tcg_res, tcg_op);
12459 } else {
12460 if (size == 0) {
12461 gen_helper_neon_cls_s8(tcg_res, tcg_op);
12462 } else {
12463 gen_helper_neon_cls_s16(tcg_res, tcg_op);
12466 break;
12467 default:
12468 g_assert_not_reached();
12472 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
12474 tcg_temp_free_i32(tcg_res);
12475 tcg_temp_free_i32(tcg_op);
12478 clear_vec_high(s, is_q, rd);
12480 if (need_rmode) {
12481 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
12482 tcg_temp_free_i32(tcg_rmode);
12484 if (need_fpstatus) {
12485 tcg_temp_free_ptr(tcg_fpstatus);
12489 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12491 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12492 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12493 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12494 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12495 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12496 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12498 * This actually covers two groups where scalar access is governed by
12499 * bit 28. A bunch of the instructions (float to integral) only exist
12500 * in the vector form and are un-allocated for the scalar decode. Also
12501 * in the scalar decode Q is always 1.
12503 static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
12505 int fpop, opcode, a, u;
12506 int rn, rd;
12507 bool is_q;
12508 bool is_scalar;
12509 bool only_in_vector = false;
12511 int pass;
12512 TCGv_i32 tcg_rmode = NULL;
12513 TCGv_ptr tcg_fpstatus = NULL;
12514 bool need_rmode = false;
12515 bool need_fpst = true;
12516 int rmode;
12518 if (!dc_isar_feature(aa64_fp16, s)) {
12519 unallocated_encoding(s);
12520 return;
12523 rd = extract32(insn, 0, 5);
12524 rn = extract32(insn, 5, 5);
12526 a = extract32(insn, 23, 1);
12527 u = extract32(insn, 29, 1);
12528 is_scalar = extract32(insn, 28, 1);
12529 is_q = extract32(insn, 30, 1);
12531 opcode = extract32(insn, 12, 5);
12532 fpop = deposit32(opcode, 5, 1, a);
12533 fpop = deposit32(fpop, 6, 1, u);
12535 rd = extract32(insn, 0, 5);
12536 rn = extract32(insn, 5, 5);
12538 switch (fpop) {
12539 case 0x1d: /* SCVTF */
12540 case 0x5d: /* UCVTF */
12542 int elements;
12544 if (is_scalar) {
12545 elements = 1;
12546 } else {
12547 elements = (is_q ? 8 : 4);
12550 if (!fp_access_check(s)) {
12551 return;
12553 handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
12554 return;
12556 break;
12557 case 0x2c: /* FCMGT (zero) */
12558 case 0x2d: /* FCMEQ (zero) */
12559 case 0x2e: /* FCMLT (zero) */
12560 case 0x6c: /* FCMGE (zero) */
12561 case 0x6d: /* FCMLE (zero) */
12562 handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
12563 return;
12564 case 0x3d: /* FRECPE */
12565 case 0x3f: /* FRECPX */
12566 break;
12567 case 0x18: /* FRINTN */
12568 need_rmode = true;
12569 only_in_vector = true;
12570 rmode = FPROUNDING_TIEEVEN;
12571 break;
12572 case 0x19: /* FRINTM */
12573 need_rmode = true;
12574 only_in_vector = true;
12575 rmode = FPROUNDING_NEGINF;
12576 break;
12577 case 0x38: /* FRINTP */
12578 need_rmode = true;
12579 only_in_vector = true;
12580 rmode = FPROUNDING_POSINF;
12581 break;
12582 case 0x39: /* FRINTZ */
12583 need_rmode = true;
12584 only_in_vector = true;
12585 rmode = FPROUNDING_ZERO;
12586 break;
12587 case 0x58: /* FRINTA */
12588 need_rmode = true;
12589 only_in_vector = true;
12590 rmode = FPROUNDING_TIEAWAY;
12591 break;
12592 case 0x59: /* FRINTX */
12593 case 0x79: /* FRINTI */
12594 only_in_vector = true;
12595 /* current rounding mode */
12596 break;
12597 case 0x1a: /* FCVTNS */
12598 need_rmode = true;
12599 rmode = FPROUNDING_TIEEVEN;
12600 break;
12601 case 0x1b: /* FCVTMS */
12602 need_rmode = true;
12603 rmode = FPROUNDING_NEGINF;
12604 break;
12605 case 0x1c: /* FCVTAS */
12606 need_rmode = true;
12607 rmode = FPROUNDING_TIEAWAY;
12608 break;
12609 case 0x3a: /* FCVTPS */
12610 need_rmode = true;
12611 rmode = FPROUNDING_POSINF;
12612 break;
12613 case 0x3b: /* FCVTZS */
12614 need_rmode = true;
12615 rmode = FPROUNDING_ZERO;
12616 break;
12617 case 0x5a: /* FCVTNU */
12618 need_rmode = true;
12619 rmode = FPROUNDING_TIEEVEN;
12620 break;
12621 case 0x5b: /* FCVTMU */
12622 need_rmode = true;
12623 rmode = FPROUNDING_NEGINF;
12624 break;
12625 case 0x5c: /* FCVTAU */
12626 need_rmode = true;
12627 rmode = FPROUNDING_TIEAWAY;
12628 break;
12629 case 0x7a: /* FCVTPU */
12630 need_rmode = true;
12631 rmode = FPROUNDING_POSINF;
12632 break;
12633 case 0x7b: /* FCVTZU */
12634 need_rmode = true;
12635 rmode = FPROUNDING_ZERO;
12636 break;
12637 case 0x2f: /* FABS */
12638 case 0x6f: /* FNEG */
12639 need_fpst = false;
12640 break;
12641 case 0x7d: /* FRSQRTE */
12642 case 0x7f: /* FSQRT (vector) */
12643 break;
12644 default:
12645 fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
12646 g_assert_not_reached();
12650 /* Check additional constraints for the scalar encoding */
12651 if (is_scalar) {
12652 if (!is_q) {
12653 unallocated_encoding(s);
12654 return;
12656 /* FRINTxx is only in the vector form */
12657 if (only_in_vector) {
12658 unallocated_encoding(s);
12659 return;
12663 if (!fp_access_check(s)) {
12664 return;
12667 if (need_rmode || need_fpst) {
12668 tcg_fpstatus = get_fpstatus_ptr(true);
12671 if (need_rmode) {
12672 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
12673 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
12676 if (is_scalar) {
12677 TCGv_i32 tcg_op = read_fp_hreg(s, rn);
12678 TCGv_i32 tcg_res = tcg_temp_new_i32();
12680 switch (fpop) {
12681 case 0x1a: /* FCVTNS */
12682 case 0x1b: /* FCVTMS */
12683 case 0x1c: /* FCVTAS */
12684 case 0x3a: /* FCVTPS */
12685 case 0x3b: /* FCVTZS */
12686 gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
12687 break;
12688 case 0x3d: /* FRECPE */
12689 gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
12690 break;
12691 case 0x3f: /* FRECPX */
12692 gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
12693 break;
12694 case 0x5a: /* FCVTNU */
12695 case 0x5b: /* FCVTMU */
12696 case 0x5c: /* FCVTAU */
12697 case 0x7a: /* FCVTPU */
12698 case 0x7b: /* FCVTZU */
12699 gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
12700 break;
12701 case 0x6f: /* FNEG */
12702 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
12703 break;
12704 case 0x7d: /* FRSQRTE */
12705 gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
12706 break;
12707 default:
12708 g_assert_not_reached();
12711 /* limit any sign extension going on */
12712 tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
12713 write_fp_sreg(s, rd, tcg_res);
12715 tcg_temp_free_i32(tcg_res);
12716 tcg_temp_free_i32(tcg_op);
12717 } else {
12718 for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
12719 TCGv_i32 tcg_op = tcg_temp_new_i32();
12720 TCGv_i32 tcg_res = tcg_temp_new_i32();
12722 read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
12724 switch (fpop) {
12725 case 0x1a: /* FCVTNS */
12726 case 0x1b: /* FCVTMS */
12727 case 0x1c: /* FCVTAS */
12728 case 0x3a: /* FCVTPS */
12729 case 0x3b: /* FCVTZS */
12730 gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
12731 break;
12732 case 0x3d: /* FRECPE */
12733 gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
12734 break;
12735 case 0x5a: /* FCVTNU */
12736 case 0x5b: /* FCVTMU */
12737 case 0x5c: /* FCVTAU */
12738 case 0x7a: /* FCVTPU */
12739 case 0x7b: /* FCVTZU */
12740 gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
12741 break;
12742 case 0x18: /* FRINTN */
12743 case 0x19: /* FRINTM */
12744 case 0x38: /* FRINTP */
12745 case 0x39: /* FRINTZ */
12746 case 0x58: /* FRINTA */
12747 case 0x79: /* FRINTI */
12748 gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
12749 break;
12750 case 0x59: /* FRINTX */
12751 gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
12752 break;
12753 case 0x2f: /* FABS */
12754 tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
12755 break;
12756 case 0x6f: /* FNEG */
12757 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
12758 break;
12759 case 0x7d: /* FRSQRTE */
12760 gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
12761 break;
12762 case 0x7f: /* FSQRT */
12763 gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
12764 break;
12765 default:
12766 g_assert_not_reached();
12769 write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
12771 tcg_temp_free_i32(tcg_res);
12772 tcg_temp_free_i32(tcg_op);
12775 clear_vec_high(s, is_q, rd);
12778 if (tcg_rmode) {
12779 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
12780 tcg_temp_free_i32(tcg_rmode);
12783 if (tcg_fpstatus) {
12784 tcg_temp_free_ptr(tcg_fpstatus);
12788 /* AdvSIMD scalar x indexed element
12789 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12790 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12791 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12792 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12793 * AdvSIMD vector x indexed element
12794 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12795 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12796 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12797 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12799 static void disas_simd_indexed(DisasContext *s, uint32_t insn)
12801 /* This encoding has two kinds of instruction:
12802 * normal, where we perform elt x idxelt => elt for each
12803 * element in the vector
12804 * long, where we perform elt x idxelt and generate a result of
12805 * double the width of the input element
12806 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12808 bool is_scalar = extract32(insn, 28, 1);
12809 bool is_q = extract32(insn, 30, 1);
12810 bool u = extract32(insn, 29, 1);
12811 int size = extract32(insn, 22, 2);
12812 int l = extract32(insn, 21, 1);
12813 int m = extract32(insn, 20, 1);
12814 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12815 int rm = extract32(insn, 16, 4);
12816 int opcode = extract32(insn, 12, 4);
12817 int h = extract32(insn, 11, 1);
12818 int rn = extract32(insn, 5, 5);
12819 int rd = extract32(insn, 0, 5);
12820 bool is_long = false;
12821 int is_fp = 0;
12822 bool is_fp16 = false;
12823 int index;
12824 TCGv_ptr fpst;
12826 switch (16 * u + opcode) {
12827 case 0x08: /* MUL */
12828 case 0x10: /* MLA */
12829 case 0x14: /* MLS */
12830 if (is_scalar) {
12831 unallocated_encoding(s);
12832 return;
12834 break;
12835 case 0x02: /* SMLAL, SMLAL2 */
12836 case 0x12: /* UMLAL, UMLAL2 */
12837 case 0x06: /* SMLSL, SMLSL2 */
12838 case 0x16: /* UMLSL, UMLSL2 */
12839 case 0x0a: /* SMULL, SMULL2 */
12840 case 0x1a: /* UMULL, UMULL2 */
12841 if (is_scalar) {
12842 unallocated_encoding(s);
12843 return;
12845 is_long = true;
12846 break;
12847 case 0x03: /* SQDMLAL, SQDMLAL2 */
12848 case 0x07: /* SQDMLSL, SQDMLSL2 */
12849 case 0x0b: /* SQDMULL, SQDMULL2 */
12850 is_long = true;
12851 break;
12852 case 0x0c: /* SQDMULH */
12853 case 0x0d: /* SQRDMULH */
12854 break;
12855 case 0x01: /* FMLA */
12856 case 0x05: /* FMLS */
12857 case 0x09: /* FMUL */
12858 case 0x19: /* FMULX */
12859 is_fp = 1;
12860 break;
12861 case 0x1d: /* SQRDMLAH */
12862 case 0x1f: /* SQRDMLSH */
12863 if (!dc_isar_feature(aa64_rdm, s)) {
12864 unallocated_encoding(s);
12865 return;
12867 break;
12868 case 0x0e: /* SDOT */
12869 case 0x1e: /* UDOT */
12870 if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) {
12871 unallocated_encoding(s);
12872 return;
12874 break;
12875 case 0x11: /* FCMLA #0 */
12876 case 0x13: /* FCMLA #90 */
12877 case 0x15: /* FCMLA #180 */
12878 case 0x17: /* FCMLA #270 */
12879 if (is_scalar || !dc_isar_feature(aa64_fcma, s)) {
12880 unallocated_encoding(s);
12881 return;
12883 is_fp = 2;
12884 break;
12885 case 0x00: /* FMLAL */
12886 case 0x04: /* FMLSL */
12887 case 0x18: /* FMLAL2 */
12888 case 0x1c: /* FMLSL2 */
12889 if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
12890 unallocated_encoding(s);
12891 return;
12893 size = MO_16;
12894 /* is_fp, but we pass cpu_env not fp_status. */
12895 break;
12896 default:
12897 unallocated_encoding(s);
12898 return;
12901 switch (is_fp) {
12902 case 1: /* normal fp */
12903 /* convert insn encoded size to MemOp size */
12904 switch (size) {
12905 case 0: /* half-precision */
12906 size = MO_16;
12907 is_fp16 = true;
12908 break;
12909 case MO_32: /* single precision */
12910 case MO_64: /* double precision */
12911 break;
12912 default:
12913 unallocated_encoding(s);
12914 return;
12916 break;
12918 case 2: /* complex fp */
12919 /* Each indexable element is a complex pair. */
12920 size += 1;
12921 switch (size) {
12922 case MO_32:
12923 if (h && !is_q) {
12924 unallocated_encoding(s);
12925 return;
12927 is_fp16 = true;
12928 break;
12929 case MO_64:
12930 break;
12931 default:
12932 unallocated_encoding(s);
12933 return;
12935 break;
12937 default: /* integer */
12938 switch (size) {
12939 case MO_8:
12940 case MO_64:
12941 unallocated_encoding(s);
12942 return;
12944 break;
12946 if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) {
12947 unallocated_encoding(s);
12948 return;
12951 /* Given MemOp size, adjust register and indexing. */
12952 switch (size) {
12953 case MO_16:
12954 index = h << 2 | l << 1 | m;
12955 break;
12956 case MO_32:
12957 index = h << 1 | l;
12958 rm |= m << 4;
12959 break;
12960 case MO_64:
12961 if (l || !is_q) {
12962 unallocated_encoding(s);
12963 return;
12965 index = h;
12966 rm |= m << 4;
12967 break;
12968 default:
12969 g_assert_not_reached();
12972 if (!fp_access_check(s)) {
12973 return;
12976 if (is_fp) {
12977 fpst = get_fpstatus_ptr(is_fp16);
12978 } else {
12979 fpst = NULL;
12982 switch (16 * u + opcode) {
12983 case 0x0e: /* SDOT */
12984 case 0x1e: /* UDOT */
12985 gen_gvec_op3_ool(s, is_q, rd, rn, rm, index,
12986 u ? gen_helper_gvec_udot_idx_b
12987 : gen_helper_gvec_sdot_idx_b);
12988 return;
12989 case 0x11: /* FCMLA #0 */
12990 case 0x13: /* FCMLA #90 */
12991 case 0x15: /* FCMLA #180 */
12992 case 0x17: /* FCMLA #270 */
12994 int rot = extract32(insn, 13, 2);
12995 int data = (index << 2) | rot;
12996 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
12997 vec_full_reg_offset(s, rn),
12998 vec_full_reg_offset(s, rm), fpst,
12999 is_q ? 16 : 8, vec_full_reg_size(s), data,
13000 size == MO_64
13001 ? gen_helper_gvec_fcmlas_idx
13002 : gen_helper_gvec_fcmlah_idx);
13003 tcg_temp_free_ptr(fpst);
13005 return;
13007 case 0x00: /* FMLAL */
13008 case 0x04: /* FMLSL */
13009 case 0x18: /* FMLAL2 */
13010 case 0x1c: /* FMLSL2 */
13012 int is_s = extract32(opcode, 2, 1);
13013 int is_2 = u;
13014 int data = (index << 2) | (is_2 << 1) | is_s;
13015 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
13016 vec_full_reg_offset(s, rn),
13017 vec_full_reg_offset(s, rm), cpu_env,
13018 is_q ? 16 : 8, vec_full_reg_size(s),
13019 data, gen_helper_gvec_fmlal_idx_a64);
13021 return;
13024 if (size == 3) {
13025 TCGv_i64 tcg_idx = tcg_temp_new_i64();
13026 int pass;
13028 assert(is_fp && is_q && !is_long);
13030 read_vec_element(s, tcg_idx, rm, index, MO_64);
13032 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
13033 TCGv_i64 tcg_op = tcg_temp_new_i64();
13034 TCGv_i64 tcg_res = tcg_temp_new_i64();
13036 read_vec_element(s, tcg_op, rn, pass, MO_64);
13038 switch (16 * u + opcode) {
13039 case 0x05: /* FMLS */
13040 /* As usual for ARM, separate negation for fused multiply-add */
13041 gen_helper_vfp_negd(tcg_op, tcg_op);
13042 /* fall through */
13043 case 0x01: /* FMLA */
13044 read_vec_element(s, tcg_res, rd, pass, MO_64);
13045 gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
13046 break;
13047 case 0x09: /* FMUL */
13048 gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst);
13049 break;
13050 case 0x19: /* FMULX */
13051 gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst);
13052 break;
13053 default:
13054 g_assert_not_reached();
13057 write_vec_element(s, tcg_res, rd, pass, MO_64);
13058 tcg_temp_free_i64(tcg_op);
13059 tcg_temp_free_i64(tcg_res);
13062 tcg_temp_free_i64(tcg_idx);
13063 clear_vec_high(s, !is_scalar, rd);
13064 } else if (!is_long) {
13065 /* 32 bit floating point, or 16 or 32 bit integer.
13066 * For the 16 bit scalar case we use the usual Neon helpers and
13067 * rely on the fact that 0 op 0 == 0 with no side effects.
13069 TCGv_i32 tcg_idx = tcg_temp_new_i32();
13070 int pass, maxpasses;
13072 if (is_scalar) {
13073 maxpasses = 1;
13074 } else {
13075 maxpasses = is_q ? 4 : 2;
13078 read_vec_element_i32(s, tcg_idx, rm, index, size);
13080 if (size == 1 && !is_scalar) {
13081 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13082 * the index into both halves of the 32 bit tcg_idx and then use
13083 * the usual Neon helpers.
13085 tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
13088 for (pass = 0; pass < maxpasses; pass++) {
13089 TCGv_i32 tcg_op = tcg_temp_new_i32();
13090 TCGv_i32 tcg_res = tcg_temp_new_i32();
13092 read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
13094 switch (16 * u + opcode) {
13095 case 0x08: /* MUL */
13096 case 0x10: /* MLA */
13097 case 0x14: /* MLS */
13099 static NeonGenTwoOpFn * const fns[2][2] = {
13100 { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
13101 { tcg_gen_add_i32, tcg_gen_sub_i32 },
13103 NeonGenTwoOpFn *genfn;
13104 bool is_sub = opcode == 0x4;
13106 if (size == 1) {
13107 gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx);
13108 } else {
13109 tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx);
13111 if (opcode == 0x8) {
13112 break;
13114 read_vec_element_i32(s, tcg_op, rd, pass, MO_32);
13115 genfn = fns[size - 1][is_sub];
13116 genfn(tcg_res, tcg_op, tcg_res);
13117 break;
13119 case 0x05: /* FMLS */
13120 case 0x01: /* FMLA */
13121 read_vec_element_i32(s, tcg_res, rd, pass,
13122 is_scalar ? size : MO_32);
13123 switch (size) {
13124 case 1:
13125 if (opcode == 0x5) {
13126 /* As usual for ARM, separate negation for fused
13127 * multiply-add */
13128 tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
13130 if (is_scalar) {
13131 gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
13132 tcg_res, fpst);
13133 } else {
13134 gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
13135 tcg_res, fpst);
13137 break;
13138 case 2:
13139 if (opcode == 0x5) {
13140 /* As usual for ARM, separate negation for
13141 * fused multiply-add */
13142 tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000);
13144 gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx,
13145 tcg_res, fpst);
13146 break;
13147 default:
13148 g_assert_not_reached();
13150 break;
13151 case 0x09: /* FMUL */
13152 switch (size) {
13153 case 1:
13154 if (is_scalar) {
13155 gen_helper_advsimd_mulh(tcg_res, tcg_op,
13156 tcg_idx, fpst);
13157 } else {
13158 gen_helper_advsimd_mul2h(tcg_res, tcg_op,
13159 tcg_idx, fpst);
13161 break;
13162 case 2:
13163 gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
13164 break;
13165 default:
13166 g_assert_not_reached();
13168 break;
13169 case 0x19: /* FMULX */
13170 switch (size) {
13171 case 1:
13172 if (is_scalar) {
13173 gen_helper_advsimd_mulxh(tcg_res, tcg_op,
13174 tcg_idx, fpst);
13175 } else {
13176 gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
13177 tcg_idx, fpst);
13179 break;
13180 case 2:
13181 gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
13182 break;
13183 default:
13184 g_assert_not_reached();
13186 break;
13187 case 0x0c: /* SQDMULH */
13188 if (size == 1) {
13189 gen_helper_neon_qdmulh_s16(tcg_res, cpu_env,
13190 tcg_op, tcg_idx);
13191 } else {
13192 gen_helper_neon_qdmulh_s32(tcg_res, cpu_env,
13193 tcg_op, tcg_idx);
13195 break;
13196 case 0x0d: /* SQRDMULH */
13197 if (size == 1) {
13198 gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
13199 tcg_op, tcg_idx);
13200 } else {
13201 gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
13202 tcg_op, tcg_idx);
13204 break;
13205 case 0x1d: /* SQRDMLAH */
13206 read_vec_element_i32(s, tcg_res, rd, pass,
13207 is_scalar ? size : MO_32);
13208 if (size == 1) {
13209 gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env,
13210 tcg_op, tcg_idx, tcg_res);
13211 } else {
13212 gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env,
13213 tcg_op, tcg_idx, tcg_res);
13215 break;
13216 case 0x1f: /* SQRDMLSH */
13217 read_vec_element_i32(s, tcg_res, rd, pass,
13218 is_scalar ? size : MO_32);
13219 if (size == 1) {
13220 gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env,
13221 tcg_op, tcg_idx, tcg_res);
13222 } else {
13223 gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env,
13224 tcg_op, tcg_idx, tcg_res);
13226 break;
13227 default:
13228 g_assert_not_reached();
13231 if (is_scalar) {
13232 write_fp_sreg(s, rd, tcg_res);
13233 } else {
13234 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
13237 tcg_temp_free_i32(tcg_op);
13238 tcg_temp_free_i32(tcg_res);
13241 tcg_temp_free_i32(tcg_idx);
13242 clear_vec_high(s, is_q, rd);
13243 } else {
13244 /* long ops: 16x16->32 or 32x32->64 */
13245 TCGv_i64 tcg_res[2];
13246 int pass;
13247 bool satop = extract32(opcode, 0, 1);
13248 MemOp memop = MO_32;
13250 if (satop || !u) {
13251 memop |= MO_SIGN;
13254 if (size == 2) {
13255 TCGv_i64 tcg_idx = tcg_temp_new_i64();
13257 read_vec_element(s, tcg_idx, rm, index, memop);
13259 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
13260 TCGv_i64 tcg_op = tcg_temp_new_i64();
13261 TCGv_i64 tcg_passres;
13262 int passelt;
13264 if (is_scalar) {
13265 passelt = 0;
13266 } else {
13267 passelt = pass + (is_q * 2);
13270 read_vec_element(s, tcg_op, rn, passelt, memop);
13272 tcg_res[pass] = tcg_temp_new_i64();
13274 if (opcode == 0xa || opcode == 0xb) {
13275 /* Non-accumulating ops */
13276 tcg_passres = tcg_res[pass];
13277 } else {
13278 tcg_passres = tcg_temp_new_i64();
13281 tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx);
13282 tcg_temp_free_i64(tcg_op);
13284 if (satop) {
13285 /* saturating, doubling */
13286 gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
13287 tcg_passres, tcg_passres);
13290 if (opcode == 0xa || opcode == 0xb) {
13291 continue;
13294 /* Accumulating op: handle accumulate step */
13295 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
13297 switch (opcode) {
13298 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13299 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
13300 break;
13301 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13302 tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
13303 break;
13304 case 0x7: /* SQDMLSL, SQDMLSL2 */
13305 tcg_gen_neg_i64(tcg_passres, tcg_passres);
13306 /* fall through */
13307 case 0x3: /* SQDMLAL, SQDMLAL2 */
13308 gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
13309 tcg_res[pass],
13310 tcg_passres);
13311 break;
13312 default:
13313 g_assert_not_reached();
13315 tcg_temp_free_i64(tcg_passres);
13317 tcg_temp_free_i64(tcg_idx);
13319 clear_vec_high(s, !is_scalar, rd);
13320 } else {
13321 TCGv_i32 tcg_idx = tcg_temp_new_i32();
13323 assert(size == 1);
13324 read_vec_element_i32(s, tcg_idx, rm, index, size);
13326 if (!is_scalar) {
13327 /* The simplest way to handle the 16x16 indexed ops is to
13328 * duplicate the index into both halves of the 32 bit tcg_idx
13329 * and then use the usual Neon helpers.
13331 tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
13334 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
13335 TCGv_i32 tcg_op = tcg_temp_new_i32();
13336 TCGv_i64 tcg_passres;
13338 if (is_scalar) {
13339 read_vec_element_i32(s, tcg_op, rn, pass, size);
13340 } else {
13341 read_vec_element_i32(s, tcg_op, rn,
13342 pass + (is_q * 2), MO_32);
13345 tcg_res[pass] = tcg_temp_new_i64();
13347 if (opcode == 0xa || opcode == 0xb) {
13348 /* Non-accumulating ops */
13349 tcg_passres = tcg_res[pass];
13350 } else {
13351 tcg_passres = tcg_temp_new_i64();
13354 if (memop & MO_SIGN) {
13355 gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx);
13356 } else {
13357 gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx);
13359 if (satop) {
13360 gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
13361 tcg_passres, tcg_passres);
13363 tcg_temp_free_i32(tcg_op);
13365 if (opcode == 0xa || opcode == 0xb) {
13366 continue;
13369 /* Accumulating op: handle accumulate step */
13370 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
13372 switch (opcode) {
13373 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13374 gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass],
13375 tcg_passres);
13376 break;
13377 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13378 gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass],
13379 tcg_passres);
13380 break;
13381 case 0x7: /* SQDMLSL, SQDMLSL2 */
13382 gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
13383 /* fall through */
13384 case 0x3: /* SQDMLAL, SQDMLAL2 */
13385 gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
13386 tcg_res[pass],
13387 tcg_passres);
13388 break;
13389 default:
13390 g_assert_not_reached();
13392 tcg_temp_free_i64(tcg_passres);
13394 tcg_temp_free_i32(tcg_idx);
13396 if (is_scalar) {
13397 tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]);
13401 if (is_scalar) {
13402 tcg_res[1] = tcg_const_i64(0);
13405 for (pass = 0; pass < 2; pass++) {
13406 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
13407 tcg_temp_free_i64(tcg_res[pass]);
13411 if (fpst) {
13412 tcg_temp_free_ptr(fpst);
13416 /* Crypto AES
13417 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13418 * +-----------------+------+-----------+--------+-----+------+------+
13419 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13420 * +-----------------+------+-----------+--------+-----+------+------+
13422 static void disas_crypto_aes(DisasContext *s, uint32_t insn)
13424 int size = extract32(insn, 22, 2);
13425 int opcode = extract32(insn, 12, 5);
13426 int rn = extract32(insn, 5, 5);
13427 int rd = extract32(insn, 0, 5);
13428 int decrypt;
13429 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
13430 TCGv_i32 tcg_decrypt;
13431 CryptoThreeOpIntFn *genfn;
13433 if (!dc_isar_feature(aa64_aes, s) || size != 0) {
13434 unallocated_encoding(s);
13435 return;
13438 switch (opcode) {
13439 case 0x4: /* AESE */
13440 decrypt = 0;
13441 genfn = gen_helper_crypto_aese;
13442 break;
13443 case 0x6: /* AESMC */
13444 decrypt = 0;
13445 genfn = gen_helper_crypto_aesmc;
13446 break;
13447 case 0x5: /* AESD */
13448 decrypt = 1;
13449 genfn = gen_helper_crypto_aese;
13450 break;
13451 case 0x7: /* AESIMC */
13452 decrypt = 1;
13453 genfn = gen_helper_crypto_aesmc;
13454 break;
13455 default:
13456 unallocated_encoding(s);
13457 return;
13460 if (!fp_access_check(s)) {
13461 return;
13464 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13465 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13466 tcg_decrypt = tcg_const_i32(decrypt);
13468 genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt);
13470 tcg_temp_free_ptr(tcg_rd_ptr);
13471 tcg_temp_free_ptr(tcg_rn_ptr);
13472 tcg_temp_free_i32(tcg_decrypt);
13475 /* Crypto three-reg SHA
13476 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13477 * +-----------------+------+---+------+---+--------+-----+------+------+
13478 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13479 * +-----------------+------+---+------+---+--------+-----+------+------+
13481 static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
13483 int size = extract32(insn, 22, 2);
13484 int opcode = extract32(insn, 12, 3);
13485 int rm = extract32(insn, 16, 5);
13486 int rn = extract32(insn, 5, 5);
13487 int rd = extract32(insn, 0, 5);
13488 CryptoThreeOpFn *genfn;
13489 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
13490 bool feature;
13492 if (size != 0) {
13493 unallocated_encoding(s);
13494 return;
13497 switch (opcode) {
13498 case 0: /* SHA1C */
13499 case 1: /* SHA1P */
13500 case 2: /* SHA1M */
13501 case 3: /* SHA1SU0 */
13502 genfn = NULL;
13503 feature = dc_isar_feature(aa64_sha1, s);
13504 break;
13505 case 4: /* SHA256H */
13506 genfn = gen_helper_crypto_sha256h;
13507 feature = dc_isar_feature(aa64_sha256, s);
13508 break;
13509 case 5: /* SHA256H2 */
13510 genfn = gen_helper_crypto_sha256h2;
13511 feature = dc_isar_feature(aa64_sha256, s);
13512 break;
13513 case 6: /* SHA256SU1 */
13514 genfn = gen_helper_crypto_sha256su1;
13515 feature = dc_isar_feature(aa64_sha256, s);
13516 break;
13517 default:
13518 unallocated_encoding(s);
13519 return;
13522 if (!feature) {
13523 unallocated_encoding(s);
13524 return;
13527 if (!fp_access_check(s)) {
13528 return;
13531 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13532 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13533 tcg_rm_ptr = vec_full_reg_ptr(s, rm);
13535 if (genfn) {
13536 genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
13537 } else {
13538 TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
13540 gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
13541 tcg_rm_ptr, tcg_opcode);
13542 tcg_temp_free_i32(tcg_opcode);
13545 tcg_temp_free_ptr(tcg_rd_ptr);
13546 tcg_temp_free_ptr(tcg_rn_ptr);
13547 tcg_temp_free_ptr(tcg_rm_ptr);
13550 /* Crypto two-reg SHA
13551 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13552 * +-----------------+------+-----------+--------+-----+------+------+
13553 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13554 * +-----------------+------+-----------+--------+-----+------+------+
13556 static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
13558 int size = extract32(insn, 22, 2);
13559 int opcode = extract32(insn, 12, 5);
13560 int rn = extract32(insn, 5, 5);
13561 int rd = extract32(insn, 0, 5);
13562 CryptoTwoOpFn *genfn;
13563 bool feature;
13564 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
13566 if (size != 0) {
13567 unallocated_encoding(s);
13568 return;
13571 switch (opcode) {
13572 case 0: /* SHA1H */
13573 feature = dc_isar_feature(aa64_sha1, s);
13574 genfn = gen_helper_crypto_sha1h;
13575 break;
13576 case 1: /* SHA1SU1 */
13577 feature = dc_isar_feature(aa64_sha1, s);
13578 genfn = gen_helper_crypto_sha1su1;
13579 break;
13580 case 2: /* SHA256SU0 */
13581 feature = dc_isar_feature(aa64_sha256, s);
13582 genfn = gen_helper_crypto_sha256su0;
13583 break;
13584 default:
13585 unallocated_encoding(s);
13586 return;
13589 if (!feature) {
13590 unallocated_encoding(s);
13591 return;
13594 if (!fp_access_check(s)) {
13595 return;
13598 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13599 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13601 genfn(tcg_rd_ptr, tcg_rn_ptr);
13603 tcg_temp_free_ptr(tcg_rd_ptr);
13604 tcg_temp_free_ptr(tcg_rn_ptr);
13607 /* Crypto three-reg SHA512
13608 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13609 * +-----------------------+------+---+---+-----+--------+------+------+
13610 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13611 * +-----------------------+------+---+---+-----+--------+------+------+
13613 static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
13615 int opcode = extract32(insn, 10, 2);
13616 int o = extract32(insn, 14, 1);
13617 int rm = extract32(insn, 16, 5);
13618 int rn = extract32(insn, 5, 5);
13619 int rd = extract32(insn, 0, 5);
13620 bool feature;
13621 CryptoThreeOpFn *genfn;
13623 if (o == 0) {
13624 switch (opcode) {
13625 case 0: /* SHA512H */
13626 feature = dc_isar_feature(aa64_sha512, s);
13627 genfn = gen_helper_crypto_sha512h;
13628 break;
13629 case 1: /* SHA512H2 */
13630 feature = dc_isar_feature(aa64_sha512, s);
13631 genfn = gen_helper_crypto_sha512h2;
13632 break;
13633 case 2: /* SHA512SU1 */
13634 feature = dc_isar_feature(aa64_sha512, s);
13635 genfn = gen_helper_crypto_sha512su1;
13636 break;
13637 case 3: /* RAX1 */
13638 feature = dc_isar_feature(aa64_sha3, s);
13639 genfn = NULL;
13640 break;
13641 default:
13642 g_assert_not_reached();
13644 } else {
13645 switch (opcode) {
13646 case 0: /* SM3PARTW1 */
13647 feature = dc_isar_feature(aa64_sm3, s);
13648 genfn = gen_helper_crypto_sm3partw1;
13649 break;
13650 case 1: /* SM3PARTW2 */
13651 feature = dc_isar_feature(aa64_sm3, s);
13652 genfn = gen_helper_crypto_sm3partw2;
13653 break;
13654 case 2: /* SM4EKEY */
13655 feature = dc_isar_feature(aa64_sm4, s);
13656 genfn = gen_helper_crypto_sm4ekey;
13657 break;
13658 default:
13659 unallocated_encoding(s);
13660 return;
13664 if (!feature) {
13665 unallocated_encoding(s);
13666 return;
13669 if (!fp_access_check(s)) {
13670 return;
13673 if (genfn) {
13674 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
13676 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13677 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13678 tcg_rm_ptr = vec_full_reg_ptr(s, rm);
13680 genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
13682 tcg_temp_free_ptr(tcg_rd_ptr);
13683 tcg_temp_free_ptr(tcg_rn_ptr);
13684 tcg_temp_free_ptr(tcg_rm_ptr);
13685 } else {
13686 TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
13687 int pass;
13689 tcg_op1 = tcg_temp_new_i64();
13690 tcg_op2 = tcg_temp_new_i64();
13691 tcg_res[0] = tcg_temp_new_i64();
13692 tcg_res[1] = tcg_temp_new_i64();
13694 for (pass = 0; pass < 2; pass++) {
13695 read_vec_element(s, tcg_op1, rn, pass, MO_64);
13696 read_vec_element(s, tcg_op2, rm, pass, MO_64);
13698 tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1);
13699 tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
13701 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
13702 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
13704 tcg_temp_free_i64(tcg_op1);
13705 tcg_temp_free_i64(tcg_op2);
13706 tcg_temp_free_i64(tcg_res[0]);
13707 tcg_temp_free_i64(tcg_res[1]);
13711 /* Crypto two-reg SHA512
13712 * 31 12 11 10 9 5 4 0
13713 * +-----------------------------------------+--------+------+------+
13714 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13715 * +-----------------------------------------+--------+------+------+
13717 static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
13719 int opcode = extract32(insn, 10, 2);
13720 int rn = extract32(insn, 5, 5);
13721 int rd = extract32(insn, 0, 5);
13722 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
13723 bool feature;
13724 CryptoTwoOpFn *genfn;
13726 switch (opcode) {
13727 case 0: /* SHA512SU0 */
13728 feature = dc_isar_feature(aa64_sha512, s);
13729 genfn = gen_helper_crypto_sha512su0;
13730 break;
13731 case 1: /* SM4E */
13732 feature = dc_isar_feature(aa64_sm4, s);
13733 genfn = gen_helper_crypto_sm4e;
13734 break;
13735 default:
13736 unallocated_encoding(s);
13737 return;
13740 if (!feature) {
13741 unallocated_encoding(s);
13742 return;
13745 if (!fp_access_check(s)) {
13746 return;
13749 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13750 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13752 genfn(tcg_rd_ptr, tcg_rn_ptr);
13754 tcg_temp_free_ptr(tcg_rd_ptr);
13755 tcg_temp_free_ptr(tcg_rn_ptr);
13758 /* Crypto four-register
13759 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13760 * +-------------------+-----+------+---+------+------+------+
13761 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13762 * +-------------------+-----+------+---+------+------+------+
13764 static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
13766 int op0 = extract32(insn, 21, 2);
13767 int rm = extract32(insn, 16, 5);
13768 int ra = extract32(insn, 10, 5);
13769 int rn = extract32(insn, 5, 5);
13770 int rd = extract32(insn, 0, 5);
13771 bool feature;
13773 switch (op0) {
13774 case 0: /* EOR3 */
13775 case 1: /* BCAX */
13776 feature = dc_isar_feature(aa64_sha3, s);
13777 break;
13778 case 2: /* SM3SS1 */
13779 feature = dc_isar_feature(aa64_sm3, s);
13780 break;
13781 default:
13782 unallocated_encoding(s);
13783 return;
13786 if (!feature) {
13787 unallocated_encoding(s);
13788 return;
13791 if (!fp_access_check(s)) {
13792 return;
13795 if (op0 < 2) {
13796 TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2];
13797 int pass;
13799 tcg_op1 = tcg_temp_new_i64();
13800 tcg_op2 = tcg_temp_new_i64();
13801 tcg_op3 = tcg_temp_new_i64();
13802 tcg_res[0] = tcg_temp_new_i64();
13803 tcg_res[1] = tcg_temp_new_i64();
13805 for (pass = 0; pass < 2; pass++) {
13806 read_vec_element(s, tcg_op1, rn, pass, MO_64);
13807 read_vec_element(s, tcg_op2, rm, pass, MO_64);
13808 read_vec_element(s, tcg_op3, ra, pass, MO_64);
13810 if (op0 == 0) {
13811 /* EOR3 */
13812 tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3);
13813 } else {
13814 /* BCAX */
13815 tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3);
13817 tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
13819 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
13820 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
13822 tcg_temp_free_i64(tcg_op1);
13823 tcg_temp_free_i64(tcg_op2);
13824 tcg_temp_free_i64(tcg_op3);
13825 tcg_temp_free_i64(tcg_res[0]);
13826 tcg_temp_free_i64(tcg_res[1]);
13827 } else {
13828 TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero;
13830 tcg_op1 = tcg_temp_new_i32();
13831 tcg_op2 = tcg_temp_new_i32();
13832 tcg_op3 = tcg_temp_new_i32();
13833 tcg_res = tcg_temp_new_i32();
13834 tcg_zero = tcg_const_i32(0);
13836 read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);
13837 read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);
13838 read_vec_element_i32(s, tcg_op3, ra, 3, MO_32);
13840 tcg_gen_rotri_i32(tcg_res, tcg_op1, 20);
13841 tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2);
13842 tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3);
13843 tcg_gen_rotri_i32(tcg_res, tcg_res, 25);
13845 write_vec_element_i32(s, tcg_zero, rd, 0, MO_32);
13846 write_vec_element_i32(s, tcg_zero, rd, 1, MO_32);
13847 write_vec_element_i32(s, tcg_zero, rd, 2, MO_32);
13848 write_vec_element_i32(s, tcg_res, rd, 3, MO_32);
13850 tcg_temp_free_i32(tcg_op1);
13851 tcg_temp_free_i32(tcg_op2);
13852 tcg_temp_free_i32(tcg_op3);
13853 tcg_temp_free_i32(tcg_res);
13854 tcg_temp_free_i32(tcg_zero);
13858 /* Crypto XAR
13859 * 31 21 20 16 15 10 9 5 4 0
13860 * +-----------------------+------+--------+------+------+
13861 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13862 * +-----------------------+------+--------+------+------+
13864 static void disas_crypto_xar(DisasContext *s, uint32_t insn)
13866 int rm = extract32(insn, 16, 5);
13867 int imm6 = extract32(insn, 10, 6);
13868 int rn = extract32(insn, 5, 5);
13869 int rd = extract32(insn, 0, 5);
13870 TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
13871 int pass;
13873 if (!dc_isar_feature(aa64_sha3, s)) {
13874 unallocated_encoding(s);
13875 return;
13878 if (!fp_access_check(s)) {
13879 return;
13882 tcg_op1 = tcg_temp_new_i64();
13883 tcg_op2 = tcg_temp_new_i64();
13884 tcg_res[0] = tcg_temp_new_i64();
13885 tcg_res[1] = tcg_temp_new_i64();
13887 for (pass = 0; pass < 2; pass++) {
13888 read_vec_element(s, tcg_op1, rn, pass, MO_64);
13889 read_vec_element(s, tcg_op2, rm, pass, MO_64);
13891 tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);
13892 tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6);
13894 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
13895 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
13897 tcg_temp_free_i64(tcg_op1);
13898 tcg_temp_free_i64(tcg_op2);
13899 tcg_temp_free_i64(tcg_res[0]);
13900 tcg_temp_free_i64(tcg_res[1]);
13903 /* Crypto three-reg imm2
13904 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13905 * +-----------------------+------+-----+------+--------+------+------+
13906 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13907 * +-----------------------+------+-----+------+--------+------+------+
13909 static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
13911 int opcode = extract32(insn, 10, 2);
13912 int imm2 = extract32(insn, 12, 2);
13913 int rm = extract32(insn, 16, 5);
13914 int rn = extract32(insn, 5, 5);
13915 int rd = extract32(insn, 0, 5);
13916 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
13917 TCGv_i32 tcg_imm2, tcg_opcode;
13919 if (!dc_isar_feature(aa64_sm3, s)) {
13920 unallocated_encoding(s);
13921 return;
13924 if (!fp_access_check(s)) {
13925 return;
13928 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13929 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13930 tcg_rm_ptr = vec_full_reg_ptr(s, rm);
13931 tcg_imm2 = tcg_const_i32(imm2);
13932 tcg_opcode = tcg_const_i32(opcode);
13934 gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2,
13935 tcg_opcode);
13937 tcg_temp_free_ptr(tcg_rd_ptr);
13938 tcg_temp_free_ptr(tcg_rn_ptr);
13939 tcg_temp_free_ptr(tcg_rm_ptr);
13940 tcg_temp_free_i32(tcg_imm2);
13941 tcg_temp_free_i32(tcg_opcode);
13944 /* C3.6 Data processing - SIMD, inc Crypto
13946 * As the decode gets a little complex we are using a table based
13947 * approach for this part of the decode.
13949 static const AArch64DecodeTable data_proc_simd[] = {
13950 /* pattern , mask , fn */
13951 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same },
13952 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra },
13953 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff },
13954 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
13955 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
13956 { 0x0e000400, 0x9fe08400, disas_simd_copy },
13957 { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */
13958 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13959 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm },
13960 { 0x0f000400, 0x9f800400, disas_simd_shift_imm },
13961 { 0x0e000000, 0xbf208c00, disas_simd_tb },
13962 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
13963 { 0x2e000000, 0xbf208400, disas_simd_ext },
13964 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same },
13965 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra },
13966 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
13967 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
13968 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },
13969 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy },
13970 { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
13971 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
13972 { 0x4e280800, 0xff3e0c00, disas_crypto_aes },
13973 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
13974 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
13975 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 },
13976 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 },
13977 { 0xce000000, 0xff808000, disas_crypto_four_reg },
13978 { 0xce800000, 0xffe00000, disas_crypto_xar },
13979 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
13980 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
13981 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
13982 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 },
13983 { 0x00000000, 0x00000000, NULL }
13986 static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
13988 /* Note that this is called with all non-FP cases from
13989 * table C3-6 so it must UNDEF for entries not specifically
13990 * allocated to instructions in that table.
13992 AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
13993 if (fn) {
13994 fn(s, insn);
13995 } else {
13996 unallocated_encoding(s);
14000 /* C3.6 Data processing - SIMD and floating point */
14001 static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
14003 if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
14004 disas_data_proc_fp(s, insn);
14005 } else {
14006 /* SIMD, including crypto */
14007 disas_data_proc_simd(s, insn);
14012 * is_guarded_page:
14013 * @env: The cpu environment
14014 * @s: The DisasContext
14016 * Return true if the page is guarded.
14018 static bool is_guarded_page(CPUARMState *env, DisasContext *s)
14020 #ifdef CONFIG_USER_ONLY
14021 return false; /* FIXME */
14022 #else
14023 uint64_t addr = s->base.pc_first;
14024 int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx);
14025 unsigned int index = tlb_index(env, mmu_idx, addr);
14026 CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
14029 * We test this immediately after reading an insn, which means
14030 * that any normal page must be in the TLB. The only exception
14031 * would be for executing from flash or device memory, which
14032 * does not retain the TLB entry.
14034 * FIXME: Assume false for those, for now. We could use
14035 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14036 * table entry even for that case.
14038 return (tlb_hit(entry->addr_code, addr) &&
14039 env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0);
14040 #endif
14044 * btype_destination_ok:
14045 * @insn: The instruction at the branch destination
14046 * @bt: SCTLR_ELx.BT
14047 * @btype: PSTATE.BTYPE, and is non-zero
14049 * On a guarded page, there are a limited number of insns
14050 * that may be present at the branch target:
14051 * - branch target identifiers,
14052 * - paciasp, pacibsp,
14053 * - BRK insn
14054 * - HLT insn
14055 * Anything else causes a Branch Target Exception.
14057 * Return true if the branch is compatible, false to raise BTITRAP.
14059 static bool btype_destination_ok(uint32_t insn, bool bt, int btype)
14061 if ((insn & 0xfffff01fu) == 0xd503201fu) {
14062 /* HINT space */
14063 switch (extract32(insn, 5, 7)) {
14064 case 0b011001: /* PACIASP */
14065 case 0b011011: /* PACIBSP */
14067 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14068 * with btype == 3. Otherwise all btype are ok.
14070 return !bt || btype != 3;
14071 case 0b100000: /* BTI */
14072 /* Not compatible with any btype. */
14073 return false;
14074 case 0b100010: /* BTI c */
14075 /* Not compatible with btype == 3 */
14076 return btype != 3;
14077 case 0b100100: /* BTI j */
14078 /* Not compatible with btype == 2 */
14079 return btype != 2;
14080 case 0b100110: /* BTI jc */
14081 /* Compatible with any btype. */
14082 return true;
14084 } else {
14085 switch (insn & 0xffe0001fu) {
14086 case 0xd4200000u: /* BRK */
14087 case 0xd4400000u: /* HLT */
14088 /* Give priority to the breakpoint exception. */
14089 return true;
14092 return false;
14095 /* C3.1 A64 instruction index by encoding */
14096 static void disas_a64_insn(CPUARMState *env, DisasContext *s)
14098 uint32_t insn;
14100 s->pc_curr = s->base.pc_next;
14101 insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
14102 s->insn = insn;
14103 s->base.pc_next += 4;
14105 s->fp_access_checked = false;
14107 if (dc_isar_feature(aa64_bti, s)) {
14108 if (s->base.num_insns == 1) {
14110 * At the first insn of the TB, compute s->guarded_page.
14111 * We delayed computing this until successfully reading
14112 * the first insn of the TB, above. This (mostly) ensures
14113 * that the softmmu tlb entry has been populated, and the
14114 * page table GP bit is available.
14116 * Note that we need to compute this even if btype == 0,
14117 * because this value is used for BR instructions later
14118 * where ENV is not available.
14120 s->guarded_page = is_guarded_page(env, s);
14122 /* First insn can have btype set to non-zero. */
14123 tcg_debug_assert(s->btype >= 0);
14126 * Note that the Branch Target Exception has fairly high
14127 * priority -- below debugging exceptions but above most
14128 * everything else. This allows us to handle this now
14129 * instead of waiting until the insn is otherwise decoded.
14131 if (s->btype != 0
14132 && s->guarded_page
14133 && !btype_destination_ok(insn, s->bt, s->btype)) {
14134 gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
14135 syn_btitrap(s->btype),
14136 default_exception_el(s));
14137 return;
14139 } else {
14140 /* Not the first insn: btype must be 0. */
14141 tcg_debug_assert(s->btype == 0);
14145 switch (extract32(insn, 25, 4)) {
14146 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14147 unallocated_encoding(s);
14148 break;
14149 case 0x2:
14150 if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) {
14151 unallocated_encoding(s);
14153 break;
14154 case 0x8: case 0x9: /* Data processing - immediate */
14155 disas_data_proc_imm(s, insn);
14156 break;
14157 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14158 disas_b_exc_sys(s, insn);
14159 break;
14160 case 0x4:
14161 case 0x6:
14162 case 0xc:
14163 case 0xe: /* Loads and stores */
14164 disas_ldst(s, insn);
14165 break;
14166 case 0x5:
14167 case 0xd: /* Data processing - register */
14168 disas_data_proc_reg(s, insn);
14169 break;
14170 case 0x7:
14171 case 0xf: /* Data processing - SIMD and floating point */
14172 disas_data_proc_simd_fp(s, insn);
14173 break;
14174 default:
14175 assert(FALSE); /* all 15 cases should be handled above */
14176 break;
14179 /* if we allocated any temporaries, free them here */
14180 free_tmp_a64(s);
14183 * After execution of most insns, btype is reset to 0.
14184 * Note that we set btype == -1 when the insn sets btype.
14186 if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) {
14187 reset_btype(s);
14191 static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
14192 CPUState *cpu)
14194 DisasContext *dc = container_of(dcbase, DisasContext, base);
14195 CPUARMState *env = cpu->env_ptr;
14196 ARMCPU *arm_cpu = env_archcpu(env);
14197 uint32_t tb_flags = dc->base.tb->flags;
14198 int bound, core_mmu_idx;
14200 dc->isar = &arm_cpu->isar;
14201 dc->condjmp = 0;
14203 dc->aarch64 = 1;
14204 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14205 * there is no secure EL1, so we route exceptions to EL3.
14207 dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
14208 !arm_el_is_aa64(env, 3);
14209 dc->thumb = 0;
14210 dc->sctlr_b = 0;
14211 dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
14212 dc->condexec_mask = 0;
14213 dc->condexec_cond = 0;
14214 core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
14215 dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx);
14216 dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII);
14217 dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID);
14218 dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
14219 #if !defined(CONFIG_USER_ONLY)
14220 dc->user = (dc->current_el == 0);
14221 #endif
14222 dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
14223 dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL);
14224 dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16;
14225 dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
14226 dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT);
14227 dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE);
14228 dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV);
14229 dc->vec_len = 0;
14230 dc->vec_stride = 0;
14231 dc->cp_regs = arm_cpu->cp_regs;
14232 dc->features = env->features;
14234 /* Single step state. The code-generation logic here is:
14235 * SS_ACTIVE == 0:
14236 * generate code with no special handling for single-stepping (except
14237 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14238 * this happens anyway because those changes are all system register or
14239 * PSTATE writes).
14240 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14241 * emit code for one insn
14242 * emit code to clear PSTATE.SS
14243 * emit code to generate software step exception for completed step
14244 * end TB (as usual for having generated an exception)
14245 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14246 * emit code to generate a software step exception
14247 * end the TB
14249 dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
14250 dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
14251 dc->is_ldex = false;
14252 dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
14254 /* Bound the number of insns to execute to those left on the page. */
14255 bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
14257 /* If architectural single step active, limit to 1. */
14258 if (dc->ss_active) {
14259 bound = 1;
14261 dc->base.max_insns = MIN(dc->base.max_insns, bound);
14263 init_tmp_a64_array(dc);
14266 static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
14270 static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
14272 DisasContext *dc = container_of(dcbase, DisasContext, base);
14274 tcg_gen_insn_start(dc->base.pc_next, 0, 0);
14275 dc->insn_start = tcg_last_op();
14278 static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
14279 const CPUBreakpoint *bp)
14281 DisasContext *dc = container_of(dcbase, DisasContext, base);
14283 if (bp->flags & BP_CPU) {
14284 gen_a64_set_pc_im(dc->base.pc_next);
14285 gen_helper_check_breakpoints(cpu_env);
14286 /* End the TB early; it likely won't be executed */
14287 dc->base.is_jmp = DISAS_TOO_MANY;
14288 } else {
14289 gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
14290 /* The address covered by the breakpoint must be
14291 included in [tb->pc, tb->pc + tb->size) in order
14292 to for it to be properly cleared -- thus we
14293 increment the PC here so that the logic setting
14294 tb->size below does the right thing. */
14295 dc->base.pc_next += 4;
14296 dc->base.is_jmp = DISAS_NORETURN;
14299 return true;
14302 static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
14304 DisasContext *dc = container_of(dcbase, DisasContext, base);
14305 CPUARMState *env = cpu->env_ptr;
14307 if (dc->ss_active && !dc->pstate_ss) {
14308 /* Singlestep state is Active-pending.
14309 * If we're in this state at the start of a TB then either
14310 * a) we just took an exception to an EL which is being debugged
14311 * and this is the first insn in the exception handler
14312 * b) debug exceptions were masked and we just unmasked them
14313 * without changing EL (eg by clearing PSTATE.D)
14314 * In either case we're going to take a swstep exception in the
14315 * "did not step an insn" case, and so the syndrome ISV and EX
14316 * bits should be zero.
14318 assert(dc->base.num_insns == 1);
14319 gen_swstep_exception(dc, 0, 0);
14320 dc->base.is_jmp = DISAS_NORETURN;
14321 } else {
14322 disas_a64_insn(env, dc);
14325 translator_loop_temp_check(&dc->base);
14328 static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
14330 DisasContext *dc = container_of(dcbase, DisasContext, base);
14332 if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
14333 /* Note that this means single stepping WFI doesn't halt the CPU.
14334 * For conditional branch insns this is harmless unreachable code as
14335 * gen_goto_tb() has already handled emitting the debug exception
14336 * (and thus a tb-jump is not possible when singlestepping).
14338 switch (dc->base.is_jmp) {
14339 default:
14340 gen_a64_set_pc_im(dc->base.pc_next);
14341 /* fall through */
14342 case DISAS_EXIT:
14343 case DISAS_JUMP:
14344 if (dc->base.singlestep_enabled) {
14345 gen_exception_internal(EXCP_DEBUG);
14346 } else {
14347 gen_step_complete_exception(dc);
14349 break;
14350 case DISAS_NORETURN:
14351 break;
14353 } else {
14354 switch (dc->base.is_jmp) {
14355 case DISAS_NEXT:
14356 case DISAS_TOO_MANY:
14357 gen_goto_tb(dc, 1, dc->base.pc_next);
14358 break;
14359 default:
14360 case DISAS_UPDATE:
14361 gen_a64_set_pc_im(dc->base.pc_next);
14362 /* fall through */
14363 case DISAS_EXIT:
14364 tcg_gen_exit_tb(NULL, 0);
14365 break;
14366 case DISAS_JUMP:
14367 tcg_gen_lookup_and_goto_ptr();
14368 break;
14369 case DISAS_NORETURN:
14370 case DISAS_SWI:
14371 break;
14372 case DISAS_WFE:
14373 gen_a64_set_pc_im(dc->base.pc_next);
14374 gen_helper_wfe(cpu_env);
14375 break;
14376 case DISAS_YIELD:
14377 gen_a64_set_pc_im(dc->base.pc_next);
14378 gen_helper_yield(cpu_env);
14379 break;
14380 case DISAS_WFI:
14382 /* This is a special case because we don't want to just halt the CPU
14383 * if trying to debug across a WFI.
14385 TCGv_i32 tmp = tcg_const_i32(4);
14387 gen_a64_set_pc_im(dc->base.pc_next);
14388 gen_helper_wfi(cpu_env, tmp);
14389 tcg_temp_free_i32(tmp);
14390 /* The helper doesn't necessarily throw an exception, but we
14391 * must go back to the main loop to check for interrupts anyway.
14393 tcg_gen_exit_tb(NULL, 0);
14394 break;
14400 static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
14401 CPUState *cpu)
14403 DisasContext *dc = container_of(dcbase, DisasContext, base);
14405 qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
14406 log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size);
14409 const TranslatorOps aarch64_translator_ops = {
14410 .init_disas_context = aarch64_tr_init_disas_context,
14411 .tb_start = aarch64_tr_tb_start,
14412 .insn_start = aarch64_tr_insn_start,
14413 .breakpoint_check = aarch64_tr_breakpoint_check,
14414 .translate_insn = aarch64_tr_translate_insn,
14415 .tb_stop = aarch64_tr_tb_stop,
14416 .disas_log = aarch64_tr_disas_log,