2 * vfio based device assignment support
4 * Copyright Red Hat, Inc. 2012
7 * Alex Williamson <alex.williamson@redhat.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
12 * Based on qemu-kvm device-assignment:
13 * Adapted for KVM by Qumranet.
14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
22 #include <linux/vfio.h>
23 #include <sys/ioctl.h>
26 #include <sys/types.h>
30 #include "exec/address-spaces.h"
31 #include "exec/memory.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci.h"
35 #include "qemu-common.h"
36 #include "qemu/error-report.h"
37 #include "qemu/event_notifier.h"
38 #include "qemu/queue.h"
39 #include "qemu/range.h"
40 #include "sysemu/kvm.h"
41 #include "sysemu/sysemu.h"
43 /* #define DEBUG_VFIO */
45 #define DPRINTF(fmt, ...) \
46 do { fprintf(stderr, "vfio: " fmt, ## __VA_ARGS__); } while (0)
48 #define DPRINTF(fmt, ...) \
52 /* Extra debugging, trap acceleration paths for more logging */
53 #define VFIO_ALLOW_MMAP 1
54 #define VFIO_ALLOW_KVM_INTX 1
58 typedef struct VFIOQuirk
{
60 struct VFIODevice
*vdev
;
61 QLIST_ENTRY(VFIOQuirk
) next
;
63 uint32_t base_offset
:TARGET_PAGE_BITS
;
64 uint32_t address_offset
:TARGET_PAGE_BITS
;
65 uint32_t address_size
:3;
68 uint32_t address_match
;
69 uint32_t address_mask
;
71 uint32_t address_val
:TARGET_PAGE_BITS
;
72 uint32_t data_offset
:TARGET_PAGE_BITS
;
81 typedef struct VFIOBAR
{
82 off_t fd_offset
; /* offset of BAR within device fd */
83 int fd
; /* device fd, allows us to pass VFIOBAR as opaque data */
84 MemoryRegion mem
; /* slow, read/write access */
85 MemoryRegion mmap_mem
; /* direct mapped access */
88 uint32_t flags
; /* VFIO region flags (rd/wr/mmap) */
89 uint8_t nr
; /* cache the BAR number for debug */
92 QLIST_HEAD(, VFIOQuirk
) quirks
;
95 typedef struct VFIOVGARegion
{
99 QLIST_HEAD(, VFIOQuirk
) quirks
;
102 typedef struct VFIOVGA
{
105 VFIOVGARegion region
[QEMU_PCI_VGA_NUM_REGIONS
];
108 typedef struct VFIOINTx
{
109 bool pending
; /* interrupt pending */
110 bool kvm_accel
; /* set when QEMU bypass through KVM enabled */
111 uint8_t pin
; /* which pin to pull for qemu_set_irq */
112 EventNotifier interrupt
; /* eventfd triggered on interrupt */
113 EventNotifier unmask
; /* eventfd for unmask on QEMU bypass */
114 PCIINTxRoute route
; /* routing info for QEMU bypass */
115 uint32_t mmap_timeout
; /* delay to re-enable mmaps after interrupt */
116 QEMUTimer
*mmap_timer
; /* enable mmaps after periods w/o interrupts */
119 typedef struct VFIOMSIVector
{
120 EventNotifier interrupt
; /* eventfd triggered on interrupt */
121 struct VFIODevice
*vdev
; /* back pointer to device */
122 MSIMessage msg
; /* cache the MSI message so we know when it changes */
123 int virq
; /* KVM irqchip route for QEMU bypass */
136 typedef struct VFIOContainer
{
137 int fd
; /* /dev/vfio/vfio, empowered by the attached groups */
139 /* enable abstraction to support various iommu backends */
141 MemoryListener listener
; /* Used by type1 iommu */
143 void (*release
)(struct VFIOContainer
*);
145 QLIST_HEAD(, VFIOGroup
) group_list
;
146 QLIST_ENTRY(VFIOContainer
) next
;
149 /* Cache of MSI-X setup plus extra mmap and memory region for split BAR map */
150 typedef struct VFIOMSIXInfo
{
154 uint32_t table_offset
;
156 MemoryRegion mmap_mem
;
160 typedef struct VFIODevice
{
164 unsigned int config_size
;
165 uint8_t *emulated_config_bits
; /* QEMU emulated bits, little-endian */
166 off_t config_offset
; /* Offset of config space region within device fd */
167 unsigned int rom_size
;
168 off_t rom_offset
; /* Offset of ROM region within device fd */
170 VFIOMSIVector
*msi_vectors
;
172 int nr_vectors
; /* Number of MSI/MSIX vectors currently in use */
173 int interrupt
; /* Current interrupt type */
174 VFIOBAR bars
[PCI_NUM_REGIONS
- 1]; /* No ROM */
175 VFIOVGA vga
; /* 0xa0000, 0x3b0, 0x3c0 */
176 PCIHostDeviceAddress host
;
177 QLIST_ENTRY(VFIODevice
) next
;
178 struct VFIOGroup
*group
;
179 EventNotifier err_notifier
;
181 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
182 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
190 typedef struct VFIOGroup
{
193 VFIOContainer
*container
;
194 QLIST_HEAD(, VFIODevice
) device_list
;
195 QLIST_ENTRY(VFIOGroup
) next
;
196 QLIST_ENTRY(VFIOGroup
) container_next
;
199 #define MSIX_CAP_LENGTH 12
201 static QLIST_HEAD(, VFIOContainer
)
202 container_list
= QLIST_HEAD_INITIALIZER(container_list
);
204 static QLIST_HEAD(, VFIOGroup
)
205 group_list
= QLIST_HEAD_INITIALIZER(group_list
);
207 static void vfio_disable_interrupts(VFIODevice
*vdev
);
208 static uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
);
209 static void vfio_pci_write_config(PCIDevice
*pdev
, uint32_t addr
,
210 uint32_t val
, int len
);
211 static void vfio_mmap_set_enabled(VFIODevice
*vdev
, bool enabled
);
214 * Common VFIO interrupt disable
216 static void vfio_disable_irqindex(VFIODevice
*vdev
, int index
)
218 struct vfio_irq_set irq_set
= {
219 .argsz
= sizeof(irq_set
),
220 .flags
= VFIO_IRQ_SET_DATA_NONE
| VFIO_IRQ_SET_ACTION_TRIGGER
,
226 ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, &irq_set
);
232 static void vfio_unmask_intx(VFIODevice
*vdev
)
234 struct vfio_irq_set irq_set
= {
235 .argsz
= sizeof(irq_set
),
236 .flags
= VFIO_IRQ_SET_DATA_NONE
| VFIO_IRQ_SET_ACTION_UNMASK
,
237 .index
= VFIO_PCI_INTX_IRQ_INDEX
,
242 ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, &irq_set
);
245 #ifdef CONFIG_KVM /* Unused outside of CONFIG_KVM code */
246 static void vfio_mask_intx(VFIODevice
*vdev
)
248 struct vfio_irq_set irq_set
= {
249 .argsz
= sizeof(irq_set
),
250 .flags
= VFIO_IRQ_SET_DATA_NONE
| VFIO_IRQ_SET_ACTION_MASK
,
251 .index
= VFIO_PCI_INTX_IRQ_INDEX
,
256 ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, &irq_set
);
261 * Disabling BAR mmaping can be slow, but toggling it around INTx can
262 * also be a huge overhead. We try to get the best of both worlds by
263 * waiting until an interrupt to disable mmaps (subsequent transitions
264 * to the same state are effectively no overhead). If the interrupt has
265 * been serviced and the time gap is long enough, we re-enable mmaps for
266 * performance. This works well for things like graphics cards, which
267 * may not use their interrupt at all and are penalized to an unusable
268 * level by read/write BAR traps. Other devices, like NICs, have more
269 * regular interrupts and see much better latency by staying in non-mmap
270 * mode. We therefore set the default mmap_timeout such that a ping
271 * is just enough to keep the mmap disabled. Users can experiment with
272 * other options with the x-intx-mmap-timeout-ms parameter (a value of
273 * zero disables the timer).
275 static void vfio_intx_mmap_enable(void *opaque
)
277 VFIODevice
*vdev
= opaque
;
279 if (vdev
->intx
.pending
) {
280 timer_mod(vdev
->intx
.mmap_timer
,
281 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + vdev
->intx
.mmap_timeout
);
285 vfio_mmap_set_enabled(vdev
, true);
288 static void vfio_intx_interrupt(void *opaque
)
290 VFIODevice
*vdev
= opaque
;
292 if (!event_notifier_test_and_clear(&vdev
->intx
.interrupt
)) {
296 DPRINTF("%s(%04x:%02x:%02x.%x) Pin %c\n", __func__
, vdev
->host
.domain
,
297 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
298 'A' + vdev
->intx
.pin
);
300 vdev
->intx
.pending
= true;
301 qemu_set_irq(vdev
->pdev
.irq
[vdev
->intx
.pin
], 1);
302 vfio_mmap_set_enabled(vdev
, false);
303 if (vdev
->intx
.mmap_timeout
) {
304 timer_mod(vdev
->intx
.mmap_timer
,
305 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + vdev
->intx
.mmap_timeout
);
309 static void vfio_eoi(VFIODevice
*vdev
)
311 if (!vdev
->intx
.pending
) {
315 DPRINTF("%s(%04x:%02x:%02x.%x) EOI\n", __func__
, vdev
->host
.domain
,
316 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
318 vdev
->intx
.pending
= false;
319 qemu_set_irq(vdev
->pdev
.irq
[vdev
->intx
.pin
], 0);
320 vfio_unmask_intx(vdev
);
323 static void vfio_enable_intx_kvm(VFIODevice
*vdev
)
326 struct kvm_irqfd irqfd
= {
327 .fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
),
328 .gsi
= vdev
->intx
.route
.irq
,
329 .flags
= KVM_IRQFD_FLAG_RESAMPLE
,
331 struct vfio_irq_set
*irq_set
;
335 if (!VFIO_ALLOW_KVM_INTX
|| !kvm_irqfds_enabled() ||
336 vdev
->intx
.route
.mode
!= PCI_INTX_ENABLED
||
337 !kvm_check_extension(kvm_state
, KVM_CAP_IRQFD_RESAMPLE
)) {
341 /* Get to a known interrupt state */
342 qemu_set_fd_handler(irqfd
.fd
, NULL
, NULL
, vdev
);
343 vfio_mask_intx(vdev
);
344 vdev
->intx
.pending
= false;
345 qemu_set_irq(vdev
->pdev
.irq
[vdev
->intx
.pin
], 0);
347 /* Get an eventfd for resample/unmask */
348 if (event_notifier_init(&vdev
->intx
.unmask
, 0)) {
349 error_report("vfio: Error: event_notifier_init failed eoi");
353 /* KVM triggers it, VFIO listens for it */
354 irqfd
.resamplefd
= event_notifier_get_fd(&vdev
->intx
.unmask
);
356 if (kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
)) {
357 error_report("vfio: Error: Failed to setup resample irqfd: %m");
361 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
363 irq_set
= g_malloc0(argsz
);
364 irq_set
->argsz
= argsz
;
365 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_UNMASK
;
366 irq_set
->index
= VFIO_PCI_INTX_IRQ_INDEX
;
369 pfd
= (int32_t *)&irq_set
->data
;
371 *pfd
= irqfd
.resamplefd
;
373 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
376 error_report("vfio: Error: Failed to setup INTx unmask fd: %m");
381 vfio_unmask_intx(vdev
);
383 vdev
->intx
.kvm_accel
= true;
385 DPRINTF("%s(%04x:%02x:%02x.%x) KVM INTx accel enabled\n",
386 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
387 vdev
->host
.slot
, vdev
->host
.function
);
392 irqfd
.flags
= KVM_IRQFD_FLAG_DEASSIGN
;
393 kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
);
395 event_notifier_cleanup(&vdev
->intx
.unmask
);
397 qemu_set_fd_handler(irqfd
.fd
, vfio_intx_interrupt
, NULL
, vdev
);
398 vfio_unmask_intx(vdev
);
402 static void vfio_disable_intx_kvm(VFIODevice
*vdev
)
405 struct kvm_irqfd irqfd
= {
406 .fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
),
407 .gsi
= vdev
->intx
.route
.irq
,
408 .flags
= KVM_IRQFD_FLAG_DEASSIGN
,
411 if (!vdev
->intx
.kvm_accel
) {
416 * Get to a known state, hardware masked, QEMU ready to accept new
417 * interrupts, QEMU IRQ de-asserted.
419 vfio_mask_intx(vdev
);
420 vdev
->intx
.pending
= false;
421 qemu_set_irq(vdev
->pdev
.irq
[vdev
->intx
.pin
], 0);
423 /* Tell KVM to stop listening for an INTx irqfd */
424 if (kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
)) {
425 error_report("vfio: Error: Failed to disable INTx irqfd: %m");
428 /* We only need to close the eventfd for VFIO to cleanup the kernel side */
429 event_notifier_cleanup(&vdev
->intx
.unmask
);
431 /* QEMU starts listening for interrupt events. */
432 qemu_set_fd_handler(irqfd
.fd
, vfio_intx_interrupt
, NULL
, vdev
);
434 vdev
->intx
.kvm_accel
= false;
436 /* If we've missed an event, let it re-fire through QEMU */
437 vfio_unmask_intx(vdev
);
439 DPRINTF("%s(%04x:%02x:%02x.%x) KVM INTx accel disabled\n",
440 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
441 vdev
->host
.slot
, vdev
->host
.function
);
445 static void vfio_update_irq(PCIDevice
*pdev
)
447 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
450 if (vdev
->interrupt
!= VFIO_INT_INTx
) {
454 route
= pci_device_route_intx_to_irq(&vdev
->pdev
, vdev
->intx
.pin
);
456 if (!pci_intx_route_changed(&vdev
->intx
.route
, &route
)) {
457 return; /* Nothing changed */
460 DPRINTF("%s(%04x:%02x:%02x.%x) IRQ moved %d -> %d\n", __func__
,
461 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
462 vdev
->host
.function
, vdev
->intx
.route
.irq
, route
.irq
);
464 vfio_disable_intx_kvm(vdev
);
466 vdev
->intx
.route
= route
;
468 if (route
.mode
!= PCI_INTX_ENABLED
) {
472 vfio_enable_intx_kvm(vdev
);
474 /* Re-enable the interrupt in cased we missed an EOI */
478 static int vfio_enable_intx(VFIODevice
*vdev
)
480 uint8_t pin
= vfio_pci_read_config(&vdev
->pdev
, PCI_INTERRUPT_PIN
, 1);
482 struct vfio_irq_set
*irq_set
;
489 vfio_disable_interrupts(vdev
);
491 vdev
->intx
.pin
= pin
- 1; /* Pin A (1) -> irq[0] */
495 * Only conditional to avoid generating error messages on platforms
496 * where we won't actually use the result anyway.
498 if (kvm_irqfds_enabled() &&
499 kvm_check_extension(kvm_state
, KVM_CAP_IRQFD_RESAMPLE
)) {
500 vdev
->intx
.route
= pci_device_route_intx_to_irq(&vdev
->pdev
,
505 ret
= event_notifier_init(&vdev
->intx
.interrupt
, 0);
507 error_report("vfio: Error: event_notifier_init failed");
511 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
513 irq_set
= g_malloc0(argsz
);
514 irq_set
->argsz
= argsz
;
515 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_TRIGGER
;
516 irq_set
->index
= VFIO_PCI_INTX_IRQ_INDEX
;
519 pfd
= (int32_t *)&irq_set
->data
;
521 *pfd
= event_notifier_get_fd(&vdev
->intx
.interrupt
);
522 qemu_set_fd_handler(*pfd
, vfio_intx_interrupt
, NULL
, vdev
);
524 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
527 error_report("vfio: Error: Failed to setup INTx fd: %m");
528 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
529 event_notifier_cleanup(&vdev
->intx
.interrupt
);
533 vfio_enable_intx_kvm(vdev
);
535 vdev
->interrupt
= VFIO_INT_INTx
;
537 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
538 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
543 static void vfio_disable_intx(VFIODevice
*vdev
)
547 timer_del(vdev
->intx
.mmap_timer
);
548 vfio_disable_intx_kvm(vdev
);
549 vfio_disable_irqindex(vdev
, VFIO_PCI_INTX_IRQ_INDEX
);
550 vdev
->intx
.pending
= false;
551 qemu_set_irq(vdev
->pdev
.irq
[vdev
->intx
.pin
], 0);
552 vfio_mmap_set_enabled(vdev
, true);
554 fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
);
555 qemu_set_fd_handler(fd
, NULL
, NULL
, vdev
);
556 event_notifier_cleanup(&vdev
->intx
.interrupt
);
558 vdev
->interrupt
= VFIO_INT_NONE
;
560 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
561 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
567 static void vfio_msi_interrupt(void *opaque
)
569 VFIOMSIVector
*vector
= opaque
;
570 VFIODevice
*vdev
= vector
->vdev
;
571 int nr
= vector
- vdev
->msi_vectors
;
573 if (!event_notifier_test_and_clear(&vector
->interrupt
)) {
577 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d\n", __func__
,
578 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
579 vdev
->host
.function
, nr
);
581 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
582 msix_notify(&vdev
->pdev
, nr
);
583 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
584 msi_notify(&vdev
->pdev
, nr
);
586 error_report("vfio: MSI interrupt receieved, but not enabled?");
590 static int vfio_enable_vectors(VFIODevice
*vdev
, bool msix
)
592 struct vfio_irq_set
*irq_set
;
593 int ret
= 0, i
, argsz
;
596 argsz
= sizeof(*irq_set
) + (vdev
->nr_vectors
* sizeof(*fds
));
598 irq_set
= g_malloc0(argsz
);
599 irq_set
->argsz
= argsz
;
600 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_TRIGGER
;
601 irq_set
->index
= msix
? VFIO_PCI_MSIX_IRQ_INDEX
: VFIO_PCI_MSI_IRQ_INDEX
;
603 irq_set
->count
= vdev
->nr_vectors
;
604 fds
= (int32_t *)&irq_set
->data
;
606 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
607 if (!vdev
->msi_vectors
[i
].use
) {
612 fds
[i
] = event_notifier_get_fd(&vdev
->msi_vectors
[i
].interrupt
);
615 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
622 static int vfio_msix_vector_do_use(PCIDevice
*pdev
, unsigned int nr
,
623 MSIMessage
*msg
, IOHandler
*handler
)
625 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
626 VFIOMSIVector
*vector
;
629 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d used\n", __func__
,
630 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
631 vdev
->host
.function
, nr
);
633 vector
= &vdev
->msi_vectors
[nr
];
637 msix_vector_use(pdev
, nr
);
639 if (event_notifier_init(&vector
->interrupt
, 0)) {
640 error_report("vfio: Error: event_notifier_init failed");
644 * Attempt to enable route through KVM irqchip,
645 * default to userspace handling if unavailable.
647 vector
->virq
= msg
? kvm_irqchip_add_msi_route(kvm_state
, *msg
) : -1;
648 if (vector
->virq
< 0 ||
649 kvm_irqchip_add_irqfd_notifier(kvm_state
, &vector
->interrupt
,
650 NULL
, vector
->virq
) < 0) {
651 if (vector
->virq
>= 0) {
652 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
655 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
656 handler
, NULL
, vector
);
660 * We don't want to have the host allocate all possible MSI vectors
661 * for a device if they're not in use, so we shutdown and incrementally
662 * increase them as needed.
664 if (vdev
->nr_vectors
< nr
+ 1) {
665 vfio_disable_irqindex(vdev
, VFIO_PCI_MSIX_IRQ_INDEX
);
666 vdev
->nr_vectors
= nr
+ 1;
667 ret
= vfio_enable_vectors(vdev
, true);
669 error_report("vfio: failed to enable vectors, %d", ret
);
673 struct vfio_irq_set
*irq_set
;
676 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
678 irq_set
= g_malloc0(argsz
);
679 irq_set
->argsz
= argsz
;
680 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
681 VFIO_IRQ_SET_ACTION_TRIGGER
;
682 irq_set
->index
= VFIO_PCI_MSIX_IRQ_INDEX
;
685 pfd
= (int32_t *)&irq_set
->data
;
687 *pfd
= event_notifier_get_fd(&vector
->interrupt
);
689 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
692 error_report("vfio: failed to modify vector, %d", ret
);
699 static int vfio_msix_vector_use(PCIDevice
*pdev
,
700 unsigned int nr
, MSIMessage msg
)
702 return vfio_msix_vector_do_use(pdev
, nr
, &msg
, vfio_msi_interrupt
);
705 static void vfio_msix_vector_release(PCIDevice
*pdev
, unsigned int nr
)
707 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
708 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[nr
];
710 struct vfio_irq_set
*irq_set
;
713 DPRINTF("%s(%04x:%02x:%02x.%x) vector %d released\n", __func__
,
714 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
715 vdev
->host
.function
, nr
);
718 * XXX What's the right thing to do here? This turns off the interrupt
719 * completely, but do we really just want to switch the interrupt to
720 * bouncing through userspace and let msix.c drop it? Not sure.
722 msix_vector_unuse(pdev
, nr
);
724 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
726 irq_set
= g_malloc0(argsz
);
727 irq_set
->argsz
= argsz
;
728 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
729 VFIO_IRQ_SET_ACTION_TRIGGER
;
730 irq_set
->index
= VFIO_PCI_MSIX_IRQ_INDEX
;
733 pfd
= (int32_t *)&irq_set
->data
;
737 ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
741 if (vector
->virq
< 0) {
742 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
745 kvm_irqchip_remove_irqfd_notifier(kvm_state
, &vector
->interrupt
,
747 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
751 event_notifier_cleanup(&vector
->interrupt
);
755 static void vfio_enable_msix(VFIODevice
*vdev
)
757 vfio_disable_interrupts(vdev
);
759 vdev
->msi_vectors
= g_malloc0(vdev
->msix
->entries
* sizeof(VFIOMSIVector
));
761 vdev
->interrupt
= VFIO_INT_MSIX
;
764 * Some communication channels between VF & PF or PF & fw rely on the
765 * physical state of the device and expect that enabling MSI-X from the
766 * guest enables the same on the host. When our guest is Linux, the
767 * guest driver call to pci_enable_msix() sets the enabling bit in the
768 * MSI-X capability, but leaves the vector table masked. We therefore
769 * can't rely on a vector_use callback (from request_irq() in the guest)
770 * to switch the physical device into MSI-X mode because that may come a
771 * long time after pci_enable_msix(). This code enables vector 0 with
772 * triggering to userspace, then immediately release the vector, leaving
773 * the physical device with no vectors enabled, but MSI-X enabled, just
774 * like the guest view.
776 vfio_msix_vector_do_use(&vdev
->pdev
, 0, NULL
, NULL
);
777 vfio_msix_vector_release(&vdev
->pdev
, 0);
779 if (msix_set_vector_notifiers(&vdev
->pdev
, vfio_msix_vector_use
,
780 vfio_msix_vector_release
, NULL
)) {
781 error_report("vfio: msix_set_vector_notifiers failed");
784 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
785 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
788 static void vfio_enable_msi(VFIODevice
*vdev
)
792 vfio_disable_interrupts(vdev
);
794 vdev
->nr_vectors
= msi_nr_vectors_allocated(&vdev
->pdev
);
796 vdev
->msi_vectors
= g_malloc0(vdev
->nr_vectors
* sizeof(VFIOMSIVector
));
798 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
799 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
804 if (event_notifier_init(&vector
->interrupt
, 0)) {
805 error_report("vfio: Error: event_notifier_init failed");
808 vector
->msg
= msi_get_message(&vdev
->pdev
, i
);
811 * Attempt to enable route through KVM irqchip,
812 * default to userspace handling if unavailable.
814 vector
->virq
= kvm_irqchip_add_msi_route(kvm_state
, vector
->msg
);
815 if (vector
->virq
< 0 ||
816 kvm_irqchip_add_irqfd_notifier(kvm_state
, &vector
->interrupt
,
817 NULL
, vector
->virq
) < 0) {
818 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
819 vfio_msi_interrupt
, NULL
, vector
);
823 ret
= vfio_enable_vectors(vdev
, false);
826 error_report("vfio: Error: Failed to setup MSI fds: %m");
827 } else if (ret
!= vdev
->nr_vectors
) {
828 error_report("vfio: Error: Failed to enable %d "
829 "MSI vectors, retry with %d", vdev
->nr_vectors
, ret
);
832 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
833 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
834 if (vector
->virq
>= 0) {
835 kvm_irqchip_remove_irqfd_notifier(kvm_state
, &vector
->interrupt
,
837 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
840 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
843 event_notifier_cleanup(&vector
->interrupt
);
846 g_free(vdev
->msi_vectors
);
848 if (ret
> 0 && ret
!= vdev
->nr_vectors
) {
849 vdev
->nr_vectors
= ret
;
852 vdev
->nr_vectors
= 0;
857 vdev
->interrupt
= VFIO_INT_MSI
;
859 DPRINTF("%s(%04x:%02x:%02x.%x) Enabled %d MSI vectors\n", __func__
,
860 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
861 vdev
->host
.function
, vdev
->nr_vectors
);
864 static void vfio_disable_msi_common(VFIODevice
*vdev
)
866 g_free(vdev
->msi_vectors
);
867 vdev
->msi_vectors
= NULL
;
868 vdev
->nr_vectors
= 0;
869 vdev
->interrupt
= VFIO_INT_NONE
;
871 vfio_enable_intx(vdev
);
874 static void vfio_disable_msix(VFIODevice
*vdev
)
876 msix_unset_vector_notifiers(&vdev
->pdev
);
878 if (vdev
->nr_vectors
) {
879 vfio_disable_irqindex(vdev
, VFIO_PCI_MSIX_IRQ_INDEX
);
882 vfio_disable_msi_common(vdev
);
884 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
885 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
888 static void vfio_disable_msi(VFIODevice
*vdev
)
892 vfio_disable_irqindex(vdev
, VFIO_PCI_MSI_IRQ_INDEX
);
894 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
895 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
901 if (vector
->virq
>= 0) {
902 kvm_irqchip_remove_irqfd_notifier(kvm_state
,
903 &vector
->interrupt
, vector
->virq
);
904 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
907 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
911 event_notifier_cleanup(&vector
->interrupt
);
914 vfio_disable_msi_common(vdev
);
916 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
917 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
920 static void vfio_update_msi(VFIODevice
*vdev
)
924 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
925 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
928 if (!vector
->use
|| vector
->virq
< 0) {
932 msg
= msi_get_message(&vdev
->pdev
, i
);
934 if (msg
.address
!= vector
->msg
.address
||
935 msg
.data
!= vector
->msg
.data
) {
937 DPRINTF("%s(%04x:%02x:%02x.%x) MSI vector %d changed\n",
938 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
939 vdev
->host
.slot
, vdev
->host
.function
, i
);
941 kvm_irqchip_update_msi_route(kvm_state
, vector
->virq
, msg
);
948 * IO Port/MMIO - Beware of the endians, VFIO is always little endian
950 static void vfio_bar_write(void *opaque
, hwaddr addr
,
951 uint64_t data
, unsigned size
)
953 VFIOBAR
*bar
= opaque
;
966 buf
.word
= cpu_to_le16(data
);
969 buf
.dword
= cpu_to_le32(data
);
972 hw_error("vfio: unsupported write size, %d bytes\n", size
);
976 if (pwrite(bar
->fd
, &buf
, size
, bar
->fd_offset
+ addr
) != size
) {
977 error_report("%s(,0x%"HWADDR_PRIx
", 0x%"PRIx64
", %d) failed: %m",
978 __func__
, addr
, data
, size
);
983 VFIODevice
*vdev
= container_of(bar
, VFIODevice
, bars
[bar
->nr
]);
985 DPRINTF("%s(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", 0x%"PRIx64
986 ", %d)\n", __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
987 vdev
->host
.slot
, vdev
->host
.function
, bar
->nr
, addr
,
993 * A read or write to a BAR always signals an INTx EOI. This will
994 * do nothing if not pending (including not in INTx mode). We assume
995 * that a BAR access is in response to an interrupt and that BAR
996 * accesses will service the interrupt. Unfortunately, we don't know
997 * which access will service the interrupt, so we're potentially
998 * getting quite a few host interrupts per guest interrupt.
1000 vfio_eoi(container_of(bar
, VFIODevice
, bars
[bar
->nr
]));
1003 static uint64_t vfio_bar_read(void *opaque
,
1004 hwaddr addr
, unsigned size
)
1006 VFIOBAR
*bar
= opaque
;
1015 if (pread(bar
->fd
, &buf
, size
, bar
->fd_offset
+ addr
) != size
) {
1016 error_report("%s(,0x%"HWADDR_PRIx
", %d) failed: %m",
1017 __func__
, addr
, size
);
1018 return (uint64_t)-1;
1026 data
= le16_to_cpu(buf
.word
);
1029 data
= le32_to_cpu(buf
.dword
);
1032 hw_error("vfio: unsupported read size, %d bytes\n", size
);
1038 VFIODevice
*vdev
= container_of(bar
, VFIODevice
, bars
[bar
->nr
]);
1040 DPRINTF("%s(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
1041 ", %d) = 0x%"PRIx64
"\n", __func__
, vdev
->host
.domain
,
1042 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
1043 bar
->nr
, addr
, size
, data
);
1047 /* Same as write above */
1048 vfio_eoi(container_of(bar
, VFIODevice
, bars
[bar
->nr
]));
1053 static const MemoryRegionOps vfio_bar_ops
= {
1054 .read
= vfio_bar_read
,
1055 .write
= vfio_bar_write
,
1056 .endianness
= DEVICE_LITTLE_ENDIAN
,
1059 static void vfio_vga_write(void *opaque
, hwaddr addr
,
1060 uint64_t data
, unsigned size
)
1062 VFIOVGARegion
*region
= opaque
;
1063 VFIOVGA
*vga
= container_of(region
, VFIOVGA
, region
[region
->nr
]);
1070 off_t offset
= vga
->fd_offset
+ region
->offset
+ addr
;
1077 buf
.word
= cpu_to_le16(data
);
1080 buf
.dword
= cpu_to_le32(data
);
1083 hw_error("vfio: unsupported write size, %d bytes\n", size
);
1087 if (pwrite(vga
->fd
, &buf
, size
, offset
) != size
) {
1088 error_report("%s(,0x%"HWADDR_PRIx
", 0x%"PRIx64
", %d) failed: %m",
1089 __func__
, region
->offset
+ addr
, data
, size
);
1092 DPRINTF("%s(0x%"HWADDR_PRIx
", 0x%"PRIx64
", %d)\n",
1093 __func__
, region
->offset
+ addr
, data
, size
);
1096 static uint64_t vfio_vga_read(void *opaque
, hwaddr addr
, unsigned size
)
1098 VFIOVGARegion
*region
= opaque
;
1099 VFIOVGA
*vga
= container_of(region
, VFIOVGA
, region
[region
->nr
]);
1107 off_t offset
= vga
->fd_offset
+ region
->offset
+ addr
;
1109 if (pread(vga
->fd
, &buf
, size
, offset
) != size
) {
1110 error_report("%s(,0x%"HWADDR_PRIx
", %d) failed: %m",
1111 __func__
, region
->offset
+ addr
, size
);
1112 return (uint64_t)-1;
1120 data
= le16_to_cpu(buf
.word
);
1123 data
= le32_to_cpu(buf
.dword
);
1126 hw_error("vfio: unsupported read size, %d bytes\n", size
);
1130 DPRINTF("%s(0x%"HWADDR_PRIx
", %d) = 0x%"PRIx64
"\n",
1131 __func__
, region
->offset
+ addr
, size
, data
);
1136 static const MemoryRegionOps vfio_vga_ops
= {
1137 .read
= vfio_vga_read
,
1138 .write
= vfio_vga_write
,
1139 .endianness
= DEVICE_LITTLE_ENDIAN
,
1143 * Device specific quirks
1146 /* Is range1 fully contained within range2? */
1147 static bool vfio_range_contained(uint64_t first1
, uint64_t len1
,
1148 uint64_t first2
, uint64_t len2
) {
1149 return (first1
>= first2
&& first1
+ len1
<= first2
+ len2
);
1152 static bool vfio_flags_enabled(uint8_t flags
, uint8_t mask
)
1154 return (mask
&& (flags
& mask
) == mask
);
1157 static uint64_t vfio_generic_window_quirk_read(void *opaque
,
1158 hwaddr addr
, unsigned size
)
1160 VFIOQuirk
*quirk
= opaque
;
1161 VFIODevice
*vdev
= quirk
->vdev
;
1164 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.read_flags
) &&
1165 ranges_overlap(addr
, size
,
1166 quirk
->data
.data_offset
, quirk
->data
.data_size
)) {
1167 hwaddr offset
= addr
- quirk
->data
.data_offset
;
1169 if (!vfio_range_contained(addr
, size
, quirk
->data
.data_offset
,
1170 quirk
->data
.data_size
)) {
1171 hw_error("%s: window data read not fully contained: %s\n",
1172 __func__
, memory_region_name(&quirk
->mem
));
1175 data
= vfio_pci_read_config(&vdev
->pdev
,
1176 quirk
->data
.address_val
+ offset
, size
);
1178 DPRINTF("%s read(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", %d) = 0x%"
1179 PRIx64
"\n", memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1180 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
1181 quirk
->data
.bar
, addr
, size
, data
);
1183 data
= vfio_bar_read(&vdev
->bars
[quirk
->data
.bar
],
1184 addr
+ quirk
->data
.base_offset
, size
);
1190 static void vfio_generic_window_quirk_write(void *opaque
, hwaddr addr
,
1191 uint64_t data
, unsigned size
)
1193 VFIOQuirk
*quirk
= opaque
;
1194 VFIODevice
*vdev
= quirk
->vdev
;
1196 if (ranges_overlap(addr
, size
,
1197 quirk
->data
.address_offset
, quirk
->data
.address_size
)) {
1199 if (addr
!= quirk
->data
.address_offset
) {
1200 hw_error("%s: offset write into address window: %s\n",
1201 __func__
, memory_region_name(&quirk
->mem
));
1204 if ((data
& ~quirk
->data
.address_mask
) == quirk
->data
.address_match
) {
1205 quirk
->data
.flags
|= quirk
->data
.write_flags
|
1206 quirk
->data
.read_flags
;
1207 quirk
->data
.address_val
= data
& quirk
->data
.address_mask
;
1209 quirk
->data
.flags
&= ~(quirk
->data
.write_flags
|
1210 quirk
->data
.read_flags
);
1214 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.write_flags
) &&
1215 ranges_overlap(addr
, size
,
1216 quirk
->data
.data_offset
, quirk
->data
.data_size
)) {
1217 hwaddr offset
= addr
- quirk
->data
.data_offset
;
1219 if (!vfio_range_contained(addr
, size
, quirk
->data
.data_offset
,
1220 quirk
->data
.data_size
)) {
1221 hw_error("%s: window data write not fully contained: %s\n",
1222 __func__
, memory_region_name(&quirk
->mem
));
1225 vfio_pci_write_config(&vdev
->pdev
,
1226 quirk
->data
.address_val
+ offset
, data
, size
);
1227 DPRINTF("%s write(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", 0x%"
1228 PRIx64
", %d)\n", memory_region_name(&quirk
->mem
),
1229 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1230 vdev
->host
.function
, quirk
->data
.bar
, addr
, data
, size
);
1234 vfio_bar_write(&vdev
->bars
[quirk
->data
.bar
],
1235 addr
+ quirk
->data
.base_offset
, data
, size
);
1238 static const MemoryRegionOps vfio_generic_window_quirk
= {
1239 .read
= vfio_generic_window_quirk_read
,
1240 .write
= vfio_generic_window_quirk_write
,
1241 .endianness
= DEVICE_LITTLE_ENDIAN
,
1244 static uint64_t vfio_generic_quirk_read(void *opaque
,
1245 hwaddr addr
, unsigned size
)
1247 VFIOQuirk
*quirk
= opaque
;
1248 VFIODevice
*vdev
= quirk
->vdev
;
1249 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1250 hwaddr offset
= quirk
->data
.address_match
& ~TARGET_PAGE_MASK
;
1253 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.read_flags
) &&
1254 ranges_overlap(addr
, size
, offset
, quirk
->data
.address_mask
+ 1)) {
1255 if (!vfio_range_contained(addr
, size
, offset
,
1256 quirk
->data
.address_mask
+ 1)) {
1257 hw_error("%s: read not fully contained: %s\n",
1258 __func__
, memory_region_name(&quirk
->mem
));
1261 data
= vfio_pci_read_config(&vdev
->pdev
, addr
- offset
, size
);
1263 DPRINTF("%s read(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", %d) = 0x%"
1264 PRIx64
"\n", memory_region_name(&quirk
->mem
), vdev
->host
.domain
,
1265 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
1266 quirk
->data
.bar
, addr
+ base
, size
, data
);
1268 data
= vfio_bar_read(&vdev
->bars
[quirk
->data
.bar
], addr
+ base
, size
);
1274 static void vfio_generic_quirk_write(void *opaque
, hwaddr addr
,
1275 uint64_t data
, unsigned size
)
1277 VFIOQuirk
*quirk
= opaque
;
1278 VFIODevice
*vdev
= quirk
->vdev
;
1279 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1280 hwaddr offset
= quirk
->data
.address_match
& ~TARGET_PAGE_MASK
;
1282 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.write_flags
) &&
1283 ranges_overlap(addr
, size
, offset
, quirk
->data
.address_mask
+ 1)) {
1284 if (!vfio_range_contained(addr
, size
, offset
,
1285 quirk
->data
.address_mask
+ 1)) {
1286 hw_error("%s: write not fully contained: %s\n",
1287 __func__
, memory_region_name(&quirk
->mem
));
1290 vfio_pci_write_config(&vdev
->pdev
, addr
- offset
, data
, size
);
1292 DPRINTF("%s write(%04x:%02x:%02x.%x:BAR%d+0x%"HWADDR_PRIx
", 0x%"
1293 PRIx64
", %d)\n", memory_region_name(&quirk
->mem
),
1294 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1295 vdev
->host
.function
, quirk
->data
.bar
, addr
+ base
, data
, size
);
1297 vfio_bar_write(&vdev
->bars
[quirk
->data
.bar
], addr
+ base
, data
, size
);
1301 static const MemoryRegionOps vfio_generic_quirk
= {
1302 .read
= vfio_generic_quirk_read
,
1303 .write
= vfio_generic_quirk_write
,
1304 .endianness
= DEVICE_LITTLE_ENDIAN
,
1307 #define PCI_VENDOR_ID_ATI 0x1002
1310 * Radeon HD cards (HD5450 & HD7850) report the upper byte of the I/O port BAR
1311 * through VGA register 0x3c3. On newer cards, the I/O port BAR is always
1312 * BAR4 (older cards like the X550 used BAR1, but we don't care to support
1313 * those). Note that on bare metal, a read of 0x3c3 doesn't always return the
1314 * I/O port BAR address. Originally this was coded to return the virtual BAR
1315 * address only if the physical register read returns the actual BAR address,
1316 * but users have reported greater success if we return the virtual address
1319 static uint64_t vfio_ati_3c3_quirk_read(void *opaque
,
1320 hwaddr addr
, unsigned size
)
1322 VFIOQuirk
*quirk
= opaque
;
1323 VFIODevice
*vdev
= quirk
->vdev
;
1324 uint64_t data
= vfio_pci_read_config(&vdev
->pdev
,
1325 PCI_BASE_ADDRESS_0
+ (4 * 4) + 1,
1327 DPRINTF("%s(0x3c3, 1) = 0x%"PRIx64
"\n", __func__
, data
);
1332 static const MemoryRegionOps vfio_ati_3c3_quirk
= {
1333 .read
= vfio_ati_3c3_quirk_read
,
1334 .endianness
= DEVICE_LITTLE_ENDIAN
,
1337 static void vfio_vga_probe_ati_3c3_quirk(VFIODevice
*vdev
)
1339 PCIDevice
*pdev
= &vdev
->pdev
;
1342 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1347 * As long as the BAR is >= 256 bytes it will be aligned such that the
1348 * lower byte is always zero. Filter out anything else, if it exists.
1350 if (!vdev
->bars
[4].ioport
|| vdev
->bars
[4].size
< 256) {
1354 quirk
= g_malloc0(sizeof(*quirk
));
1357 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_ati_3c3_quirk
, quirk
,
1358 "vfio-ati-3c3-quirk", 1);
1359 memory_region_add_subregion(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
1360 3 /* offset 3 bytes from 0x3c0 */, &quirk
->mem
);
1362 QLIST_INSERT_HEAD(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
,
1365 DPRINTF("Enabled ATI/AMD quirk 0x3c3 BAR4for device %04x:%02x:%02x.%x\n",
1366 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1367 vdev
->host
.function
);
1371 * Newer ATI/AMD devices, including HD5450 and HD7850, have a window to PCI
1372 * config space through MMIO BAR2 at offset 0x4000. Nothing seems to access
1373 * the MMIO space directly, but a window to this space is provided through
1374 * I/O port BAR4. Offset 0x0 is the address register and offset 0x4 is the
1375 * data register. When the address is programmed to a range of 0x4000-0x4fff
1376 * PCI configuration space is available. Experimentation seems to indicate
1377 * that only read-only access is provided, but we drop writes when the window
1378 * is enabled to config space nonetheless.
1380 static void vfio_probe_ati_bar4_window_quirk(VFIODevice
*vdev
, int nr
)
1382 PCIDevice
*pdev
= &vdev
->pdev
;
1385 if (!vdev
->has_vga
|| nr
!= 4 ||
1386 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1390 quirk
= g_malloc0(sizeof(*quirk
));
1392 quirk
->data
.address_size
= 4;
1393 quirk
->data
.data_offset
= 4;
1394 quirk
->data
.data_size
= 4;
1395 quirk
->data
.address_match
= 0x4000;
1396 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1397 quirk
->data
.bar
= nr
;
1398 quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1400 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
),
1401 &vfio_generic_window_quirk
, quirk
,
1402 "vfio-ati-bar4-window-quirk", 8);
1403 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
1404 quirk
->data
.base_offset
, &quirk
->mem
, 1);
1406 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1408 DPRINTF("Enabled ATI/AMD BAR4 window quirk for device %04x:%02x:%02x.%x\n",
1409 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1410 vdev
->host
.function
);
1414 * Trap the BAR2 MMIO window to config space as well.
1416 static void vfio_probe_ati_bar2_4000_quirk(VFIODevice
*vdev
, int nr
)
1418 PCIDevice
*pdev
= &vdev
->pdev
;
1421 /* Only enable on newer devices where BAR2 is 64bit */
1422 if (!vdev
->has_vga
|| nr
!= 2 || !vdev
->bars
[2].mem64
||
1423 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1427 quirk
= g_malloc0(sizeof(*quirk
));
1429 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1430 quirk
->data
.address_match
= 0x4000;
1431 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1432 quirk
->data
.bar
= nr
;
1434 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
, quirk
,
1435 "vfio-ati-bar2-4000-quirk",
1436 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1437 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
1438 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1441 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1443 DPRINTF("Enabled ATI/AMD BAR2 0x4000 quirk for device %04x:%02x:%02x.%x\n",
1444 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1445 vdev
->host
.function
);
1449 * Older ATI/AMD cards like the X550 have a similar window to that above.
1450 * I/O port BAR1 provides a window to a mirror of PCI config space located
1451 * in BAR2 at offset 0xf00. We don't care to support such older cards, but
1452 * note it for future reference.
1455 #define PCI_VENDOR_ID_NVIDIA 0x10de
1458 * Nvidia has several different methods to get to config space, the
1459 * nouveu project has several of these documented here:
1460 * https://github.com/pathscale/envytools/tree/master/hwdocs
1462 * The first quirk is actually not documented in envytools and is found
1463 * on 10de:01d1 (NVIDIA Corporation G72 [GeForce 7300 LE]). This is an
1464 * NV46 chipset. The backdoor uses the legacy VGA I/O ports to access
1465 * the mirror of PCI config space found at BAR0 offset 0x1800. The access
1466 * sequence first writes 0x338 to I/O port 0x3d4. The target offset is
1467 * then written to 0x3d0. Finally 0x538 is written for a read and 0x738
1468 * is written for a write to 0x3d4. The BAR0 offset is then accessible
1469 * through 0x3d0. This quirk doesn't seem to be necessary on newer cards
1470 * that use the I/O port BAR5 window but it doesn't hurt to leave it.
1480 static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque
,
1481 hwaddr addr
, unsigned size
)
1483 VFIOQuirk
*quirk
= opaque
;
1484 VFIODevice
*vdev
= quirk
->vdev
;
1485 PCIDevice
*pdev
= &vdev
->pdev
;
1486 uint64_t data
= vfio_vga_read(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
1487 addr
+ quirk
->data
.base_offset
, size
);
1489 if (quirk
->data
.flags
== NV_3D0_READ
&& addr
== quirk
->data
.data_offset
) {
1490 data
= vfio_pci_read_config(pdev
, quirk
->data
.address_val
, size
);
1491 DPRINTF("%s(0x3d0, %d) = 0x%"PRIx64
"\n", __func__
, size
, data
);
1494 quirk
->data
.flags
= NV_3D0_NONE
;
1499 static void vfio_nvidia_3d0_quirk_write(void *opaque
, hwaddr addr
,
1500 uint64_t data
, unsigned size
)
1502 VFIOQuirk
*quirk
= opaque
;
1503 VFIODevice
*vdev
= quirk
->vdev
;
1504 PCIDevice
*pdev
= &vdev
->pdev
;
1506 switch (quirk
->data
.flags
) {
1508 if (addr
== quirk
->data
.address_offset
&& data
== 0x338) {
1509 quirk
->data
.flags
= NV_3D0_SELECT
;
1513 quirk
->data
.flags
= NV_3D0_NONE
;
1514 if (addr
== quirk
->data
.data_offset
&&
1515 (data
& ~quirk
->data
.address_mask
) == quirk
->data
.address_match
) {
1516 quirk
->data
.flags
= NV_3D0_WINDOW
;
1517 quirk
->data
.address_val
= data
& quirk
->data
.address_mask
;
1521 quirk
->data
.flags
= NV_3D0_NONE
;
1522 if (addr
== quirk
->data
.address_offset
) {
1523 if (data
== 0x538) {
1524 quirk
->data
.flags
= NV_3D0_READ
;
1525 } else if (data
== 0x738) {
1526 quirk
->data
.flags
= NV_3D0_WRITE
;
1531 quirk
->data
.flags
= NV_3D0_NONE
;
1532 if (addr
== quirk
->data
.data_offset
) {
1533 vfio_pci_write_config(pdev
, quirk
->data
.address_val
, data
, size
);
1534 DPRINTF("%s(0x3d0, 0x%"PRIx64
", %d)\n", __func__
, data
, size
);
1540 vfio_vga_write(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
1541 addr
+ quirk
->data
.base_offset
, data
, size
);
1544 static const MemoryRegionOps vfio_nvidia_3d0_quirk
= {
1545 .read
= vfio_nvidia_3d0_quirk_read
,
1546 .write
= vfio_nvidia_3d0_quirk_write
,
1547 .endianness
= DEVICE_LITTLE_ENDIAN
,
1550 static void vfio_vga_probe_nvidia_3d0_quirk(VFIODevice
*vdev
)
1552 PCIDevice
*pdev
= &vdev
->pdev
;
1555 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
||
1556 !vdev
->bars
[1].size
) {
1560 quirk
= g_malloc0(sizeof(*quirk
));
1562 quirk
->data
.base_offset
= 0x10;
1563 quirk
->data
.address_offset
= 4;
1564 quirk
->data
.address_size
= 2;
1565 quirk
->data
.address_match
= 0x1800;
1566 quirk
->data
.address_mask
= PCI_CONFIG_SPACE_SIZE
- 1;
1567 quirk
->data
.data_offset
= 0;
1568 quirk
->data
.data_size
= 4;
1570 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_nvidia_3d0_quirk
,
1571 quirk
, "vfio-nvidia-3d0-quirk", 6);
1572 memory_region_add_subregion(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
1573 quirk
->data
.base_offset
, &quirk
->mem
);
1575 QLIST_INSERT_HEAD(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
,
1578 DPRINTF("Enabled NVIDIA VGA 0x3d0 quirk for device %04x:%02x:%02x.%x\n",
1579 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1580 vdev
->host
.function
);
1584 * The second quirk is documented in envytools. The I/O port BAR5 is just
1585 * a set of address/data ports to the MMIO BARs. The BAR we care about is
1586 * again BAR0. This backdoor is apparently a bit newer than the one above
1587 * so we need to not only trap 256 bytes @0x1800, but all of PCI config
1588 * space, including extended space is available at the 4k @0x88000.
1591 NV_BAR5_ADDRESS
= 0x1,
1592 NV_BAR5_ENABLE
= 0x2,
1593 NV_BAR5_MASTER
= 0x4,
1594 NV_BAR5_VALID
= 0x7,
1597 static void vfio_nvidia_bar5_window_quirk_write(void *opaque
, hwaddr addr
,
1598 uint64_t data
, unsigned size
)
1600 VFIOQuirk
*quirk
= opaque
;
1605 quirk
->data
.flags
|= NV_BAR5_MASTER
;
1607 quirk
->data
.flags
&= ~NV_BAR5_MASTER
;
1612 quirk
->data
.flags
|= NV_BAR5_ENABLE
;
1614 quirk
->data
.flags
&= ~NV_BAR5_ENABLE
;
1618 if (quirk
->data
.flags
& NV_BAR5_MASTER
) {
1619 if ((data
& ~0xfff) == 0x88000) {
1620 quirk
->data
.flags
|= NV_BAR5_ADDRESS
;
1621 quirk
->data
.address_val
= data
& 0xfff;
1622 } else if ((data
& ~0xff) == 0x1800) {
1623 quirk
->data
.flags
|= NV_BAR5_ADDRESS
;
1624 quirk
->data
.address_val
= data
& 0xff;
1626 quirk
->data
.flags
&= ~NV_BAR5_ADDRESS
;
1632 vfio_generic_window_quirk_write(opaque
, addr
, data
, size
);
1635 static const MemoryRegionOps vfio_nvidia_bar5_window_quirk
= {
1636 .read
= vfio_generic_window_quirk_read
,
1637 .write
= vfio_nvidia_bar5_window_quirk_write
,
1638 .valid
.min_access_size
= 4,
1639 .endianness
= DEVICE_LITTLE_ENDIAN
,
1642 static void vfio_probe_nvidia_bar5_window_quirk(VFIODevice
*vdev
, int nr
)
1644 PCIDevice
*pdev
= &vdev
->pdev
;
1647 if (!vdev
->has_vga
|| nr
!= 5 ||
1648 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
1652 quirk
= g_malloc0(sizeof(*quirk
));
1654 quirk
->data
.read_flags
= quirk
->data
.write_flags
= NV_BAR5_VALID
;
1655 quirk
->data
.address_offset
= 0x8;
1656 quirk
->data
.address_size
= 0; /* actually 4, but avoids generic code */
1657 quirk
->data
.data_offset
= 0xc;
1658 quirk
->data
.data_size
= 4;
1659 quirk
->data
.bar
= nr
;
1661 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
),
1662 &vfio_nvidia_bar5_window_quirk
, quirk
,
1663 "vfio-nvidia-bar5-window-quirk", 16);
1664 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
, 0, &quirk
->mem
, 1);
1666 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1668 DPRINTF("Enabled NVIDIA BAR5 window quirk for device %04x:%02x:%02x.%x\n",
1669 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1670 vdev
->host
.function
);
1674 * Finally, BAR0 itself. We want to redirect any accesses to either
1675 * 0x1800 or 0x88000 through the PCI config space access functions.
1677 * NB - quirk at a page granularity or else they don't seem to work when
1680 * Here's offset 0x88000...
1682 static void vfio_probe_nvidia_bar0_88000_quirk(VFIODevice
*vdev
, int nr
)
1684 PCIDevice
*pdev
= &vdev
->pdev
;
1687 if (!vdev
->has_vga
|| nr
!= 0 ||
1688 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
1692 quirk
= g_malloc0(sizeof(*quirk
));
1694 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1695 quirk
->data
.address_match
= 0x88000;
1696 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1697 quirk
->data
.bar
= nr
;
1699 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
,
1700 quirk
, "vfio-nvidia-bar0-88000-quirk",
1701 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1702 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
1703 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1706 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1708 DPRINTF("Enabled NVIDIA BAR0 0x88000 quirk for device %04x:%02x:%02x.%x\n",
1709 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1710 vdev
->host
.function
);
1714 * And here's the same for BAR0 offset 0x1800...
1716 static void vfio_probe_nvidia_bar0_1800_quirk(VFIODevice
*vdev
, int nr
)
1718 PCIDevice
*pdev
= &vdev
->pdev
;
1721 if (!vdev
->has_vga
|| nr
!= 0 ||
1722 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
1726 /* Log the chipset ID */
1727 DPRINTF("Nvidia NV%02x\n",
1728 (unsigned int)(vfio_bar_read(&vdev
->bars
[0], 0, 4) >> 20) & 0xff);
1730 quirk
= g_malloc0(sizeof(*quirk
));
1732 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1733 quirk
->data
.address_match
= 0x1800;
1734 quirk
->data
.address_mask
= PCI_CONFIG_SPACE_SIZE
- 1;
1735 quirk
->data
.bar
= nr
;
1737 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
, quirk
,
1738 "vfio-nvidia-bar0-1800-quirk",
1739 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1740 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].mem
,
1741 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1744 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1746 DPRINTF("Enabled NVIDIA BAR0 0x1800 quirk for device %04x:%02x:%02x.%x\n",
1747 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1748 vdev
->host
.function
);
1752 * TODO - Some Nvidia devices provide config access to their companion HDA
1753 * device and even to their parent bridge via these config space mirrors.
1754 * Add quirks for those regions.
1758 * Common quirk probe entry points.
1760 static void vfio_vga_quirk_setup(VFIODevice
*vdev
)
1762 vfio_vga_probe_ati_3c3_quirk(vdev
);
1763 vfio_vga_probe_nvidia_3d0_quirk(vdev
);
1766 static void vfio_vga_quirk_teardown(VFIODevice
*vdev
)
1770 for (i
= 0; i
< ARRAY_SIZE(vdev
->vga
.region
); i
++) {
1771 while (!QLIST_EMPTY(&vdev
->vga
.region
[i
].quirks
)) {
1772 VFIOQuirk
*quirk
= QLIST_FIRST(&vdev
->vga
.region
[i
].quirks
);
1773 memory_region_del_subregion(&vdev
->vga
.region
[i
].mem
, &quirk
->mem
);
1774 QLIST_REMOVE(quirk
, next
);
1780 static void vfio_bar_quirk_setup(VFIODevice
*vdev
, int nr
)
1782 vfio_probe_ati_bar4_window_quirk(vdev
, nr
);
1783 vfio_probe_ati_bar2_4000_quirk(vdev
, nr
);
1784 vfio_probe_nvidia_bar5_window_quirk(vdev
, nr
);
1785 vfio_probe_nvidia_bar0_88000_quirk(vdev
, nr
);
1786 vfio_probe_nvidia_bar0_1800_quirk(vdev
, nr
);
1789 static void vfio_bar_quirk_teardown(VFIODevice
*vdev
, int nr
)
1791 VFIOBAR
*bar
= &vdev
->bars
[nr
];
1793 while (!QLIST_EMPTY(&bar
->quirks
)) {
1794 VFIOQuirk
*quirk
= QLIST_FIRST(&bar
->quirks
);
1795 memory_region_del_subregion(&bar
->mem
, &quirk
->mem
);
1796 QLIST_REMOVE(quirk
, next
);
1804 static uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
)
1806 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
1807 uint32_t emu_bits
= 0, emu_val
= 0, phys_val
= 0, val
;
1809 memcpy(&emu_bits
, vdev
->emulated_config_bits
+ addr
, len
);
1810 emu_bits
= le32_to_cpu(emu_bits
);
1813 emu_val
= pci_default_read_config(pdev
, addr
, len
);
1816 if (~emu_bits
& (0xffffffffU
>> (32 - len
* 8))) {
1819 ret
= pread(vdev
->fd
, &phys_val
, len
, vdev
->config_offset
+ addr
);
1821 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x) failed: %m",
1822 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
1823 vdev
->host
.slot
, vdev
->host
.function
, addr
, len
);
1826 phys_val
= le32_to_cpu(phys_val
);
1829 val
= (emu_val
& emu_bits
) | (phys_val
& ~emu_bits
);
1831 DPRINTF("%s(%04x:%02x:%02x.%x, @0x%x, len=0x%x) %x\n", __func__
,
1832 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1833 vdev
->host
.function
, addr
, len
, val
);
1838 static void vfio_pci_write_config(PCIDevice
*pdev
, uint32_t addr
,
1839 uint32_t val
, int len
)
1841 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
1842 uint32_t val_le
= cpu_to_le32(val
);
1844 DPRINTF("%s(%04x:%02x:%02x.%x, @0x%x, 0x%x, len=0x%x)\n", __func__
,
1845 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1846 vdev
->host
.function
, addr
, val
, len
);
1848 /* Write everything to VFIO, let it filter out what we can't write */
1849 if (pwrite(vdev
->fd
, &val_le
, len
, vdev
->config_offset
+ addr
) != len
) {
1850 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x, 0x%x) failed: %m",
1851 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
1852 vdev
->host
.slot
, vdev
->host
.function
, addr
, val
, len
);
1855 /* MSI/MSI-X Enabling/Disabling */
1856 if (pdev
->cap_present
& QEMU_PCI_CAP_MSI
&&
1857 ranges_overlap(addr
, len
, pdev
->msi_cap
, vdev
->msi_cap_size
)) {
1858 int is_enabled
, was_enabled
= msi_enabled(pdev
);
1860 pci_default_write_config(pdev
, addr
, val
, len
);
1862 is_enabled
= msi_enabled(pdev
);
1866 vfio_enable_msi(vdev
);
1870 vfio_disable_msi(vdev
);
1872 vfio_update_msi(vdev
);
1875 } else if (pdev
->cap_present
& QEMU_PCI_CAP_MSIX
&&
1876 ranges_overlap(addr
, len
, pdev
->msix_cap
, MSIX_CAP_LENGTH
)) {
1877 int is_enabled
, was_enabled
= msix_enabled(pdev
);
1879 pci_default_write_config(pdev
, addr
, val
, len
);
1881 is_enabled
= msix_enabled(pdev
);
1883 if (!was_enabled
&& is_enabled
) {
1884 vfio_enable_msix(vdev
);
1885 } else if (was_enabled
&& !is_enabled
) {
1886 vfio_disable_msix(vdev
);
1889 /* Write everything to QEMU to keep emulated bits correct */
1890 pci_default_write_config(pdev
, addr
, val
, len
);
1895 * DMA - Mapping and unmapping for the "type1" IOMMU interface used on x86
1897 static int vfio_dma_unmap(VFIOContainer
*container
,
1898 hwaddr iova
, ram_addr_t size
)
1900 struct vfio_iommu_type1_dma_unmap unmap
= {
1901 .argsz
= sizeof(unmap
),
1907 if (ioctl(container
->fd
, VFIO_IOMMU_UNMAP_DMA
, &unmap
)) {
1908 DPRINTF("VFIO_UNMAP_DMA: %d\n", -errno
);
1915 static int vfio_dma_map(VFIOContainer
*container
, hwaddr iova
,
1916 ram_addr_t size
, void *vaddr
, bool readonly
)
1918 struct vfio_iommu_type1_dma_map map
= {
1919 .argsz
= sizeof(map
),
1920 .flags
= VFIO_DMA_MAP_FLAG_READ
,
1921 .vaddr
= (__u64
)(uintptr_t)vaddr
,
1927 map
.flags
|= VFIO_DMA_MAP_FLAG_WRITE
;
1931 * Try the mapping, if it fails with EBUSY, unmap the region and try
1932 * again. This shouldn't be necessary, but we sometimes see it in
1933 * the the VGA ROM space.
1935 if (ioctl(container
->fd
, VFIO_IOMMU_MAP_DMA
, &map
) == 0 ||
1936 (errno
== EBUSY
&& vfio_dma_unmap(container
, iova
, size
) == 0 &&
1937 ioctl(container
->fd
, VFIO_IOMMU_MAP_DMA
, &map
) == 0)) {
1941 DPRINTF("VFIO_MAP_DMA: %d\n", -errno
);
1945 static bool vfio_listener_skipped_section(MemoryRegionSection
*section
)
1947 return !memory_region_is_ram(section
->mr
);
1950 static void vfio_listener_region_add(MemoryListener
*listener
,
1951 MemoryRegionSection
*section
)
1953 VFIOContainer
*container
= container_of(listener
, VFIOContainer
,
1954 iommu_data
.listener
);
1959 assert(!memory_region_is_iommu(section
->mr
));
1961 if (vfio_listener_skipped_section(section
)) {
1962 DPRINTF("SKIPPING region_add %"HWADDR_PRIx
" - %"PRIx64
"\n",
1963 section
->offset_within_address_space
,
1964 section
->offset_within_address_space
+ section
->size
- 1);
1968 if (unlikely((section
->offset_within_address_space
& ~TARGET_PAGE_MASK
) !=
1969 (section
->offset_within_region
& ~TARGET_PAGE_MASK
))) {
1970 error_report("%s received unaligned region", __func__
);
1974 iova
= TARGET_PAGE_ALIGN(section
->offset_within_address_space
);
1975 end
= (section
->offset_within_address_space
+ int128_get64(section
->size
)) &
1982 vaddr
= memory_region_get_ram_ptr(section
->mr
) +
1983 section
->offset_within_region
+
1984 (iova
- section
->offset_within_address_space
);
1986 DPRINTF("region_add %"HWADDR_PRIx
" - %"HWADDR_PRIx
" [%p]\n",
1987 iova
, end
- 1, vaddr
);
1989 memory_region_ref(section
->mr
);
1990 ret
= vfio_dma_map(container
, iova
, end
- iova
, vaddr
, section
->readonly
);
1992 error_report("vfio_dma_map(%p, 0x%"HWADDR_PRIx
", "
1993 "0x%"HWADDR_PRIx
", %p) = %d (%m)",
1994 container
, iova
, end
- iova
, vaddr
, ret
);
1998 static void vfio_listener_region_del(MemoryListener
*listener
,
1999 MemoryRegionSection
*section
)
2001 VFIOContainer
*container
= container_of(listener
, VFIOContainer
,
2002 iommu_data
.listener
);
2006 if (vfio_listener_skipped_section(section
)) {
2007 DPRINTF("SKIPPING region_del %"HWADDR_PRIx
" - %"PRIx64
"\n",
2008 section
->offset_within_address_space
,
2009 section
->offset_within_address_space
+ section
->size
- 1);
2013 if (unlikely((section
->offset_within_address_space
& ~TARGET_PAGE_MASK
) !=
2014 (section
->offset_within_region
& ~TARGET_PAGE_MASK
))) {
2015 error_report("%s received unaligned region", __func__
);
2019 iova
= TARGET_PAGE_ALIGN(section
->offset_within_address_space
);
2020 end
= (section
->offset_within_address_space
+ int128_get64(section
->size
)) &
2027 DPRINTF("region_del %"HWADDR_PRIx
" - %"HWADDR_PRIx
"\n",
2030 ret
= vfio_dma_unmap(container
, iova
, end
- iova
);
2031 memory_region_unref(section
->mr
);
2033 error_report("vfio_dma_unmap(%p, 0x%"HWADDR_PRIx
", "
2034 "0x%"HWADDR_PRIx
") = %d (%m)",
2035 container
, iova
, end
- iova
, ret
);
2039 static MemoryListener vfio_memory_listener
= {
2040 .region_add
= vfio_listener_region_add
,
2041 .region_del
= vfio_listener_region_del
,
2044 static void vfio_listener_release(VFIOContainer
*container
)
2046 memory_listener_unregister(&container
->iommu_data
.listener
);
2052 static void vfio_disable_interrupts(VFIODevice
*vdev
)
2054 switch (vdev
->interrupt
) {
2056 vfio_disable_intx(vdev
);
2059 vfio_disable_msi(vdev
);
2062 vfio_disable_msix(vdev
);
2067 static int vfio_setup_msi(VFIODevice
*vdev
, int pos
)
2070 bool msi_64bit
, msi_maskbit
;
2073 if (pread(vdev
->fd
, &ctrl
, sizeof(ctrl
),
2074 vdev
->config_offset
+ pos
+ PCI_CAP_FLAGS
) != sizeof(ctrl
)) {
2077 ctrl
= le16_to_cpu(ctrl
);
2079 msi_64bit
= !!(ctrl
& PCI_MSI_FLAGS_64BIT
);
2080 msi_maskbit
= !!(ctrl
& PCI_MSI_FLAGS_MASKBIT
);
2081 entries
= 1 << ((ctrl
& PCI_MSI_FLAGS_QMASK
) >> 1);
2083 DPRINTF("%04x:%02x:%02x.%x PCI MSI CAP @0x%x\n", vdev
->host
.domain
,
2084 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
, pos
);
2086 ret
= msi_init(&vdev
->pdev
, pos
, entries
, msi_64bit
, msi_maskbit
);
2088 if (ret
== -ENOTSUP
) {
2091 error_report("vfio: msi_init failed");
2094 vdev
->msi_cap_size
= 0xa + (msi_maskbit
? 0xa : 0) + (msi_64bit
? 0x4 : 0);
2100 * We don't have any control over how pci_add_capability() inserts
2101 * capabilities into the chain. In order to setup MSI-X we need a
2102 * MemoryRegion for the BAR. In order to setup the BAR and not
2103 * attempt to mmap the MSI-X table area, which VFIO won't allow, we
2104 * need to first look for where the MSI-X table lives. So we
2105 * unfortunately split MSI-X setup across two functions.
2107 static int vfio_early_setup_msix(VFIODevice
*vdev
)
2111 uint32_t table
, pba
;
2113 pos
= pci_find_capability(&vdev
->pdev
, PCI_CAP_ID_MSIX
);
2118 if (pread(vdev
->fd
, &ctrl
, sizeof(ctrl
),
2119 vdev
->config_offset
+ pos
+ PCI_CAP_FLAGS
) != sizeof(ctrl
)) {
2123 if (pread(vdev
->fd
, &table
, sizeof(table
),
2124 vdev
->config_offset
+ pos
+ PCI_MSIX_TABLE
) != sizeof(table
)) {
2128 if (pread(vdev
->fd
, &pba
, sizeof(pba
),
2129 vdev
->config_offset
+ pos
+ PCI_MSIX_PBA
) != sizeof(pba
)) {
2133 ctrl
= le16_to_cpu(ctrl
);
2134 table
= le32_to_cpu(table
);
2135 pba
= le32_to_cpu(pba
);
2137 vdev
->msix
= g_malloc0(sizeof(*(vdev
->msix
)));
2138 vdev
->msix
->table_bar
= table
& PCI_MSIX_FLAGS_BIRMASK
;
2139 vdev
->msix
->table_offset
= table
& ~PCI_MSIX_FLAGS_BIRMASK
;
2140 vdev
->msix
->pba_bar
= pba
& PCI_MSIX_FLAGS_BIRMASK
;
2141 vdev
->msix
->pba_offset
= pba
& ~PCI_MSIX_FLAGS_BIRMASK
;
2142 vdev
->msix
->entries
= (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
2144 DPRINTF("%04x:%02x:%02x.%x "
2145 "PCI MSI-X CAP @0x%x, BAR %d, offset 0x%x, entries %d\n",
2146 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2147 vdev
->host
.function
, pos
, vdev
->msix
->table_bar
,
2148 vdev
->msix
->table_offset
, vdev
->msix
->entries
);
2153 static int vfio_setup_msix(VFIODevice
*vdev
, int pos
)
2157 ret
= msix_init(&vdev
->pdev
, vdev
->msix
->entries
,
2158 &vdev
->bars
[vdev
->msix
->table_bar
].mem
,
2159 vdev
->msix
->table_bar
, vdev
->msix
->table_offset
,
2160 &vdev
->bars
[vdev
->msix
->pba_bar
].mem
,
2161 vdev
->msix
->pba_bar
, vdev
->msix
->pba_offset
, pos
);
2163 if (ret
== -ENOTSUP
) {
2166 error_report("vfio: msix_init failed");
2173 static void vfio_teardown_msi(VFIODevice
*vdev
)
2175 msi_uninit(&vdev
->pdev
);
2178 msix_uninit(&vdev
->pdev
, &vdev
->bars
[vdev
->msix
->table_bar
].mem
,
2179 &vdev
->bars
[vdev
->msix
->pba_bar
].mem
);
2186 static void vfio_mmap_set_enabled(VFIODevice
*vdev
, bool enabled
)
2190 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2191 VFIOBAR
*bar
= &vdev
->bars
[i
];
2197 memory_region_set_enabled(&bar
->mmap_mem
, enabled
);
2198 if (vdev
->msix
&& vdev
->msix
->table_bar
== i
) {
2199 memory_region_set_enabled(&vdev
->msix
->mmap_mem
, enabled
);
2204 static void vfio_unmap_bar(VFIODevice
*vdev
, int nr
)
2206 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2212 vfio_bar_quirk_teardown(vdev
, nr
);
2214 memory_region_del_subregion(&bar
->mem
, &bar
->mmap_mem
);
2215 munmap(bar
->mmap
, memory_region_size(&bar
->mmap_mem
));
2217 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2218 memory_region_del_subregion(&bar
->mem
, &vdev
->msix
->mmap_mem
);
2219 munmap(vdev
->msix
->mmap
, memory_region_size(&vdev
->msix
->mmap_mem
));
2222 memory_region_destroy(&bar
->mem
);
2225 static int vfio_mmap_bar(VFIODevice
*vdev
, VFIOBAR
*bar
,
2226 MemoryRegion
*mem
, MemoryRegion
*submem
,
2227 void **map
, size_t size
, off_t offset
,
2232 if (VFIO_ALLOW_MMAP
&& size
&& bar
->flags
& VFIO_REGION_INFO_FLAG_MMAP
) {
2235 if (bar
->flags
& VFIO_REGION_INFO_FLAG_READ
) {
2239 if (bar
->flags
& VFIO_REGION_INFO_FLAG_WRITE
) {
2243 *map
= mmap(NULL
, size
, prot
, MAP_SHARED
,
2244 bar
->fd
, bar
->fd_offset
+ offset
);
2245 if (*map
== MAP_FAILED
) {
2251 memory_region_init_ram_ptr(submem
, OBJECT(vdev
), name
, size
, *map
);
2254 /* Create a zero sized sub-region to make cleanup easy. */
2255 memory_region_init(submem
, OBJECT(vdev
), name
, 0);
2258 memory_region_add_subregion(mem
, offset
, submem
);
2263 static void vfio_map_bar(VFIODevice
*vdev
, int nr
)
2265 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2266 unsigned size
= bar
->size
;
2272 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */
2277 snprintf(name
, sizeof(name
), "VFIO %04x:%02x:%02x.%x BAR %d",
2278 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2279 vdev
->host
.function
, nr
);
2281 /* Determine what type of BAR this is for registration */
2282 ret
= pread(vdev
->fd
, &pci_bar
, sizeof(pci_bar
),
2283 vdev
->config_offset
+ PCI_BASE_ADDRESS_0
+ (4 * nr
));
2284 if (ret
!= sizeof(pci_bar
)) {
2285 error_report("vfio: Failed to read BAR %d (%m)", nr
);
2289 pci_bar
= le32_to_cpu(pci_bar
);
2290 bar
->ioport
= (pci_bar
& PCI_BASE_ADDRESS_SPACE_IO
);
2291 bar
->mem64
= bar
->ioport
? 0 : (pci_bar
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
2292 type
= pci_bar
& (bar
->ioport
? ~PCI_BASE_ADDRESS_IO_MASK
:
2293 ~PCI_BASE_ADDRESS_MEM_MASK
);
2295 /* A "slow" read/write mapping underlies all BARs */
2296 memory_region_init_io(&bar
->mem
, OBJECT(vdev
), &vfio_bar_ops
,
2298 pci_register_bar(&vdev
->pdev
, nr
, type
, &bar
->mem
);
2301 * We can't mmap areas overlapping the MSIX vector table, so we
2302 * potentially insert a direct-mapped subregion before and after it.
2304 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2305 size
= vdev
->msix
->table_offset
& TARGET_PAGE_MASK
;
2308 strncat(name
, " mmap", sizeof(name
) - strlen(name
) - 1);
2309 if (vfio_mmap_bar(vdev
, bar
, &bar
->mem
,
2310 &bar
->mmap_mem
, &bar
->mmap
, size
, 0, name
)) {
2311 error_report("%s unsupported. Performance may be slow", name
);
2314 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2317 start
= TARGET_PAGE_ALIGN(vdev
->msix
->table_offset
+
2318 (vdev
->msix
->entries
* PCI_MSIX_ENTRY_SIZE
));
2320 size
= start
< bar
->size
? bar
->size
- start
: 0;
2321 strncat(name
, " msix-hi", sizeof(name
) - strlen(name
) - 1);
2322 /* VFIOMSIXInfo contains another MemoryRegion for this mapping */
2323 if (vfio_mmap_bar(vdev
, bar
, &bar
->mem
, &vdev
->msix
->mmap_mem
,
2324 &vdev
->msix
->mmap
, size
, start
, name
)) {
2325 error_report("%s unsupported. Performance may be slow", name
);
2329 vfio_bar_quirk_setup(vdev
, nr
);
2332 static void vfio_map_bars(VFIODevice
*vdev
)
2336 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2337 vfio_map_bar(vdev
, i
);
2340 if (vdev
->has_vga
) {
2341 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
,
2342 OBJECT(vdev
), &vfio_vga_ops
,
2343 &vdev
->vga
.region
[QEMU_PCI_VGA_MEM
],
2344 "vfio-vga-mmio@0xa0000",
2345 QEMU_PCI_VGA_MEM_SIZE
);
2346 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
,
2347 OBJECT(vdev
), &vfio_vga_ops
,
2348 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
],
2349 "vfio-vga-io@0x3b0",
2350 QEMU_PCI_VGA_IO_LO_SIZE
);
2351 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
2352 OBJECT(vdev
), &vfio_vga_ops
,
2353 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
2354 "vfio-vga-io@0x3c0",
2355 QEMU_PCI_VGA_IO_HI_SIZE
);
2357 pci_register_vga(&vdev
->pdev
, &vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
,
2358 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
,
2359 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
);
2360 vfio_vga_quirk_setup(vdev
);
2364 static void vfio_unmap_bars(VFIODevice
*vdev
)
2368 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2369 vfio_unmap_bar(vdev
, i
);
2372 if (vdev
->has_vga
) {
2373 vfio_vga_quirk_teardown(vdev
);
2374 pci_unregister_vga(&vdev
->pdev
);
2375 memory_region_destroy(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
);
2376 memory_region_destroy(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
);
2377 memory_region_destroy(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
);
2384 static uint8_t vfio_std_cap_max_size(PCIDevice
*pdev
, uint8_t pos
)
2386 uint8_t tmp
, next
= 0xff;
2388 for (tmp
= pdev
->config
[PCI_CAPABILITY_LIST
]; tmp
;
2389 tmp
= pdev
->config
[tmp
+ 1]) {
2390 if (tmp
> pos
&& tmp
< next
) {
2398 static void vfio_set_word_bits(uint8_t *buf
, uint16_t val
, uint16_t mask
)
2400 pci_set_word(buf
, (pci_get_word(buf
) & ~mask
) | val
);
2403 static void vfio_add_emulated_word(VFIODevice
*vdev
, int pos
,
2404 uint16_t val
, uint16_t mask
)
2406 vfio_set_word_bits(vdev
->pdev
.config
+ pos
, val
, mask
);
2407 vfio_set_word_bits(vdev
->pdev
.wmask
+ pos
, ~mask
, mask
);
2408 vfio_set_word_bits(vdev
->emulated_config_bits
+ pos
, mask
, mask
);
2411 static void vfio_set_long_bits(uint8_t *buf
, uint32_t val
, uint32_t mask
)
2413 pci_set_long(buf
, (pci_get_long(buf
) & ~mask
) | val
);
2416 static void vfio_add_emulated_long(VFIODevice
*vdev
, int pos
,
2417 uint32_t val
, uint32_t mask
)
2419 vfio_set_long_bits(vdev
->pdev
.config
+ pos
, val
, mask
);
2420 vfio_set_long_bits(vdev
->pdev
.wmask
+ pos
, ~mask
, mask
);
2421 vfio_set_long_bits(vdev
->emulated_config_bits
+ pos
, mask
, mask
);
2424 static int vfio_setup_pcie_cap(VFIODevice
*vdev
, int pos
, uint8_t size
)
2429 flags
= pci_get_word(vdev
->pdev
.config
+ pos
+ PCI_CAP_FLAGS
);
2430 type
= (flags
& PCI_EXP_FLAGS_TYPE
) >> 4;
2432 if (type
!= PCI_EXP_TYPE_ENDPOINT
&&
2433 type
!= PCI_EXP_TYPE_LEG_END
&&
2434 type
!= PCI_EXP_TYPE_RC_END
) {
2436 error_report("vfio: Assignment of PCIe type 0x%x "
2437 "devices is not currently supported", type
);
2441 if (!pci_bus_is_express(vdev
->pdev
.bus
)) {
2443 * Use express capability as-is on PCI bus. It doesn't make much
2444 * sense to even expose, but some drivers (ex. tg3) depend on it
2445 * and guests don't seem to be particular about it. We'll need
2446 * to revist this or force express devices to express buses if we
2447 * ever expose an IOMMU to the guest.
2449 } else if (pci_bus_is_root(vdev
->pdev
.bus
)) {
2451 * On a Root Complex bus Endpoints become Root Complex Integrated
2452 * Endpoints, which changes the type and clears the LNK & LNK2 fields.
2454 if (type
== PCI_EXP_TYPE_ENDPOINT
) {
2455 vfio_add_emulated_word(vdev
, pos
+ PCI_CAP_FLAGS
,
2456 PCI_EXP_TYPE_RC_END
<< 4,
2457 PCI_EXP_FLAGS_TYPE
);
2459 /* Link Capabilities, Status, and Control goes away */
2460 if (size
> PCI_EXP_LNKCTL
) {
2461 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP
, 0, ~0);
2462 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL
, 0, ~0);
2463 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA
, 0, ~0);
2465 #ifndef PCI_EXP_LNKCAP2
2466 #define PCI_EXP_LNKCAP2 44
2468 #ifndef PCI_EXP_LNKSTA2
2469 #define PCI_EXP_LNKSTA2 50
2471 /* Link 2 Capabilities, Status, and Control goes away */
2472 if (size
> PCI_EXP_LNKCAP2
) {
2473 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP2
, 0, ~0);
2474 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL2
, 0, ~0);
2475 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA2
, 0, ~0);
2479 } else if (type
== PCI_EXP_TYPE_LEG_END
) {
2481 * Legacy endpoints don't belong on the root complex. Windows
2482 * seems to be happier with devices if we skip the capability.
2489 * Convert Root Complex Integrated Endpoints to regular endpoints.
2490 * These devices don't support LNK/LNK2 capabilities, so make them up.
2492 if (type
== PCI_EXP_TYPE_RC_END
) {
2493 vfio_add_emulated_word(vdev
, pos
+ PCI_CAP_FLAGS
,
2494 PCI_EXP_TYPE_ENDPOINT
<< 4,
2495 PCI_EXP_FLAGS_TYPE
);
2496 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP
,
2497 PCI_EXP_LNK_MLW_1
| PCI_EXP_LNK_LS_25
, ~0);
2498 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL
, 0, ~0);
2501 /* Mark the Link Status bits as emulated to allow virtual negotiation */
2502 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA
,
2503 pci_get_word(vdev
->pdev
.config
+ pos
+
2505 PCI_EXP_LNKCAP_MLW
| PCI_EXP_LNKCAP_SLS
);
2508 pos
= pci_add_capability(&vdev
->pdev
, PCI_CAP_ID_EXP
, pos
, size
);
2510 vdev
->pdev
.exp
.exp_cap
= pos
;
2516 static int vfio_add_std_cap(VFIODevice
*vdev
, uint8_t pos
)
2518 PCIDevice
*pdev
= &vdev
->pdev
;
2519 uint8_t cap_id
, next
, size
;
2522 cap_id
= pdev
->config
[pos
];
2523 next
= pdev
->config
[pos
+ 1];
2526 * If it becomes important to configure capabilities to their actual
2527 * size, use this as the default when it's something we don't recognize.
2528 * Since QEMU doesn't actually handle many of the config accesses,
2529 * exact size doesn't seem worthwhile.
2531 size
= vfio_std_cap_max_size(pdev
, pos
);
2534 * pci_add_capability always inserts the new capability at the head
2535 * of the chain. Therefore to end up with a chain that matches the
2536 * physical device, we insert from the end by making this recursive.
2537 * This is also why we pre-caclulate size above as cached config space
2538 * will be changed as we unwind the stack.
2541 ret
= vfio_add_std_cap(vdev
, next
);
2546 /* Begin the rebuild, use QEMU emulated list bits */
2547 pdev
->config
[PCI_CAPABILITY_LIST
] = 0;
2548 vdev
->emulated_config_bits
[PCI_CAPABILITY_LIST
] = 0xff;
2549 vdev
->emulated_config_bits
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2552 /* Use emulated next pointer to allow dropping caps */
2553 pci_set_byte(vdev
->emulated_config_bits
+ pos
+ 1, 0xff);
2556 case PCI_CAP_ID_MSI
:
2557 ret
= vfio_setup_msi(vdev
, pos
);
2559 case PCI_CAP_ID_EXP
:
2560 ret
= vfio_setup_pcie_cap(vdev
, pos
, size
);
2562 case PCI_CAP_ID_MSIX
:
2563 ret
= vfio_setup_msix(vdev
, pos
);
2568 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
2573 error_report("vfio: %04x:%02x:%02x.%x Error adding PCI capability "
2574 "0x%x[0x%x]@0x%x: %d", vdev
->host
.domain
,
2575 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
2576 cap_id
, size
, pos
, ret
);
2583 static int vfio_add_capabilities(VFIODevice
*vdev
)
2585 PCIDevice
*pdev
= &vdev
->pdev
;
2587 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
) ||
2588 !pdev
->config
[PCI_CAPABILITY_LIST
]) {
2589 return 0; /* Nothing to add */
2592 return vfio_add_std_cap(vdev
, pdev
->config
[PCI_CAPABILITY_LIST
]);
2595 static int vfio_load_rom(VFIODevice
*vdev
)
2597 uint64_t size
= vdev
->rom_size
;
2599 off_t off
= 0, voff
= vdev
->rom_offset
;
2603 /* If loading ROM from file, pci handles it */
2604 if (vdev
->pdev
.romfile
|| !vdev
->pdev
.rom_bar
|| !size
) {
2608 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
2609 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
2611 snprintf(name
, sizeof(name
), "vfio[%04x:%02x:%02x.%x].rom",
2612 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2613 vdev
->host
.function
);
2614 memory_region_init_ram(&vdev
->pdev
.rom
, OBJECT(vdev
), name
, size
);
2615 ptr
= memory_region_get_ram_ptr(&vdev
->pdev
.rom
);
2616 memset(ptr
, 0xff, size
);
2619 bytes
= pread(vdev
->fd
, ptr
+ off
, size
, voff
+ off
);
2621 break; /* expect that we could get back less than the ROM BAR */
2622 } else if (bytes
> 0) {
2626 if (errno
== EINTR
|| errno
== EAGAIN
) {
2629 error_report("vfio: Error reading device ROM: %m");
2630 memory_region_destroy(&vdev
->pdev
.rom
);
2635 pci_register_bar(&vdev
->pdev
, PCI_ROM_SLOT
, 0, &vdev
->pdev
.rom
);
2636 vdev
->pdev
.has_rom
= true;
2640 static int vfio_connect_container(VFIOGroup
*group
)
2642 VFIOContainer
*container
;
2645 if (group
->container
) {
2649 QLIST_FOREACH(container
, &container_list
, next
) {
2650 if (!ioctl(group
->fd
, VFIO_GROUP_SET_CONTAINER
, &container
->fd
)) {
2651 group
->container
= container
;
2652 QLIST_INSERT_HEAD(&container
->group_list
, group
, container_next
);
2657 fd
= qemu_open("/dev/vfio/vfio", O_RDWR
);
2659 error_report("vfio: failed to open /dev/vfio/vfio: %m");
2663 ret
= ioctl(fd
, VFIO_GET_API_VERSION
);
2664 if (ret
!= VFIO_API_VERSION
) {
2665 error_report("vfio: supported vfio version: %d, "
2666 "reported version: %d", VFIO_API_VERSION
, ret
);
2671 container
= g_malloc0(sizeof(*container
));
2674 if (ioctl(fd
, VFIO_CHECK_EXTENSION
, VFIO_TYPE1_IOMMU
)) {
2675 ret
= ioctl(group
->fd
, VFIO_GROUP_SET_CONTAINER
, &fd
);
2677 error_report("vfio: failed to set group container: %m");
2683 ret
= ioctl(fd
, VFIO_SET_IOMMU
, VFIO_TYPE1_IOMMU
);
2685 error_report("vfio: failed to set iommu for container: %m");
2691 container
->iommu_data
.listener
= vfio_memory_listener
;
2692 container
->iommu_data
.release
= vfio_listener_release
;
2694 memory_listener_register(&container
->iommu_data
.listener
, &address_space_memory
);
2696 error_report("vfio: No available IOMMU models");
2702 QLIST_INIT(&container
->group_list
);
2703 QLIST_INSERT_HEAD(&container_list
, container
, next
);
2705 group
->container
= container
;
2706 QLIST_INSERT_HEAD(&container
->group_list
, group
, container_next
);
2711 static void vfio_disconnect_container(VFIOGroup
*group
)
2713 VFIOContainer
*container
= group
->container
;
2715 if (ioctl(group
->fd
, VFIO_GROUP_UNSET_CONTAINER
, &container
->fd
)) {
2716 error_report("vfio: error disconnecting group %d from container",
2720 QLIST_REMOVE(group
, container_next
);
2721 group
->container
= NULL
;
2723 if (QLIST_EMPTY(&container
->group_list
)) {
2724 if (container
->iommu_data
.release
) {
2725 container
->iommu_data
.release(container
);
2727 QLIST_REMOVE(container
, next
);
2728 DPRINTF("vfio_disconnect_container: close container->fd\n");
2729 close(container
->fd
);
2734 static VFIOGroup
*vfio_get_group(int groupid
)
2738 struct vfio_group_status status
= { .argsz
= sizeof(status
) };
2740 QLIST_FOREACH(group
, &group_list
, next
) {
2741 if (group
->groupid
== groupid
) {
2746 group
= g_malloc0(sizeof(*group
));
2748 snprintf(path
, sizeof(path
), "/dev/vfio/%d", groupid
);
2749 group
->fd
= qemu_open(path
, O_RDWR
);
2750 if (group
->fd
< 0) {
2751 error_report("vfio: error opening %s: %m", path
);
2756 if (ioctl(group
->fd
, VFIO_GROUP_GET_STATUS
, &status
)) {
2757 error_report("vfio: error getting group status: %m");
2763 if (!(status
.flags
& VFIO_GROUP_FLAGS_VIABLE
)) {
2764 error_report("vfio: error, group %d is not viable, please ensure "
2765 "all devices within the iommu_group are bound to their "
2766 "vfio bus driver.", groupid
);
2772 group
->groupid
= groupid
;
2773 QLIST_INIT(&group
->device_list
);
2775 if (vfio_connect_container(group
)) {
2776 error_report("vfio: failed to setup container for group %d", groupid
);
2782 QLIST_INSERT_HEAD(&group_list
, group
, next
);
2787 static void vfio_put_group(VFIOGroup
*group
)
2789 if (!QLIST_EMPTY(&group
->device_list
)) {
2793 vfio_disconnect_container(group
);
2794 QLIST_REMOVE(group
, next
);
2795 DPRINTF("vfio_put_group: close group->fd\n");
2800 static int vfio_get_device(VFIOGroup
*group
, const char *name
, VFIODevice
*vdev
)
2802 struct vfio_device_info dev_info
= { .argsz
= sizeof(dev_info
) };
2803 struct vfio_region_info reg_info
= { .argsz
= sizeof(reg_info
) };
2804 struct vfio_irq_info irq_info
= { .argsz
= sizeof(irq_info
) };
2807 ret
= ioctl(group
->fd
, VFIO_GROUP_GET_DEVICE_FD
, name
);
2809 error_report("vfio: error getting device %s from group %d: %m",
2810 name
, group
->groupid
);
2811 error_printf("Verify all devices in group %d are bound to vfio-pci "
2812 "or pci-stub and not already in use\n", group
->groupid
);
2817 vdev
->group
= group
;
2818 QLIST_INSERT_HEAD(&group
->device_list
, vdev
, next
);
2820 /* Sanity check device */
2821 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_INFO
, &dev_info
);
2823 error_report("vfio: error getting device info: %m");
2827 DPRINTF("Device %s flags: %u, regions: %u, irgs: %u\n", name
,
2828 dev_info
.flags
, dev_info
.num_regions
, dev_info
.num_irqs
);
2830 if (!(dev_info
.flags
& VFIO_DEVICE_FLAGS_PCI
)) {
2831 error_report("vfio: Um, this isn't a PCI device");
2835 vdev
->reset_works
= !!(dev_info
.flags
& VFIO_DEVICE_FLAGS_RESET
);
2836 if (!vdev
->reset_works
) {
2837 error_report("Warning, device %s does not support reset", name
);
2840 if (dev_info
.num_regions
< VFIO_PCI_CONFIG_REGION_INDEX
+ 1) {
2841 error_report("vfio: unexpected number of io regions %u",
2842 dev_info
.num_regions
);
2846 if (dev_info
.num_irqs
< VFIO_PCI_MSIX_IRQ_INDEX
+ 1) {
2847 error_report("vfio: unexpected number of irqs %u", dev_info
.num_irqs
);
2851 for (i
= VFIO_PCI_BAR0_REGION_INDEX
; i
< VFIO_PCI_ROM_REGION_INDEX
; i
++) {
2854 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
2856 error_report("vfio: Error getting region %d info: %m", i
);
2860 DPRINTF("Device %s region %d:\n", name
, i
);
2861 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
2862 (unsigned long)reg_info
.size
, (unsigned long)reg_info
.offset
,
2863 (unsigned long)reg_info
.flags
);
2865 vdev
->bars
[i
].flags
= reg_info
.flags
;
2866 vdev
->bars
[i
].size
= reg_info
.size
;
2867 vdev
->bars
[i
].fd_offset
= reg_info
.offset
;
2868 vdev
->bars
[i
].fd
= vdev
->fd
;
2869 vdev
->bars
[i
].nr
= i
;
2870 QLIST_INIT(&vdev
->bars
[i
].quirks
);
2873 reg_info
.index
= VFIO_PCI_ROM_REGION_INDEX
;
2875 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
2877 error_report("vfio: Error getting ROM info: %m");
2881 DPRINTF("Device %s ROM:\n", name
);
2882 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
2883 (unsigned long)reg_info
.size
, (unsigned long)reg_info
.offset
,
2884 (unsigned long)reg_info
.flags
);
2886 vdev
->rom_size
= reg_info
.size
;
2887 vdev
->rom_offset
= reg_info
.offset
;
2889 reg_info
.index
= VFIO_PCI_CONFIG_REGION_INDEX
;
2891 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
2893 error_report("vfio: Error getting config info: %m");
2897 DPRINTF("Device %s config:\n", name
);
2898 DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
2899 (unsigned long)reg_info
.size
, (unsigned long)reg_info
.offset
,
2900 (unsigned long)reg_info
.flags
);
2902 vdev
->config_size
= reg_info
.size
;
2903 if (vdev
->config_size
== PCI_CONFIG_SPACE_SIZE
) {
2904 vdev
->pdev
.cap_present
&= ~QEMU_PCI_CAP_EXPRESS
;
2906 vdev
->config_offset
= reg_info
.offset
;
2908 if ((vdev
->features
& VFIO_FEATURE_ENABLE_VGA
) &&
2909 dev_info
.num_regions
> VFIO_PCI_VGA_REGION_INDEX
) {
2910 struct vfio_region_info vga_info
= {
2911 .argsz
= sizeof(vga_info
),
2912 .index
= VFIO_PCI_VGA_REGION_INDEX
,
2915 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, &vga_info
);
2918 "vfio: Device does not support requested feature x-vga");
2922 if (!(vga_info
.flags
& VFIO_REGION_INFO_FLAG_READ
) ||
2923 !(vga_info
.flags
& VFIO_REGION_INFO_FLAG_WRITE
) ||
2924 vga_info
.size
< 0xbffff + 1) {
2925 error_report("vfio: Unexpected VGA info, flags 0x%lx, size 0x%lx",
2926 (unsigned long)vga_info
.flags
,
2927 (unsigned long)vga_info
.size
);
2931 vdev
->vga
.fd_offset
= vga_info
.offset
;
2932 vdev
->vga
.fd
= vdev
->fd
;
2934 vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].offset
= QEMU_PCI_VGA_MEM_BASE
;
2935 vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].nr
= QEMU_PCI_VGA_MEM
;
2936 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].quirks
);
2938 vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].offset
= QEMU_PCI_VGA_IO_LO_BASE
;
2939 vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].nr
= QEMU_PCI_VGA_IO_LO
;
2940 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].quirks
);
2942 vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].offset
= QEMU_PCI_VGA_IO_HI_BASE
;
2943 vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].nr
= QEMU_PCI_VGA_IO_HI
;
2944 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
);
2946 vdev
->has_vga
= true;
2948 irq_info
.index
= VFIO_PCI_ERR_IRQ_INDEX
;
2950 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_GET_IRQ_INFO
, &irq_info
);
2952 /* This can fail for an old kernel or legacy PCI dev */
2953 DPRINTF("VFIO_DEVICE_GET_IRQ_INFO failure ret=%d\n", ret
);
2955 } else if (irq_info
.count
== 1) {
2956 vdev
->pci_aer
= true;
2958 error_report("vfio: Warning: "
2959 "Could not enable error recovery for the device\n");
2964 QLIST_REMOVE(vdev
, next
);
2971 static void vfio_put_device(VFIODevice
*vdev
)
2973 QLIST_REMOVE(vdev
, next
);
2975 DPRINTF("vfio_put_device: close vdev->fd\n");
2983 static void vfio_err_notifier_handler(void *opaque
)
2985 VFIODevice
*vdev
= opaque
;
2987 if (!event_notifier_test_and_clear(&vdev
->err_notifier
)) {
2992 * TBD. Retrieve the error details and decide what action
2993 * needs to be taken. One of the actions could be to pass
2994 * the error to the guest and have the guest driver recover
2995 * from the error. This requires that PCIe capabilities be
2996 * exposed to the guest. For now, we just terminate the
2997 * guest to contain the error.
3000 error_report("%s (%04x:%02x:%02x.%x)"
3001 "Unrecoverable error detected...\n"
3002 "Please collect any data possible and then kill the guest",
3003 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
3004 vdev
->host
.slot
, vdev
->host
.function
);
3006 vm_stop(RUN_STATE_IO_ERROR
);
3010 * Registers error notifier for devices supporting error recovery.
3011 * If we encounter a failure in this function, we report an error
3012 * and continue after disabling error recovery support for the
3015 static void vfio_register_err_notifier(VFIODevice
*vdev
)
3019 struct vfio_irq_set
*irq_set
;
3022 if (!vdev
->pci_aer
) {
3026 if (event_notifier_init(&vdev
->err_notifier
, 0)) {
3027 error_report("vfio: Warning: "
3028 "Unable to init event notifier for error detection\n");
3029 vdev
->pci_aer
= false;
3033 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3035 irq_set
= g_malloc0(argsz
);
3036 irq_set
->argsz
= argsz
;
3037 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3038 VFIO_IRQ_SET_ACTION_TRIGGER
;
3039 irq_set
->index
= VFIO_PCI_ERR_IRQ_INDEX
;
3042 pfd
= (int32_t *)&irq_set
->data
;
3044 *pfd
= event_notifier_get_fd(&vdev
->err_notifier
);
3045 qemu_set_fd_handler(*pfd
, vfio_err_notifier_handler
, NULL
, vdev
);
3047 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
3049 error_report("vfio: Failed to set up error notification\n");
3050 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
3051 event_notifier_cleanup(&vdev
->err_notifier
);
3052 vdev
->pci_aer
= false;
3057 static void vfio_unregister_err_notifier(VFIODevice
*vdev
)
3060 struct vfio_irq_set
*irq_set
;
3064 if (!vdev
->pci_aer
) {
3068 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3070 irq_set
= g_malloc0(argsz
);
3071 irq_set
->argsz
= argsz
;
3072 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3073 VFIO_IRQ_SET_ACTION_TRIGGER
;
3074 irq_set
->index
= VFIO_PCI_ERR_IRQ_INDEX
;
3077 pfd
= (int32_t *)&irq_set
->data
;
3080 ret
= ioctl(vdev
->fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
3082 error_report("vfio: Failed to de-assign error fd: %d\n", ret
);
3085 qemu_set_fd_handler(event_notifier_get_fd(&vdev
->err_notifier
),
3087 event_notifier_cleanup(&vdev
->err_notifier
);
3090 static int vfio_initfn(PCIDevice
*pdev
)
3092 VFIODevice
*pvdev
, *vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
3094 char path
[PATH_MAX
], iommu_group_path
[PATH_MAX
], *group_name
;
3100 /* Check that the host device exists */
3101 snprintf(path
, sizeof(path
),
3102 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
3103 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3104 vdev
->host
.function
);
3105 if (stat(path
, &st
) < 0) {
3106 error_report("vfio: error: no such host device: %s", path
);
3110 strncat(path
, "iommu_group", sizeof(path
) - strlen(path
) - 1);
3112 len
= readlink(path
, iommu_group_path
, PATH_MAX
);
3114 error_report("vfio: error no iommu_group for device");
3118 iommu_group_path
[len
] = 0;
3119 group_name
= basename(iommu_group_path
);
3121 if (sscanf(group_name
, "%d", &groupid
) != 1) {
3122 error_report("vfio: error reading %s: %m", path
);
3126 DPRINTF("%s(%04x:%02x:%02x.%x) group %d\n", __func__
, vdev
->host
.domain
,
3127 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
, groupid
);
3129 group
= vfio_get_group(groupid
);
3131 error_report("vfio: failed to get group %d", groupid
);
3135 snprintf(path
, sizeof(path
), "%04x:%02x:%02x.%01x",
3136 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3137 vdev
->host
.function
);
3139 QLIST_FOREACH(pvdev
, &group
->device_list
, next
) {
3140 if (pvdev
->host
.domain
== vdev
->host
.domain
&&
3141 pvdev
->host
.bus
== vdev
->host
.bus
&&
3142 pvdev
->host
.slot
== vdev
->host
.slot
&&
3143 pvdev
->host
.function
== vdev
->host
.function
) {
3145 error_report("vfio: error: device %s is already attached", path
);
3146 vfio_put_group(group
);
3151 ret
= vfio_get_device(group
, path
, vdev
);
3153 error_report("vfio: failed to get device %s", path
);
3154 vfio_put_group(group
);
3158 /* Get a copy of config space */
3159 ret
= pread(vdev
->fd
, vdev
->pdev
.config
,
3160 MIN(pci_config_size(&vdev
->pdev
), vdev
->config_size
),
3161 vdev
->config_offset
);
3162 if (ret
< (int)MIN(pci_config_size(&vdev
->pdev
), vdev
->config_size
)) {
3163 ret
= ret
< 0 ? -errno
: -EFAULT
;
3164 error_report("vfio: Failed to read device config space");
3168 /* vfio emulates a lot for us, but some bits need extra love */
3169 vdev
->emulated_config_bits
= g_malloc0(vdev
->config_size
);
3171 /* QEMU can choose to expose the ROM or not */
3172 memset(vdev
->emulated_config_bits
+ PCI_ROM_ADDRESS
, 0xff, 4);
3174 /* QEMU can change multi-function devices to single function, or reverse */
3175 vdev
->emulated_config_bits
[PCI_HEADER_TYPE
] =
3176 PCI_HEADER_TYPE_MULTI_FUNCTION
;
3179 * Clear host resource mapping info. If we choose not to register a
3180 * BAR, such as might be the case with the option ROM, we can get
3181 * confusing, unwritable, residual addresses from the host here.
3183 memset(&vdev
->pdev
.config
[PCI_BASE_ADDRESS_0
], 0, 24);
3184 memset(&vdev
->pdev
.config
[PCI_ROM_ADDRESS
], 0, 4);
3186 vfio_load_rom(vdev
);
3188 ret
= vfio_early_setup_msix(vdev
);
3193 vfio_map_bars(vdev
);
3195 ret
= vfio_add_capabilities(vdev
);
3200 /* QEMU emulates all of MSI & MSIX */
3201 if (pdev
->cap_present
& QEMU_PCI_CAP_MSIX
) {
3202 memset(vdev
->emulated_config_bits
+ pdev
->msix_cap
, 0xff,
3206 if (pdev
->cap_present
& QEMU_PCI_CAP_MSI
) {
3207 memset(vdev
->emulated_config_bits
+ pdev
->msi_cap
, 0xff,
3208 vdev
->msi_cap_size
);
3211 if (vfio_pci_read_config(&vdev
->pdev
, PCI_INTERRUPT_PIN
, 1)) {
3212 vdev
->intx
.mmap_timer
= timer_new_ms(QEMU_CLOCK_VIRTUAL
,
3213 vfio_intx_mmap_enable
, vdev
);
3214 pci_device_set_intx_routing_notifier(&vdev
->pdev
, vfio_update_irq
);
3215 ret
= vfio_enable_intx(vdev
);
3221 add_boot_device_path(vdev
->bootindex
, &pdev
->qdev
, NULL
);
3222 vfio_register_err_notifier(vdev
);
3227 pci_device_set_intx_routing_notifier(&vdev
->pdev
, NULL
);
3228 vfio_teardown_msi(vdev
);
3229 vfio_unmap_bars(vdev
);
3231 g_free(vdev
->emulated_config_bits
);
3232 vfio_put_device(vdev
);
3233 vfio_put_group(group
);
3237 static void vfio_exitfn(PCIDevice
*pdev
)
3239 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
3240 VFIOGroup
*group
= vdev
->group
;
3242 vfio_unregister_err_notifier(vdev
);
3243 pci_device_set_intx_routing_notifier(&vdev
->pdev
, NULL
);
3244 vfio_disable_interrupts(vdev
);
3245 if (vdev
->intx
.mmap_timer
) {
3246 timer_free(vdev
->intx
.mmap_timer
);
3248 vfio_teardown_msi(vdev
);
3249 vfio_unmap_bars(vdev
);
3250 g_free(vdev
->emulated_config_bits
);
3251 vfio_put_device(vdev
);
3252 vfio_put_group(group
);
3255 static void vfio_pci_reset(DeviceState
*dev
)
3257 PCIDevice
*pdev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
3258 VFIODevice
*vdev
= DO_UPCAST(VFIODevice
, pdev
, pdev
);
3261 DPRINTF("%s(%04x:%02x:%02x.%x)\n", __func__
, vdev
->host
.domain
,
3262 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
3264 vfio_disable_interrupts(vdev
);
3266 /* Make sure the device is in D0 */
3271 pmcsr
= vfio_pci_read_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, 2);
3272 state
= pmcsr
& PCI_PM_CTRL_STATE_MASK
;
3274 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
3275 vfio_pci_write_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
, 2);
3276 /* vfio handles the necessary delay here */
3277 pmcsr
= vfio_pci_read_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, 2);
3278 state
= pmcsr
& PCI_PM_CTRL_STATE_MASK
;
3280 error_report("vfio: Unable to power on device, stuck in D%d\n",
3287 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master.
3288 * Also put INTx Disable in known state.
3290 cmd
= vfio_pci_read_config(pdev
, PCI_COMMAND
, 2);
3291 cmd
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
3292 PCI_COMMAND_INTX_DISABLE
);
3293 vfio_pci_write_config(pdev
, PCI_COMMAND
, cmd
, 2);
3295 if (vdev
->reset_works
) {
3296 if (ioctl(vdev
->fd
, VFIO_DEVICE_RESET
)) {
3297 error_report("vfio: Error unable to reset physical device "
3298 "(%04x:%02x:%02x.%x): %m", vdev
->host
.domain
,
3299 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
3303 vfio_enable_intx(vdev
);
3306 static Property vfio_pci_dev_properties
[] = {
3307 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIODevice
, host
),
3308 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIODevice
,
3309 intx
.mmap_timeout
, 1100),
3310 DEFINE_PROP_BIT("x-vga", VFIODevice
, features
,
3311 VFIO_FEATURE_ENABLE_VGA_BIT
, false),
3312 DEFINE_PROP_INT32("bootindex", VFIODevice
, bootindex
, -1),
3314 * TODO - support passed fds... is this necessary?
3315 * DEFINE_PROP_STRING("vfiofd", VFIODevice, vfiofd_name),
3316 * DEFINE_PROP_STRING("vfiogroupfd, VFIODevice, vfiogroupfd_name),
3318 DEFINE_PROP_END_OF_LIST(),
3321 static const VMStateDescription vfio_pci_vmstate
= {
3326 static void vfio_pci_dev_class_init(ObjectClass
*klass
, void *data
)
3328 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3329 PCIDeviceClass
*pdc
= PCI_DEVICE_CLASS(klass
);
3331 dc
->reset
= vfio_pci_reset
;
3332 dc
->props
= vfio_pci_dev_properties
;
3333 dc
->vmsd
= &vfio_pci_vmstate
;
3334 dc
->desc
= "VFIO-based PCI device assignment";
3335 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
3336 pdc
->init
= vfio_initfn
;
3337 pdc
->exit
= vfio_exitfn
;
3338 pdc
->config_read
= vfio_pci_read_config
;
3339 pdc
->config_write
= vfio_pci_write_config
;
3340 pdc
->is_express
= 1; /* We might be */
3343 static const TypeInfo vfio_pci_dev_info
= {
3345 .parent
= TYPE_PCI_DEVICE
,
3346 .instance_size
= sizeof(VFIODevice
),
3347 .class_init
= vfio_pci_dev_class_init
,
3350 static void register_vfio_pci_dev_type(void)
3352 type_register_static(&vfio_pci_dev_info
);
3355 type_init(register_vfio_pci_dev_type
)