3 * TI X3130 pci express downstream port switch
5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "hw/pci/pci_ids.h"
24 #include "hw/pci/msi.h"
25 #include "hw/pci/pcie.h"
26 #include "xio3130_downstream.h"
28 #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
29 #define XIO3130_REVISION 0x1
30 #define XIO3130_MSI_OFFSET 0x70
31 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
32 #define XIO3130_MSI_NR_VECTOR 1
33 #define XIO3130_SSVID_OFFSET 0x80
34 #define XIO3130_SSVID_SVID 0
35 #define XIO3130_SSVID_SSID 0
36 #define XIO3130_EXP_OFFSET 0x90
37 #define XIO3130_AER_OFFSET 0x100
39 static void xio3130_downstream_write_config(PCIDevice
*d
, uint32_t address
,
40 uint32_t val
, int len
)
42 pci_bridge_write_config(d
, address
, val
, len
);
43 pcie_cap_flr_write_config(d
, address
, val
, len
);
44 pcie_cap_slot_write_config(d
, address
, val
, len
);
45 pcie_aer_write_config(d
, address
, val
, len
);
48 static void xio3130_downstream_reset(DeviceState
*qdev
)
50 PCIDevice
*d
= PCI_DEVICE(qdev
);
52 pcie_cap_deverr_reset(d
);
53 pcie_cap_slot_reset(d
);
54 pcie_cap_arifwd_reset(d
);
55 pci_bridge_reset(qdev
);
58 static int xio3130_downstream_initfn(PCIDevice
*d
)
60 PCIEPort
*p
= PCIE_PORT(d
);
61 PCIESlot
*s
= PCIE_SLOT(d
);
64 pci_bridge_initfn(d
, TYPE_PCIE_BUS
);
65 pcie_port_init_reg(d
);
67 rc
= msi_init(d
, XIO3130_MSI_OFFSET
, XIO3130_MSI_NR_VECTOR
,
68 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_64BIT
,
69 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_MASKBIT
);
74 rc
= pci_bridge_ssvid_init(d
, XIO3130_SSVID_OFFSET
,
75 XIO3130_SSVID_SVID
, XIO3130_SSVID_SSID
);
80 rc
= pcie_cap_init(d
, XIO3130_EXP_OFFSET
, PCI_EXP_TYPE_DOWNSTREAM
,
86 pcie_cap_deverr_init(d
);
87 pcie_cap_slot_init(d
, s
->slot
);
88 pcie_cap_arifwd_init(d
);
90 pcie_chassis_create(s
->chassis
);
91 rc
= pcie_chassis_add_slot(s
);
96 rc
= pcie_aer_init(d
, XIO3130_AER_OFFSET
, PCI_ERR_SIZEOF
);
104 pcie_chassis_del_slot(s
);
110 pci_bridge_exitfn(d
);
114 static void xio3130_downstream_exitfn(PCIDevice
*d
)
116 PCIESlot
*s
= PCIE_SLOT(d
);
119 pcie_chassis_del_slot(s
);
122 pci_bridge_exitfn(d
);
125 PCIESlot
*xio3130_downstream_init(PCIBus
*bus
, int devfn
, bool multifunction
,
126 const char *bus_name
, pci_map_irq_fn map_irq
,
127 uint8_t port
, uint8_t chassis
,
134 d
= pci_create_multifunction(bus
, devfn
, multifunction
,
135 "xio3130-downstream");
142 pci_bridge_map_irq(br
, bus_name
, map_irq
);
143 qdev_prop_set_uint8(qdev
, "port", port
);
144 qdev_prop_set_uint8(qdev
, "chassis", chassis
);
145 qdev_prop_set_uint16(qdev
, "slot", slot
);
146 qdev_init_nofail(qdev
);
151 static Property xio3130_downstream_props
[] = {
152 DEFINE_PROP_BIT(COMPAT_PROP_PCP
, PCIDevice
, cap_present
,
153 QEMU_PCIE_SLTCAP_PCP_BITNR
, true),
154 DEFINE_PROP_END_OF_LIST()
157 static const VMStateDescription vmstate_xio3130_downstream
= {
158 .name
= "xio3130-express-downstream-port",
160 .minimum_version_id
= 1,
161 .post_load
= pcie_cap_slot_post_load
,
162 .fields
= (VMStateField
[]) {
163 VMSTATE_PCIE_DEVICE(parent_obj
.parent_obj
.parent_obj
, PCIESlot
),
164 VMSTATE_STRUCT(parent_obj
.parent_obj
.parent_obj
.exp
.aer_log
,
165 PCIESlot
, 0, vmstate_pcie_aer_log
, PCIEAERLog
),
166 VMSTATE_END_OF_LIST()
170 static void xio3130_downstream_class_init(ObjectClass
*klass
, void *data
)
172 DeviceClass
*dc
= DEVICE_CLASS(klass
);
173 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
177 k
->config_write
= xio3130_downstream_write_config
;
178 k
->init
= xio3130_downstream_initfn
;
179 k
->exit
= xio3130_downstream_exitfn
;
180 k
->vendor_id
= PCI_VENDOR_ID_TI
;
181 k
->device_id
= PCI_DEVICE_ID_TI_XIO3130D
;
182 k
->revision
= XIO3130_REVISION
;
183 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
184 dc
->desc
= "TI X3130 Downstream Port of PCI Express Switch";
185 dc
->reset
= xio3130_downstream_reset
;
186 dc
->vmsd
= &vmstate_xio3130_downstream
;
187 dc
->props
= xio3130_downstream_props
;
190 static const TypeInfo xio3130_downstream_info
= {
191 .name
= "xio3130-downstream",
192 .parent
= TYPE_PCIE_SLOT
,
193 .class_init
= xio3130_downstream_class_init
,
196 static void xio3130_downstream_register_types(void)
198 type_register_static(&xio3130_downstream_info
);
201 type_init(xio3130_downstream_register_types
)
208 * indent-tab-mode: nil