?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
trace: fix PRIx64 constants in trace-events
[qemu/ar7.git] / target-ppc / cpu.h
blob9706000f8bf17de3eda7a4ffc291be62de89c6fe
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 #define TARGET_IS_BIENDIAN 1
33
34 /* Note that the official physical address space bits is 62-M where M
35 is implementation dependent. I've not looked up M for the set of
36 cpus we emulate at the system level. */
37 #define TARGET_PHYS_ADDR_SPACE_BITS 62
38
39 /* Note that the PPC environment architecture talks about 80 bit virtual
40 addresses, with segmentation. Obviously that's not all visible to a
41 single process, which is all we're concerned with here. */
42 #ifdef TARGET_ABI32
43 # define TARGET_VIRT_ADDR_SPACE_BITS 32
44 #else
45 # define TARGET_VIRT_ADDR_SPACE_BITS 64
46 #endif
47
48 #define TARGET_PAGE_BITS_64K 16
49 #define TARGET_PAGE_BITS_16M 24
50
51 #else /* defined (TARGET_PPC64) */
52 /* PowerPC 32 definitions */
53 #define TARGET_LONG_BITS 32
54
55 #if defined(TARGET_PPCEMB)
56 /* Specific definitions for PowerPC embedded */
57 /* BookE have 36 bits physical address space */
58 #if defined(CONFIG_USER_ONLY)
59 /* It looks like a lot of Linux programs assume page size
60 * is 4kB long. This is evil, but we have to deal with it...
61 */
62 #define TARGET_PAGE_BITS 12
63 #else /* defined(CONFIG_USER_ONLY) */
64 /* Pages can be 1 kB small */
65 #define TARGET_PAGE_BITS 10
66 #endif /* defined(CONFIG_USER_ONLY) */
67 #else /* defined(TARGET_PPCEMB) */
68 /* "standard" PowerPC 32 definitions */
69 #define TARGET_PAGE_BITS 12
70 #endif /* defined(TARGET_PPCEMB) */
71
72 #define TARGET_PHYS_ADDR_SPACE_BITS 36
73 #define TARGET_VIRT_ADDR_SPACE_BITS 32
74
75 #endif /* defined (TARGET_PPC64) */
76
77 #define CPUArchState struct CPUPPCState
78
79 #include "exec/cpu-defs.h"
80
81 #include "fpu/softfloat.h"
82
83 #if defined (TARGET_PPC64)
84 #define PPC_ELF_MACHINE EM_PPC64
85 #else
86 #define PPC_ELF_MACHINE EM_PPC
87 #endif
88
89 /*****************************************************************************/
90 /* MMU model */
91 typedef enum powerpc_mmu_t powerpc_mmu_t;
92 enum powerpc_mmu_t {
93 POWERPC_MMU_UNKNOWN = 0x00000000,
94 /* Standard 32 bits PowerPC MMU */
95 POWERPC_MMU_32B = 0x00000001,
96 /* PowerPC 6xx MMU with software TLB */
97 POWERPC_MMU_SOFT_6xx = 0x00000002,
98 /* PowerPC 74xx MMU with software TLB */
99 POWERPC_MMU_SOFT_74xx = 0x00000003,
100 /* PowerPC 4xx MMU with software TLB */
101 POWERPC_MMU_SOFT_4xx = 0x00000004,
102 /* PowerPC 4xx MMU with software TLB and zones protections */
103 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
104 /* PowerPC MMU in real mode only */
105 POWERPC_MMU_REAL = 0x00000006,
106 /* Freescale MPC8xx MMU model */
107 POWERPC_MMU_MPC8xx = 0x00000007,
108 /* BookE MMU model */
109 POWERPC_MMU_BOOKE = 0x00000008,
110 /* BookE 2.06 MMU model */
111 POWERPC_MMU_BOOKE206 = 0x00000009,
112 /* PowerPC 601 MMU model (specific BATs format) */
113 POWERPC_MMU_601 = 0x0000000A,
114 #if defined(TARGET_PPC64)
115 #define POWERPC_MMU_64 0x00010000
116 #define POWERPC_MMU_1TSEG 0x00020000
117 #define POWERPC_MMU_AMR 0x00040000
118 /* 64 bits PowerPC MMU */
119 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
120 /* Architecture 2.03 and later (has LPCR) */
121 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
122 /* Architecture 2.06 variant */
123 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
124 | POWERPC_MMU_AMR | 0x00000003,
125 /* Architecture 2.06 "degraded" (no 1T segments) */
126 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
127 | 0x00000003,
128 /* Architecture 2.07 variant */
129 POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
130 | POWERPC_MMU_AMR | 0x00000004,
131 /* Architecture 2.07 "degraded" (no 1T segments) */
132 POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
133 | 0x00000004,
134 #endif /* defined(TARGET_PPC64) */
135 };
136
137 /*****************************************************************************/
138 /* Exception model */
139 typedef enum powerpc_excp_t powerpc_excp_t;
140 enum powerpc_excp_t {
141 POWERPC_EXCP_UNKNOWN = 0,
142 /* Standard PowerPC exception model */
143 POWERPC_EXCP_STD,
144 /* PowerPC 40x exception model */
145 POWERPC_EXCP_40x,
146 /* PowerPC 601 exception model */
147 POWERPC_EXCP_601,
148 /* PowerPC 602 exception model */
149 POWERPC_EXCP_602,
150 /* PowerPC 603 exception model */
151 POWERPC_EXCP_603,
152 /* PowerPC 603e exception model */
153 POWERPC_EXCP_603E,
154 /* PowerPC G2 exception model */
155 POWERPC_EXCP_G2,
156 /* PowerPC 604 exception model */
157 POWERPC_EXCP_604,
158 /* PowerPC 7x0 exception model */
159 POWERPC_EXCP_7x0,
160 /* PowerPC 7x5 exception model */
161 POWERPC_EXCP_7x5,
162 /* PowerPC 74xx exception model */
163 POWERPC_EXCP_74xx,
164 /* BookE exception model */
165 POWERPC_EXCP_BOOKE,
166 #if defined(TARGET_PPC64)
167 /* PowerPC 970 exception model */
168 POWERPC_EXCP_970,
169 /* POWER7 exception model */
170 POWERPC_EXCP_POWER7,
171 #endif /* defined(TARGET_PPC64) */
172 };
173
174 /*****************************************************************************/
175 /* Exception vectors definitions */
176 enum {
177 POWERPC_EXCP_NONE = -1,
178 /* The 64 first entries are used by the PowerPC embedded specification */
179 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
180 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
181 POWERPC_EXCP_DSI = 2, /* Data storage exception */
182 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
183 POWERPC_EXCP_EXTERNAL = 4, /* External input */
184 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
185 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
186 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
187 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
188 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
189 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
190 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
191 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
192 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
193 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
194 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
195 /* Vectors 16 to 31 are reserved */
196 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
197 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
198 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
199 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
200 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
201 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
202 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
203 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
204 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
205 /* Vectors 42 to 63 are reserved */
206 /* Exceptions defined in the PowerPC server specification */
207 POWERPC_EXCP_RESET = 64, /* System reset exception */
208 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
209 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
210 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
211 POWERPC_EXCP_TRACE = 68, /* Trace exception */
212 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
213 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
214 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
215 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
216 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
217 /* 40x specific exceptions */
218 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
219 /* 601 specific exceptions */
220 POWERPC_EXCP_IO = 75, /* IO error exception */
221 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
222 /* 602 specific exceptions */
223 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
224 /* 602/603 specific exceptions */
225 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
226 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
227 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
228 /* Exceptions available on most PowerPC */
229 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
230 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
231 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
232 POWERPC_EXCP_SMI = 84, /* System management interrupt */
233 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
234 /* 7xx/74xx specific exceptions */
235 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
236 /* 74xx specific exceptions */
237 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
238 /* 970FX specific exceptions */
239 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
240 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
241 /* Freescale embedded cores specific exceptions */
242 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
243 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
244 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
245 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
246 /* VSX Unavailable (Power ISA 2.06 and later) */
247 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
248 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
249 /* EOL */
250 POWERPC_EXCP_NB = 96,
251 /* QEMU exceptions: used internally during code translation */
252 POWERPC_EXCP_STOP = 0x200, /* stop translation */
253 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
254 /* QEMU exceptions: special cases we want to stop translation */
255 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
256 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
257 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
258 };
259
260 /* Exceptions error codes */
261 enum {
262 /* Exception subtypes for POWERPC_EXCP_ALIGN */
263 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
264 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
265 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
266 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
267 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
268 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
269 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
270 /* FP exceptions */
271 POWERPC_EXCP_FP = 0x10,
272 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
273 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
274 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
275 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
276 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
277 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
278 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
279 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
280 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
281 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
282 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
283 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
284 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
285 /* Invalid instruction */
286 POWERPC_EXCP_INVAL = 0x20,
287 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
288 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
289 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
290 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
291 /* Privileged instruction */
292 POWERPC_EXCP_PRIV = 0x30,
293 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
294 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
295 /* Trap */
296 POWERPC_EXCP_TRAP = 0x40,
297 };
298
299 /*****************************************************************************/
300 /* Input pins model */
301 typedef enum powerpc_input_t powerpc_input_t;
302 enum powerpc_input_t {
303 PPC_FLAGS_INPUT_UNKNOWN = 0,
304 /* PowerPC 6xx bus */
305 PPC_FLAGS_INPUT_6xx,
306 /* BookE bus */
307 PPC_FLAGS_INPUT_BookE,
308 /* PowerPC 405 bus */
309 PPC_FLAGS_INPUT_405,
310 /* PowerPC 970 bus */
311 PPC_FLAGS_INPUT_970,
312 /* PowerPC POWER7 bus */
313 PPC_FLAGS_INPUT_POWER7,
314 /* PowerPC 401 bus */
315 PPC_FLAGS_INPUT_401,
316 /* Freescale RCPU bus */
317 PPC_FLAGS_INPUT_RCPU,
318 };
319
320 #define PPC_INPUT(env) (env->bus_model)
321
322 /*****************************************************************************/
323 typedef struct opc_handler_t opc_handler_t;
324
325 /*****************************************************************************/
326 /* Types used to describe some PowerPC registers */
327 typedef struct CPUPPCState CPUPPCState;
328 typedef struct DisasContext DisasContext;
329 typedef struct ppc_tb_t ppc_tb_t;
330 typedef struct ppc_spr_t ppc_spr_t;
331 typedef struct ppc_dcr_t ppc_dcr_t;
332 typedef union ppc_avr_t ppc_avr_t;
333 typedef union ppc_tlb_t ppc_tlb_t;
334
335 /* SPR access micro-ops generations callbacks */
336 struct ppc_spr_t {
337 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
338 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
339 #if !defined(CONFIG_USER_ONLY)
340 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
341 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
342 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
343 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
344 #endif
345 const char *name;
346 target_ulong default_value;
347 #ifdef CONFIG_KVM
348 /* We (ab)use the fact that all the SPRs will have ids for the
349 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
350 * don't sync this */
351 uint64_t one_reg_id;
352 #endif
353 };
354
355 /* Altivec registers (128 bits) */
356 union ppc_avr_t {
357 float32 f[4];
358 uint8_t u8[16];
359 uint16_t u16[8];
360 uint32_t u32[4];
361 int8_t s8[16];
362 int16_t s16[8];
363 int32_t s32[4];
364 uint64_t u64[2];
365 int64_t s64[2];
366 #ifdef CONFIG_INT128
367 __uint128_t u128;
368 #endif
369 };
370
371 #if !defined(CONFIG_USER_ONLY)
372 /* Software TLB cache */
373 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
374 struct ppc6xx_tlb_t {
375 target_ulong pte0;
376 target_ulong pte1;
377 target_ulong EPN;
378 };
379
380 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
381 struct ppcemb_tlb_t {
382 uint64_t RPN;
383 target_ulong EPN;
384 target_ulong PID;
385 target_ulong size;
386 uint32_t prot;
387 uint32_t attr; /* Storage attributes */
388 };
389
390 typedef struct ppcmas_tlb_t {
391 uint32_t mas8;
392 uint32_t mas1;
393 uint64_t mas2;
394 uint64_t mas7_3;
395 } ppcmas_tlb_t;
396
397 union ppc_tlb_t {
398 ppc6xx_tlb_t *tlb6;
399 ppcemb_tlb_t *tlbe;
400 ppcmas_tlb_t *tlbm;
401 };
402
403 /* possible TLB variants */
404 #define TLB_NONE 0
405 #define TLB_6XX 1
406 #define TLB_EMB 2
407 #define TLB_MAS 3
408 #endif
409
410 #define SDR_32_HTABORG 0xFFFF0000UL
411 #define SDR_32_HTABMASK 0x000001FFUL
412
413 #if defined(TARGET_PPC64)
414 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
415 #define SDR_64_HTABSIZE 0x000000000000001FULL
416 #endif /* defined(TARGET_PPC64 */
417
418 typedef struct ppc_slb_t ppc_slb_t;
419 struct ppc_slb_t {
420 uint64_t esid;
421 uint64_t vsid;
422 };
423
424 #define MAX_SLB_ENTRIES 64
425 #define SEGMENT_SHIFT_256M 28
426 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
427
428 #define SEGMENT_SHIFT_1T 40
429 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
430
431
432 /*****************************************************************************/
433 /* Machine state register bits definition */
434 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
435 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
436 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
437 #define MSR_SHV 60 /* hypervisor state hflags */
438 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
439 #define MSR_TS1 33
440 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
441 #define MSR_CM 31 /* Computation mode for BookE hflags */
442 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
443 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
444 #define MSR_GS 28 /* guest state for BookE */
445 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
446 #define MSR_VR 25 /* altivec available x hflags */
447 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
448 #define MSR_AP 23 /* Access privilege state on 602 hflags */
449 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
450 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
451 #define MSR_KEY 19 /* key bit on 603e */
452 #define MSR_POW 18 /* Power management */
453 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
454 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
455 #define MSR_ILE 16 /* Interrupt little-endian mode */
456 #define MSR_EE 15 /* External interrupt enable */
457 #define MSR_PR 14 /* Problem state hflags */
458 #define MSR_FP 13 /* Floating point available hflags */
459 #define MSR_ME 12 /* Machine check interrupt enable */
460 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
461 #define MSR_SE 10 /* Single-step trace enable x hflags */
462 #define MSR_DWE 10 /* Debug wait enable on 405 x */
463 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
464 #define MSR_BE 9 /* Branch trace enable x hflags */
465 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
466 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
467 #define MSR_AL 7 /* AL bit on POWER */
468 #define MSR_EP 6 /* Exception prefix on 601 */
469 #define MSR_IR 5 /* Instruction relocate */
470 #define MSR_DR 4 /* Data relocate */
471 #define MSR_PE 3 /* Protection enable on 403 */
472 #define MSR_PX 2 /* Protection exclusive on 403 x */
473 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
474 #define MSR_RI 1 /* Recoverable interrupt 1 */
475 #define MSR_LE 0 /* Little-endian mode 1 hflags */
476
477 #define LPCR_ILE (1 << (63-38))
478 #define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
479 #define LPCR_AIL (3 << LPCR_AIL_SHIFT)
480
481 #define msr_sf ((env->msr >> MSR_SF) & 1)
482 #define msr_isf ((env->msr >> MSR_ISF) & 1)
483 #define msr_shv ((env->msr >> MSR_SHV) & 1)
484 #define msr_cm ((env->msr >> MSR_CM) & 1)
485 #define msr_icm ((env->msr >> MSR_ICM) & 1)
486 #define msr_thv ((env->msr >> MSR_THV) & 1)
487 #define msr_gs ((env->msr >> MSR_GS) & 1)
488 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
489 #define msr_vr ((env->msr >> MSR_VR) & 1)
490 #define msr_spe ((env->msr >> MSR_SPE) & 1)
491 #define msr_ap ((env->msr >> MSR_AP) & 1)
492 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
493 #define msr_sa ((env->msr >> MSR_SA) & 1)
494 #define msr_key ((env->msr >> MSR_KEY) & 1)
495 #define msr_pow ((env->msr >> MSR_POW) & 1)
496 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
497 #define msr_ce ((env->msr >> MSR_CE) & 1)
498 #define msr_ile ((env->msr >> MSR_ILE) & 1)
499 #define msr_ee ((env->msr >> MSR_EE) & 1)
500 #define msr_pr ((env->msr >> MSR_PR) & 1)
501 #define msr_fp ((env->msr >> MSR_FP) & 1)
502 #define msr_me ((env->msr >> MSR_ME) & 1)
503 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
504 #define msr_se ((env->msr >> MSR_SE) & 1)
505 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
506 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
507 #define msr_be ((env->msr >> MSR_BE) & 1)
508 #define msr_de ((env->msr >> MSR_DE) & 1)
509 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
510 #define msr_al ((env->msr >> MSR_AL) & 1)
511 #define msr_ep ((env->msr >> MSR_EP) & 1)
512 #define msr_ir ((env->msr >> MSR_IR) & 1)
513 #define msr_dr ((env->msr >> MSR_DR) & 1)
514 #define msr_pe ((env->msr >> MSR_PE) & 1)
515 #define msr_px ((env->msr >> MSR_PX) & 1)
516 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
517 #define msr_ri ((env->msr >> MSR_RI) & 1)
518 #define msr_le ((env->msr >> MSR_LE) & 1)
519 #define msr_ts ((env->msr >> MSR_TS1) & 3)
520 #define msr_tm ((env->msr >> MSR_TM) & 1)
521
522 /* Hypervisor bit is more specific */
523 #if defined(TARGET_PPC64)
524 #define MSR_HVB (1ULL << MSR_SHV)
525 #define msr_hv msr_shv
526 #else
527 #if defined(PPC_EMULATE_32BITS_HYPV)
528 #define MSR_HVB (1ULL << MSR_THV)
529 #define msr_hv msr_thv
530 #else
531 #define MSR_HVB (0ULL)
532 #define msr_hv (0)
533 #endif
534 #endif
535
536 /* Facility Status and Control (FSCR) bits */
537 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
538 #define FSCR_TAR (63 - 55) /* Target Address Register */
539 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
540 #define FSCR_IC_MASK (0xFFULL)
541 #define FSCR_IC_POS (63 - 7)
542 #define FSCR_IC_DSCR_SPR3 2
543 #define FSCR_IC_PMU 3
544 #define FSCR_IC_BHRB 4
545 #define FSCR_IC_TM 5
546 #define FSCR_IC_EBB 7
547 #define FSCR_IC_TAR 8
548
549 /* Exception state register bits definition */
550 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
551 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
552 #define ESR_PTR (1 << (63 - 38)) /* Trap */
553 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
554 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
555 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
556 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
557 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
558 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
559 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
560 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
561 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
562 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
563 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
564 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
565 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
566
567 /* Transaction EXception And Summary Register bits */
568 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
569 #define TEXASR_DISALLOWED (63 - 8)
570 #define TEXASR_NESTING_OVERFLOW (63 - 9)
571 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
572 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
573 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
574 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
575 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
576 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
577 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
578 #define TEXASR_ABORT (63 - 31)
579 #define TEXASR_SUSPENDED (63 - 32)
580 #define TEXASR_PRIVILEGE_HV (63 - 34)
581 #define TEXASR_PRIVILEGE_PR (63 - 35)
582 #define TEXASR_FAILURE_SUMMARY (63 - 36)
583 #define TEXASR_TFIAR_EXACT (63 - 37)
584 #define TEXASR_ROT (63 - 38)
585 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
586
587 enum {
588 POWERPC_FLAG_NONE = 0x00000000,
589 /* Flag for MSR bit 25 signification (VRE/SPE) */
590 POWERPC_FLAG_SPE = 0x00000001,
591 POWERPC_FLAG_VRE = 0x00000002,
592 /* Flag for MSR bit 17 signification (TGPR/CE) */
593 POWERPC_FLAG_TGPR = 0x00000004,
594 POWERPC_FLAG_CE = 0x00000008,
595 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
596 POWERPC_FLAG_SE = 0x00000010,
597 POWERPC_FLAG_DWE = 0x00000020,
598 POWERPC_FLAG_UBLE = 0x00000040,
599 /* Flag for MSR bit 9 signification (BE/DE) */
600 POWERPC_FLAG_BE = 0x00000080,
601 POWERPC_FLAG_DE = 0x00000100,
602 /* Flag for MSR bit 2 signification (PX/PMM) */
603 POWERPC_FLAG_PX = 0x00000200,
604 POWERPC_FLAG_PMM = 0x00000400,
605 /* Flag for special features */
606 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
607 POWERPC_FLAG_RTC_CLK = 0x00010000,
608 POWERPC_FLAG_BUS_CLK = 0x00020000,
609 /* Has CFAR */
610 POWERPC_FLAG_CFAR = 0x00040000,
611 /* Has VSX */
612 POWERPC_FLAG_VSX = 0x00080000,
613 /* Has Transaction Memory (ISA 2.07) */
614 POWERPC_FLAG_TM = 0x00100000,
615 };
616
617 /*****************************************************************************/
618 /* Floating point status and control register */
619 #define FPSCR_FX 31 /* Floating-point exception summary */
620 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
621 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
622 #define FPSCR_OX 28 /* Floating-point overflow exception */
623 #define FPSCR_UX 27 /* Floating-point underflow exception */
624 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
625 #define FPSCR_XX 25 /* Floating-point inexact exception */
626 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
627 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
628 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
629 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
630 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
631 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
632 #define FPSCR_FR 18 /* Floating-point fraction rounded */
633 #define FPSCR_FI 17 /* Floating-point fraction inexact */
634 #define FPSCR_C 16 /* Floating-point result class descriptor */
635 #define FPSCR_FL 15 /* Floating-point less than or negative */
636 #define FPSCR_FG 14 /* Floating-point greater than or negative */
637 #define FPSCR_FE 13 /* Floating-point equal or zero */
638 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
639 #define FPSCR_FPCC 12 /* Floating-point condition code */
640 #define FPSCR_FPRF 12 /* Floating-point result flags */
641 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
642 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
643 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
644 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
645 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
646 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
647 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
648 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
649 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
650 #define FPSCR_RN1 1
651 #define FPSCR_RN 0 /* Floating-point rounding control */
652 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
653 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
654 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
655 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
656 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
657 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
658 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
659 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
660 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
661 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
662 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
663 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
664 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
665 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
666 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
667 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
668 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
669 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
670 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
671 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
672 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
673 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
674 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
675 /* Invalid operation exception summary */
676 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
677 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
678 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
679 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
680 (1 << FPSCR_VXCVI)))
681 /* exception summary */
682 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
683 /* enabled exception summary */
684 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
685 0x1F)
686
687 #define FP_FX (1ull << FPSCR_FX)
688 #define FP_FEX (1ull << FPSCR_FEX)
689 #define FP_OX (1ull << FPSCR_OX)
690 #define FP_OE (1ull << FPSCR_OE)
691 #define FP_UX (1ull << FPSCR_UX)
692 #define FP_UE (1ull << FPSCR_UE)
693 #define FP_XX (1ull << FPSCR_XX)
694 #define FP_XE (1ull << FPSCR_XE)
695 #define FP_ZX (1ull << FPSCR_ZX)
696 #define FP_ZE (1ull << FPSCR_ZE)
697 #define FP_VX (1ull << FPSCR_VX)
698 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
699 #define FP_VXISI (1ull << FPSCR_VXISI)
700 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
701 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
702 #define FP_VXIDI (1ull << FPSCR_VXIDI)
703 #define FP_VXVC (1ull << FPSCR_VXVC)
704 #define FP_VXCVI (1ull << FPSCR_VXCVI)
705 #define FP_VE (1ull << FPSCR_VE)
706 #define FP_FI (1ull << FPSCR_FI)
707
708 /*****************************************************************************/
709 /* Vector status and control register */
710 #define VSCR_NJ 16 /* Vector non-java */
711 #define VSCR_SAT 0 /* Vector saturation */
712 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
713 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
714
715 /*****************************************************************************/
716 /* BookE e500 MMU registers */
717
718 #define MAS0_NV_SHIFT 0
719 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
720
721 #define MAS0_WQ_SHIFT 12
722 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
723 /* Write TLB entry regardless of reservation */
724 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
725 /* Write TLB entry only already in use */
726 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
727 /* Clear TLB entry */
728 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
729
730 #define MAS0_HES_SHIFT 14
731 #define MAS0_HES (1 << MAS0_HES_SHIFT)
732
733 #define MAS0_ESEL_SHIFT 16
734 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
735
736 #define MAS0_TLBSEL_SHIFT 28
737 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
738 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
739 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
740 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
741 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
742
743 #define MAS0_ATSEL_SHIFT 31
744 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
745 #define MAS0_ATSEL_TLB 0
746 #define MAS0_ATSEL_LRAT MAS0_ATSEL
747
748 #define MAS1_TSIZE_SHIFT 7
749 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
750
751 #define MAS1_TS_SHIFT 12
752 #define MAS1_TS (1 << MAS1_TS_SHIFT)
753
754 #define MAS1_IND_SHIFT 13
755 #define MAS1_IND (1 << MAS1_IND_SHIFT)
756
757 #define MAS1_TID_SHIFT 16
758 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
759
760 #define MAS1_IPROT_SHIFT 30
761 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
762
763 #define MAS1_VALID_SHIFT 31
764 #define MAS1_VALID 0x80000000
765
766 #define MAS2_EPN_SHIFT 12
767 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
768
769 #define MAS2_ACM_SHIFT 6
770 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
771
772 #define MAS2_VLE_SHIFT 5
773 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
774
775 #define MAS2_W_SHIFT 4
776 #define MAS2_W (1 << MAS2_W_SHIFT)
777
778 #define MAS2_I_SHIFT 3
779 #define MAS2_I (1 << MAS2_I_SHIFT)
780
781 #define MAS2_M_SHIFT 2
782 #define MAS2_M (1 << MAS2_M_SHIFT)
783
784 #define MAS2_G_SHIFT 1
785 #define MAS2_G (1 << MAS2_G_SHIFT)
786
787 #define MAS2_E_SHIFT 0
788 #define MAS2_E (1 << MAS2_E_SHIFT)
789
790 #define MAS3_RPN_SHIFT 12
791 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
792
793 #define MAS3_U0 0x00000200
794 #define MAS3_U1 0x00000100
795 #define MAS3_U2 0x00000080
796 #define MAS3_U3 0x00000040
797 #define MAS3_UX 0x00000020
798 #define MAS3_SX 0x00000010
799 #define MAS3_UW 0x00000008
800 #define MAS3_SW 0x00000004
801 #define MAS3_UR 0x00000002
802 #define MAS3_SR 0x00000001
803 #define MAS3_SPSIZE_SHIFT 1
804 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
805
806 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
807 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
808 #define MAS4_TIDSELD_MASK 0x00030000
809 #define MAS4_TIDSELD_PID0 0x00000000
810 #define MAS4_TIDSELD_PID1 0x00010000
811 #define MAS4_TIDSELD_PID2 0x00020000
812 #define MAS4_TIDSELD_PIDZ 0x00030000
813 #define MAS4_INDD 0x00008000 /* Default IND */
814 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
815 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
816 #define MAS4_ACMD 0x00000040
817 #define MAS4_VLED 0x00000020
818 #define MAS4_WD 0x00000010
819 #define MAS4_ID 0x00000008
820 #define MAS4_MD 0x00000004
821 #define MAS4_GD 0x00000002
822 #define MAS4_ED 0x00000001
823 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
824 #define MAS4_WIMGED_SHIFT 0
825
826 #define MAS5_SGS 0x80000000
827 #define MAS5_SLPID_MASK 0x00000fff
828
829 #define MAS6_SPID0 0x3fff0000
830 #define MAS6_SPID1 0x00007ffe
831 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
832 #define MAS6_SAS 0x00000001
833 #define MAS6_SPID MAS6_SPID0
834 #define MAS6_SIND 0x00000002 /* Indirect page */
835 #define MAS6_SIND_SHIFT 1
836 #define MAS6_SPID_MASK 0x3fff0000
837 #define MAS6_SPID_SHIFT 16
838 #define MAS6_ISIZE_MASK 0x00000f80
839 #define MAS6_ISIZE_SHIFT 7
840
841 #define MAS7_RPN 0xffffffff
842
843 #define MAS8_TGS 0x80000000
844 #define MAS8_VF 0x40000000
845 #define MAS8_TLBPID 0x00000fff
846
847 /* Bit definitions for MMUCFG */
848 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
849 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
850 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
851 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
852 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
853 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
854 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
855 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
856 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
857
858 /* Bit definitions for MMUCSR0 */
859 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
860 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
861 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
862 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
863 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
864 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
865 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
866 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
867 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
868 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
869
870 /* TLBnCFG encoding */
871 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
872 #define TLBnCFG_HES 0x00002000 /* HW select supported */
873 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
874 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
875 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
876 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
877 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
878 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
879 #define TLBnCFG_MINSIZE_SHIFT 20
880 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
881 #define TLBnCFG_MAXSIZE_SHIFT 16
882 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
883 #define TLBnCFG_ASSOC_SHIFT 24
884
885 /* TLBnPS encoding */
886 #define TLBnPS_4K 0x00000004
887 #define TLBnPS_8K 0x00000008
888 #define TLBnPS_16K 0x00000010
889 #define TLBnPS_32K 0x00000020
890 #define TLBnPS_64K 0x00000040
891 #define TLBnPS_128K 0x00000080
892 #define TLBnPS_256K 0x00000100
893 #define TLBnPS_512K 0x00000200
894 #define TLBnPS_1M 0x00000400
895 #define TLBnPS_2M 0x00000800
896 #define TLBnPS_4M 0x00001000
897 #define TLBnPS_8M 0x00002000
898 #define TLBnPS_16M 0x00004000
899 #define TLBnPS_32M 0x00008000
900 #define TLBnPS_64M 0x00010000
901 #define TLBnPS_128M 0x00020000
902 #define TLBnPS_256M 0x00040000
903 #define TLBnPS_512M 0x00080000
904 #define TLBnPS_1G 0x00100000
905 #define TLBnPS_2G 0x00200000
906 #define TLBnPS_4G 0x00400000
907 #define TLBnPS_8G 0x00800000
908 #define TLBnPS_16G 0x01000000
909 #define TLBnPS_32G 0x02000000
910 #define TLBnPS_64G 0x04000000
911 #define TLBnPS_128G 0x08000000
912 #define TLBnPS_256G 0x10000000
913
914 /* tlbilx action encoding */
915 #define TLBILX_T_ALL 0
916 #define TLBILX_T_TID 1
917 #define TLBILX_T_FULLMATCH 3
918 #define TLBILX_T_CLASS0 4
919 #define TLBILX_T_CLASS1 5
920 #define TLBILX_T_CLASS2 6
921 #define TLBILX_T_CLASS3 7
922
923 /* BookE 2.06 helper defines */
924
925 #define BOOKE206_FLUSH_TLB0 (1 << 0)
926 #define BOOKE206_FLUSH_TLB1 (1 << 1)
927 #define BOOKE206_FLUSH_TLB2 (1 << 2)
928 #define BOOKE206_FLUSH_TLB3 (1 << 3)
929
930 /* number of possible TLBs */
931 #define BOOKE206_MAX_TLBN 4
932
933 /*****************************************************************************/
934 /* Embedded.Processor Control */
935
936 #define DBELL_TYPE_SHIFT 27
937 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
938 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
939 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
940 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
941 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
942 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
943
944 #define DBELL_BRDCAST (1 << 26)
945 #define DBELL_LPIDTAG_SHIFT 14
946 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
947 #define DBELL_PIRTAG_MASK 0x3fff
948
949 /*****************************************************************************/
950 /* Segment page size information, used by recent hash MMUs
951 * The format of this structure mirrors kvm_ppc_smmu_info
952 */
953
954 #define PPC_PAGE_SIZES_MAX_SZ 8
955
956 struct ppc_one_page_size {
957 uint32_t page_shift; /* Page shift (or 0) */
958 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
959 };
960
961 struct ppc_one_seg_page_size {
962 uint32_t page_shift; /* Base page shift of segment (or 0) */
963 uint32_t slb_enc; /* SLB encoding for BookS */
964 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
965 };
966
967 struct ppc_segment_page_sizes {
968 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
969 };
970
971
972 /*****************************************************************************/
973 /* The whole PowerPC CPU context */
974 #define NB_MMU_MODES 3
975
976 #define PPC_CPU_OPCODES_LEN 0x40
977 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
978
979 struct CPUPPCState {
980 /* First are the most commonly used resources
981 * during translated code execution
982 */
983 /* general purpose registers */
984 target_ulong gpr[32];
985 /* Storage for GPR MSB, used by the SPE extension */
986 target_ulong gprh[32];
987 /* LR */
988 target_ulong lr;
989 /* CTR */
990 target_ulong ctr;
991 /* condition register */
992 uint32_t crf[8];
993 #if defined(TARGET_PPC64)
994 /* CFAR */
995 target_ulong cfar;
996 #endif
997 /* XER (with SO, OV, CA split out) */
998 target_ulong xer;
999 target_ulong so;
1000 target_ulong ov;
1001 target_ulong ca;
1002 /* Reservation address */
1003 target_ulong reserve_addr;
1004 /* Reservation value */
1005 target_ulong reserve_val;
1006 target_ulong reserve_val2;
1007 /* Reservation store address */
1008 target_ulong reserve_ea;
1009 /* Reserved store source register and size */
1010 target_ulong reserve_info;
1011
1012 /* Those ones are used in supervisor mode only */
1013 /* machine state register */
1014 target_ulong msr;
1015 /* temporary general purpose registers */
1016 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1017
1018 /* Floating point execution context */
1019 float_status fp_status;
1020 /* floating point registers */
1021 float64 fpr[32];
1022 /* floating point status and control register */
1023 target_ulong fpscr;
1024
1025 /* Next instruction pointer */
1026 target_ulong nip;
1027
1028 int access_type; /* when a memory exception occurs, the access
1029 type is stored here */
1030
1031 CPU_COMMON
1032
1033 /* MMU context - only relevant for full system emulation */
1034 #if !defined(CONFIG_USER_ONLY)
1035 #if defined(TARGET_PPC64)
1036 /* PowerPC 64 SLB area */
1037 ppc_slb_t slb[MAX_SLB_ENTRIES];
1038 int32_t slb_nr;
1039 #endif
1040 /* segment registers */
1041 hwaddr htab_base;
1042 /* mask used to normalize hash value to PTEG index */
1043 hwaddr htab_mask;
1044 target_ulong sr[32];
1045 /* externally stored hash table */
1046 uint8_t *external_htab;
1047 /* BATs */
1048 uint32_t nb_BATs;
1049 target_ulong DBAT[2][8];
1050 target_ulong IBAT[2][8];
1051 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1052 int32_t nb_tlb; /* Total number of TLB */
1053 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1054 int nb_ways; /* Number of ways in the TLB set */
1055 int last_way; /* Last used way used to allocate TLB in a LRU way */
1056 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1057 int nb_pids; /* Number of available PID registers */
1058 int tlb_type; /* Type of TLB we're dealing with */
1059 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1060 /* 403 dedicated access protection registers */
1061 target_ulong pb[4];
1062 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1063 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1064 #endif
1065
1066 /* Other registers */
1067 /* Special purpose registers */
1068 target_ulong spr[1024];
1069 ppc_spr_t spr_cb[1024];
1070 /* Altivec registers */
1071 ppc_avr_t avr[32];
1072 uint32_t vscr;
1073 /* VSX registers */
1074 uint64_t vsr[32];
1075 /* SPE registers */
1076 uint64_t spe_acc;
1077 uint32_t spe_fscr;
1078 /* SPE and Altivec can share a status since they will never be used
1079 * simultaneously */
1080 float_status vec_status;
1081
1082 /* Internal devices resources */
1083 /* Time base and decrementer */
1084 ppc_tb_t *tb_env;
1085 /* Device control registers */
1086 ppc_dcr_t *dcr_env;
1087
1088 int dcache_line_size;
1089 int icache_line_size;
1090
1091 /* Those resources are used during exception processing */
1092 /* CPU model definition */
1093 target_ulong msr_mask;
1094 powerpc_mmu_t mmu_model;
1095 powerpc_excp_t excp_model;
1096 powerpc_input_t bus_model;
1097 int bfd_mach;
1098 uint32_t flags;
1099 uint64_t insns_flags;
1100 uint64_t insns_flags2;
1101 #if defined(TARGET_PPC64)
1102 struct ppc_segment_page_sizes sps;
1103 bool ci_large_pages;
1104 #endif
1105
1106 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1107 uint64_t vpa_addr;
1108 uint64_t slb_shadow_addr, slb_shadow_size;
1109 uint64_t dtl_addr, dtl_size;
1110 #endif /* TARGET_PPC64 */
1111
1112 int error_code;
1113 uint32_t pending_interrupts;
1114 #if !defined(CONFIG_USER_ONLY)
1115 /* This is the IRQ controller, which is implementation dependent
1116 * and only relevant when emulating a complete machine.
1117 */
1118 uint32_t irq_input_state;
1119 void **irq_inputs;
1120 /* Exception vectors */
1121 target_ulong excp_vectors[POWERPC_EXCP_NB];
1122 target_ulong excp_prefix;
1123 target_ulong ivor_mask;
1124 target_ulong ivpr_mask;
1125 target_ulong hreset_vector;
1126 hwaddr mpic_iack;
1127 /* true when the external proxy facility mode is enabled */
1128 bool mpic_proxy;
1129 #endif
1130
1131 /* Those resources are used only during code translation */
1132 /* opcode handlers */
1133 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1134
1135 /* Those resources are used only in QEMU core */
1136 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1137 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1138 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1139
1140 /* Power management */
1141 int (*check_pow)(CPUPPCState *env);
1142
1143 #if !defined(CONFIG_USER_ONLY)
1144 void *load_info; /* Holds boot loading state. */
1145 #endif
1146
1147 /* booke timers */
1148
1149 /* Specifies bit locations of the Time Base used to signal a fixed timer
1150 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1151 *
1152 * 0 selects the least significant bit.
1153 * 63 selects the most significant bit.
1154 */
1155 uint8_t fit_period[4];
1156 uint8_t wdt_period[4];
1157
1158 /* Transactional memory state */
1159 target_ulong tm_gpr[32];
1160 ppc_avr_t tm_vsr[64];
1161 uint64_t tm_cr;
1162 uint64_t tm_lr;
1163 uint64_t tm_ctr;
1164 uint64_t tm_fpscr;
1165 uint64_t tm_amr;
1166 uint64_t tm_ppr;
1167 uint64_t tm_vrsave;
1168 uint32_t tm_vscr;
1169 uint64_t tm_dscr;
1170 uint64_t tm_tar;
1171 };
1172
1173 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1174 do { \
1175 env->fit_period[0] = (a_); \
1176 env->fit_period[1] = (b_); \
1177 env->fit_period[2] = (c_); \
1178 env->fit_period[3] = (d_); \
1179 } while (0)
1180
1181 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1182 do { \
1183 env->wdt_period[0] = (a_); \
1184 env->wdt_period[1] = (b_); \
1185 env->wdt_period[2] = (c_); \
1186 env->wdt_period[3] = (d_); \
1187 } while (0)
1188
1189 #include "cpu-qom.h"
1190
1191 /*****************************************************************************/
1192 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1193 void ppc_translate_init(void);
1194 void gen_update_current_nip(void *opaque);
1195 int cpu_ppc_exec (CPUState *s);
1196 /* you can call this signal handler from your SIGBUS and SIGSEGV
1197 signal handlers to inform the virtual CPU of exceptions. non zero
1198 is returned if the signal was handled by the virtual CPU. */
1199 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1200 void *puc);
1201 #if defined(CONFIG_USER_ONLY)
1202 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1203 int mmu_idx);
1204 #endif
1205
1206 #if !defined(CONFIG_USER_ONLY)
1207 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1208 #endif /* !defined(CONFIG_USER_ONLY) */
1209 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1210
1211 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1212 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1213 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
1214
1215 /* Time-base and decrementer management */
1216 #ifndef NO_CPU_IO_DEFS
1217 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1218 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1219 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1220 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1221 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1222 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1223 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1224 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1225 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1226 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1227 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1228 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1229 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1230 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1231 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1232 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1233 #if !defined(CONFIG_USER_ONLY)
1234 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1235 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1236 target_ulong load_40x_pit (CPUPPCState *env);
1237 void store_40x_pit (CPUPPCState *env, target_ulong val);
1238 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1239 void store_40x_sler (CPUPPCState *env, uint32_t val);
1240 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1241 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1242 void ppc_tlb_invalidate_all (CPUPPCState *env);
1243 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1244 #endif
1245 #endif
1246
1247 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1248
1249 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1250 {
1251 uint64_t gprv;
1252
1253 gprv = env->gpr[gprn];
1254 if (env->flags & POWERPC_FLAG_SPE) {
1255 /* If the CPU implements the SPE extension, we have to get the
1256 * high bits of the GPR from the gprh storage area
1257 */
1258 gprv &= 0xFFFFFFFFULL;
1259 gprv |= (uint64_t)env->gprh[gprn] << 32;
1260 }
1261
1262 return gprv;
1263 }
1264
1265 /* Device control registers */
1266 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1267 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1268
1269 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1270
1271 #define cpu_exec cpu_ppc_exec
1272 #define cpu_signal_handler cpu_ppc_signal_handler
1273 #define cpu_list ppc_cpu_list
1274
1275 /* MMU modes definitions */
1276 #define MMU_MODE0_SUFFIX _user
1277 #define MMU_MODE1_SUFFIX _kernel
1278 #define MMU_MODE2_SUFFIX _hypv
1279 #define MMU_USER_IDX 0
1280 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1281 {
1282 return env->mmu_idx;
1283 }
1284
1285 #include "exec/cpu-all.h"
1286
1287 /*****************************************************************************/
1288 /* CRF definitions */
1289 #define CRF_LT 3
1290 #define CRF_GT 2
1291 #define CRF_EQ 1
1292 #define CRF_SO 0
1293 #define CRF_CH (1 << CRF_LT)
1294 #define CRF_CL (1 << CRF_GT)
1295 #define CRF_CH_OR_CL (1 << CRF_EQ)
1296 #define CRF_CH_AND_CL (1 << CRF_SO)
1297
1298 /* XER definitions */
1299 #define XER_SO 31
1300 #define XER_OV 30
1301 #define XER_CA 29
1302 #define XER_CMP 8
1303 #define XER_BC 0
1304 #define xer_so (env->so)
1305 #define xer_ov (env->ov)
1306 #define xer_ca (env->ca)
1307 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1308 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1309
1310 /* SPR definitions */
1311 #define SPR_MQ (0x000)
1312 #define SPR_XER (0x001)
1313 #define SPR_601_VRTCU (0x004)
1314 #define SPR_601_VRTCL (0x005)
1315 #define SPR_601_UDECR (0x006)
1316 #define SPR_LR (0x008)
1317 #define SPR_CTR (0x009)
1318 #define SPR_UAMR (0x00C)
1319 #define SPR_DSCR (0x011)
1320 #define SPR_DSISR (0x012)
1321 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1322 #define SPR_601_RTCU (0x014)
1323 #define SPR_601_RTCL (0x015)
1324 #define SPR_DECR (0x016)
1325 #define SPR_SDR1 (0x019)
1326 #define SPR_SRR0 (0x01A)
1327 #define SPR_SRR1 (0x01B)
1328 #define SPR_CFAR (0x01C)
1329 #define SPR_AMR (0x01D)
1330 #define SPR_BOOKE_PID (0x030)
1331 #define SPR_BOOKE_DECAR (0x036)
1332 #define SPR_BOOKE_CSRR0 (0x03A)
1333 #define SPR_BOOKE_CSRR1 (0x03B)
1334 #define SPR_BOOKE_DEAR (0x03D)
1335 #define SPR_BOOKE_ESR (0x03E)
1336 #define SPR_BOOKE_IVPR (0x03F)
1337 #define SPR_MPC_EIE (0x050)
1338 #define SPR_MPC_EID (0x051)
1339 #define SPR_MPC_NRI (0x052)
1340 #define SPR_TFHAR (0x080)
1341 #define SPR_TFIAR (0x081)
1342 #define SPR_TEXASR (0x082)
1343 #define SPR_TEXASRU (0x083)
1344 #define SPR_UCTRL (0x088)
1345 #define SPR_MPC_CMPA (0x090)
1346 #define SPR_MPC_CMPB (0x091)
1347 #define SPR_MPC_CMPC (0x092)
1348 #define SPR_MPC_CMPD (0x093)
1349 #define SPR_MPC_ECR (0x094)
1350 #define SPR_MPC_DER (0x095)
1351 #define SPR_MPC_COUNTA (0x096)
1352 #define SPR_MPC_COUNTB (0x097)
1353 #define SPR_CTRL (0x098)
1354 #define SPR_MPC_CMPE (0x098)
1355 #define SPR_MPC_CMPF (0x099)
1356 #define SPR_FSCR (0x099)
1357 #define SPR_MPC_CMPG (0x09A)
1358 #define SPR_MPC_CMPH (0x09B)
1359 #define SPR_MPC_LCTRL1 (0x09C)
1360 #define SPR_MPC_LCTRL2 (0x09D)
1361 #define SPR_UAMOR (0x09D)
1362 #define SPR_MPC_ICTRL (0x09E)
1363 #define SPR_MPC_BAR (0x09F)
1364 #define SPR_VRSAVE (0x100)
1365 #define SPR_USPRG0 (0x100)
1366 #define SPR_USPRG1 (0x101)
1367 #define SPR_USPRG2 (0x102)
1368 #define SPR_USPRG3 (0x103)
1369 #define SPR_USPRG4 (0x104)
1370 #define SPR_USPRG5 (0x105)
1371 #define SPR_USPRG6 (0x106)
1372 #define SPR_USPRG7 (0x107)
1373 #define SPR_VTBL (0x10C)
1374 #define SPR_VTBU (0x10D)
1375 #define SPR_SPRG0 (0x110)
1376 #define SPR_SPRG1 (0x111)
1377 #define SPR_SPRG2 (0x112)
1378 #define SPR_SPRG3 (0x113)
1379 #define SPR_SPRG4 (0x114)
1380 #define SPR_SCOMC (0x114)
1381 #define SPR_SPRG5 (0x115)
1382 #define SPR_SCOMD (0x115)
1383 #define SPR_SPRG6 (0x116)
1384 #define SPR_SPRG7 (0x117)
1385 #define SPR_ASR (0x118)
1386 #define SPR_EAR (0x11A)
1387 #define SPR_TBL (0x11C)
1388 #define SPR_TBU (0x11D)
1389 #define SPR_TBU40 (0x11E)
1390 #define SPR_SVR (0x11E)
1391 #define SPR_BOOKE_PIR (0x11E)
1392 #define SPR_PVR (0x11F)
1393 #define SPR_HSPRG0 (0x130)
1394 #define SPR_BOOKE_DBSR (0x130)
1395 #define SPR_HSPRG1 (0x131)
1396 #define SPR_HDSISR (0x132)
1397 #define SPR_HDAR (0x133)
1398 #define SPR_BOOKE_EPCR (0x133)
1399 #define SPR_SPURR (0x134)
1400 #define SPR_BOOKE_DBCR0 (0x134)
1401 #define SPR_IBCR (0x135)
1402 #define SPR_PURR (0x135)
1403 #define SPR_BOOKE_DBCR1 (0x135)
1404 #define SPR_DBCR (0x136)
1405 #define SPR_HDEC (0x136)
1406 #define SPR_BOOKE_DBCR2 (0x136)
1407 #define SPR_HIOR (0x137)
1408 #define SPR_MBAR (0x137)
1409 #define SPR_RMOR (0x138)
1410 #define SPR_BOOKE_IAC1 (0x138)
1411 #define SPR_HRMOR (0x139)
1412 #define SPR_BOOKE_IAC2 (0x139)
1413 #define SPR_HSRR0 (0x13A)
1414 #define SPR_BOOKE_IAC3 (0x13A)
1415 #define SPR_HSRR1 (0x13B)
1416 #define SPR_BOOKE_IAC4 (0x13B)
1417 #define SPR_BOOKE_DAC1 (0x13C)
1418 #define SPR_LPIDR (0x13D)
1419 #define SPR_DABR2 (0x13D)
1420 #define SPR_BOOKE_DAC2 (0x13D)
1421 #define SPR_BOOKE_DVC1 (0x13E)
1422 #define SPR_LPCR (0x13E)
1423 #define SPR_BOOKE_DVC2 (0x13F)
1424 #define SPR_BOOKE_TSR (0x150)
1425 #define SPR_PCR (0x152)
1426 #define SPR_BOOKE_TCR (0x154)
1427 #define SPR_BOOKE_TLB0PS (0x158)
1428 #define SPR_BOOKE_TLB1PS (0x159)
1429 #define SPR_BOOKE_TLB2PS (0x15A)
1430 #define SPR_BOOKE_TLB3PS (0x15B)
1431 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1432 #define SPR_BOOKE_IVOR0 (0x190)
1433 #define SPR_BOOKE_IVOR1 (0x191)
1434 #define SPR_BOOKE_IVOR2 (0x192)
1435 #define SPR_BOOKE_IVOR3 (0x193)
1436 #define SPR_BOOKE_IVOR4 (0x194)
1437 #define SPR_BOOKE_IVOR5 (0x195)
1438 #define SPR_BOOKE_IVOR6 (0x196)
1439 #define SPR_BOOKE_IVOR7 (0x197)
1440 #define SPR_BOOKE_IVOR8 (0x198)
1441 #define SPR_BOOKE_IVOR9 (0x199)
1442 #define SPR_BOOKE_IVOR10 (0x19A)
1443 #define SPR_BOOKE_IVOR11 (0x19B)
1444 #define SPR_BOOKE_IVOR12 (0x19C)
1445 #define SPR_BOOKE_IVOR13 (0x19D)
1446 #define SPR_BOOKE_IVOR14 (0x19E)
1447 #define SPR_BOOKE_IVOR15 (0x19F)
1448 #define SPR_BOOKE_IVOR38 (0x1B0)
1449 #define SPR_BOOKE_IVOR39 (0x1B1)
1450 #define SPR_BOOKE_IVOR40 (0x1B2)
1451 #define SPR_BOOKE_IVOR41 (0x1B3)
1452 #define SPR_BOOKE_IVOR42 (0x1B4)
1453 #define SPR_BOOKE_GIVOR2 (0x1B8)
1454 #define SPR_BOOKE_GIVOR3 (0x1B9)
1455 #define SPR_BOOKE_GIVOR4 (0x1BA)
1456 #define SPR_BOOKE_GIVOR8 (0x1BB)
1457 #define SPR_BOOKE_GIVOR13 (0x1BC)
1458 #define SPR_BOOKE_GIVOR14 (0x1BD)
1459 #define SPR_TIR (0x1BE)
1460 #define SPR_BOOKE_SPEFSCR (0x200)
1461 #define SPR_Exxx_BBEAR (0x201)
1462 #define SPR_Exxx_BBTAR (0x202)
1463 #define SPR_Exxx_L1CFG0 (0x203)
1464 #define SPR_Exxx_L1CFG1 (0x204)
1465 #define SPR_Exxx_NPIDR (0x205)
1466 #define SPR_ATBL (0x20E)
1467 #define SPR_ATBU (0x20F)
1468 #define SPR_IBAT0U (0x210)
1469 #define SPR_BOOKE_IVOR32 (0x210)
1470 #define SPR_RCPU_MI_GRA (0x210)
1471 #define SPR_IBAT0L (0x211)
1472 #define SPR_BOOKE_IVOR33 (0x211)
1473 #define SPR_IBAT1U (0x212)
1474 #define SPR_BOOKE_IVOR34 (0x212)
1475 #define SPR_IBAT1L (0x213)
1476 #define SPR_BOOKE_IVOR35 (0x213)
1477 #define SPR_IBAT2U (0x214)
1478 #define SPR_BOOKE_IVOR36 (0x214)
1479 #define SPR_IBAT2L (0x215)
1480 #define SPR_BOOKE_IVOR37 (0x215)
1481 #define SPR_IBAT3U (0x216)
1482 #define SPR_IBAT3L (0x217)
1483 #define SPR_DBAT0U (0x218)
1484 #define SPR_RCPU_L2U_GRA (0x218)
1485 #define SPR_DBAT0L (0x219)
1486 #define SPR_DBAT1U (0x21A)
1487 #define SPR_DBAT1L (0x21B)
1488 #define SPR_DBAT2U (0x21C)
1489 #define SPR_DBAT2L (0x21D)
1490 #define SPR_DBAT3U (0x21E)
1491 #define SPR_DBAT3L (0x21F)
1492 #define SPR_IBAT4U (0x230)
1493 #define SPR_RPCU_BBCMCR (0x230)
1494 #define SPR_MPC_IC_CST (0x230)
1495 #define SPR_Exxx_CTXCR (0x230)
1496 #define SPR_IBAT4L (0x231)
1497 #define SPR_MPC_IC_ADR (0x231)
1498 #define SPR_Exxx_DBCR3 (0x231)
1499 #define SPR_IBAT5U (0x232)
1500 #define SPR_MPC_IC_DAT (0x232)
1501 #define SPR_Exxx_DBCNT (0x232)
1502 #define SPR_IBAT5L (0x233)
1503 #define SPR_IBAT6U (0x234)
1504 #define SPR_IBAT6L (0x235)
1505 #define SPR_IBAT7U (0x236)
1506 #define SPR_IBAT7L (0x237)
1507 #define SPR_DBAT4U (0x238)
1508 #define SPR_RCPU_L2U_MCR (0x238)
1509 #define SPR_MPC_DC_CST (0x238)
1510 #define SPR_Exxx_ALTCTXCR (0x238)
1511 #define SPR_DBAT4L (0x239)
1512 #define SPR_MPC_DC_ADR (0x239)
1513 #define SPR_DBAT5U (0x23A)
1514 #define SPR_BOOKE_MCSRR0 (0x23A)
1515 #define SPR_MPC_DC_DAT (0x23A)
1516 #define SPR_DBAT5L (0x23B)
1517 #define SPR_BOOKE_MCSRR1 (0x23B)
1518 #define SPR_DBAT6U (0x23C)
1519 #define SPR_BOOKE_MCSR (0x23C)
1520 #define SPR_DBAT6L (0x23D)
1521 #define SPR_Exxx_MCAR (0x23D)
1522 #define SPR_DBAT7U (0x23E)
1523 #define SPR_BOOKE_DSRR0 (0x23E)
1524 #define SPR_DBAT7L (0x23F)
1525 #define SPR_BOOKE_DSRR1 (0x23F)
1526 #define SPR_BOOKE_SPRG8 (0x25C)
1527 #define SPR_BOOKE_SPRG9 (0x25D)
1528 #define SPR_BOOKE_MAS0 (0x270)
1529 #define SPR_BOOKE_MAS1 (0x271)
1530 #define SPR_BOOKE_MAS2 (0x272)
1531 #define SPR_BOOKE_MAS3 (0x273)
1532 #define SPR_BOOKE_MAS4 (0x274)
1533 #define SPR_BOOKE_MAS5 (0x275)
1534 #define SPR_BOOKE_MAS6 (0x276)
1535 #define SPR_BOOKE_PID1 (0x279)
1536 #define SPR_BOOKE_PID2 (0x27A)
1537 #define SPR_MPC_DPDR (0x280)
1538 #define SPR_MPC_IMMR (0x288)
1539 #define SPR_BOOKE_TLB0CFG (0x2B0)
1540 #define SPR_BOOKE_TLB1CFG (0x2B1)
1541 #define SPR_BOOKE_TLB2CFG (0x2B2)
1542 #define SPR_BOOKE_TLB3CFG (0x2B3)
1543 #define SPR_BOOKE_EPR (0x2BE)
1544 #define SPR_PERF0 (0x300)
1545 #define SPR_RCPU_MI_RBA0 (0x300)
1546 #define SPR_MPC_MI_CTR (0x300)
1547 #define SPR_PERF1 (0x301)
1548 #define SPR_RCPU_MI_RBA1 (0x301)
1549 #define SPR_POWER_UMMCR2 (0x301)
1550 #define SPR_PERF2 (0x302)
1551 #define SPR_RCPU_MI_RBA2 (0x302)
1552 #define SPR_MPC_MI_AP (0x302)
1553 #define SPR_POWER_UMMCRA (0x302)
1554 #define SPR_PERF3 (0x303)
1555 #define SPR_RCPU_MI_RBA3 (0x303)
1556 #define SPR_MPC_MI_EPN (0x303)
1557 #define SPR_POWER_UPMC1 (0x303)
1558 #define SPR_PERF4 (0x304)
1559 #define SPR_POWER_UPMC2 (0x304)
1560 #define SPR_PERF5 (0x305)
1561 #define SPR_MPC_MI_TWC (0x305)
1562 #define SPR_POWER_UPMC3 (0x305)
1563 #define SPR_PERF6 (0x306)
1564 #define SPR_MPC_MI_RPN (0x306)
1565 #define SPR_POWER_UPMC4 (0x306)
1566 #define SPR_PERF7 (0x307)
1567 #define SPR_POWER_UPMC5 (0x307)
1568 #define SPR_PERF8 (0x308)
1569 #define SPR_RCPU_L2U_RBA0 (0x308)
1570 #define SPR_MPC_MD_CTR (0x308)
1571 #define SPR_POWER_UPMC6 (0x308)
1572 #define SPR_PERF9 (0x309)
1573 #define SPR_RCPU_L2U_RBA1 (0x309)
1574 #define SPR_MPC_MD_CASID (0x309)
1575 #define SPR_970_UPMC7 (0X309)
1576 #define SPR_PERFA (0x30A)
1577 #define SPR_RCPU_L2U_RBA2 (0x30A)
1578 #define SPR_MPC_MD_AP (0x30A)
1579 #define SPR_970_UPMC8 (0X30A)
1580 #define SPR_PERFB (0x30B)
1581 #define SPR_RCPU_L2U_RBA3 (0x30B)
1582 #define SPR_MPC_MD_EPN (0x30B)
1583 #define SPR_POWER_UMMCR0 (0X30B)
1584 #define SPR_PERFC (0x30C)
1585 #define SPR_MPC_MD_TWB (0x30C)
1586 #define SPR_POWER_USIAR (0X30C)
1587 #define SPR_PERFD (0x30D)
1588 #define SPR_MPC_MD_TWC (0x30D)
1589 #define SPR_POWER_USDAR (0X30D)
1590 #define SPR_PERFE (0x30E)
1591 #define SPR_MPC_MD_RPN (0x30E)
1592 #define SPR_POWER_UMMCR1 (0X30E)
1593 #define SPR_PERFF (0x30F)
1594 #define SPR_MPC_MD_TW (0x30F)
1595 #define SPR_UPERF0 (0x310)
1596 #define SPR_UPERF1 (0x311)
1597 #define SPR_POWER_MMCR2 (0x311)
1598 #define SPR_UPERF2 (0x312)
1599 #define SPR_POWER_MMCRA (0X312)
1600 #define SPR_UPERF3 (0x313)
1601 #define SPR_POWER_PMC1 (0X313)
1602 #define SPR_UPERF4 (0x314)
1603 #define SPR_POWER_PMC2 (0X314)
1604 #define SPR_UPERF5 (0x315)
1605 #define SPR_POWER_PMC3 (0X315)
1606 #define SPR_UPERF6 (0x316)
1607 #define SPR_POWER_PMC4 (0X316)
1608 #define SPR_UPERF7 (0x317)
1609 #define SPR_POWER_PMC5 (0X317)
1610 #define SPR_UPERF8 (0x318)
1611 #define SPR_POWER_PMC6 (0X318)
1612 #define SPR_UPERF9 (0x319)
1613 #define SPR_970_PMC7 (0X319)
1614 #define SPR_UPERFA (0x31A)
1615 #define SPR_970_PMC8 (0X31A)
1616 #define SPR_UPERFB (0x31B)
1617 #define SPR_POWER_MMCR0 (0X31B)
1618 #define SPR_UPERFC (0x31C)
1619 #define SPR_POWER_SIAR (0X31C)
1620 #define SPR_UPERFD (0x31D)
1621 #define SPR_POWER_SDAR (0X31D)
1622 #define SPR_UPERFE (0x31E)
1623 #define SPR_POWER_MMCR1 (0X31E)
1624 #define SPR_UPERFF (0x31F)
1625 #define SPR_RCPU_MI_RA0 (0x320)
1626 #define SPR_MPC_MI_DBCAM (0x320)
1627 #define SPR_BESCRS (0x320)
1628 #define SPR_RCPU_MI_RA1 (0x321)
1629 #define SPR_MPC_MI_DBRAM0 (0x321)
1630 #define SPR_BESCRSU (0x321)
1631 #define SPR_RCPU_MI_RA2 (0x322)
1632 #define SPR_MPC_MI_DBRAM1 (0x322)
1633 #define SPR_BESCRR (0x322)
1634 #define SPR_RCPU_MI_RA3 (0x323)
1635 #define SPR_BESCRRU (0x323)
1636 #define SPR_EBBHR (0x324)
1637 #define SPR_EBBRR (0x325)
1638 #define SPR_BESCR (0x326)
1639 #define SPR_RCPU_L2U_RA0 (0x328)
1640 #define SPR_MPC_MD_DBCAM (0x328)
1641 #define SPR_RCPU_L2U_RA1 (0x329)
1642 #define SPR_MPC_MD_DBRAM0 (0x329)
1643 #define SPR_RCPU_L2U_RA2 (0x32A)
1644 #define SPR_MPC_MD_DBRAM1 (0x32A)
1645 #define SPR_RCPU_L2U_RA3 (0x32B)
1646 #define SPR_TAR (0x32F)
1647 #define SPR_VTB (0x351)
1648 #define SPR_440_INV0 (0x370)
1649 #define SPR_440_INV1 (0x371)
1650 #define SPR_440_INV2 (0x372)
1651 #define SPR_440_INV3 (0x373)
1652 #define SPR_440_ITV0 (0x374)
1653 #define SPR_440_ITV1 (0x375)
1654 #define SPR_440_ITV2 (0x376)
1655 #define SPR_440_ITV3 (0x377)
1656 #define SPR_440_CCR1 (0x378)
1657 #define SPR_DCRIPR (0x37B)
1658 #define SPR_POWER_MMCRS (0x37E)
1659 #define SPR_PPR (0x380)
1660 #define SPR_750_GQR0 (0x390)
1661 #define SPR_440_DNV0 (0x390)
1662 #define SPR_750_GQR1 (0x391)
1663 #define SPR_440_DNV1 (0x391)
1664 #define SPR_750_GQR2 (0x392)
1665 #define SPR_440_DNV2 (0x392)
1666 #define SPR_750_GQR3 (0x393)
1667 #define SPR_440_DNV3 (0x393)
1668 #define SPR_750_GQR4 (0x394)
1669 #define SPR_440_DTV0 (0x394)
1670 #define SPR_750_GQR5 (0x395)
1671 #define SPR_440_DTV1 (0x395)
1672 #define SPR_750_GQR6 (0x396)
1673 #define SPR_440_DTV2 (0x396)
1674 #define SPR_750_GQR7 (0x397)
1675 #define SPR_440_DTV3 (0x397)
1676 #define SPR_750_THRM4 (0x398)
1677 #define SPR_750CL_HID2 (0x398)
1678 #define SPR_440_DVLIM (0x398)
1679 #define SPR_750_WPAR (0x399)
1680 #define SPR_440_IVLIM (0x399)
1681 #define SPR_750_DMAU (0x39A)
1682 #define SPR_750_DMAL (0x39B)
1683 #define SPR_440_RSTCFG (0x39B)
1684 #define SPR_BOOKE_DCDBTRL (0x39C)
1685 #define SPR_BOOKE_DCDBTRH (0x39D)
1686 #define SPR_BOOKE_ICDBTRL (0x39E)
1687 #define SPR_BOOKE_ICDBTRH (0x39F)
1688 #define SPR_74XX_UMMCR2 (0x3A0)
1689 #define SPR_7XX_UPMC5 (0x3A1)
1690 #define SPR_7XX_UPMC6 (0x3A2)
1691 #define SPR_UBAMR (0x3A7)
1692 #define SPR_7XX_UMMCR0 (0x3A8)
1693 #define SPR_7XX_UPMC1 (0x3A9)
1694 #define SPR_7XX_UPMC2 (0x3AA)
1695 #define SPR_7XX_USIAR (0x3AB)
1696 #define SPR_7XX_UMMCR1 (0x3AC)
1697 #define SPR_7XX_UPMC3 (0x3AD)
1698 #define SPR_7XX_UPMC4 (0x3AE)
1699 #define SPR_USDA (0x3AF)
1700 #define SPR_40x_ZPR (0x3B0)
1701 #define SPR_BOOKE_MAS7 (0x3B0)
1702 #define SPR_74XX_MMCR2 (0x3B0)
1703 #define SPR_7XX_PMC5 (0x3B1)
1704 #define SPR_40x_PID (0x3B1)
1705 #define SPR_7XX_PMC6 (0x3B2)
1706 #define SPR_440_MMUCR (0x3B2)
1707 #define SPR_4xx_CCR0 (0x3B3)
1708 #define SPR_BOOKE_EPLC (0x3B3)
1709 #define SPR_405_IAC3 (0x3B4)
1710 #define SPR_BOOKE_EPSC (0x3B4)
1711 #define SPR_405_IAC4 (0x3B5)
1712 #define SPR_405_DVC1 (0x3B6)
1713 #define SPR_405_DVC2 (0x3B7)
1714 #define SPR_BAMR (0x3B7)
1715 #define SPR_7XX_MMCR0 (0x3B8)
1716 #define SPR_7XX_PMC1 (0x3B9)
1717 #define SPR_40x_SGR (0x3B9)
1718 #define SPR_7XX_PMC2 (0x3BA)
1719 #define SPR_40x_DCWR (0x3BA)
1720 #define SPR_7XX_SIAR (0x3BB)
1721 #define SPR_405_SLER (0x3BB)
1722 #define SPR_7XX_MMCR1 (0x3BC)
1723 #define SPR_405_SU0R (0x3BC)
1724 #define SPR_401_SKR (0x3BC)
1725 #define SPR_7XX_PMC3 (0x3BD)
1726 #define SPR_405_DBCR1 (0x3BD)
1727 #define SPR_7XX_PMC4 (0x3BE)
1728 #define SPR_SDA (0x3BF)
1729 #define SPR_403_VTBL (0x3CC)
1730 #define SPR_403_VTBU (0x3CD)
1731 #define SPR_DMISS (0x3D0)
1732 #define SPR_DCMP (0x3D1)
1733 #define SPR_HASH1 (0x3D2)
1734 #define SPR_HASH2 (0x3D3)
1735 #define SPR_BOOKE_ICDBDR (0x3D3)
1736 #define SPR_TLBMISS (0x3D4)
1737 #define SPR_IMISS (0x3D4)
1738 #define SPR_40x_ESR (0x3D4)
1739 #define SPR_PTEHI (0x3D5)
1740 #define SPR_ICMP (0x3D5)
1741 #define SPR_40x_DEAR (0x3D5)
1742 #define SPR_PTELO (0x3D6)
1743 #define SPR_RPA (0x3D6)
1744 #define SPR_40x_EVPR (0x3D6)
1745 #define SPR_L3PM (0x3D7)
1746 #define SPR_403_CDBCR (0x3D7)
1747 #define SPR_L3ITCR0 (0x3D8)
1748 #define SPR_TCR (0x3D8)
1749 #define SPR_40x_TSR (0x3D8)
1750 #define SPR_IBR (0x3DA)
1751 #define SPR_40x_TCR (0x3DA)
1752 #define SPR_ESASRR (0x3DB)
1753 #define SPR_40x_PIT (0x3DB)
1754 #define SPR_403_TBL (0x3DC)
1755 #define SPR_403_TBU (0x3DD)
1756 #define SPR_SEBR (0x3DE)
1757 #define SPR_40x_SRR2 (0x3DE)
1758 #define SPR_SER (0x3DF)
1759 #define SPR_40x_SRR3 (0x3DF)
1760 #define SPR_L3OHCR (0x3E8)
1761 #define SPR_L3ITCR1 (0x3E9)
1762 #define SPR_L3ITCR2 (0x3EA)
1763 #define SPR_L3ITCR3 (0x3EB)
1764 #define SPR_HID0 (0x3F0)
1765 #define SPR_40x_DBSR (0x3F0)
1766 #define SPR_HID1 (0x3F1)
1767 #define SPR_IABR (0x3F2)
1768 #define SPR_40x_DBCR0 (0x3F2)
1769 #define SPR_601_HID2 (0x3F2)
1770 #define SPR_Exxx_L1CSR0 (0x3F2)
1771 #define SPR_ICTRL (0x3F3)
1772 #define SPR_HID2 (0x3F3)
1773 #define SPR_750CL_HID4 (0x3F3)
1774 #define SPR_Exxx_L1CSR1 (0x3F3)
1775 #define SPR_440_DBDR (0x3F3)
1776 #define SPR_LDSTDB (0x3F4)
1777 #define SPR_750_TDCL (0x3F4)
1778 #define SPR_40x_IAC1 (0x3F4)
1779 #define SPR_MMUCSR0 (0x3F4)
1780 #define SPR_970_HID4 (0x3F4)
1781 #define SPR_DABR (0x3F5)
1782 #define DABR_MASK (~(target_ulong)0x7)
1783 #define SPR_Exxx_BUCSR (0x3F5)
1784 #define SPR_40x_IAC2 (0x3F5)
1785 #define SPR_601_HID5 (0x3F5)
1786 #define SPR_40x_DAC1 (0x3F6)
1787 #define SPR_MSSCR0 (0x3F6)
1788 #define SPR_970_HID5 (0x3F6)
1789 #define SPR_MSSSR0 (0x3F7)
1790 #define SPR_MSSCR1 (0x3F7)
1791 #define SPR_DABRX (0x3F7)
1792 #define SPR_40x_DAC2 (0x3F7)
1793 #define SPR_MMUCFG (0x3F7)
1794 #define SPR_LDSTCR (0x3F8)
1795 #define SPR_L2PMCR (0x3F8)
1796 #define SPR_750FX_HID2 (0x3F8)
1797 #define SPR_Exxx_L1FINV0 (0x3F8)
1798 #define SPR_L2CR (0x3F9)
1799 #define SPR_L3CR (0x3FA)
1800 #define SPR_750_TDCH (0x3FA)
1801 #define SPR_IABR2 (0x3FA)
1802 #define SPR_40x_DCCR (0x3FA)
1803 #define SPR_ICTC (0x3FB)
1804 #define SPR_40x_ICCR (0x3FB)
1805 #define SPR_THRM1 (0x3FC)
1806 #define SPR_403_PBL1 (0x3FC)
1807 #define SPR_SP (0x3FD)
1808 #define SPR_THRM2 (0x3FD)
1809 #define SPR_403_PBU1 (0x3FD)
1810 #define SPR_604_HID13 (0x3FD)
1811 #define SPR_LT (0x3FE)
1812 #define SPR_THRM3 (0x3FE)
1813 #define SPR_RCPU_FPECR (0x3FE)
1814 #define SPR_403_PBL2 (0x3FE)
1815 #define SPR_PIR (0x3FF)
1816 #define SPR_403_PBU2 (0x3FF)
1817 #define SPR_601_HID15 (0x3FF)
1818 #define SPR_604_HID15 (0x3FF)
1819 #define SPR_E500_SVR (0x3FF)
1820
1821 /* Disable MAS Interrupt Updates for Hypervisor */
1822 #define EPCR_DMIUH (1 << 22)
1823 /* Disable Guest TLB Management Instructions */
1824 #define EPCR_DGTMI (1 << 23)
1825 /* Guest Interrupt Computation Mode */
1826 #define EPCR_GICM (1 << 24)
1827 /* Interrupt Computation Mode */
1828 #define EPCR_ICM (1 << 25)
1829 /* Disable Embedded Hypervisor Debug */
1830 #define EPCR_DUVD (1 << 26)
1831 /* Instruction Storage Interrupt Directed to Guest State */
1832 #define EPCR_ISIGS (1 << 27)
1833 /* Data Storage Interrupt Directed to Guest State */
1834 #define EPCR_DSIGS (1 << 28)
1835 /* Instruction TLB Error Interrupt Directed to Guest State */
1836 #define EPCR_ITLBGS (1 << 29)
1837 /* Data TLB Error Interrupt Directed to Guest State */
1838 #define EPCR_DTLBGS (1 << 30)
1839 /* External Input Interrupt Directed to Guest State */
1840 #define EPCR_EXTGS (1 << 31)
1841
1842 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1843 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1844 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1845 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1846 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1847
1848 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1849 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1850 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1851 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1852 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1853
1854 /* HID0 bits */
1855 #define HID0_DEEPNAP (1 << 24)
1856 #define HID0_DOZE (1 << 23)
1857 #define HID0_NAP (1 << 22)
1858
1859 /*****************************************************************************/
1860 /* PowerPC Instructions types definitions */
1861 enum {
1862 PPC_NONE = 0x0000000000000000ULL,
1863 /* PowerPC base instructions set */
1864 PPC_INSNS_BASE = 0x0000000000000001ULL,
1865 /* integer operations instructions */
1866 #define PPC_INTEGER PPC_INSNS_BASE
1867 /* flow control instructions */
1868 #define PPC_FLOW PPC_INSNS_BASE
1869 /* virtual memory instructions */
1870 #define PPC_MEM PPC_INSNS_BASE
1871 /* ld/st with reservation instructions */
1872 #define PPC_RES PPC_INSNS_BASE
1873 /* spr/msr access instructions */
1874 #define PPC_MISC PPC_INSNS_BASE
1875 /* Deprecated instruction sets */
1876 /* Original POWER instruction set */
1877 PPC_POWER = 0x0000000000000002ULL,
1878 /* POWER2 instruction set extension */
1879 PPC_POWER2 = 0x0000000000000004ULL,
1880 /* Power RTC support */
1881 PPC_POWER_RTC = 0x0000000000000008ULL,
1882 /* Power-to-PowerPC bridge (601) */
1883 PPC_POWER_BR = 0x0000000000000010ULL,
1884 /* 64 bits PowerPC instruction set */
1885 PPC_64B = 0x0000000000000020ULL,
1886 /* New 64 bits extensions (PowerPC 2.0x) */
1887 PPC_64BX = 0x0000000000000040ULL,
1888 /* 64 bits hypervisor extensions */
1889 PPC_64H = 0x0000000000000080ULL,
1890 /* New wait instruction (PowerPC 2.0x) */
1891 PPC_WAIT = 0x0000000000000100ULL,
1892 /* Time base mftb instruction */
1893 PPC_MFTB = 0x0000000000000200ULL,
1894
1895 /* Fixed-point unit extensions */
1896 /* PowerPC 602 specific */
1897 PPC_602_SPEC = 0x0000000000000400ULL,
1898 /* isel instruction */
1899 PPC_ISEL = 0x0000000000000800ULL,
1900 /* popcntb instruction */
1901 PPC_POPCNTB = 0x0000000000001000ULL,
1902 /* string load / store */
1903 PPC_STRING = 0x0000000000002000ULL,
1904
1905 /* Floating-point unit extensions */
1906 /* Optional floating point instructions */
1907 PPC_FLOAT = 0x0000000000010000ULL,
1908 /* New floating-point extensions (PowerPC 2.0x) */
1909 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1910 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1911 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1912 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1913 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1914 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1915 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1916
1917 /* Vector/SIMD extensions */
1918 /* Altivec support */
1919 PPC_ALTIVEC = 0x0000000001000000ULL,
1920 /* PowerPC 2.03 SPE extension */
1921 PPC_SPE = 0x0000000002000000ULL,
1922 /* PowerPC 2.03 SPE single-precision floating-point extension */
1923 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1924 /* PowerPC 2.03 SPE double-precision floating-point extension */
1925 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1926
1927 /* Optional memory control instructions */
1928 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1929 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1930 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1931 /* sync instruction */
1932 PPC_MEM_SYNC = 0x0000000080000000ULL,
1933 /* eieio instruction */
1934 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1935
1936 /* Cache control instructions */
1937 PPC_CACHE = 0x0000000200000000ULL,
1938 /* icbi instruction */
1939 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1940 /* dcbz instruction */
1941 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1942 /* dcba instruction */
1943 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1944 /* Freescale cache locking instructions */
1945 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1946
1947 /* MMU related extensions */
1948 /* external control instructions */
1949 PPC_EXTERN = 0x0000010000000000ULL,
1950 /* segment register access instructions */
1951 PPC_SEGMENT = 0x0000020000000000ULL,
1952 /* PowerPC 6xx TLB management instructions */
1953 PPC_6xx_TLB = 0x0000040000000000ULL,
1954 /* PowerPC 74xx TLB management instructions */
1955 PPC_74xx_TLB = 0x0000080000000000ULL,
1956 /* PowerPC 40x TLB management instructions */
1957 PPC_40x_TLB = 0x0000100000000000ULL,
1958 /* segment register access instructions for PowerPC 64 "bridge" */
1959 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1960 /* SLB management */
1961 PPC_SLBI = 0x0000400000000000ULL,
1962
1963 /* Embedded PowerPC dedicated instructions */
1964 PPC_WRTEE = 0x0001000000000000ULL,
1965 /* PowerPC 40x exception model */
1966 PPC_40x_EXCP = 0x0002000000000000ULL,
1967 /* PowerPC 405 Mac instructions */
1968 PPC_405_MAC = 0x0004000000000000ULL,
1969 /* PowerPC 440 specific instructions */
1970 PPC_440_SPEC = 0x0008000000000000ULL,
1971 /* BookE (embedded) PowerPC specification */
1972 PPC_BOOKE = 0x0010000000000000ULL,
1973 /* mfapidi instruction */
1974 PPC_MFAPIDI = 0x0020000000000000ULL,
1975 /* tlbiva instruction */
1976 PPC_TLBIVA = 0x0040000000000000ULL,
1977 /* tlbivax instruction */
1978 PPC_TLBIVAX = 0x0080000000000000ULL,
1979 /* PowerPC 4xx dedicated instructions */
1980 PPC_4xx_COMMON = 0x0100000000000000ULL,
1981 /* PowerPC 40x ibct instructions */
1982 PPC_40x_ICBT = 0x0200000000000000ULL,
1983 /* rfmci is not implemented in all BookE PowerPC */
1984 PPC_RFMCI = 0x0400000000000000ULL,
1985 /* rfdi instruction */
1986 PPC_RFDI = 0x0800000000000000ULL,
1987 /* DCR accesses */
1988 PPC_DCR = 0x1000000000000000ULL,
1989 /* DCR extended accesse */
1990 PPC_DCRX = 0x2000000000000000ULL,
1991 /* user-mode DCR access, implemented in PowerPC 460 */
1992 PPC_DCRUX = 0x4000000000000000ULL,
1993 /* popcntw and popcntd instructions */
1994 PPC_POPCNTWD = 0x8000000000000000ULL,
1995
1996 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1997 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1998 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1999 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2000 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2001 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2002 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2003 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2004 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2005 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2006 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2007 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2008 | PPC_CACHE | PPC_CACHE_ICBI \
2009 | PPC_CACHE_DCBZ \
2010 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2011 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2012 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2013 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2014 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2015 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2016 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2017 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2018 | PPC_POPCNTWD)
2019
2020 /* extended type values */
2021
2022 /* BookE 2.06 PowerPC specification */
2023 PPC2_BOOKE206 = 0x0000000000000001ULL,
2024 /* VSX (extensions to Altivec / VMX) */
2025 PPC2_VSX = 0x0000000000000002ULL,
2026 /* Decimal Floating Point (DFP) */
2027 PPC2_DFP = 0x0000000000000004ULL,
2028 /* Embedded.Processor Control */
2029 PPC2_PRCNTL = 0x0000000000000008ULL,
2030 /* Byte-reversed, indexed, double-word load and store */
2031 PPC2_DBRX = 0x0000000000000010ULL,
2032 /* Book I 2.05 PowerPC specification */
2033 PPC2_ISA205 = 0x0000000000000020ULL,
2034 /* VSX additions in ISA 2.07 */
2035 PPC2_VSX207 = 0x0000000000000040ULL,
2036 /* ISA 2.06B bpermd */
2037 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2038 /* ISA 2.06B divide extended variants */
2039 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2040 /* ISA 2.06B larx/stcx. instructions */
2041 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2042 /* ISA 2.06B floating point integer conversion */
2043 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2044 /* ISA 2.06B floating point test instructions */
2045 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2046 /* ISA 2.07 bctar instruction */
2047 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2048 /* ISA 2.07 load/store quadword */
2049 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2050 /* ISA 2.07 Altivec */
2051 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2052 /* PowerISA 2.07 Book3s specification */
2053 PPC2_ISA207S = 0x0000000000008000ULL,
2054 /* Double precision floating point conversion for signed integer 64 */
2055 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2056 /* Transactional Memory (ISA 2.07, Book II) */
2057 PPC2_TM = 0x0000000000020000ULL,
2058
2059 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2060 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2061 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2062 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2063 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2064 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2065 PPC2_FP_CVT_S64 | PPC2_TM)
2066 };
2067
2068 /*****************************************************************************/
2069 /* Memory access type :
2070 * may be needed for precise access rights control and precise exceptions.
2071 */
2072 enum {
2073 /* 1 bit to define user level / supervisor access */
2074 ACCESS_USER = 0x00,
2075 ACCESS_SUPER = 0x01,
2076 /* Type of instruction that generated the access */
2077 ACCESS_CODE = 0x10, /* Code fetch access */
2078 ACCESS_INT = 0x20, /* Integer load/store access */
2079 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2080 ACCESS_RES = 0x40, /* load/store with reservation */
2081 ACCESS_EXT = 0x50, /* external access */
2082 ACCESS_CACHE = 0x60, /* Cache manipulation */
2083 };
2084
2085 /* Hardware interruption sources:
2086 * all those exception can be raised simulteaneously
2087 */
2088 /* Input pins definitions */
2089 enum {
2090 /* 6xx bus input pins */
2091 PPC6xx_INPUT_HRESET = 0,
2092 PPC6xx_INPUT_SRESET = 1,
2093 PPC6xx_INPUT_CKSTP_IN = 2,
2094 PPC6xx_INPUT_MCP = 3,
2095 PPC6xx_INPUT_SMI = 4,
2096 PPC6xx_INPUT_INT = 5,
2097 PPC6xx_INPUT_TBEN = 6,
2098 PPC6xx_INPUT_WAKEUP = 7,
2099 PPC6xx_INPUT_NB,
2100 };
2101
2102 enum {
2103 /* Embedded PowerPC input pins */
2104 PPCBookE_INPUT_HRESET = 0,
2105 PPCBookE_INPUT_SRESET = 1,
2106 PPCBookE_INPUT_CKSTP_IN = 2,
2107 PPCBookE_INPUT_MCP = 3,
2108 PPCBookE_INPUT_SMI = 4,
2109 PPCBookE_INPUT_INT = 5,
2110 PPCBookE_INPUT_CINT = 6,
2111 PPCBookE_INPUT_NB,
2112 };
2113
2114 enum {
2115 /* PowerPC E500 input pins */
2116 PPCE500_INPUT_RESET_CORE = 0,
2117 PPCE500_INPUT_MCK = 1,
2118 PPCE500_INPUT_CINT = 3,
2119 PPCE500_INPUT_INT = 4,
2120 PPCE500_INPUT_DEBUG = 6,
2121 PPCE500_INPUT_NB,
2122 };
2123
2124 enum {
2125 /* PowerPC 40x input pins */
2126 PPC40x_INPUT_RESET_CORE = 0,
2127 PPC40x_INPUT_RESET_CHIP = 1,
2128 PPC40x_INPUT_RESET_SYS = 2,
2129 PPC40x_INPUT_CINT = 3,
2130 PPC40x_INPUT_INT = 4,
2131 PPC40x_INPUT_HALT = 5,
2132 PPC40x_INPUT_DEBUG = 6,
2133 PPC40x_INPUT_NB,
2134 };
2135
2136 enum {
2137 /* RCPU input pins */
2138 PPCRCPU_INPUT_PORESET = 0,
2139 PPCRCPU_INPUT_HRESET = 1,
2140 PPCRCPU_INPUT_SRESET = 2,
2141 PPCRCPU_INPUT_IRQ0 = 3,
2142 PPCRCPU_INPUT_IRQ1 = 4,
2143 PPCRCPU_INPUT_IRQ2 = 5,
2144 PPCRCPU_INPUT_IRQ3 = 6,
2145 PPCRCPU_INPUT_IRQ4 = 7,
2146 PPCRCPU_INPUT_IRQ5 = 8,
2147 PPCRCPU_INPUT_IRQ6 = 9,
2148 PPCRCPU_INPUT_IRQ7 = 10,
2149 PPCRCPU_INPUT_NB,
2150 };
2151
2152 #if defined(TARGET_PPC64)
2153 enum {
2154 /* PowerPC 970 input pins */
2155 PPC970_INPUT_HRESET = 0,
2156 PPC970_INPUT_SRESET = 1,
2157 PPC970_INPUT_CKSTP = 2,
2158 PPC970_INPUT_TBEN = 3,
2159 PPC970_INPUT_MCP = 4,
2160 PPC970_INPUT_INT = 5,
2161 PPC970_INPUT_THINT = 6,
2162 PPC970_INPUT_NB,
2163 };
2164
2165 enum {
2166 /* POWER7 input pins */
2167 POWER7_INPUT_INT = 0,
2168 /* POWER7 probably has other inputs, but we don't care about them
2169 * for any existing machine. We can wire these up when we need
2170 * them */
2171 POWER7_INPUT_NB,
2172 };
2173 #endif
2174
2175 /* Hardware exceptions definitions */
2176 enum {
2177 /* External hardware exception sources */
2178 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2179 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2180 PPC_INTERRUPT_MCK, /* Machine check exception */
2181 PPC_INTERRUPT_EXT, /* External interrupt */
2182 PPC_INTERRUPT_SMI, /* System management interrupt */
2183 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2184 PPC_INTERRUPT_DEBUG, /* External debug exception */
2185 PPC_INTERRUPT_THERM, /* Thermal exception */
2186 /* Internal hardware exception sources */
2187 PPC_INTERRUPT_DECR, /* Decrementer exception */
2188 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2189 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2190 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2191 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2192 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2193 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2194 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2195 };
2196
2197 /* Processor Compatibility mask (PCR) */
2198 enum {
2199 PCR_COMPAT_2_05 = 1ull << (63-62),
2200 PCR_COMPAT_2_06 = 1ull << (63-61),
2201 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2202 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2203 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2204 };
2205
2206 /*****************************************************************************/
2207
2208 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2209 {
2210 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2211 }
2212
2213 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2214 {
2215 env->so = (xer >> XER_SO) & 1;
2216 env->ov = (xer >> XER_OV) & 1;
2217 env->ca = (xer >> XER_CA) & 1;
2218 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2219 }
2220
2221 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2222 target_ulong *cs_base, int *flags)
2223 {
2224 *pc = env->nip;
2225 *cs_base = 0;
2226 *flags = env->hflags;
2227 }
2228
2229 #if !defined(CONFIG_USER_ONLY)
2230 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2231 {
2232 uintptr_t tlbml = (uintptr_t)tlbm;
2233 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2234
2235 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2236 }
2237
2238 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2239 {
2240 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2241 int r = tlbncfg & TLBnCFG_N_ENTRY;
2242 return r;
2243 }
2244
2245 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2246 {
2247 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2248 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2249 return r;
2250 }
2251
2252 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2253 {
2254 int id = booke206_tlbm_id(env, tlbm);
2255 int end = 0;
2256 int i;
2257
2258 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2259 end += booke206_tlb_size(env, i);
2260 if (id < end) {
2261 return i;
2262 }
2263 }
2264
2265 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2266 return 0;
2267 }
2268
2269 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2270 {
2271 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2272 int tlbid = booke206_tlbm_id(env, tlb);
2273 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2274 }
2275
2276 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2277 target_ulong ea, int way)
2278 {
2279 int r;
2280 uint32_t ways = booke206_tlb_ways(env, tlbn);
2281 int ways_bits = ctz32(ways);
2282 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2283 int i;
2284
2285 way &= ways - 1;
2286 ea >>= MAS2_EPN_SHIFT;
2287 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2288 r = (ea << ways_bits) | way;
2289
2290 if (r >= booke206_tlb_size(env, tlbn)) {
2291 return NULL;
2292 }
2293
2294 /* bump up to tlbn index */
2295 for (i = 0; i < tlbn; i++) {
2296 r += booke206_tlb_size(env, i);
2297 }
2298
2299 return &env->tlb.tlbm[r];
2300 }
2301
2302 /* returns bitmap of supported page sizes for a given TLB */
2303 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2304 {
2305 bool mav2 = false;
2306 uint32_t ret = 0;
2307
2308 if (mav2) {
2309 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2310 } else {
2311 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2312 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2313 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2314 int i;
2315 for (i = min; i <= max; i++) {
2316 ret |= (1 << (i << 1));
2317 }
2318 }
2319
2320 return ret;
2321 }
2322
2323 #endif
2324
2325 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2326 {
2327 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2328 return msr & (1ULL << MSR_CM);
2329 }
2330
2331 return msr & (1ULL << MSR_SF);
2332 }
2333
2334 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2335
2336 #include "exec/exec-all.h"
2337
2338 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2339
2340 /**
2341 * ppc_get_vcpu_dt_id:
2342 * @cs: a PowerPCCPU struct.
2343 *
2344 * Returns a device-tree ID for a CPU.
2345 */
2346 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2347
2348 /**
2349 * ppc_get_vcpu_by_dt_id:
2350 * @cpu_dt_id: a device tree id
2351 *
2352 * Searches for a CPU by @cpu_dt_id.
2353 *
2354 * Returns: a PowerPCCPU struct
2355 */
2356 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2357
2358 #endif /* !defined (__CPU_PPC_H__) */
AR7 emulation for QEMU