hw/mips/gt64xxx_pci.c

   1 /*
   2  * QEMU GT64120 PCI host
   3  *
   4  * Copyright (c) 2006,2007 Aurelien Jarno
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/mips/mips.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/i386/pc.h"
  30 #include "exec/address-spaces.h"
  31
  32 //#define DEBUG
  33
  34 #ifdef DEBUG
  35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 #define GT_REGS                 (0x1000 >> 2)
  41
  42 /* CPU Configuration */
  43 #define GT_CPU                  (0x000 >> 2)
  44 #define GT_MULTI                (0x120 >> 2)
  45
  46 /* CPU Address Decode */
  47 #define GT_SCS10LD              (0x008 >> 2)
  48 #define GT_SCS10HD              (0x010 >> 2)
  49 #define GT_SCS32LD              (0x018 >> 2)
  50 #define GT_SCS32HD              (0x020 >> 2)
  51 #define GT_CS20LD               (0x028 >> 2)
  52 #define GT_CS20HD               (0x030 >> 2)
  53 #define GT_CS3BOOTLD            (0x038 >> 2)
  54 #define GT_CS3BOOTHD            (0x040 >> 2)
  55 #define GT_PCI0IOLD             (0x048 >> 2)
  56 #define GT_PCI0IOHD             (0x050 >> 2)
  57 #define GT_PCI0M0LD             (0x058 >> 2)
  58 #define GT_PCI0M0HD             (0x060 >> 2)
  59 #define GT_PCI0M1LD             (0x080 >> 2)
  60 #define GT_PCI0M1HD             (0x088 >> 2)
  61 #define GT_PCI1IOLD             (0x090 >> 2)
  62 #define GT_PCI1IOHD             (0x098 >> 2)
  63 #define GT_PCI1M0LD             (0x0a0 >> 2)
  64 #define GT_PCI1M0HD             (0x0a8 >> 2)
  65 #define GT_PCI1M1LD             (0x0b0 >> 2)
  66 #define GT_PCI1M1HD             (0x0b8 >> 2)
  67 #define GT_ISD                  (0x068 >> 2)
  68
  69 #define GT_SCS10AR              (0x0d0 >> 2)
  70 #define GT_SCS32AR              (0x0d8 >> 2)
  71 #define GT_CS20R                (0x0e0 >> 2)
  72 #define GT_CS3BOOTR             (0x0e8 >> 2)
  73
  74 #define GT_PCI0IOREMAP          (0x0f0 >> 2)
  75 #define GT_PCI0M0REMAP          (0x0f8 >> 2)
  76 #define GT_PCI0M1REMAP          (0x100 >> 2)
  77 #define GT_PCI1IOREMAP          (0x108 >> 2)
  78 #define GT_PCI1M0REMAP          (0x110 >> 2)
  79 #define GT_PCI1M1REMAP          (0x118 >> 2)
  80
  81 /* CPU Error Report */
  82 #define GT_CPUERR_ADDRLO        (0x070 >> 2)
  83 #define GT_CPUERR_ADDRHI        (0x078 >> 2)
  84 #define GT_CPUERR_DATALO        (0x128 >> 2)            /* GT-64120A only  */
  85 #define GT_CPUERR_DATAHI        (0x130 >> 2)            /* GT-64120A only  */
  86 #define GT_CPUERR_PARITY        (0x138 >> 2)            /* GT-64120A only  */
  87
  88 /* CPU Sync Barrier */
  89 #define GT_PCI0SYNC             (0x0c0 >> 2)
  90 #define GT_PCI1SYNC             (0x0c8 >> 2)
  91
  92 /* SDRAM and Device Address Decode */
  93 #define GT_SCS0LD               (0x400 >> 2)
  94 #define GT_SCS0HD               (0x404 >> 2)
  95 #define GT_SCS1LD               (0x408 >> 2)
  96 #define GT_SCS1HD               (0x40c >> 2)
  97 #define GT_SCS2LD               (0x410 >> 2)
  98 #define GT_SCS2HD               (0x414 >> 2)
  99 #define GT_SCS3LD               (0x418 >> 2)
 100 #define GT_SCS3HD               (0x41c >> 2)
 101 #define GT_CS0LD                (0x420 >> 2)
 102 #define GT_CS0HD                (0x424 >> 2)
 103 #define GT_CS1LD                (0x428 >> 2)
 104 #define GT_CS1HD                (0x42c >> 2)
 105 #define GT_CS2LD                (0x430 >> 2)
 106 #define GT_CS2HD                (0x434 >> 2)
 107 #define GT_CS3LD                (0x438 >> 2)
 108 #define GT_CS3HD                (0x43c >> 2)
 109 #define GT_BOOTLD               (0x440 >> 2)
 110 #define GT_BOOTHD               (0x444 >> 2)
 111 #define GT_ADERR                (0x470 >> 2)
 112
 113 /* SDRAM Configuration */
 114 #define GT_SDRAM_CFG            (0x448 >> 2)
 115 #define GT_SDRAM_OPMODE         (0x474 >> 2)
 116 #define GT_SDRAM_BM             (0x478 >> 2)
 117 #define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
 118
 119 /* SDRAM Parameters */
 120 #define GT_SDRAM_B0             (0x44c >> 2)
 121 #define GT_SDRAM_B1             (0x450 >> 2)
 122 #define GT_SDRAM_B2             (0x454 >> 2)
 123 #define GT_SDRAM_B3             (0x458 >> 2)
 124
 125 /* Device Parameters */
 126 #define GT_DEV_B0               (0x45c >> 2)
 127 #define GT_DEV_B1               (0x460 >> 2)
 128 #define GT_DEV_B2               (0x464 >> 2)
 129 #define GT_DEV_B3               (0x468 >> 2)
 130 #define GT_DEV_BOOT             (0x46c >> 2)
 131
 132 /* ECC */
 133 #define GT_ECC_ERRDATALO        (0x480 >> 2)            /* GT-64120A only  */
 134 #define GT_ECC_ERRDATAHI        (0x484 >> 2)            /* GT-64120A only  */
 135 #define GT_ECC_MEM              (0x488 >> 2)            /* GT-64120A only  */
 136 #define GT_ECC_CALC             (0x48c >> 2)            /* GT-64120A only  */
 137 #define GT_ECC_ERRADDR          (0x490 >> 2)            /* GT-64120A only  */
 138
 139 /* DMA Record */
 140 #define GT_DMA0_CNT             (0x800 >> 2)
 141 #define GT_DMA1_CNT             (0x804 >> 2)
 142 #define GT_DMA2_CNT             (0x808 >> 2)
 143 #define GT_DMA3_CNT             (0x80c >> 2)
 144 #define GT_DMA0_SA              (0x810 >> 2)
 145 #define GT_DMA1_SA              (0x814 >> 2)
 146 #define GT_DMA2_SA              (0x818 >> 2)
 147 #define GT_DMA3_SA              (0x81c >> 2)
 148 #define GT_DMA0_DA              (0x820 >> 2)
 149 #define GT_DMA1_DA              (0x824 >> 2)
 150 #define GT_DMA2_DA              (0x828 >> 2)
 151 #define GT_DMA3_DA              (0x82c >> 2)
 152 #define GT_DMA0_NEXT            (0x830 >> 2)
 153 #define GT_DMA1_NEXT            (0x834 >> 2)
 154 #define GT_DMA2_NEXT            (0x838 >> 2)
 155 #define GT_DMA3_NEXT            (0x83c >> 2)
 156 #define GT_DMA0_CUR             (0x870 >> 2)
 157 #define GT_DMA1_CUR             (0x874 >> 2)
 158 #define GT_DMA2_CUR             (0x878 >> 2)
 159 #define GT_DMA3_CUR             (0x87c >> 2)
 160
 161 /* DMA Channel Control */
 162 #define GT_DMA0_CTRL            (0x840 >> 2)
 163 #define GT_DMA1_CTRL            (0x844 >> 2)
 164 #define GT_DMA2_CTRL            (0x848 >> 2)
 165 #define GT_DMA3_CTRL            (0x84c >> 2)
 166
 167 /* DMA Arbiter */
 168 #define GT_DMA_ARB              (0x860 >> 2)
 169
 170 /* Timer/Counter */
 171 #define GT_TC0                  (0x850 >> 2)
 172 #define GT_TC1                  (0x854 >> 2)
 173 #define GT_TC2                  (0x858 >> 2)
 174 #define GT_TC3                  (0x85c >> 2)
 175 #define GT_TC_CONTROL           (0x864 >> 2)
 176
 177 /* PCI Internal */
 178 #define GT_PCI0_CMD             (0xc00 >> 2)
 179 #define GT_PCI0_TOR             (0xc04 >> 2)
 180 #define GT_PCI0_BS_SCS10        (0xc08 >> 2)
 181 #define GT_PCI0_BS_SCS32        (0xc0c >> 2)
 182 #define GT_PCI0_BS_CS20         (0xc10 >> 2)
 183 #define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
 184 #define GT_PCI1_IACK            (0xc30 >> 2)
 185 #define GT_PCI0_IACK            (0xc34 >> 2)
 186 #define GT_PCI0_BARE            (0xc3c >> 2)
 187 #define GT_PCI0_PREFMBR         (0xc40 >> 2)
 188 #define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
 189 #define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
 190 #define GT_PCI0_CS20_BAR        (0xc50 >> 2)
 191 #define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
 192 #define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
 193 #define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
 194 #define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
 195 #define GT_PCI1_CMD             (0xc80 >> 2)
 196 #define GT_PCI1_TOR             (0xc84 >> 2)
 197 #define GT_PCI1_BS_SCS10        (0xc88 >> 2)
 198 #define GT_PCI1_BS_SCS32        (0xc8c >> 2)
 199 #define GT_PCI1_BS_CS20         (0xc90 >> 2)
 200 #define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
 201 #define GT_PCI1_BARE            (0xcbc >> 2)
 202 #define GT_PCI1_PREFMBR         (0xcc0 >> 2)
 203 #define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
 204 #define GT_PCI1_SCS32_BAR       (0xccc >> 2)
 205 #define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
 206 #define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
 207 #define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
 208 #define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
 209 #define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
 210 #define GT_PCI1_CFGADDR         (0xcf0 >> 2)
 211 #define GT_PCI1_CFGDATA         (0xcf4 >> 2)
 212 #define GT_PCI0_CFGADDR         (0xcf8 >> 2)
 213 #define GT_PCI0_CFGDATA         (0xcfc >> 2)
 214
 215 /* Interrupts */
 216 #define GT_INTRCAUSE            (0xc18 >> 2)
 217 #define GT_INTRMASK             (0xc1c >> 2)
 218 #define GT_PCI0_ICMASK          (0xc24 >> 2)
 219 #define GT_PCI0_SERR0MASK       (0xc28 >> 2)
 220 #define GT_CPU_INTSEL           (0xc70 >> 2)
 221 #define GT_PCI0_INTSEL          (0xc74 >> 2)
 222 #define GT_HINTRCAUSE           (0xc98 >> 2)
 223 #define GT_HINTRMASK            (0xc9c >> 2)
 224 #define GT_PCI0_HICMASK         (0xca4 >> 2)
 225 #define GT_PCI1_SERR1MASK       (0xca8 >> 2)
 226
 227 #define PCI_MAPPING_ENTRY(regname)            \
 228     hwaddr regname ##_start;      \
 229     hwaddr regname ##_length;     \
 230     MemoryRegion regname ##_mem
 231
 232 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
 233
 234 #define GT64120_PCI_HOST_BRIDGE(obj) \
 235     OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
 236
 237 typedef struct GT64120State {
 238     PCIHostState parent_obj;
 239
 240     uint32_t regs[GT_REGS];
 241     PCI_MAPPING_ENTRY(PCI0IO);
 242     PCI_MAPPING_ENTRY(PCI0M0);
 243     PCI_MAPPING_ENTRY(PCI0M1);
 244     PCI_MAPPING_ENTRY(ISD);
 245     MemoryRegion pci0_mem;
 246     AddressSpace pci0_mem_as;
 247 } GT64120State;
 248
 249 /* Adjust range to avoid touching space which isn't mappable via PCI */
 250 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
 251                                     0x1fc00000 - 0x1fd00000  */
 252 static void check_reserved_space (hwaddr *start,
 253                                   hwaddr *length)
 254 {
 255     hwaddr begin = *start;
 256     hwaddr end = *start + *length;
 257
 258     if (end >= 0x1e000000LL && end < 0x1f100000LL)
 259         end = 0x1e000000LL;
 260     if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
 261         begin = 0x1f100000LL;
 262     if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
 263         end = 0x1fc00000LL;
 264     if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
 265         begin = 0x1fd00000LL;
 266     /* XXX: This is broken when a reserved range splits the requested range */
 267     if (end >= 0x1f100000LL && begin < 0x1e000000LL)
 268         end = 0x1e000000LL;
 269     if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
 270         end = 0x1fc00000LL;
 271
 272     *start = begin;
 273     *length = end - begin;
 274 }
 275
 276 static void gt64120_isd_mapping(GT64120State *s)
 277 {
 278     /* Bits 14:0 of ISD map to bits 35:21 of the start address.  */
 279     hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
 280     hwaddr length = 0x1000;
 281
 282     if (s->ISD_length) {
 283         memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
 284     }
 285     check_reserved_space(&start, &length);
 286     length = 0x1000;
 287     /* Map new address */
 288     DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx
 289         " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n",
 290         s->ISD_length, s->ISD_start, length, start);
 291     s->ISD_start = start;
 292     s->ISD_length = length;
 293     memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
 294 }
 295
 296 static void gt64120_pci_mapping(GT64120State *s)
 297 {
 298     /* Update PCI0IO mapping */
 299     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
 300         /* Unmap old IO address */
 301         if (s->PCI0IO_length) {
 302             memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
 303             object_unparent(OBJECT(&s->PCI0IO_mem));
 304         }
 305         /* Map new IO address */
 306         s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
 307         s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
 308                             (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
 309         if (s->PCI0IO_length) {
 310             memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
 311                                      get_system_io(), 0, s->PCI0IO_length);
 312             memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
 313                                         &s->PCI0IO_mem);
 314         }
 315     }
 316
 317     /* Update PCI0M0 mapping */
 318     if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
 319         /* Unmap old MEM address */
 320         if (s->PCI0M0_length) {
 321             memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
 322             object_unparent(OBJECT(&s->PCI0M0_mem));
 323         }
 324         /* Map new mem address */
 325         s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
 326         s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
 327                             (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
 328         if (s->PCI0M0_length) {
 329             memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
 330                                      &s->pci0_mem, s->PCI0M0_start,
 331                                      s->PCI0M0_length);
 332             memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
 333                                         &s->PCI0M0_mem);
 334         }
 335     }
 336
 337     /* Update PCI0M1 mapping */
 338     if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
 339         /* Unmap old MEM address */
 340         if (s->PCI0M1_length) {
 341             memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
 342             object_unparent(OBJECT(&s->PCI0M1_mem));
 343         }
 344         /* Map new mem address */
 345         s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
 346         s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
 347                             (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
 348         if (s->PCI0M1_length) {
 349             memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
 350                                      &s->pci0_mem, s->PCI0M1_start,
 351                                      s->PCI0M1_length);
 352             memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
 353                                         &s->PCI0M1_mem);
 354         }
 355     }
 356 }
 357
 358 static int gt64120_post_load(void *opaque, int version_id)
 359 {
 360     GT64120State *s = opaque;
 361
 362     gt64120_isd_mapping(s);
 363     gt64120_pci_mapping(s);
 364
 365     return 0;
 366 }
 367
 368 static const VMStateDescription vmstate_gt64120 = {
 369     .name = "gt64120",
 370     .version_id = 1,
 371     .minimum_version_id = 1,
 372     .post_load = gt64120_post_load,
 373     .fields = (VMStateField[]) {
 374         VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
 375         VMSTATE_END_OF_LIST()
 376     }
 377 };
 378
 379 static void gt64120_writel (void *opaque, hwaddr addr,
 380                             uint64_t val, unsigned size)
 381 {
 382     GT64120State *s = opaque;
 383     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 384     uint32_t saddr;
 385
 386     if (!(s->regs[GT_CPU] & 0x00001000))
 387         val = bswap32(val);
 388
 389     saddr = (addr & 0xfff) >> 2;
 390     switch (saddr) {
 391
 392     /* CPU Configuration */
 393     case GT_CPU:
 394         s->regs[GT_CPU] = val;
 395         break;
 396     case GT_MULTI:
 397         /* Read-only register as only one GT64xxx is present on the CPU bus */
 398         break;
 399
 400     /* CPU Address Decode */
 401     case GT_PCI0IOLD:
 402         s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
 403         s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
 404         gt64120_pci_mapping(s);
 405         break;
 406     case GT_PCI0M0LD:
 407         s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
 408         s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
 409         gt64120_pci_mapping(s);
 410         break;
 411     case GT_PCI0M1LD:
 412         s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
 413         s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
 414         gt64120_pci_mapping(s);
 415         break;
 416     case GT_PCI1IOLD:
 417         s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
 418         s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
 419         break;
 420     case GT_PCI1M0LD:
 421         s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
 422         s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
 423         break;
 424     case GT_PCI1M1LD:
 425         s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
 426         s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
 427         break;
 428     case GT_PCI0M0HD:
 429     case GT_PCI0M1HD:
 430     case GT_PCI0IOHD:
 431         s->regs[saddr] = val & 0x0000007f;
 432         gt64120_pci_mapping(s);
 433         break;
 434     case GT_PCI1IOHD:
 435     case GT_PCI1M0HD:
 436     case GT_PCI1M1HD:
 437         s->regs[saddr] = val & 0x0000007f;
 438         break;
 439     case GT_ISD:
 440         s->regs[saddr] = val & 0x00007fff;
 441         gt64120_isd_mapping(s);
 442         break;
 443
 444     case GT_PCI0IOREMAP:
 445     case GT_PCI0M0REMAP:
 446     case GT_PCI0M1REMAP:
 447     case GT_PCI1IOREMAP:
 448     case GT_PCI1M0REMAP:
 449     case GT_PCI1M1REMAP:
 450         s->regs[saddr] = val & 0x000007ff;
 451         break;
 452
 453     /* CPU Error Report */
 454     case GT_CPUERR_ADDRLO:
 455     case GT_CPUERR_ADDRHI:
 456     case GT_CPUERR_DATALO:
 457     case GT_CPUERR_DATAHI:
 458     case GT_CPUERR_PARITY:
 459         /* Read-only registers, do nothing */
 460         break;
 461
 462     /* CPU Sync Barrier */
 463     case GT_PCI0SYNC:
 464     case GT_PCI1SYNC:
 465         /* Read-only registers, do nothing */
 466         break;
 467
 468     /* SDRAM and Device Address Decode */
 469     case GT_SCS0LD:
 470     case GT_SCS0HD:
 471     case GT_SCS1LD:
 472     case GT_SCS1HD:
 473     case GT_SCS2LD:
 474     case GT_SCS2HD:
 475     case GT_SCS3LD:
 476     case GT_SCS3HD:
 477     case GT_CS0LD:
 478     case GT_CS0HD:
 479     case GT_CS1LD:
 480     case GT_CS1HD:
 481     case GT_CS2LD:
 482     case GT_CS2HD:
 483     case GT_CS3LD:
 484     case GT_CS3HD:
 485     case GT_BOOTLD:
 486     case GT_BOOTHD:
 487     case GT_ADERR:
 488     /* SDRAM Configuration */
 489     case GT_SDRAM_CFG:
 490     case GT_SDRAM_OPMODE:
 491     case GT_SDRAM_BM:
 492     case GT_SDRAM_ADDRDECODE:
 493         /* Accept and ignore SDRAM interleave configuration */
 494         s->regs[saddr] = val;
 495         break;
 496
 497     /* Device Parameters */
 498     case GT_DEV_B0:
 499     case GT_DEV_B1:
 500     case GT_DEV_B2:
 501     case GT_DEV_B3:
 502     case GT_DEV_BOOT:
 503         /* Not implemented */
 504         DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
 505         break;
 506
 507     /* ECC */
 508     case GT_ECC_ERRDATALO:
 509     case GT_ECC_ERRDATAHI:
 510     case GT_ECC_MEM:
 511     case GT_ECC_CALC:
 512     case GT_ECC_ERRADDR:
 513         /* Read-only registers, do nothing */
 514         break;
 515
 516     /* DMA Record */
 517     case GT_DMA0_CNT:
 518     case GT_DMA1_CNT:
 519     case GT_DMA2_CNT:
 520     case GT_DMA3_CNT:
 521     case GT_DMA0_SA:
 522     case GT_DMA1_SA:
 523     case GT_DMA2_SA:
 524     case GT_DMA3_SA:
 525     case GT_DMA0_DA:
 526     case GT_DMA1_DA:
 527     case GT_DMA2_DA:
 528     case GT_DMA3_DA:
 529     case GT_DMA0_NEXT:
 530     case GT_DMA1_NEXT:
 531     case GT_DMA2_NEXT:
 532     case GT_DMA3_NEXT:
 533     case GT_DMA0_CUR:
 534     case GT_DMA1_CUR:
 535     case GT_DMA2_CUR:
 536     case GT_DMA3_CUR:
 537         /* Not implemented */
 538         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 539         break;
 540
 541     /* DMA Channel Control */
 542     case GT_DMA0_CTRL:
 543     case GT_DMA1_CTRL:
 544     case GT_DMA2_CTRL:
 545     case GT_DMA3_CTRL:
 546         /* Not implemented */
 547         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 548         break;
 549
 550     /* DMA Arbiter */
 551     case GT_DMA_ARB:
 552         /* Not implemented */
 553         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 554         break;
 555
 556     /* Timer/Counter */
 557     case GT_TC0:
 558     case GT_TC1:
 559     case GT_TC2:
 560     case GT_TC3:
 561     case GT_TC_CONTROL:
 562         /* Not implemented */
 563         DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
 564         break;
 565
 566     /* PCI Internal */
 567     case GT_PCI0_CMD:
 568     case GT_PCI1_CMD:
 569         s->regs[saddr] = val & 0x0401fc0f;
 570         break;
 571     case GT_PCI0_TOR:
 572     case GT_PCI0_BS_SCS10:
 573     case GT_PCI0_BS_SCS32:
 574     case GT_PCI0_BS_CS20:
 575     case GT_PCI0_BS_CS3BT:
 576     case GT_PCI1_IACK:
 577     case GT_PCI0_IACK:
 578     case GT_PCI0_BARE:
 579     case GT_PCI0_PREFMBR:
 580     case GT_PCI0_SCS10_BAR:
 581     case GT_PCI0_SCS32_BAR:
 582     case GT_PCI0_CS20_BAR:
 583     case GT_PCI0_CS3BT_BAR:
 584     case GT_PCI0_SSCS10_BAR:
 585     case GT_PCI0_SSCS32_BAR:
 586     case GT_PCI0_SCS3BT_BAR:
 587     case GT_PCI1_TOR:
 588     case GT_PCI1_BS_SCS10:
 589     case GT_PCI1_BS_SCS32:
 590     case GT_PCI1_BS_CS20:
 591     case GT_PCI1_BS_CS3BT:
 592     case GT_PCI1_BARE:
 593     case GT_PCI1_PREFMBR:
 594     case GT_PCI1_SCS10_BAR:
 595     case GT_PCI1_SCS32_BAR:
 596     case GT_PCI1_CS20_BAR:
 597     case GT_PCI1_CS3BT_BAR:
 598     case GT_PCI1_SSCS10_BAR:
 599     case GT_PCI1_SSCS32_BAR:
 600     case GT_PCI1_SCS3BT_BAR:
 601     case GT_PCI1_CFGADDR:
 602     case GT_PCI1_CFGDATA:
 603         /* not implemented */
 604         break;
 605     case GT_PCI0_CFGADDR:
 606         phb->config_reg = val & 0x80fffffc;
 607         break;
 608     case GT_PCI0_CFGDATA:
 609         if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
 610             val = bswap32(val);
 611         }
 612         if (phb->config_reg & (1u << 31)) {
 613             pci_data_write(phb->bus, phb->config_reg, val, 4);
 614         }
 615         break;
 616
 617     /* Interrupts */
 618     case GT_INTRCAUSE:
 619         /* not really implemented */
 620         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
 621         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
 622         DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
 623         break;
 624     case GT_INTRMASK:
 625         s->regs[saddr] = val & 0x3c3ffffe;
 626         DPRINTF("INTRMASK %" PRIx64 "\n", val);
 627         break;
 628     case GT_PCI0_ICMASK:
 629         s->regs[saddr] = val & 0x03fffffe;
 630         DPRINTF("ICMASK %" PRIx64 "\n", val);
 631         break;
 632     case GT_PCI0_SERR0MASK:
 633         s->regs[saddr] = val & 0x0000003f;
 634         DPRINTF("SERR0MASK %" PRIx64 "\n", val);
 635         break;
 636
 637     /* Reserved when only PCI_0 is configured. */
 638     case GT_HINTRCAUSE:
 639     case GT_CPU_INTSEL:
 640     case GT_PCI0_INTSEL:
 641     case GT_HINTRMASK:
 642     case GT_PCI0_HICMASK:
 643     case GT_PCI1_SERR1MASK:
 644         /* not implemented */
 645         break;
 646
 647     /* SDRAM Parameters */
 648     case GT_SDRAM_B0:
 649     case GT_SDRAM_B1:
 650     case GT_SDRAM_B2:
 651     case GT_SDRAM_B3:
 652         /* We don't simulate electrical parameters of the SDRAM.
 653            Accept, but ignore the values. */
 654         s->regs[saddr] = val;
 655         break;
 656
 657     default:
 658         DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 659         break;
 660     }
 661 }
 662
 663 static uint64_t gt64120_readl (void *opaque,
 664                                hwaddr addr, unsigned size)
 665 {
 666     GT64120State *s = opaque;
 667     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 668     uint32_t val;
 669     uint32_t saddr;
 670
 671     saddr = (addr & 0xfff) >> 2;
 672     switch (saddr) {
 673
 674     /* CPU Configuration */
 675     case GT_MULTI:
 676         /* Only one GT64xxx is present on the CPU bus, return
 677            the initial value */
 678         val = s->regs[saddr];
 679         break;
 680
 681     /* CPU Error Report */
 682     case GT_CPUERR_ADDRLO:
 683     case GT_CPUERR_ADDRHI:
 684     case GT_CPUERR_DATALO:
 685     case GT_CPUERR_DATAHI:
 686     case GT_CPUERR_PARITY:
 687         /* Emulated memory has no error, always return the initial
 688            values */
 689         val = s->regs[saddr];
 690         break;
 691
 692     /* CPU Sync Barrier */
 693     case GT_PCI0SYNC:
 694     case GT_PCI1SYNC:
 695         /* Reading those register should empty all FIFO on the PCI
 696            bus, which are not emulated. The return value should be
 697            a random value that should be ignored. */
 698         val = 0xc000ffee;
 699         break;
 700
 701     /* ECC */
 702     case GT_ECC_ERRDATALO:
 703     case GT_ECC_ERRDATAHI:
 704     case GT_ECC_MEM:
 705     case GT_ECC_CALC:
 706     case GT_ECC_ERRADDR:
 707         /* Emulated memory has no error, always return the initial
 708            values */
 709         val = s->regs[saddr];
 710         break;
 711
 712     case GT_CPU:
 713     case GT_SCS10LD:
 714     case GT_SCS10HD:
 715     case GT_SCS32LD:
 716     case GT_SCS32HD:
 717     case GT_CS20LD:
 718     case GT_CS20HD:
 719     case GT_CS3BOOTLD:
 720     case GT_CS3BOOTHD:
 721     case GT_SCS10AR:
 722     case GT_SCS32AR:
 723     case GT_CS20R:
 724     case GT_CS3BOOTR:
 725     case GT_PCI0IOLD:
 726     case GT_PCI0M0LD:
 727     case GT_PCI0M1LD:
 728     case GT_PCI1IOLD:
 729     case GT_PCI1M0LD:
 730     case GT_PCI1M1LD:
 731     case GT_PCI0IOHD:
 732     case GT_PCI0M0HD:
 733     case GT_PCI0M1HD:
 734     case GT_PCI1IOHD:
 735     case GT_PCI1M0HD:
 736     case GT_PCI1M1HD:
 737     case GT_PCI0IOREMAP:
 738     case GT_PCI0M0REMAP:
 739     case GT_PCI0M1REMAP:
 740     case GT_PCI1IOREMAP:
 741     case GT_PCI1M0REMAP:
 742     case GT_PCI1M1REMAP:
 743     case GT_ISD:
 744         val = s->regs[saddr];
 745         break;
 746     case GT_PCI0_IACK:
 747         /* Read the IRQ number */
 748         val = pic_read_irq(isa_pic);
 749         break;
 750
 751     /* SDRAM and Device Address Decode */
 752     case GT_SCS0LD:
 753     case GT_SCS0HD:
 754     case GT_SCS1LD:
 755     case GT_SCS1HD:
 756     case GT_SCS2LD:
 757     case GT_SCS2HD:
 758     case GT_SCS3LD:
 759     case GT_SCS3HD:
 760     case GT_CS0LD:
 761     case GT_CS0HD:
 762     case GT_CS1LD:
 763     case GT_CS1HD:
 764     case GT_CS2LD:
 765     case GT_CS2HD:
 766     case GT_CS3LD:
 767     case GT_CS3HD:
 768     case GT_BOOTLD:
 769     case GT_BOOTHD:
 770     case GT_ADERR:
 771         val = s->regs[saddr];
 772         break;
 773
 774     /* SDRAM Configuration */
 775     case GT_SDRAM_CFG:
 776     case GT_SDRAM_OPMODE:
 777     case GT_SDRAM_BM:
 778     case GT_SDRAM_ADDRDECODE:
 779         val = s->regs[saddr];
 780         break;
 781
 782     /* SDRAM Parameters */
 783     case GT_SDRAM_B0:
 784     case GT_SDRAM_B1:
 785     case GT_SDRAM_B2:
 786     case GT_SDRAM_B3:
 787         /* We don't simulate electrical parameters of the SDRAM.
 788            Just return the last written value. */
 789         val = s->regs[saddr];
 790         break;
 791
 792     /* Device Parameters */
 793     case GT_DEV_B0:
 794     case GT_DEV_B1:
 795     case GT_DEV_B2:
 796     case GT_DEV_B3:
 797     case GT_DEV_BOOT:
 798         val = s->regs[saddr];
 799         break;
 800
 801     /* DMA Record */
 802     case GT_DMA0_CNT:
 803     case GT_DMA1_CNT:
 804     case GT_DMA2_CNT:
 805     case GT_DMA3_CNT:
 806     case GT_DMA0_SA:
 807     case GT_DMA1_SA:
 808     case GT_DMA2_SA:
 809     case GT_DMA3_SA:
 810     case GT_DMA0_DA:
 811     case GT_DMA1_DA:
 812     case GT_DMA2_DA:
 813     case GT_DMA3_DA:
 814     case GT_DMA0_NEXT:
 815     case GT_DMA1_NEXT:
 816     case GT_DMA2_NEXT:
 817     case GT_DMA3_NEXT:
 818     case GT_DMA0_CUR:
 819     case GT_DMA1_CUR:
 820     case GT_DMA2_CUR:
 821     case GT_DMA3_CUR:
 822         val = s->regs[saddr];
 823         break;
 824
 825     /* DMA Channel Control */
 826     case GT_DMA0_CTRL:
 827     case GT_DMA1_CTRL:
 828     case GT_DMA2_CTRL:
 829     case GT_DMA3_CTRL:
 830         val = s->regs[saddr];
 831         break;
 832
 833     /* DMA Arbiter */
 834     case GT_DMA_ARB:
 835         val = s->regs[saddr];
 836         break;
 837
 838     /* Timer/Counter */
 839     case GT_TC0:
 840     case GT_TC1:
 841     case GT_TC2:
 842     case GT_TC3:
 843     case GT_TC_CONTROL:
 844         val = s->regs[saddr];
 845         break;
 846
 847     /* PCI Internal */
 848     case GT_PCI0_CFGADDR:
 849         val = phb->config_reg;
 850         break;
 851     case GT_PCI0_CFGDATA:
 852         if (!(phb->config_reg & (1 << 31))) {
 853             val = 0xffffffff;
 854         } else {
 855             val = pci_data_read(phb->bus, phb->config_reg, 4);
 856         }
 857         if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
 858             val = bswap32(val);
 859         }
 860         break;
 861
 862     case GT_PCI0_CMD:
 863     case GT_PCI0_TOR:
 864     case GT_PCI0_BS_SCS10:
 865     case GT_PCI0_BS_SCS32:
 866     case GT_PCI0_BS_CS20:
 867     case GT_PCI0_BS_CS3BT:
 868     case GT_PCI1_IACK:
 869     case GT_PCI0_BARE:
 870     case GT_PCI0_PREFMBR:
 871     case GT_PCI0_SCS10_BAR:
 872     case GT_PCI0_SCS32_BAR:
 873     case GT_PCI0_CS20_BAR:
 874     case GT_PCI0_CS3BT_BAR:
 875     case GT_PCI0_SSCS10_BAR:
 876     case GT_PCI0_SSCS32_BAR:
 877     case GT_PCI0_SCS3BT_BAR:
 878     case GT_PCI1_CMD:
 879     case GT_PCI1_TOR:
 880     case GT_PCI1_BS_SCS10:
 881     case GT_PCI1_BS_SCS32:
 882     case GT_PCI1_BS_CS20:
 883     case GT_PCI1_BS_CS3BT:
 884     case GT_PCI1_BARE:
 885     case GT_PCI1_PREFMBR:
 886     case GT_PCI1_SCS10_BAR:
 887     case GT_PCI1_SCS32_BAR:
 888     case GT_PCI1_CS20_BAR:
 889     case GT_PCI1_CS3BT_BAR:
 890     case GT_PCI1_SSCS10_BAR:
 891     case GT_PCI1_SSCS32_BAR:
 892     case GT_PCI1_SCS3BT_BAR:
 893     case GT_PCI1_CFGADDR:
 894     case GT_PCI1_CFGDATA:
 895         val = s->regs[saddr];
 896         break;
 897
 898     /* Interrupts */
 899     case GT_INTRCAUSE:
 900         val = s->regs[saddr];
 901         DPRINTF("INTRCAUSE %x\n", val);
 902         break;
 903     case GT_INTRMASK:
 904         val = s->regs[saddr];
 905         DPRINTF("INTRMASK %x\n", val);
 906         break;
 907     case GT_PCI0_ICMASK:
 908         val = s->regs[saddr];
 909         DPRINTF("ICMASK %x\n", val);
 910         break;
 911     case GT_PCI0_SERR0MASK:
 912         val = s->regs[saddr];
 913         DPRINTF("SERR0MASK %x\n", val);
 914         break;
 915
 916     /* Reserved when only PCI_0 is configured. */
 917     case GT_HINTRCAUSE:
 918     case GT_CPU_INTSEL:
 919     case GT_PCI0_INTSEL:
 920     case GT_HINTRMASK:
 921     case GT_PCI0_HICMASK:
 922     case GT_PCI1_SERR1MASK:
 923         val = s->regs[saddr];
 924         break;
 925
 926     default:
 927         val = s->regs[saddr];
 928         DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 929         break;
 930     }
 931
 932     if (!(s->regs[GT_CPU] & 0x00001000))
 933         val = bswap32(val);
 934
 935     return val;
 936 }
 937
 938 static const MemoryRegionOps isd_mem_ops = {
 939     .read = gt64120_readl,
 940     .write = gt64120_writel,
 941     .endianness = DEVICE_NATIVE_ENDIAN,
 942 };
 943
 944 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 945 {
 946     int slot;
 947
 948     slot = (pci_dev->devfn >> 3);
 949
 950     switch (slot) {
 951       /* PIIX4 USB */
 952       case 10:
 953         return 3;
 954       /* AMD 79C973 Ethernet */
 955       case 11:
 956         return 1;
 957       /* Crystal 4281 Sound */
 958       case 12:
 959         return 2;
 960       /* PCI slot 1 to 4 */
 961       case 18 ... 21:
 962         return ((slot - 18) + irq_num) & 0x03;
 963       /* Unknown device, don't do any translation */
 964       default:
 965         return irq_num;
 966     }
 967 }
 968
 969 static int pci_irq_levels[4];
 970
 971 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
 972 {
 973     int i, pic_irq, pic_level;
 974     qemu_irq *pic = opaque;
 975
 976     pci_irq_levels[irq_num] = level;
 977
 978     /* now we change the pic irq level according to the piix irq mappings */
 979     /* XXX: optimize */
 980     pic_irq = piix4_dev->config[0x60 + irq_num];
 981     if (pic_irq < 16) {
 982         /* The pic level is the logical OR of all the PCI irqs mapped
 983            to it */
 984         pic_level = 0;
 985         for (i = 0; i < 4; i++) {
 986             if (pic_irq == piix4_dev->config[0x60 + i])
 987                 pic_level |= pci_irq_levels[i];
 988         }
 989         qemu_set_irq(pic[pic_irq], pic_level);
 990     }
 991 }
 992
 993
 994 static void gt64120_reset(void *opaque)
 995 {
 996     GT64120State *s = opaque;
 997
 998     /* FIXME: Malta specific hw assumptions ahead */
 999
1000     /* CPU Configuration */
1001 #ifdef TARGET_WORDS_BIGENDIAN
1002     s->regs[GT_CPU]           = 0x00000000;
1003 #else
1004     s->regs[GT_CPU]           = 0x00001000;
1005 #endif
1006     s->regs[GT_MULTI]         = 0x00000003;
1007
1008     /* CPU Address decode */
1009     s->regs[GT_SCS10LD]       = 0x00000000;
1010     s->regs[GT_SCS10HD]       = 0x00000007;
1011     s->regs[GT_SCS32LD]       = 0x00000008;
1012     s->regs[GT_SCS32HD]       = 0x0000000f;
1013     s->regs[GT_CS20LD]        = 0x000000e0;
1014     s->regs[GT_CS20HD]        = 0x00000070;
1015     s->regs[GT_CS3BOOTLD]     = 0x000000f8;
1016     s->regs[GT_CS3BOOTHD]     = 0x0000007f;
1017
1018     s->regs[GT_PCI0IOLD]      = 0x00000080;
1019     s->regs[GT_PCI0IOHD]      = 0x0000000f;
1020     s->regs[GT_PCI0M0LD]      = 0x00000090;
1021     s->regs[GT_PCI0M0HD]      = 0x0000001f;
1022     s->regs[GT_ISD]           = 0x000000a0;
1023     s->regs[GT_PCI0M1LD]      = 0x00000790;
1024     s->regs[GT_PCI0M1HD]      = 0x0000001f;
1025     s->regs[GT_PCI1IOLD]      = 0x00000100;
1026     s->regs[GT_PCI1IOHD]      = 0x0000000f;
1027     s->regs[GT_PCI1M0LD]      = 0x00000110;
1028     s->regs[GT_PCI1M0HD]      = 0x0000001f;
1029     s->regs[GT_PCI1M1LD]      = 0x00000120;
1030     s->regs[GT_PCI1M1HD]      = 0x0000002f;
1031
1032     s->regs[GT_SCS10AR]       = 0x00000000;
1033     s->regs[GT_SCS32AR]       = 0x00000008;
1034     s->regs[GT_CS20R]         = 0x000000e0;
1035     s->regs[GT_CS3BOOTR]      = 0x000000f8;
1036
1037     s->regs[GT_PCI0IOREMAP]   = 0x00000080;
1038     s->regs[GT_PCI0M0REMAP]   = 0x00000090;
1039     s->regs[GT_PCI0M1REMAP]   = 0x00000790;
1040     s->regs[GT_PCI1IOREMAP]   = 0x00000100;
1041     s->regs[GT_PCI1M0REMAP]   = 0x00000110;
1042     s->regs[GT_PCI1M1REMAP]   = 0x00000120;
1043
1044     /* CPU Error Report */
1045     s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1046     s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1047     s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1048     s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1049     s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1050
1051     /* CPU Sync Barrier */
1052     s->regs[GT_PCI0SYNC]      = 0x00000000;
1053     s->regs[GT_PCI1SYNC]      = 0x00000000;
1054
1055     /* SDRAM and Device Address Decode */
1056     s->regs[GT_SCS0LD]        = 0x00000000;
1057     s->regs[GT_SCS0HD]        = 0x00000007;
1058     s->regs[GT_SCS1LD]        = 0x00000008;
1059     s->regs[GT_SCS1HD]        = 0x0000000f;
1060     s->regs[GT_SCS2LD]        = 0x00000010;
1061     s->regs[GT_SCS2HD]        = 0x00000017;
1062     s->regs[GT_SCS3LD]        = 0x00000018;
1063     s->regs[GT_SCS3HD]        = 0x0000001f;
1064     s->regs[GT_CS0LD]         = 0x000000c0;
1065     s->regs[GT_CS0HD]         = 0x000000c7;
1066     s->regs[GT_CS1LD]         = 0x000000c8;
1067     s->regs[GT_CS1HD]         = 0x000000cf;
1068     s->regs[GT_CS2LD]         = 0x000000d0;
1069     s->regs[GT_CS2HD]         = 0x000000df;
1070     s->regs[GT_CS3LD]         = 0x000000f0;
1071     s->regs[GT_CS3HD]         = 0x000000fb;
1072     s->regs[GT_BOOTLD]        = 0x000000fc;
1073     s->regs[GT_BOOTHD]        = 0x000000ff;
1074     s->regs[GT_ADERR]         = 0xffffffff;
1075
1076     /* SDRAM Configuration */
1077     s->regs[GT_SDRAM_CFG]     = 0x00000200;
1078     s->regs[GT_SDRAM_OPMODE]  = 0x00000000;
1079     s->regs[GT_SDRAM_BM]      = 0x00000007;
1080     s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1081
1082     /* SDRAM Parameters */
1083     s->regs[GT_SDRAM_B0]      = 0x00000005;
1084     s->regs[GT_SDRAM_B1]      = 0x00000005;
1085     s->regs[GT_SDRAM_B2]      = 0x00000005;
1086     s->regs[GT_SDRAM_B3]      = 0x00000005;
1087
1088     /* ECC */
1089     s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1090     s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1091     s->regs[GT_ECC_MEM]       = 0x00000000;
1092     s->regs[GT_ECC_CALC]      = 0x00000000;
1093     s->regs[GT_ECC_ERRADDR]   = 0x00000000;
1094
1095     /* Device Parameters */
1096     s->regs[GT_DEV_B0]        = 0x386fffff;
1097     s->regs[GT_DEV_B1]        = 0x386fffff;
1098     s->regs[GT_DEV_B2]        = 0x386fffff;
1099     s->regs[GT_DEV_B3]        = 0x386fffff;
1100     s->regs[GT_DEV_BOOT]      = 0x146fffff;
1101
1102     /* DMA registers are all zeroed at reset */
1103
1104     /* Timer/Counter */
1105     s->regs[GT_TC0]           = 0xffffffff;
1106     s->regs[GT_TC1]           = 0x00ffffff;
1107     s->regs[GT_TC2]           = 0x00ffffff;
1108     s->regs[GT_TC3]           = 0x00ffffff;
1109     s->regs[GT_TC_CONTROL]    = 0x00000000;
1110
1111     /* PCI Internal */
1112 #ifdef TARGET_WORDS_BIGENDIAN
1113     s->regs[GT_PCI0_CMD]      = 0x00000000;
1114 #else
1115     s->regs[GT_PCI0_CMD]      = 0x00010001;
1116 #endif
1117     s->regs[GT_PCI0_TOR]      = 0x0000070f;
1118     s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1119     s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1120     s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;
1121     s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1122     s->regs[GT_PCI1_IACK]     = 0x00000000;
1123     s->regs[GT_PCI0_IACK]     = 0x00000000;
1124     s->regs[GT_PCI0_BARE]     = 0x0000000f;
1125     s->regs[GT_PCI0_PREFMBR]  = 0x00000040;
1126     s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1127     s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1128     s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1129     s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1130     s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1131     s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1132     s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1133 #ifdef TARGET_WORDS_BIGENDIAN
1134     s->regs[GT_PCI1_CMD]      = 0x00000000;
1135 #else
1136     s->regs[GT_PCI1_CMD]      = 0x00010001;
1137 #endif
1138     s->regs[GT_PCI1_TOR]      = 0x0000070f;
1139     s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1140     s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1141     s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;
1142     s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1143     s->regs[GT_PCI1_BARE]     = 0x0000000f;
1144     s->regs[GT_PCI1_PREFMBR]  = 0x00000040;
1145     s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1146     s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1147     s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1148     s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1149     s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1150     s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1151     s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1152     s->regs[GT_PCI1_CFGADDR]  = 0x00000000;
1153     s->regs[GT_PCI1_CFGDATA]  = 0x00000000;
1154     s->regs[GT_PCI0_CFGADDR]  = 0x00000000;
1155
1156     /* Interrupt registers are all zeroed at reset */
1157
1158     gt64120_isd_mapping(s);
1159     gt64120_pci_mapping(s);
1160 }
1161
1162 PCIBus *gt64120_register(qemu_irq *pic)
1163 {
1164     GT64120State *d;
1165     PCIHostState *phb;
1166     DeviceState *dev;
1167
1168     dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
1169     qdev_init_nofail(dev);
1170     d = GT64120_PCI_HOST_BRIDGE(dev);
1171     phb = PCI_HOST_BRIDGE(dev);
1172     memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX);
1173     address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
1174     phb->bus = pci_register_bus(dev, "pci",
1175                                 gt64120_pci_set_irq, gt64120_pci_map_irq,
1176                                 pic,
1177                                 &d->pci0_mem,
1178                                 get_system_io(),
1179                                 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1180     memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);
1181
1182     pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1183     return phb->bus;
1184 }
1185
1186 static int gt64120_init(SysBusDevice *dev)
1187 {
1188     GT64120State *s;
1189
1190     s = GT64120_PCI_HOST_BRIDGE(dev);
1191
1192     qemu_register_reset(gt64120_reset, s);
1193     return 0;
1194 }
1195
1196 static int gt64120_pci_init(PCIDevice *d)
1197 {
1198     /* FIXME: Malta specific hw assumptions ahead */
1199     pci_set_word(d->config + PCI_COMMAND, 0);
1200     pci_set_word(d->config + PCI_STATUS,
1201                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1202     pci_config_set_prog_interface(d->config, 0);
1203     pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1204     pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1205     pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1206     pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1207     pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1208     pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1209     pci_set_byte(d->config + 0x3d, 0x01);
1210
1211     return 0;
1212 }
1213
1214 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1215 {
1216     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1217     DeviceClass *dc = DEVICE_CLASS(klass);
1218
1219     k->init = gt64120_pci_init;
1220     k->vendor_id = PCI_VENDOR_ID_MARVELL;
1221     k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1222     k->revision = 0x10;
1223     k->class_id = PCI_CLASS_BRIDGE_HOST;
1224     /*
1225      * PCI-facing part of the host bridge, not usable without the
1226      * host-facing part, which can't be device_add'ed, yet.
1227      */
1228     dc->cannot_instantiate_with_device_add_yet = true;
1229 }
1230
1231 static const TypeInfo gt64120_pci_info = {
1232     .name          = "gt64120_pci",
1233     .parent        = TYPE_PCI_DEVICE,
1234     .instance_size = sizeof(PCIDevice),
1235     .class_init    = gt64120_pci_class_init,
1236 };
1237
1238 static void gt64120_class_init(ObjectClass *klass, void *data)
1239 {
1240     DeviceClass *dc = DEVICE_CLASS(klass);
1241     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1242
1243     sdc->init = gt64120_init;
1244     dc->vmsd = &vmstate_gt64120;
1245 }
1246
1247 static const TypeInfo gt64120_info = {
1248     .name          = TYPE_GT64120_PCI_HOST_BRIDGE,
1249     .parent        = TYPE_PCI_HOST_BRIDGE,
1250     .instance_size = sizeof(GT64120State),
1251     .class_init    = gt64120_class_init,
1252 };
1253
1254 static void gt64120_pci_register_types(void)
1255 {
1256     type_register_static(&gt64120_info);
1257     type_register_static(&gt64120_pci_info);
1258 }
1259
1260 type_init(gt64120_pci_register_types)