hw/display/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU LGPL
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "ui/console.h"
  12 #include "framebuffer.h"
  13 #include "ui/pixel_ops.h"
  14
  15 #define PL110_CR_EN   0x001
  16 #define PL110_CR_BGR  0x100
  17 #define PL110_CR_BEBO 0x200
  18 #define PL110_CR_BEPO 0x400
  19 #define PL110_CR_PWR  0x800
  20
  21 enum pl110_bppmode
  22 {
  23     BPP_1,
  24     BPP_2,
  25     BPP_4,
  26     BPP_8,
  27     BPP_16,
  28     BPP_32,
  29     BPP_16_565, /* PL111 only */
  30     BPP_12      /* PL111 only */
  31 };
  32
  33
  34 /* The Versatile/PB uses a slightly modified PL110 controller.  */
  35 enum pl110_version
  36 {
  37     PL110,
  38     PL110_VERSATILE,
  39     PL111
  40 };
  41
  42 #define TYPE_PL110 "pl110"
  43 #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
  44
  45 typedef struct PL110State {
  46     SysBusDevice parent_obj;
  47
  48     MemoryRegion iomem;
  49     MemoryRegionSection fbsection;
  50     QemuConsole *con;
  51
  52     int version;
  53     uint32_t timing[4];
  54     uint32_t cr;
  55     uint32_t upbase;
  56     uint32_t lpbase;
  57     uint32_t int_status;
  58     uint32_t int_mask;
  59     int cols;
  60     int rows;
  61     enum pl110_bppmode bpp;
  62     int invalidate;
  63     uint32_t mux_ctrl;
  64     uint32_t palette[256];
  65     uint32_t raw_palette[128];
  66     qemu_irq irq;
  67 } PL110State;
  68
  69 static int vmstate_pl110_post_load(void *opaque, int version_id);
  70
  71 static const VMStateDescription vmstate_pl110 = {
  72     .name = "pl110",
  73     .version_id = 2,
  74     .minimum_version_id = 1,
  75     .post_load = vmstate_pl110_post_load,
  76     .fields = (VMStateField[]) {
  77         VMSTATE_INT32(version, PL110State),
  78         VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
  79         VMSTATE_UINT32(cr, PL110State),
  80         VMSTATE_UINT32(upbase, PL110State),
  81         VMSTATE_UINT32(lpbase, PL110State),
  82         VMSTATE_UINT32(int_status, PL110State),
  83         VMSTATE_UINT32(int_mask, PL110State),
  84         VMSTATE_INT32(cols, PL110State),
  85         VMSTATE_INT32(rows, PL110State),
  86         VMSTATE_UINT32(bpp, PL110State),
  87         VMSTATE_INT32(invalidate, PL110State),
  88         VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
  89         VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
  90         VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
  91         VMSTATE_END_OF_LIST()
  92     }
  93 };
  94
  95 static const unsigned char pl110_id[] =
  96 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  97
  98 static const unsigned char pl111_id[] = {
  99     0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
 100 };
 101
 102
 103 /* Indexed by pl110_version */
 104 static const unsigned char *idregs[] = {
 105     pl110_id,
 106     /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
 107      * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
 108      * itself has the same ID values as a stock PL110, and guests (in
 109      * particular Linux) rely on this. We emulate what the hardware does,
 110      * rather than what the docs claim it ought to do.
 111      */
 112     pl110_id,
 113     pl111_id
 114 };
 115
 116 #define BITS 8
 117 #include "pl110_template.h"
 118 #define BITS 15
 119 #include "pl110_template.h"
 120 #define BITS 16
 121 #include "pl110_template.h"
 122 #define BITS 24
 123 #include "pl110_template.h"
 124 #define BITS 32
 125 #include "pl110_template.h"
 126
 127 static int pl110_enabled(PL110State *s)
 128 {
 129   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 130 }
 131
 132 static void pl110_update_display(void *opaque)
 133 {
 134     PL110State *s = (PL110State *)opaque;
 135     SysBusDevice *sbd;
 136     DisplaySurface *surface = qemu_console_surface(s->con);
 137     drawfn* fntable;
 138     drawfn fn;
 139     int dest_width;
 140     int src_width;
 141     int bpp_offset;
 142     int first;
 143     int last;
 144
 145     if (!pl110_enabled(s)) {
 146         return;
 147     }
 148
 149     sbd = SYS_BUS_DEVICE(s);
 150
 151     switch (surface_bits_per_pixel(surface)) {
 152     case 0:
 153         return;
 154     case 8:
 155         fntable = pl110_draw_fn_8;
 156         dest_width = 1;
 157         break;
 158     case 15:
 159         fntable = pl110_draw_fn_15;
 160         dest_width = 2;
 161         break;
 162     case 16:
 163         fntable = pl110_draw_fn_16;
 164         dest_width = 2;
 165         break;
 166     case 24:
 167         fntable = pl110_draw_fn_24;
 168         dest_width = 3;
 169         break;
 170     case 32:
 171         fntable = pl110_draw_fn_32;
 172         dest_width = 4;
 173         break;
 174     default:
 175         fprintf(stderr, "pl110: Bad color depth\n");
 176         exit(1);
 177     }
 178     if (s->cr & PL110_CR_BGR)
 179         bpp_offset = 0;
 180     else
 181         bpp_offset = 24;
 182
 183     if ((s->version != PL111) && (s->bpp == BPP_16)) {
 184         /* The PL110's native 16 bit mode is 5551; however
 185          * most boards with a PL110 implement an external
 186          * mux which allows bits to be reshuffled to give
 187          * 565 format. The mux is typically controlled by
 188          * an external system register.
 189          * This is controlled by a GPIO input pin
 190          * so boards can wire it up to their register.
 191          *
 192          * The PL111 straightforwardly implements both
 193          * 5551 and 565 under control of the bpp field
 194          * in the LCDControl register.
 195          */
 196         switch (s->mux_ctrl) {
 197         case 3: /* 565 BGR */
 198             bpp_offset = (BPP_16_565 - BPP_16);
 199             break;
 200         case 1: /* 5551 */
 201             break;
 202         case 0: /* 888; also if we have loaded vmstate from an old version */
 203         case 2: /* 565 RGB */
 204         default:
 205             /* treat as 565 but honour BGR bit */
 206             bpp_offset += (BPP_16_565 - BPP_16);
 207             break;
 208         }
 209     }
 210
 211     if (s->cr & PL110_CR_BEBO)
 212         fn = fntable[s->bpp + 8 + bpp_offset];
 213     else if (s->cr & PL110_CR_BEPO)
 214         fn = fntable[s->bpp + 16 + bpp_offset];
 215     else
 216         fn = fntable[s->bpp + bpp_offset];
 217
 218     src_width = s->cols;
 219     switch (s->bpp) {
 220     case BPP_1:
 221         src_width >>= 3;
 222         break;
 223     case BPP_2:
 224         src_width >>= 2;
 225         break;
 226     case BPP_4:
 227         src_width >>= 1;
 228         break;
 229     case BPP_8:
 230         break;
 231     case BPP_16:
 232     case BPP_16_565:
 233     case BPP_12:
 234         src_width <<= 1;
 235         break;
 236     case BPP_32:
 237         src_width <<= 2;
 238         break;
 239     }
 240     dest_width *= s->cols;
 241     first = 0;
 242     if (s->invalidate) {
 243         framebuffer_update_memory_section(&s->fbsection,
 244                                           sysbus_address_space(sbd),
 245                                           s->upbase,
 246                                           s->rows, src_width);
 247     }
 248
 249     framebuffer_update_display(surface, &s->fbsection,
 250                                s->cols, s->rows,
 251                                src_width, dest_width, 0,
 252                                s->invalidate,
 253                                fn, s->palette,
 254                                &first, &last);
 255
 256     if (first >= 0) {
 257         dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
 258     }
 259     s->invalidate = 0;
 260 }
 261
 262 static void pl110_invalidate_display(void * opaque)
 263 {
 264     PL110State *s = (PL110State *)opaque;
 265     s->invalidate = 1;
 266     if (pl110_enabled(s)) {
 267         qemu_console_resize(s->con, s->cols, s->rows);
 268     }
 269 }
 270
 271 static void pl110_update_palette(PL110State *s, int n)
 272 {
 273     DisplaySurface *surface = qemu_console_surface(s->con);
 274     int i;
 275     uint32_t raw;
 276     unsigned int r, g, b;
 277
 278     raw = s->raw_palette[n];
 279     n <<= 1;
 280     for (i = 0; i < 2; i++) {
 281         r = (raw & 0x1f) << 3;
 282         raw >>= 5;
 283         g = (raw & 0x1f) << 3;
 284         raw >>= 5;
 285         b = (raw & 0x1f) << 3;
 286         /* The I bit is ignored.  */
 287         raw >>= 6;
 288         switch (surface_bits_per_pixel(surface)) {
 289         case 8:
 290             s->palette[n] = rgb_to_pixel8(r, g, b);
 291             break;
 292         case 15:
 293             s->palette[n] = rgb_to_pixel15(r, g, b);
 294             break;
 295         case 16:
 296             s->palette[n] = rgb_to_pixel16(r, g, b);
 297             break;
 298         case 24:
 299         case 32:
 300             s->palette[n] = rgb_to_pixel32(r, g, b);
 301             break;
 302         }
 303         n++;
 304     }
 305 }
 306
 307 static void pl110_resize(PL110State *s, int width, int height)
 308 {
 309     if (width != s->cols || height != s->rows) {
 310         if (pl110_enabled(s)) {
 311             qemu_console_resize(s->con, width, height);
 312         }
 313     }
 314     s->cols = width;
 315     s->rows = height;
 316 }
 317
 318 /* Update interrupts.  */
 319 static void pl110_update(PL110State *s)
 320 {
 321   /* TODO: Implement interrupts.  */
 322 }
 323
 324 static uint64_t pl110_read(void *opaque, hwaddr offset,
 325                            unsigned size)
 326 {
 327     PL110State *s = (PL110State *)opaque;
 328
 329     if (offset >= 0xfe0 && offset < 0x1000) {
 330         return idregs[s->version][(offset - 0xfe0) >> 2];
 331     }
 332     if (offset >= 0x200 && offset < 0x400) {
 333         return s->raw_palette[(offset - 0x200) >> 2];
 334     }
 335     switch (offset >> 2) {
 336     case 0: /* LCDTiming0 */
 337         return s->timing[0];
 338     case 1: /* LCDTiming1 */
 339         return s->timing[1];
 340     case 2: /* LCDTiming2 */
 341         return s->timing[2];
 342     case 3: /* LCDTiming3 */
 343         return s->timing[3];
 344     case 4: /* LCDUPBASE */
 345         return s->upbase;
 346     case 5: /* LCDLPBASE */
 347         return s->lpbase;
 348     case 6: /* LCDIMSC */
 349         if (s->version != PL110) {
 350             return s->cr;
 351         }
 352         return s->int_mask;
 353     case 7: /* LCDControl */
 354         if (s->version != PL110) {
 355             return s->int_mask;
 356         }
 357         return s->cr;
 358     case 8: /* LCDRIS */
 359         return s->int_status;
 360     case 9: /* LCDMIS */
 361         return s->int_status & s->int_mask;
 362     case 11: /* LCDUPCURR */
 363         /* TODO: Implement vertical refresh.  */
 364         return s->upbase;
 365     case 12: /* LCDLPCURR */
 366         return s->lpbase;
 367     default:
 368         qemu_log_mask(LOG_GUEST_ERROR,
 369                       "pl110_read: Bad offset %x\n", (int)offset);
 370         return 0;
 371     }
 372 }
 373
 374 static void pl110_write(void *opaque, hwaddr offset,
 375                         uint64_t val, unsigned size)
 376 {
 377     PL110State *s = (PL110State *)opaque;
 378     int n;
 379
 380     /* For simplicity invalidate the display whenever a control register
 381        is written to.  */
 382     s->invalidate = 1;
 383     if (offset >= 0x200 && offset < 0x400) {
 384         /* Palette.  */
 385         n = (offset - 0x200) >> 2;
 386         s->raw_palette[(offset - 0x200) >> 2] = val;
 387         pl110_update_palette(s, n);
 388         return;
 389     }
 390     switch (offset >> 2) {
 391     case 0: /* LCDTiming0 */
 392         s->timing[0] = val;
 393         n = ((val & 0xfc) + 4) * 4;
 394         pl110_resize(s, n, s->rows);
 395         break;
 396     case 1: /* LCDTiming1 */
 397         s->timing[1] = val;
 398         n = (val & 0x3ff) + 1;
 399         pl110_resize(s, s->cols, n);
 400         break;
 401     case 2: /* LCDTiming2 */
 402         s->timing[2] = val;
 403         break;
 404     case 3: /* LCDTiming3 */
 405         s->timing[3] = val;
 406         break;
 407     case 4: /* LCDUPBASE */
 408         s->upbase = val;
 409         break;
 410     case 5: /* LCDLPBASE */
 411         s->lpbase = val;
 412         break;
 413     case 6: /* LCDIMSC */
 414         if (s->version != PL110) {
 415             goto control;
 416         }
 417     imsc:
 418         s->int_mask = val;
 419         pl110_update(s);
 420         break;
 421     case 7: /* LCDControl */
 422         if (s->version != PL110) {
 423             goto imsc;
 424         }
 425     control:
 426         s->cr = val;
 427         s->bpp = (val >> 1) & 7;
 428         if (pl110_enabled(s)) {
 429             qemu_console_resize(s->con, s->cols, s->rows);
 430         }
 431         break;
 432     case 10: /* LCDICR */
 433         s->int_status &= ~val;
 434         pl110_update(s);
 435         break;
 436     default:
 437         qemu_log_mask(LOG_GUEST_ERROR,
 438                       "pl110_write: Bad offset %x\n", (int)offset);
 439     }
 440 }
 441
 442 static const MemoryRegionOps pl110_ops = {
 443     .read = pl110_read,
 444     .write = pl110_write,
 445     .endianness = DEVICE_NATIVE_ENDIAN,
 446 };
 447
 448 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
 449 {
 450     PL110State *s = (PL110State *)opaque;
 451     s->mux_ctrl = level;
 452 }
 453
 454 static int vmstate_pl110_post_load(void *opaque, int version_id)
 455 {
 456     PL110State *s = opaque;
 457     /* Make sure we redraw, and at the right size */
 458     pl110_invalidate_display(s);
 459     return 0;
 460 }
 461
 462 static const GraphicHwOps pl110_gfx_ops = {
 463     .invalidate  = pl110_invalidate_display,
 464     .gfx_update  = pl110_update_display,
 465 };
 466
 467 static int pl110_initfn(SysBusDevice *sbd)
 468 {
 469     DeviceState *dev = DEVICE(sbd);
 470     PL110State *s = PL110(dev);
 471
 472     memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
 473     sysbus_init_mmio(sbd, &s->iomem);
 474     sysbus_init_irq(sbd, &s->irq);
 475     qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
 476     s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
 477     return 0;
 478 }
 479
 480 static void pl110_init(Object *obj)
 481 {
 482     PL110State *s = PL110(obj);
 483
 484     s->version = PL110;
 485 }
 486
 487 static void pl110_versatile_init(Object *obj)
 488 {
 489     PL110State *s = PL110(obj);
 490
 491     s->version = PL110_VERSATILE;
 492 }
 493
 494 static void pl111_init(Object *obj)
 495 {
 496     PL110State *s = PL110(obj);
 497
 498     s->version = PL111;
 499 }
 500
 501 static void pl110_class_init(ObjectClass *klass, void *data)
 502 {
 503     DeviceClass *dc = DEVICE_CLASS(klass);
 504     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 505
 506     k->init = pl110_initfn;
 507     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 508     dc->vmsd = &vmstate_pl110;
 509 }
 510
 511 static const TypeInfo pl110_info = {
 512     .name          = TYPE_PL110,
 513     .parent        = TYPE_SYS_BUS_DEVICE,
 514     .instance_size = sizeof(PL110State),
 515     .instance_init = pl110_init,
 516     .class_init    = pl110_class_init,
 517 };
 518
 519 static const TypeInfo pl110_versatile_info = {
 520     .name          = "pl110_versatile",
 521     .parent        = TYPE_PL110,
 522     .instance_init = pl110_versatile_init,
 523 };
 524
 525 static const TypeInfo pl111_info = {
 526     .name          = "pl111",
 527     .parent        = TYPE_PL110,
 528     .instance_init = pl111_init,
 529 };
 530
 531 static void pl110_register_types(void)
 532 {
 533     type_register_static(&pl110_info);
 534     type_register_static(&pl110_versatile_info);
 535     type_register_static(&pl111_info);
 536 }
 537
 538 type_init(pl110_register_types)