hw/arm/xilinx_zynq.c

   1 /*
   2  * Xilinx Zynq Baseboard System emulation.
   3  *
   4  * Copyright (c) 2010 Xilinx.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
   6  * Copyright (c) 2012 Petalogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "hw/sysbus.h"
  19 #include "hw/arm/arm.h"
  20 #include "net/net.h"
  21 #include "exec/address-spaces.h"
  22 #include "sysemu/sysemu.h"
  23 #include "hw/boards.h"
  24 #include "hw/block/flash.h"
  25 #include "sysemu/block-backend.h"
  26 #include "hw/loader.h"
  27 #include "hw/ssi.h"
  28 #include "qemu/error-report.h"
  29
  30 #define NUM_SPI_FLASHES 4
  31 #define NUM_QSPI_FLASHES 2
  32 #define NUM_QSPI_BUSSES 2
  33
  34 #define FLASH_SIZE (64 * 1024 * 1024)
  35 #define FLASH_SECTOR_SIZE (128 * 1024)
  36
  37 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
  38
  39 #define MPCORE_PERIPHBASE 0xF8F00000
  40 #define ZYNQ_BOARD_MIDR 0x413FC090
  41
  42 static const int dma_irqs[8] = {
  43     46, 47, 48, 49, 72, 73, 74, 75
  44 };
  45
  46 static struct arm_boot_info zynq_binfo = {};
  47
  48 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
  49 {
  50     DeviceState *dev;
  51     SysBusDevice *s;
  52
  53     dev = qdev_create(NULL, "cadence_gem");
  54     if (nd->used) {
  55         qemu_check_nic_model(nd, "cadence_gem");
  56         qdev_set_nic_properties(dev, nd);
  57     }
  58     qdev_init_nofail(dev);
  59     s = SYS_BUS_DEVICE(dev);
  60     sysbus_mmio_map(s, 0, base);
  61     sysbus_connect_irq(s, 0, irq);
  62 }
  63
  64 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
  65                                          bool is_qspi)
  66 {
  67     DeviceState *dev;
  68     SysBusDevice *busdev;
  69     SSIBus *spi;
  70     DeviceState *flash_dev;
  71     int i, j;
  72     int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
  73     int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
  74
  75     dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
  76     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
  77     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
  78     qdev_prop_set_uint8(dev, "num-busses", num_busses);
  79     qdev_init_nofail(dev);
  80     busdev = SYS_BUS_DEVICE(dev);
  81     sysbus_mmio_map(busdev, 0, base_addr);
  82     if (is_qspi) {
  83         sysbus_mmio_map(busdev, 1, 0xFC000000);
  84     }
  85     sysbus_connect_irq(busdev, 0, irq);
  86
  87     for (i = 0; i < num_busses; ++i) {
  88         char bus_name[16];
  89         qemu_irq cs_line;
  90
  91         snprintf(bus_name, 16, "spi%d", i);
  92         spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
  93
  94         for (j = 0; j < num_ss; ++j) {
  95             flash_dev = ssi_create_slave(spi, "n25q128");
  96
  97             cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
  98             sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
  99         }
 100     }
 101
 102 }
 103
 104 static void zynq_init(MachineState *machine)
 105 {
 106     ram_addr_t ram_size = machine->ram_size;
 107     const char *cpu_model = machine->cpu_model;
 108     const char *kernel_filename = machine->kernel_filename;
 109     const char *kernel_cmdline = machine->kernel_cmdline;
 110     const char *initrd_filename = machine->initrd_filename;
 111     ObjectClass *cpu_oc;
 112     ARMCPU *cpu;
 113     MemoryRegion *address_space_mem = get_system_memory();
 114     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
 115     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
 116     DeviceState *dev;
 117     SysBusDevice *busdev;
 118     qemu_irq pic[64];
 119     Error *err = NULL;
 120     int n;
 121
 122     if (!cpu_model) {
 123         cpu_model = "cortex-a9";
 124     }
 125     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 126
 127     cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
 128
 129     /* By default A9 CPUs have EL3 enabled.  This board does not
 130      * currently support EL3 so the CPU EL3 property is disabled before
 131      * realization.
 132      */
 133     if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
 134         object_property_set_bool(OBJECT(cpu), false, "has_el3", &err);
 135         if (err) {
 136             error_report_err(err);
 137             exit(1);
 138         }
 139     }
 140
 141     object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", &err);
 142     if (err) {
 143         error_report_err(err);
 144         exit(1);
 145     }
 146
 147     object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err);
 148     if (err) {
 149         error_report_err(err);
 150         exit(1);
 151     }
 152     object_property_set_bool(OBJECT(cpu), true, "realized", &err);
 153     if (err) {
 154         error_report_err(err);
 155         exit(1);
 156     }
 157
 158     /* max 2GB ram */
 159     if (ram_size > 0x80000000) {
 160         ram_size = 0x80000000;
 161     }
 162
 163     /* DDR remapped to address zero.  */
 164     memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
 165                                          ram_size);
 166     memory_region_add_subregion(address_space_mem, 0, ext_ram);
 167
 168     /* 256K of on-chip memory */
 169     memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
 170                            &error_abort);
 171     vmstate_register_ram_global(ocm_ram);
 172     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
 173
 174     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
 175
 176     /* AMD */
 177     pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
 178                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 179                           FLASH_SECTOR_SIZE,
 180                           FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
 181                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
 182                               0);
 183
 184     dev = qdev_create(NULL, "xilinx,zynq_slcr");
 185     qdev_init_nofail(dev);
 186     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
 187
 188     dev = qdev_create(NULL, "a9mpcore_priv");
 189     qdev_prop_set_uint32(dev, "num-cpu", 1);
 190     qdev_init_nofail(dev);
 191     busdev = SYS_BUS_DEVICE(dev);
 192     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 193     sysbus_connect_irq(busdev, 0,
 194                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 195
 196     for (n = 0; n < 64; n++) {
 197         pic[n] = qdev_get_gpio_in(dev, n);
 198     }
 199
 200     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
 201     zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
 202     zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
 203
 204     sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
 205     sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
 206
 207     sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
 208     sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
 209
 210     sysbus_create_varargs("cadence_ttc", 0xF8001000,
 211             pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
 212     sysbus_create_varargs("cadence_ttc", 0xF8002000,
 213             pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
 214
 215     gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
 216     gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
 217
 218     dev = qdev_create(NULL, "generic-sdhci");
 219     qdev_init_nofail(dev);
 220     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
 221     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
 222
 223     dev = qdev_create(NULL, "generic-sdhci");
 224     qdev_init_nofail(dev);
 225     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
 226     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
 227
 228     dev = qdev_create(NULL, "pl330");
 229     qdev_prop_set_uint8(dev, "num_chnls",  8);
 230     qdev_prop_set_uint8(dev, "num_periph_req",  4);
 231     qdev_prop_set_uint8(dev, "num_events",  16);
 232
 233     qdev_prop_set_uint8(dev, "data_width",  64);
 234     qdev_prop_set_uint8(dev, "wr_cap",  8);
 235     qdev_prop_set_uint8(dev, "wr_q_dep",  16);
 236     qdev_prop_set_uint8(dev, "rd_cap",  8);
 237     qdev_prop_set_uint8(dev, "rd_q_dep",  16);
 238     qdev_prop_set_uint16(dev, "data_buffer_dep",  256);
 239
 240     qdev_init_nofail(dev);
 241     busdev = SYS_BUS_DEVICE(dev);
 242     sysbus_mmio_map(busdev, 0, 0xF8003000);
 243     sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
 244     for (n = 0; n < 8; ++n) { /* event irqs */
 245         sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
 246     }
 247
 248     zynq_binfo.ram_size = ram_size;
 249     zynq_binfo.kernel_filename = kernel_filename;
 250     zynq_binfo.kernel_cmdline = kernel_cmdline;
 251     zynq_binfo.initrd_filename = initrd_filename;
 252     zynq_binfo.nb_cpus = 1;
 253     zynq_binfo.board_id = 0xd32;
 254     zynq_binfo.loader_start = 0;
 255     arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
 256 }
 257
 258 static QEMUMachine zynq_machine = {
 259     .name = "xilinx-zynq-a9",
 260     .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
 261     .init = zynq_init,
 262     .block_default_type = IF_SCSI,
 263     .max_cpus = 1,
 264     .no_sdcard = 1,
 265 };
 266
 267 static void zynq_machine_init(void)
 268 {
 269     qemu_register_machine(&zynq_machine);
 270 }
 271
 272 machine_init(zynq_machine_init);