1 #include "qemu/osdep.h"
2 #include "target/arm/idau.h"
6 #include "exec/gdbstub.h"
7 #include "exec/helper-proto.h"
8 #include "qemu/host-utils.h"
9 #include "sysemu/arch_init.h"
10 #include "sysemu/sysemu.h"
11 #include "qemu/bitops.h"
12 #include "qemu/crc32c.h"
13 #include "exec/exec-all.h"
14 #include "exec/cpu_ldst.h"
16 #include <zlib.h> /* For crc32 */
17 #include "exec/semihost.h"
18 #include "sysemu/kvm.h"
19 #include "fpu/softfloat.h"
20 #include "qemu/range.h"
22 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
24 #ifndef CONFIG_USER_ONLY
25 /* Cacheability and shareability attributes for a memory access */
26 typedef struct ARMCacheAttrs
{
27 unsigned int attrs
:8; /* as in the MAIR register encoding */
28 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
31 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
32 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
33 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
34 target_ulong
*page_size
,
35 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
37 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
38 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
39 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
40 target_ulong
*page_size_ptr
,
41 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
43 /* Security attributes for an address, as returned by v8m_security_lookup. */
44 typedef struct V8M_SAttributes
{
45 bool subpage
; /* true if these attrs don't cover the whole TARGET_PAGE */
54 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
55 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
56 V8M_SAttributes
*sattrs
);
59 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
63 /* VFP data registers are always little-endian. */
64 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
66 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
69 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
70 /* Aliases for Q regs. */
73 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
75 stq_le_p(buf
+ 8, q
[1]);
79 switch (reg
- nregs
) {
80 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
81 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
82 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
87 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
91 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
93 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
96 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
99 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
100 q
[0] = ldq_le_p(buf
);
101 q
[1] = ldq_le_p(buf
+ 8);
105 switch (reg
- nregs
) {
106 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
107 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
108 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
113 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
117 /* 128 bit FP register */
119 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
121 stq_le_p(buf
+ 8, q
[1]);
126 stl_p(buf
, vfp_get_fpsr(env
));
130 stl_p(buf
, vfp_get_fpcr(env
));
137 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
141 /* 128 bit FP register */
143 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
144 q
[0] = ldq_le_p(buf
);
145 q
[1] = ldq_le_p(buf
+ 8);
150 vfp_set_fpsr(env
, ldl_p(buf
));
154 vfp_set_fpcr(env
, ldl_p(buf
));
161 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
163 assert(ri
->fieldoffset
);
164 if (cpreg_field_is_64bit(ri
)) {
165 return CPREG_FIELD64(env
, ri
);
167 return CPREG_FIELD32(env
, ri
);
171 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
174 assert(ri
->fieldoffset
);
175 if (cpreg_field_is_64bit(ri
)) {
176 CPREG_FIELD64(env
, ri
) = value
;
178 CPREG_FIELD32(env
, ri
) = value
;
182 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
184 return (char *)env
+ ri
->fieldoffset
;
187 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
189 /* Raw read of a coprocessor register (as needed for migration, etc). */
190 if (ri
->type
& ARM_CP_CONST
) {
191 return ri
->resetvalue
;
192 } else if (ri
->raw_readfn
) {
193 return ri
->raw_readfn(env
, ri
);
194 } else if (ri
->readfn
) {
195 return ri
->readfn(env
, ri
);
197 return raw_read(env
, ri
);
201 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
204 /* Raw write of a coprocessor register (as needed for migration, etc).
205 * Note that constant registers are treated as write-ignored; the
206 * caller should check for success by whether a readback gives the
209 if (ri
->type
& ARM_CP_CONST
) {
211 } else if (ri
->raw_writefn
) {
212 ri
->raw_writefn(env
, ri
, v
);
213 } else if (ri
->writefn
) {
214 ri
->writefn(env
, ri
, v
);
216 raw_write(env
, ri
, v
);
220 static int arm_gdb_get_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
222 ARMCPU
*cpu
= arm_env_get_cpu(env
);
223 const ARMCPRegInfo
*ri
;
226 key
= cpu
->dyn_xml
.cpregs_keys
[reg
];
227 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
229 if (cpreg_field_is_64bit(ri
)) {
230 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
232 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
238 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
243 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
245 /* Return true if the regdef would cause an assertion if you called
246 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
247 * program bug for it not to have the NO_RAW flag).
248 * NB that returning false here doesn't necessarily mean that calling
249 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
250 * read/write access functions which are safe for raw use" from "has
251 * read/write access functions which have side effects but has forgotten
252 * to provide raw access functions".
253 * The tests here line up with the conditions in read/write_raw_cp_reg()
254 * and assertions in raw_read()/raw_write().
256 if ((ri
->type
& ARM_CP_CONST
) ||
258 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
264 bool write_cpustate_to_list(ARMCPU
*cpu
)
266 /* Write the coprocessor state from cpu->env to the (index,value) list. */
270 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
271 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
272 const ARMCPRegInfo
*ri
;
274 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
279 if (ri
->type
& ARM_CP_NO_RAW
) {
282 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
287 bool write_list_to_cpustate(ARMCPU
*cpu
)
292 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
293 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
294 uint64_t v
= cpu
->cpreg_values
[i
];
295 const ARMCPRegInfo
*ri
;
297 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
302 if (ri
->type
& ARM_CP_NO_RAW
) {
305 /* Write value and confirm it reads back as written
306 * (to catch read-only registers and partially read-only
307 * registers where the incoming migration value doesn't match)
309 write_raw_cp_reg(&cpu
->env
, ri
, v
);
310 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
317 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
319 ARMCPU
*cpu
= opaque
;
321 const ARMCPRegInfo
*ri
;
323 regidx
= *(uint32_t *)key
;
324 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
326 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
327 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
328 /* The value array need not be initialized at this point */
329 cpu
->cpreg_array_len
++;
333 static void count_cpreg(gpointer key
, gpointer opaque
)
335 ARMCPU
*cpu
= opaque
;
337 const ARMCPRegInfo
*ri
;
339 regidx
= *(uint32_t *)key
;
340 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
342 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
343 cpu
->cpreg_array_len
++;
347 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
349 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
350 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
361 void init_cpreg_list(ARMCPU
*cpu
)
363 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
364 * Note that we require cpreg_tuples[] to be sorted by key ID.
369 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
370 keys
= g_list_sort(keys
, cpreg_key_compare
);
372 cpu
->cpreg_array_len
= 0;
374 g_list_foreach(keys
, count_cpreg
, cpu
);
376 arraylen
= cpu
->cpreg_array_len
;
377 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
378 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
379 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
380 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
381 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
382 cpu
->cpreg_array_len
= 0;
384 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
386 assert(cpu
->cpreg_array_len
== arraylen
);
392 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
393 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
395 * access_el3_aa32ns: Used to check AArch32 register views.
396 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
398 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
399 const ARMCPRegInfo
*ri
,
402 bool secure
= arm_is_secure_below_el3(env
);
404 assert(!arm_el_is_aa64(env
, 3));
406 return CP_ACCESS_TRAP_UNCATEGORIZED
;
411 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
412 const ARMCPRegInfo
*ri
,
415 if (!arm_el_is_aa64(env
, 3)) {
416 return access_el3_aa32ns(env
, ri
, isread
);
421 /* Some secure-only AArch32 registers trap to EL3 if used from
422 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
423 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
424 * We assume that the .access field is set to PL1_RW.
426 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
427 const ARMCPRegInfo
*ri
,
430 if (arm_current_el(env
) == 3) {
433 if (arm_is_secure_below_el3(env
)) {
434 return CP_ACCESS_TRAP_EL3
;
436 /* This will be EL1 NS and EL2 NS, which just UNDEF */
437 return CP_ACCESS_TRAP_UNCATEGORIZED
;
440 /* Check for traps to "powerdown debug" registers, which are controlled
443 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
446 int el
= arm_current_el(env
);
448 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDOSA
)
449 && !arm_is_secure_below_el3(env
)) {
450 return CP_ACCESS_TRAP_EL2
;
452 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
453 return CP_ACCESS_TRAP_EL3
;
458 /* Check for traps to "debug ROM" registers, which are controlled
459 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
461 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
464 int el
= arm_current_el(env
);
466 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDRA
)
467 && !arm_is_secure_below_el3(env
)) {
468 return CP_ACCESS_TRAP_EL2
;
470 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
471 return CP_ACCESS_TRAP_EL3
;
476 /* Check for traps to general debug registers, which are controlled
477 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
479 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
482 int el
= arm_current_el(env
);
484 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDA
)
485 && !arm_is_secure_below_el3(env
)) {
486 return CP_ACCESS_TRAP_EL2
;
488 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
489 return CP_ACCESS_TRAP_EL3
;
494 /* Check for traps to performance monitor registers, which are controlled
495 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
497 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
500 int el
= arm_current_el(env
);
502 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
503 && !arm_is_secure_below_el3(env
)) {
504 return CP_ACCESS_TRAP_EL2
;
506 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
507 return CP_ACCESS_TRAP_EL3
;
512 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
514 ARMCPU
*cpu
= arm_env_get_cpu(env
);
516 raw_write(env
, ri
, value
);
517 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
520 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
522 ARMCPU
*cpu
= arm_env_get_cpu(env
);
524 if (raw_read(env
, ri
) != value
) {
525 /* Unlike real hardware the qemu TLB uses virtual addresses,
526 * not modified virtual addresses, so this causes a TLB flush.
529 raw_write(env
, ri
, value
);
533 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
536 ARMCPU
*cpu
= arm_env_get_cpu(env
);
538 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
539 && !extended_addresses_enabled(env
)) {
540 /* For VMSA (when not using the LPAE long descriptor page table
541 * format) this register includes the ASID, so do a TLB flush.
542 * For PMSA it is purely a process ID and no action is needed.
546 raw_write(env
, ri
, value
);
549 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
552 /* Invalidate all (TLBIALL) */
553 ARMCPU
*cpu
= arm_env_get_cpu(env
);
558 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
561 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
562 ARMCPU
*cpu
= arm_env_get_cpu(env
);
564 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
567 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
570 /* Invalidate by ASID (TLBIASID) */
571 ARMCPU
*cpu
= arm_env_get_cpu(env
);
576 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
579 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
580 ARMCPU
*cpu
= arm_env_get_cpu(env
);
582 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
585 /* IS variants of TLB operations must affect all cores */
586 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
589 CPUState
*cs
= ENV_GET_CPU(env
);
591 tlb_flush_all_cpus_synced(cs
);
594 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 CPUState
*cs
= ENV_GET_CPU(env
);
599 tlb_flush_all_cpus_synced(cs
);
602 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
605 CPUState
*cs
= ENV_GET_CPU(env
);
607 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
610 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
613 CPUState
*cs
= ENV_GET_CPU(env
);
615 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
618 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
621 CPUState
*cs
= ENV_GET_CPU(env
);
623 tlb_flush_by_mmuidx(cs
,
624 ARMMMUIdxBit_S12NSE1
|
625 ARMMMUIdxBit_S12NSE0
|
629 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
632 CPUState
*cs
= ENV_GET_CPU(env
);
634 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
635 ARMMMUIdxBit_S12NSE1
|
636 ARMMMUIdxBit_S12NSE0
|
640 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
643 /* Invalidate by IPA. This has to invalidate any structures that
644 * contain only stage 2 translation information, but does not need
645 * to apply to structures that contain combined stage 1 and stage 2
646 * translation information.
647 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
649 CPUState
*cs
= ENV_GET_CPU(env
);
652 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
656 pageaddr
= sextract64(value
<< 12, 0, 40);
658 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
661 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
664 CPUState
*cs
= ENV_GET_CPU(env
);
667 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
671 pageaddr
= sextract64(value
<< 12, 0, 40);
673 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
677 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
680 CPUState
*cs
= ENV_GET_CPU(env
);
682 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
685 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
688 CPUState
*cs
= ENV_GET_CPU(env
);
690 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
693 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
696 CPUState
*cs
= ENV_GET_CPU(env
);
697 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
699 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
702 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
705 CPUState
*cs
= ENV_GET_CPU(env
);
706 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
708 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
712 static const ARMCPRegInfo cp_reginfo
[] = {
713 /* Define the secure and non-secure FCSE identifier CP registers
714 * separately because there is no secure bank in V8 (no _EL3). This allows
715 * the secure register to be properly reset and migrated. There is also no
716 * v8 EL1 version of the register so the non-secure instance stands alone.
719 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
720 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
721 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
722 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
723 { .name
= "FCSEIDR_S",
724 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
725 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
726 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
727 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
728 /* Define the secure and non-secure context identifier CP registers
729 * separately because there is no secure bank in V8 (no _EL3). This allows
730 * the secure register to be properly reset and migrated. In the
731 * non-secure case, the 32-bit register will have reset and migration
732 * disabled during registration as it is handled by the 64-bit instance.
734 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
735 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
736 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
737 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
738 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
739 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
740 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
741 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
742 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
743 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
747 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
748 /* NB: Some of these registers exist in v8 but with more precise
749 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
751 /* MMU Domain access control / MPU write buffer control */
753 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
754 .access
= PL1_RW
, .resetvalue
= 0,
755 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
756 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
757 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
758 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
759 * For v6 and v5, these mappings are overly broad.
761 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
762 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
763 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
764 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
765 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
766 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
767 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
768 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
769 /* Cache maintenance ops; some of this space may be overridden later. */
770 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
771 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
772 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
776 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
777 /* Not all pre-v6 cores implemented this WFI, so this is slightly
780 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
781 .access
= PL1_W
, .type
= ARM_CP_WFI
},
785 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
786 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
787 * is UNPREDICTABLE; we choose to NOP as most implementations do).
789 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
790 .access
= PL1_W
, .type
= ARM_CP_WFI
},
791 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
792 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
793 * OMAPCP will override this space.
795 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
796 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
798 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
799 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
801 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
802 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
803 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
805 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
806 * implementing it as RAZ means the "debug architecture version" bits
807 * will read as a reserved value, which should cause Linux to not try
808 * to use the debug hardware.
810 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
811 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
812 /* MMU TLB control. Note that the wildcarding means we cover not just
813 * the unified TLB ops but also the dside/iside/inner-shareable variants.
815 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
816 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
817 .type
= ARM_CP_NO_RAW
},
818 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
819 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
820 .type
= ARM_CP_NO_RAW
},
821 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
822 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
823 .type
= ARM_CP_NO_RAW
},
824 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
825 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
826 .type
= ARM_CP_NO_RAW
},
827 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
828 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
829 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
830 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
834 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
839 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
840 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
841 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
842 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
843 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
845 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
846 /* VFP coprocessor: cp10 & cp11 [23:20] */
847 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
849 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
850 /* ASEDIS [31] bit is RAO/WI */
854 /* VFPv3 and upwards with NEON implement 32 double precision
855 * registers (D0-D31).
857 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
858 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
859 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
865 env
->cp15
.cpacr_el1
= value
;
868 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
870 /* Call cpacr_write() so that we reset with the correct RAO bits set
871 * for our CPU features.
873 cpacr_write(env
, ri
, 0);
876 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
879 if (arm_feature(env
, ARM_FEATURE_V8
)) {
880 /* Check if CPACR accesses are to be trapped to EL2 */
881 if (arm_current_el(env
) == 1 &&
882 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
883 return CP_ACCESS_TRAP_EL2
;
884 /* Check if CPACR accesses are to be trapped to EL3 */
885 } else if (arm_current_el(env
) < 3 &&
886 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
887 return CP_ACCESS_TRAP_EL3
;
894 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
897 /* Check if CPTR accesses are set to trap to EL3 */
898 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
899 return CP_ACCESS_TRAP_EL3
;
905 static const ARMCPRegInfo v6_cp_reginfo
[] = {
906 /* prefetch by MVA in v6, NOP in v7 */
907 { .name
= "MVA_prefetch",
908 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
909 .access
= PL1_W
, .type
= ARM_CP_NOP
},
910 /* We need to break the TB after ISB to execute self-modifying code
911 * correctly and also to take any pending interrupts immediately.
912 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
914 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
915 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
916 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
917 .access
= PL0_W
, .type
= ARM_CP_NOP
},
918 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
919 .access
= PL0_W
, .type
= ARM_CP_NOP
},
920 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
922 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
923 offsetof(CPUARMState
, cp15
.ifar_ns
) },
925 /* Watchpoint Fault Address Register : should actually only be present
926 * for 1136, 1176, 11MPCore.
928 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
929 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
930 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
931 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
932 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
933 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
},
937 /* Definitions for the PMU registers */
938 #define PMCRN_MASK 0xf800
939 #define PMCRN_SHIFT 11
944 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
946 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
949 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
950 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
952 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
955 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
958 /* Performance monitor registers user accessibility is controlled
959 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
960 * trapping to EL2 or EL3 for other accesses.
962 int el
= arm_current_el(env
);
964 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
965 return CP_ACCESS_TRAP
;
967 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
968 && !arm_is_secure_below_el3(env
)) {
969 return CP_ACCESS_TRAP_EL2
;
971 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
972 return CP_ACCESS_TRAP_EL3
;
978 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
979 const ARMCPRegInfo
*ri
,
982 /* ER: event counter read trap control */
983 if (arm_feature(env
, ARM_FEATURE_V8
)
984 && arm_current_el(env
) == 0
985 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
990 return pmreg_access(env
, ri
, isread
);
993 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
994 const ARMCPRegInfo
*ri
,
997 /* SW: software increment write trap control */
998 if (arm_feature(env
, ARM_FEATURE_V8
)
999 && arm_current_el(env
) == 0
1000 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1002 return CP_ACCESS_OK
;
1005 return pmreg_access(env
, ri
, isread
);
1008 #ifndef CONFIG_USER_ONLY
1010 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1011 const ARMCPRegInfo
*ri
,
1014 /* ER: event counter read trap control */
1015 if (arm_feature(env
, ARM_FEATURE_V8
)
1016 && arm_current_el(env
) == 0
1017 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1018 return CP_ACCESS_OK
;
1021 return pmreg_access(env
, ri
, isread
);
1024 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1025 const ARMCPRegInfo
*ri
,
1028 /* CR: cycle counter read trap control */
1029 if (arm_feature(env
, ARM_FEATURE_V8
)
1030 && arm_current_el(env
) == 0
1031 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1033 return CP_ACCESS_OK
;
1036 return pmreg_access(env
, ri
, isread
);
1039 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
1041 /* This does not support checking PMCCFILTR_EL0 register */
1043 if (!(env
->cp15
.c9_pmcr
& PMCRE
) || !(env
->cp15
.c9_pmcnten
& (1 << 31))) {
1050 void pmccntr_sync(CPUARMState
*env
)
1052 uint64_t temp_ticks
;
1054 temp_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1055 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1057 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1058 /* Increment once every 64 processor clock cycles */
1062 if (arm_ccnt_enabled(env
)) {
1063 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
1067 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1072 if (value
& PMCRC
) {
1073 /* The counter has been reset */
1074 env
->cp15
.c15_ccnt
= 0;
1077 /* only the DP, X, D and E bits are writable */
1078 env
->cp15
.c9_pmcr
&= ~0x39;
1079 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1084 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1086 uint64_t total_ticks
;
1088 if (!arm_ccnt_enabled(env
)) {
1089 /* Counter is disabled, do not change value */
1090 return env
->cp15
.c15_ccnt
;
1093 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1094 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1096 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1097 /* Increment once every 64 processor clock cycles */
1100 return total_ticks
- env
->cp15
.c15_ccnt
;
1103 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1106 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1107 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1108 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1111 env
->cp15
.c9_pmselr
= value
& 0x1f;
1114 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1117 uint64_t total_ticks
;
1119 if (!arm_ccnt_enabled(env
)) {
1120 /* Counter is disabled, set the absolute value */
1121 env
->cp15
.c15_ccnt
= value
;
1125 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1126 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1128 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1129 /* Increment once every 64 processor clock cycles */
1132 env
->cp15
.c15_ccnt
= total_ticks
- value
;
1135 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1138 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1140 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1143 #else /* CONFIG_USER_ONLY */
1145 void pmccntr_sync(CPUARMState
*env
)
1151 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1155 env
->cp15
.pmccfiltr_el0
= value
& 0xfc000000;
1159 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1162 value
&= pmu_counter_mask(env
);
1163 env
->cp15
.c9_pmcnten
|= value
;
1166 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1169 value
&= pmu_counter_mask(env
);
1170 env
->cp15
.c9_pmcnten
&= ~value
;
1173 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1176 env
->cp15
.c9_pmovsr
&= ~value
;
1179 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1182 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1183 * PMSELR value is equal to or greater than the number of implemented
1184 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1186 if (env
->cp15
.c9_pmselr
== 0x1f) {
1187 pmccfiltr_write(env
, ri
, value
);
1191 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1193 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1194 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1196 if (env
->cp15
.c9_pmselr
== 0x1f) {
1197 return env
->cp15
.pmccfiltr_el0
;
1203 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1206 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1207 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1209 env
->cp15
.c9_pmuserenr
= value
& 1;
1213 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1216 /* We have no event counters so only the C bit can be changed */
1217 value
&= pmu_counter_mask(env
);
1218 env
->cp15
.c9_pminten
|= value
;
1221 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1224 value
&= pmu_counter_mask(env
);
1225 env
->cp15
.c9_pminten
&= ~value
;
1228 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1231 /* Note that even though the AArch64 view of this register has bits
1232 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1233 * architectural requirements for bits which are RES0 only in some
1234 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1235 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1237 raw_write(env
, ri
, value
& ~0x1FULL
);
1240 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1242 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1243 * For bits that vary between AArch32/64, code needs to check the
1244 * current execution mode before directly using the feature bit.
1246 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
1248 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1249 valid_mask
&= ~SCR_HCE
;
1251 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1252 * supported if EL2 exists. The bit is UNK/SBZP when
1253 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1254 * when EL2 is unavailable.
1255 * On ARMv8, this bit is always available.
1257 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1258 !arm_feature(env
, ARM_FEATURE_V8
)) {
1259 valid_mask
&= ~SCR_SMD
;
1263 /* Clear all-context RES0 bits. */
1264 value
&= valid_mask
;
1265 raw_write(env
, ri
, value
);
1268 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1270 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1272 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1275 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1276 ri
->secure
& ARM_CP_SECSTATE_S
);
1278 return cpu
->ccsidr
[index
];
1281 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1284 raw_write(env
, ri
, value
& 0xf);
1287 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1289 CPUState
*cs
= ENV_GET_CPU(env
);
1292 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1295 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1298 /* External aborts are not possible in QEMU so A bit is always clear */
1302 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1303 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1304 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1305 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1306 /* Performance monitors are implementation defined in v7,
1307 * but with an ARM recommended set of registers, which we
1308 * follow (although we don't actually implement any counters)
1310 * Performance registers fall into three categories:
1311 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1312 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1313 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1314 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1315 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1317 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1318 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1319 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1320 .writefn
= pmcntenset_write
,
1321 .accessfn
= pmreg_access
,
1322 .raw_writefn
= raw_write
},
1323 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1324 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1325 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1326 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1327 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1328 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1330 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1331 .accessfn
= pmreg_access
,
1332 .writefn
= pmcntenclr_write
,
1333 .type
= ARM_CP_ALIAS
},
1334 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1335 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1336 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1337 .type
= ARM_CP_ALIAS
,
1338 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1339 .writefn
= pmcntenclr_write
},
1340 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1342 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1343 .accessfn
= pmreg_access
,
1344 .writefn
= pmovsr_write
,
1345 .raw_writefn
= raw_write
},
1346 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1347 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1348 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1349 .type
= ARM_CP_ALIAS
,
1350 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1351 .writefn
= pmovsr_write
,
1352 .raw_writefn
= raw_write
},
1353 /* Unimplemented so WI. */
1354 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1355 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
, .type
= ARM_CP_NOP
},
1356 #ifndef CONFIG_USER_ONLY
1357 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1358 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1359 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1360 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1361 .raw_writefn
= raw_write
},
1362 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1363 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1364 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1365 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1366 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1367 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1368 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1369 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1370 .accessfn
= pmreg_access_ccntr
},
1371 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1372 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1373 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1375 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
1377 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1378 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1379 .writefn
= pmccfiltr_write
,
1380 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1382 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1384 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1385 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1386 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1387 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1388 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1389 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1390 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1391 /* Unimplemented, RAZ/WI. */
1392 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1393 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1394 .accessfn
= pmreg_access_xevcntr
},
1395 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1396 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
1397 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
1399 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1400 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
1401 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
1402 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1403 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1405 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1406 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1407 .access
= PL1_RW
, .accessfn
= access_tpm
,
1408 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1409 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
1411 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1412 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
1413 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
1414 .access
= PL1_RW
, .accessfn
= access_tpm
,
1416 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1417 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
1418 .resetvalue
= 0x0 },
1419 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1420 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1421 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1422 .writefn
= pmintenclr_write
, },
1423 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
1424 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
1425 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1426 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1427 .writefn
= pmintenclr_write
},
1428 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1429 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1430 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1431 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1432 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1433 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1434 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1435 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1436 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1437 * just RAZ for all cores:
1439 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1440 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1441 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1442 /* Auxiliary fault status registers: these also are IMPDEF, and we
1443 * choose to RAZ/WI for all cores.
1445 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1446 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1447 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1448 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1449 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1450 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1451 /* MAIR can just read-as-written because we don't implement caches
1452 * and so don't need to care about memory attributes.
1454 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1455 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1456 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1458 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1459 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1460 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1462 /* For non-long-descriptor page tables these are PRRR and NMRR;
1463 * regardless they still act as reads-as-written for QEMU.
1465 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1466 * allows them to assign the correct fieldoffset based on the endianness
1467 * handled in the field definitions.
1469 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1470 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1471 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1472 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1473 .resetfn
= arm_cp_reset_ignore
},
1474 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1475 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1476 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1477 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1478 .resetfn
= arm_cp_reset_ignore
},
1479 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1480 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1481 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1482 /* 32 bit ITLB invalidates */
1483 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1484 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1485 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1486 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1487 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1488 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1489 /* 32 bit DTLB invalidates */
1490 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1491 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1492 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1493 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1494 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1495 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1496 /* 32 bit TLB invalidates */
1497 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1498 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1499 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1500 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1501 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1502 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1503 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1504 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1508 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1509 /* 32 bit TLB invalidates, Inner Shareable */
1510 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1511 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1512 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1513 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1514 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1515 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1516 .writefn
= tlbiasid_is_write
},
1517 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1518 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1519 .writefn
= tlbimvaa_is_write
},
1523 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1530 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1533 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1534 return CP_ACCESS_TRAP
;
1536 return CP_ACCESS_OK
;
1539 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1540 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1541 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1543 .writefn
= teecr_write
},
1544 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1545 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1546 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1550 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1551 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1552 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1554 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1555 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1557 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1558 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1559 .resetfn
= arm_cp_reset_ignore
},
1560 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1561 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1562 .access
= PL0_R
|PL1_W
,
1563 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1565 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1566 .access
= PL0_R
|PL1_W
,
1567 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1568 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1569 .resetfn
= arm_cp_reset_ignore
},
1570 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1571 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1573 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1574 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1576 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1577 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1582 #ifndef CONFIG_USER_ONLY
1584 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1587 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1588 * Writable only at the highest implemented exception level.
1590 int el
= arm_current_el(env
);
1594 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1595 return CP_ACCESS_TRAP
;
1599 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
1600 arm_is_secure_below_el3(env
)) {
1601 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1602 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1610 if (!isread
&& el
< arm_highest_el(env
)) {
1611 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1614 return CP_ACCESS_OK
;
1617 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
1620 unsigned int cur_el
= arm_current_el(env
);
1621 bool secure
= arm_is_secure(env
);
1623 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1625 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1626 return CP_ACCESS_TRAP
;
1629 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1630 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1631 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1632 return CP_ACCESS_TRAP_EL2
;
1634 return CP_ACCESS_OK
;
1637 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
1640 unsigned int cur_el
= arm_current_el(env
);
1641 bool secure
= arm_is_secure(env
);
1643 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1644 * EL0[PV]TEN is zero.
1647 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1648 return CP_ACCESS_TRAP
;
1651 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1652 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1653 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1654 return CP_ACCESS_TRAP_EL2
;
1656 return CP_ACCESS_OK
;
1659 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1660 const ARMCPRegInfo
*ri
,
1663 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
1666 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1667 const ARMCPRegInfo
*ri
,
1670 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
1673 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1676 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
1679 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1682 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
1685 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1686 const ARMCPRegInfo
*ri
,
1689 /* The AArch64 register view of the secure physical timer is
1690 * always accessible from EL3, and configurably accessible from
1693 switch (arm_current_el(env
)) {
1695 if (!arm_is_secure(env
)) {
1696 return CP_ACCESS_TRAP
;
1698 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1699 return CP_ACCESS_TRAP_EL3
;
1701 return CP_ACCESS_OK
;
1704 return CP_ACCESS_TRAP
;
1706 return CP_ACCESS_OK
;
1708 g_assert_not_reached();
1712 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1714 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1717 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1719 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1722 /* Timer enabled: calculate and set current ISTATUS, irq, and
1723 * reset timer to when ISTATUS next has to change
1725 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1726 cpu
->env
.cp15
.cntvoff_el2
: 0;
1727 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1728 /* Note that this must be unsigned 64 bit arithmetic: */
1729 int istatus
= count
- offset
>= gt
->cval
;
1733 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1735 irqstate
= (istatus
&& !(gt
->ctl
& 2));
1736 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1739 /* Next transition is when count rolls back over to zero */
1740 nexttick
= UINT64_MAX
;
1742 /* Next transition is when we hit cval */
1743 nexttick
= gt
->cval
+ offset
;
1745 /* Note that the desired next expiry time might be beyond the
1746 * signed-64-bit range of a QEMUTimer -- in this case we just
1747 * set the timer for as far in the future as possible. When the
1748 * timer expires we will reset the timer for any remaining period.
1750 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1751 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1753 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1754 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
1756 /* Timer disabled: ISTATUS and timer output always clear */
1758 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1759 timer_del(cpu
->gt_timer
[timeridx
]);
1760 trace_arm_gt_recalc_disabled(timeridx
);
1764 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1767 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1769 timer_del(cpu
->gt_timer
[timeridx
]);
1772 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1774 return gt_get_countervalue(env
);
1777 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1779 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1782 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1786 trace_arm_gt_cval_write(timeridx
, value
);
1787 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1788 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1791 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1794 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1796 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1797 (gt_get_countervalue(env
) - offset
));
1800 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1804 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1806 trace_arm_gt_tval_write(timeridx
, value
);
1807 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1808 sextract64(value
, 0, 32);
1809 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1812 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1816 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1817 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1819 trace_arm_gt_ctl_write(timeridx
, value
);
1820 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1821 if ((oldval
^ value
) & 1) {
1822 /* Enable toggled */
1823 gt_recalc_timer(cpu
, timeridx
);
1824 } else if ((oldval
^ value
) & 2) {
1825 /* IMASK toggled: don't need to recalculate,
1826 * just set the interrupt line based on ISTATUS
1828 int irqstate
= (oldval
& 4) && !(value
& 2);
1830 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
1831 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1835 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1837 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1840 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1843 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1846 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1848 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1851 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1854 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1857 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1860 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1863 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1865 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1868 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1871 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1874 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1876 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1879 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1882 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1885 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1888 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1891 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1894 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1896 trace_arm_gt_cntvoff_write(value
);
1897 raw_write(env
, ri
, value
);
1898 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1901 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1903 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1906 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1909 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1912 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1914 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1917 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1920 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1923 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1926 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1929 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1931 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1934 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1937 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1940 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1942 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1945 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1948 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1951 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1954 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1957 void arm_gt_ptimer_cb(void *opaque
)
1959 ARMCPU
*cpu
= opaque
;
1961 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1964 void arm_gt_vtimer_cb(void *opaque
)
1966 ARMCPU
*cpu
= opaque
;
1968 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1971 void arm_gt_htimer_cb(void *opaque
)
1973 ARMCPU
*cpu
= opaque
;
1975 gt_recalc_timer(cpu
, GTIMER_HYP
);
1978 void arm_gt_stimer_cb(void *opaque
)
1980 ARMCPU
*cpu
= opaque
;
1982 gt_recalc_timer(cpu
, GTIMER_SEC
);
1985 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1986 /* Note that CNTFRQ is purely reads-as-written for the benefit
1987 * of software; writing it doesn't actually change the timer frequency.
1988 * Our reset value matches the fixed frequency we implement the timer at.
1990 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1991 .type
= ARM_CP_ALIAS
,
1992 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1993 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1995 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1996 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1997 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1998 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1999 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
2001 /* overall control: mostly access permissions */
2002 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2003 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2005 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2008 /* per-timer control */
2009 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2010 .secure
= ARM_CP_SECSTATE_NS
,
2011 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2012 .accessfn
= gt_ptimer_access
,
2013 .fieldoffset
= offsetoflow32(CPUARMState
,
2014 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2015 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2017 { .name
= "CNTP_CTL_S",
2018 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2019 .secure
= ARM_CP_SECSTATE_S
,
2020 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2021 .accessfn
= gt_ptimer_access
,
2022 .fieldoffset
= offsetoflow32(CPUARMState
,
2023 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2024 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2026 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2027 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2028 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2029 .accessfn
= gt_ptimer_access
,
2030 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2032 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2034 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2035 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
2036 .accessfn
= gt_vtimer_access
,
2037 .fieldoffset
= offsetoflow32(CPUARMState
,
2038 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2039 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2041 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2042 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2043 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2044 .accessfn
= gt_vtimer_access
,
2045 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2047 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2049 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2050 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2051 .secure
= ARM_CP_SECSTATE_NS
,
2052 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2053 .accessfn
= gt_ptimer_access
,
2054 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2056 { .name
= "CNTP_TVAL_S",
2057 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2058 .secure
= ARM_CP_SECSTATE_S
,
2059 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2060 .accessfn
= gt_ptimer_access
,
2061 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2063 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2064 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2065 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2066 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2067 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2069 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2070 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2071 .accessfn
= gt_vtimer_access
,
2072 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2074 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2075 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2076 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2077 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2078 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2080 /* The counter itself */
2081 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2082 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2083 .accessfn
= gt_pct_access
,
2084 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2086 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2087 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2088 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2089 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2091 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2092 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2093 .accessfn
= gt_vct_access
,
2094 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2096 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2097 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2098 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2099 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2101 /* Comparison value, indicating when the timer goes off */
2102 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2103 .secure
= ARM_CP_SECSTATE_NS
,
2104 .access
= PL1_RW
| PL0_R
,
2105 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2106 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2107 .accessfn
= gt_ptimer_access
,
2108 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2110 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
2111 .secure
= ARM_CP_SECSTATE_S
,
2112 .access
= PL1_RW
| PL0_R
,
2113 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2114 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2115 .accessfn
= gt_ptimer_access
,
2116 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2118 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2119 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2120 .access
= PL1_RW
| PL0_R
,
2122 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2123 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2124 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2126 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2127 .access
= PL1_RW
| PL0_R
,
2128 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2129 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2130 .accessfn
= gt_vtimer_access
,
2131 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2133 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2134 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2135 .access
= PL1_RW
| PL0_R
,
2137 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2138 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2139 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2141 /* Secure timer -- this is actually restricted to only EL3
2142 * and configurably Secure-EL1 via the accessfn.
2144 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2145 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2146 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2147 .accessfn
= gt_stimer_access
,
2148 .readfn
= gt_sec_tval_read
,
2149 .writefn
= gt_sec_tval_write
,
2150 .resetfn
= gt_sec_timer_reset
,
2152 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2153 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2154 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2155 .accessfn
= gt_stimer_access
,
2156 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2158 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2160 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2161 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2162 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2163 .accessfn
= gt_stimer_access
,
2164 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2165 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2172 /* In user-mode most of the generic timer registers are inaccessible
2173 * however modern kernels (4.12+) allow access to cntvct_el0
2176 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2178 /* Currently we have no support for QEMUTimer in linux-user so we
2179 * can't call gt_get_countervalue(env), instead we directly
2180 * call the lower level functions.
2182 return cpu_get_clock() / GTIMER_SCALE
;
2185 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2186 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2187 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2188 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
2189 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2190 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
2192 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2193 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2194 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2195 .readfn
= gt_virt_cnt_read
,
2202 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2204 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2205 raw_write(env
, ri
, value
);
2206 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2207 raw_write(env
, ri
, value
& 0xfffff6ff);
2209 raw_write(env
, ri
, value
& 0xfffff1ff);
2213 #ifndef CONFIG_USER_ONLY
2214 /* get_phys_addr() isn't present for user-mode-only targets */
2216 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2220 /* The ATS12NSO* operations must trap to EL3 if executed in
2221 * Secure EL1 (which can only happen if EL3 is AArch64).
2222 * They are simply UNDEF if executed from NS EL1.
2223 * They function normally from EL2 or EL3.
2225 if (arm_current_el(env
) == 1) {
2226 if (arm_is_secure_below_el3(env
)) {
2227 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2229 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2232 return CP_ACCESS_OK
;
2235 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2236 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2239 target_ulong page_size
;
2243 bool format64
= false;
2244 MemTxAttrs attrs
= {};
2245 ARMMMUFaultInfo fi
= {};
2246 ARMCacheAttrs cacheattrs
= {};
2248 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
2249 &prot
, &page_size
, &fi
, &cacheattrs
);
2253 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2256 * * TTBCR.EAE determines whether the result is returned using the
2257 * 32-bit or the 64-bit PAR format
2258 * * Instructions executed in Hyp mode always use the 64bit format
2260 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
2261 * * The Non-secure TTBCR.EAE bit is set to 1
2262 * * The implementation includes EL2, and the value of HCR.VM is 1
2264 * ATS1Hx always uses the 64bit format (not supported yet).
2266 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
2268 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2269 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
2270 format64
|= env
->cp15
.hcr_el2
& HCR_VM
;
2272 format64
|= arm_current_el(env
) == 2;
2278 /* Create a 64-bit PAR */
2279 par64
= (1 << 11); /* LPAE bit always set */
2281 par64
|= phys_addr
& ~0xfffULL
;
2282 if (!attrs
.secure
) {
2283 par64
|= (1 << 9); /* NS */
2285 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
2286 par64
|= cacheattrs
.shareability
<< 7; /* SH */
2288 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
2291 par64
|= (fsr
& 0x3f) << 1; /* FS */
2292 /* Note that S2WLK and FSTAGE are always zero, because we don't
2293 * implement virtualization and therefore there can't be a stage 2
2298 /* fsr is a DFSR/IFSR value for the short descriptor
2299 * translation table format (with WnR always clear).
2300 * Convert it to a 32-bit PAR.
2303 /* We do not set any attribute bits in the PAR */
2304 if (page_size
== (1 << 24)
2305 && arm_feature(env
, ARM_FEATURE_V7
)) {
2306 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2308 par64
= phys_addr
& 0xfffff000;
2310 if (!attrs
.secure
) {
2311 par64
|= (1 << 9); /* NS */
2314 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
2316 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
2317 ((fsr
& 0xf) << 1) | 1;
2323 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2325 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2328 int el
= arm_current_el(env
);
2329 bool secure
= arm_is_secure_below_el3(env
);
2331 switch (ri
->opc2
& 6) {
2333 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2336 mmu_idx
= ARMMMUIdx_S1E3
;
2339 mmu_idx
= ARMMMUIdx_S1NSE1
;
2342 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2345 g_assert_not_reached();
2349 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2352 mmu_idx
= ARMMMUIdx_S1SE0
;
2355 mmu_idx
= ARMMMUIdx_S1NSE0
;
2358 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2361 g_assert_not_reached();
2365 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2366 mmu_idx
= ARMMMUIdx_S12NSE1
;
2369 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2370 mmu_idx
= ARMMMUIdx_S12NSE0
;
2373 g_assert_not_reached();
2376 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
2378 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2381 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2384 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2387 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
2389 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2392 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2395 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
2396 return CP_ACCESS_TRAP
;
2398 return CP_ACCESS_OK
;
2401 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2404 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2406 int secure
= arm_is_secure_below_el3(env
);
2408 switch (ri
->opc2
& 6) {
2411 case 0: /* AT S1E1R, AT S1E1W */
2412 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2414 case 4: /* AT S1E2R, AT S1E2W */
2415 mmu_idx
= ARMMMUIdx_S1E2
;
2417 case 6: /* AT S1E3R, AT S1E3W */
2418 mmu_idx
= ARMMMUIdx_S1E3
;
2421 g_assert_not_reached();
2424 case 2: /* AT S1E0R, AT S1E0W */
2425 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2427 case 4: /* AT S12E1R, AT S12E1W */
2428 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
2430 case 6: /* AT S12E0R, AT S12E0W */
2431 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
2434 g_assert_not_reached();
2437 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
2441 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
2442 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
2443 .access
= PL1_RW
, .resetvalue
= 0,
2444 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
2445 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
2446 .writefn
= par_write
},
2447 #ifndef CONFIG_USER_ONLY
2448 /* This underdecoding is safe because the reginfo is NO_RAW. */
2449 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
2450 .access
= PL1_W
, .accessfn
= ats_access
,
2451 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
2456 /* Return basic MPU access permission bits. */
2457 static uint32_t simple_mpu_ap_bits(uint32_t val
)
2464 for (i
= 0; i
< 16; i
+= 2) {
2465 ret
|= (val
>> i
) & mask
;
2471 /* Pad basic MPU access permission bits to extended format. */
2472 static uint32_t extended_mpu_ap_bits(uint32_t val
)
2479 for (i
= 0; i
< 16; i
+= 2) {
2480 ret
|= (val
& mask
) << i
;
2486 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2489 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
2492 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2494 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
2497 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2500 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2503 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2505 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2508 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2510 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2516 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2520 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2523 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2524 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2530 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2531 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
2535 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2538 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2539 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2541 if (value
>= nrgs
) {
2542 qemu_log_mask(LOG_GUEST_ERROR
,
2543 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2544 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2548 raw_write(env
, ri
, value
);
2551 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2552 /* Reset for all these registers is handled in arm_cpu_reset(),
2553 * because the PMSAv7 is also used by M-profile CPUs, which do
2554 * not register cpregs but still need the state to be reset.
2556 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2557 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2558 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2559 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2560 .resetfn
= arm_cp_reset_ignore
},
2561 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2562 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2563 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2564 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2565 .resetfn
= arm_cp_reset_ignore
},
2566 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2567 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2568 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2569 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2570 .resetfn
= arm_cp_reset_ignore
},
2571 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2573 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
2574 .writefn
= pmsav7_rgnr_write
,
2575 .resetfn
= arm_cp_reset_ignore
},
2579 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2580 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2581 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2582 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2583 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2584 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2585 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2586 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2587 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2588 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2590 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2592 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2594 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2596 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2598 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2599 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2601 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2602 /* Protection region base and size registers */
2603 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2604 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2605 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2606 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2607 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2608 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2609 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2610 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2611 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2612 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2613 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2614 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2615 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2616 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2617 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2618 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2619 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2620 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2621 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2622 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2623 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2624 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2625 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2626 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2630 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2633 TCR
*tcr
= raw_ptr(env
, ri
);
2634 int maskshift
= extract32(value
, 0, 3);
2636 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2637 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2638 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2639 * using Long-desciptor translation table format */
2640 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2641 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2642 /* In an implementation that includes the Security Extensions
2643 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2644 * Short-descriptor translation table format.
2646 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2652 /* Update the masks corresponding to the TCR bank being written
2653 * Note that we always calculate mask and base_mask, but
2654 * they are only used for short-descriptor tables (ie if EAE is 0);
2655 * for long-descriptor tables the TCR fields are used differently
2656 * and the mask and base_mask values are meaningless.
2658 tcr
->raw_tcr
= value
;
2659 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2660 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2663 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2666 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2668 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2669 /* With LPAE the TTBCR could result in a change of ASID
2670 * via the TTBCR.A1 bit, so do a TLB flush.
2672 tlb_flush(CPU(cpu
));
2674 vmsa_ttbcr_raw_write(env
, ri
, value
);
2677 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2679 TCR
*tcr
= raw_ptr(env
, ri
);
2681 /* Reset both the TCR as well as the masks corresponding to the bank of
2682 * the TCR being reset.
2686 tcr
->base_mask
= 0xffffc000u
;
2689 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2692 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2693 TCR
*tcr
= raw_ptr(env
, ri
);
2695 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2696 tlb_flush(CPU(cpu
));
2697 tcr
->raw_tcr
= value
;
2700 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2703 /* 64 bit accesses to the TTBRs can change the ASID and so we
2704 * must flush the TLB.
2706 if (cpreg_field_is_64bit(ri
)) {
2707 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2709 tlb_flush(CPU(cpu
));
2711 raw_write(env
, ri
, value
);
2714 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2717 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2718 CPUState
*cs
= CPU(cpu
);
2720 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2721 if (raw_read(env
, ri
) != value
) {
2722 tlb_flush_by_mmuidx(cs
,
2723 ARMMMUIdxBit_S12NSE1
|
2724 ARMMMUIdxBit_S12NSE0
|
2726 raw_write(env
, ri
, value
);
2730 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2731 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2732 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2733 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2734 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2735 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2736 .access
= PL1_RW
, .resetvalue
= 0,
2737 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2738 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2739 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2740 .access
= PL1_RW
, .resetvalue
= 0,
2741 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2742 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2743 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2744 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2745 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2750 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2751 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2752 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2754 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2755 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2756 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2757 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2758 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2759 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2760 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2761 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2762 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2763 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2764 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2765 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2766 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2767 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2768 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2769 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2770 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2771 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2772 .raw_writefn
= vmsa_ttbcr_raw_write
,
2773 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2774 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2778 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2781 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2782 /* The OS_TYPE bit in this register changes the reported CPUID! */
2783 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2784 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2787 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2790 env
->cp15
.c15_threadid
= value
& 0xffff;
2793 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2796 /* Wait-for-interrupt (deprecated) */
2797 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2800 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2803 /* On OMAP there are registers indicating the max/min index of dcache lines
2804 * containing a dirty line; cache flush operations have to reset these.
2806 env
->cp15
.c15_i_max
= 0x000;
2807 env
->cp15
.c15_i_min
= 0xff0;
2810 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2811 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2812 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2813 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2815 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2816 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2817 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2819 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2820 .writefn
= omap_ticonfig_write
},
2821 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2823 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2824 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2825 .access
= PL1_RW
, .resetvalue
= 0xff0,
2826 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2827 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2829 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2830 .writefn
= omap_threadid_write
},
2831 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2832 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2833 .type
= ARM_CP_NO_RAW
,
2834 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2835 /* TODO: Peripheral port remap register:
2836 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2837 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2840 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2841 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2842 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2843 .writefn
= omap_cachemaint_write
},
2844 { .name
= "C9", .cp
= 15, .crn
= 9,
2845 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2846 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2850 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2853 env
->cp15
.c15_cpar
= value
& 0x3fff;
2856 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2857 { .name
= "XSCALE_CPAR",
2858 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2859 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2860 .writefn
= xscale_cpar_write
, },
2861 { .name
= "XSCALE_AUXCR",
2862 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2863 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2865 /* XScale specific cache-lockdown: since we have no cache we NOP these
2866 * and hope the guest does not really rely on cache behaviour.
2868 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2869 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2870 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2871 { .name
= "XSCALE_UNLOCK_ICACHE",
2872 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2873 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2874 { .name
= "XSCALE_DCACHE_LOCK",
2875 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2876 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2877 { .name
= "XSCALE_UNLOCK_DCACHE",
2878 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2879 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2883 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2884 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2885 * implementation of this implementation-defined space.
2886 * Ideally this should eventually disappear in favour of actually
2887 * implementing the correct behaviour for all cores.
2889 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2890 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2892 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2897 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2898 /* Cache status: RAZ because we have no cache so it's always clean */
2899 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2900 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2905 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2906 /* We never have a a block transfer operation in progress */
2907 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2908 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2910 /* The cache ops themselves: these all NOP for QEMU */
2911 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2912 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2913 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2914 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2915 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2916 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2917 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2918 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2919 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2920 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2921 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2922 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2926 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2927 /* The cache test-and-clean instructions always return (1 << 30)
2928 * to indicate that there are no dirty cache lines.
2930 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2931 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2932 .resetvalue
= (1 << 30) },
2933 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2934 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2935 .resetvalue
= (1 << 30) },
2939 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2940 /* Ignore ReadBuffer accesses */
2941 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2942 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2943 .access
= PL1_RW
, .resetvalue
= 0,
2944 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2948 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2950 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2951 unsigned int cur_el
= arm_current_el(env
);
2952 bool secure
= arm_is_secure(env
);
2954 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2955 return env
->cp15
.vpidr_el2
;
2957 return raw_read(env
, ri
);
2960 static uint64_t mpidr_read_val(CPUARMState
*env
)
2962 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2963 uint64_t mpidr
= cpu
->mp_affinity
;
2965 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2966 mpidr
|= (1U << 31);
2967 /* Cores which are uniprocessor (non-coherent)
2968 * but still implement the MP extensions set
2969 * bit 30. (For instance, Cortex-R5).
2971 if (cpu
->mp_is_up
) {
2972 mpidr
|= (1u << 30);
2978 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2980 unsigned int cur_el
= arm_current_el(env
);
2981 bool secure
= arm_is_secure(env
);
2983 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2984 return env
->cp15
.vmpidr_el2
;
2986 return mpidr_read_val(env
);
2989 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2990 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2991 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2992 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2996 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2998 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2999 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
3000 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3002 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
3003 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
3004 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3006 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
3007 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
3008 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
3009 offsetof(CPUARMState
, cp15
.par_ns
)} },
3010 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
3011 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3012 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3013 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
3014 .writefn
= vmsa_ttbr_write
, },
3015 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
3016 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3017 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3018 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
3019 .writefn
= vmsa_ttbr_write
, },
3023 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3025 return vfp_get_fpcr(env
);
3028 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3031 vfp_set_fpcr(env
, value
);
3034 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3036 return vfp_get_fpsr(env
);
3039 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3042 vfp_set_fpsr(env
, value
);
3045 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3048 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
3049 return CP_ACCESS_TRAP
;
3051 return CP_ACCESS_OK
;
3054 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3057 env
->daif
= value
& PSTATE_DAIF
;
3060 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
3061 const ARMCPRegInfo
*ri
,
3064 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
3065 * SCTLR_EL1.UCI is set.
3067 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
3068 return CP_ACCESS_TRAP
;
3070 return CP_ACCESS_OK
;
3073 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3074 * Page D4-1736 (DDI0487A.b)
3077 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3080 CPUState
*cs
= ENV_GET_CPU(env
);
3082 if (arm_is_secure_below_el3(env
)) {
3083 tlb_flush_by_mmuidx(cs
,
3084 ARMMMUIdxBit_S1SE1
|
3085 ARMMMUIdxBit_S1SE0
);
3087 tlb_flush_by_mmuidx(cs
,
3088 ARMMMUIdxBit_S12NSE1
|
3089 ARMMMUIdxBit_S12NSE0
);
3093 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3096 CPUState
*cs
= ENV_GET_CPU(env
);
3097 bool sec
= arm_is_secure_below_el3(env
);
3100 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3101 ARMMMUIdxBit_S1SE1
|
3102 ARMMMUIdxBit_S1SE0
);
3104 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3105 ARMMMUIdxBit_S12NSE1
|
3106 ARMMMUIdxBit_S12NSE0
);
3110 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3113 /* Note that the 'ALL' scope must invalidate both stage 1 and
3114 * stage 2 translations, whereas most other scopes only invalidate
3115 * stage 1 translations.
3117 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3118 CPUState
*cs
= CPU(cpu
);
3120 if (arm_is_secure_below_el3(env
)) {
3121 tlb_flush_by_mmuidx(cs
,
3122 ARMMMUIdxBit_S1SE1
|
3123 ARMMMUIdxBit_S1SE0
);
3125 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3126 tlb_flush_by_mmuidx(cs
,
3127 ARMMMUIdxBit_S12NSE1
|
3128 ARMMMUIdxBit_S12NSE0
|
3131 tlb_flush_by_mmuidx(cs
,
3132 ARMMMUIdxBit_S12NSE1
|
3133 ARMMMUIdxBit_S12NSE0
);
3138 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3141 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3142 CPUState
*cs
= CPU(cpu
);
3144 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3147 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3150 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3151 CPUState
*cs
= CPU(cpu
);
3153 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3156 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3159 /* Note that the 'ALL' scope must invalidate both stage 1 and
3160 * stage 2 translations, whereas most other scopes only invalidate
3161 * stage 1 translations.
3163 CPUState
*cs
= ENV_GET_CPU(env
);
3164 bool sec
= arm_is_secure_below_el3(env
);
3165 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3168 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3169 ARMMMUIdxBit_S1SE1
|
3170 ARMMMUIdxBit_S1SE0
);
3171 } else if (has_el2
) {
3172 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3173 ARMMMUIdxBit_S12NSE1
|
3174 ARMMMUIdxBit_S12NSE0
|
3177 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3178 ARMMMUIdxBit_S12NSE1
|
3179 ARMMMUIdxBit_S12NSE0
);
3183 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3186 CPUState
*cs
= ENV_GET_CPU(env
);
3188 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3191 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3194 CPUState
*cs
= ENV_GET_CPU(env
);
3196 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3199 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3202 /* Invalidate by VA, EL1&0 (AArch64 version).
3203 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3204 * since we don't support flush-for-specific-ASID-only or
3205 * flush-last-level-only.
3207 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3208 CPUState
*cs
= CPU(cpu
);
3209 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3211 if (arm_is_secure_below_el3(env
)) {
3212 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3213 ARMMMUIdxBit_S1SE1
|
3214 ARMMMUIdxBit_S1SE0
);
3216 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3217 ARMMMUIdxBit_S12NSE1
|
3218 ARMMMUIdxBit_S12NSE0
);
3222 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3225 /* Invalidate by VA, EL2
3226 * Currently handles both VAE2 and VALE2, since we don't support
3227 * flush-last-level-only.
3229 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3230 CPUState
*cs
= CPU(cpu
);
3231 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3233 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3236 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3239 /* Invalidate by VA, EL3
3240 * Currently handles both VAE3 and VALE3, since we don't support
3241 * flush-last-level-only.
3243 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3244 CPUState
*cs
= CPU(cpu
);
3245 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3247 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
3250 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3253 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3254 CPUState
*cs
= CPU(cpu
);
3255 bool sec
= arm_is_secure_below_el3(env
);
3256 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3259 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3260 ARMMMUIdxBit_S1SE1
|
3261 ARMMMUIdxBit_S1SE0
);
3263 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3264 ARMMMUIdxBit_S12NSE1
|
3265 ARMMMUIdxBit_S12NSE0
);
3269 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3272 CPUState
*cs
= ENV_GET_CPU(env
);
3273 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3275 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3279 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3282 CPUState
*cs
= ENV_GET_CPU(env
);
3283 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3285 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3289 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3292 /* Invalidate by IPA. This has to invalidate any structures that
3293 * contain only stage 2 translation information, but does not need
3294 * to apply to structures that contain combined stage 1 and stage 2
3295 * translation information.
3296 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3298 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3299 CPUState
*cs
= CPU(cpu
);
3302 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3306 pageaddr
= sextract64(value
<< 12, 0, 48);
3308 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
3311 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3314 CPUState
*cs
= ENV_GET_CPU(env
);
3317 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3321 pageaddr
= sextract64(value
<< 12, 0, 48);
3323 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3327 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3330 /* We don't implement EL2, so the only control on DC ZVA is the
3331 * bit in the SCTLR which can prohibit access for EL0.
3333 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
3334 return CP_ACCESS_TRAP
;
3336 return CP_ACCESS_OK
;
3339 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3341 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3342 int dzp_bit
= 1 << 4;
3344 /* DZP indicates whether DC ZVA access is allowed */
3345 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
3348 return cpu
->dcz_blocksize
| dzp_bit
;
3351 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3354 if (!(env
->pstate
& PSTATE_SP
)) {
3355 /* Access to SP_EL0 is undefined if it's being used as
3356 * the stack pointer.
3358 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3360 return CP_ACCESS_OK
;
3363 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3365 return env
->pstate
& PSTATE_SP
;
3368 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
3370 update_spsel(env
, val
);
3373 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3376 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3378 if (raw_read(env
, ri
) == value
) {
3379 /* Skip the TLB flush if nothing actually changed; Linux likes
3380 * to do a lot of pointless SCTLR writes.
3385 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
3386 /* M bit is RAZ/WI for PMSA with no MPU implemented */
3390 raw_write(env
, ri
, value
);
3391 /* ??? Lots of these bits are not implemented. */
3392 /* This may enable/disable the MMU, so do a TLB flush. */
3393 tlb_flush(CPU(cpu
));
3396 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3399 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
3400 return CP_ACCESS_TRAP_FP_EL2
;
3402 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
3403 return CP_ACCESS_TRAP_FP_EL3
;
3405 return CP_ACCESS_OK
;
3408 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3411 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
3414 static const ARMCPRegInfo v8_cp_reginfo
[] = {
3415 /* Minimal set of EL0-visible registers. This will need to be expanded
3416 * significantly for system emulation of AArch64 CPUs.
3418 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
3419 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
3420 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
3421 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
3422 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
3423 .type
= ARM_CP_NO_RAW
,
3424 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
3425 .fieldoffset
= offsetof(CPUARMState
, daif
),
3426 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
3427 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
3428 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
3429 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
3430 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
3431 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
3432 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
3433 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
3434 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
3435 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
3436 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
3437 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
3438 .readfn
= aa64_dczid_read
},
3439 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
3440 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
3441 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
3442 #ifndef CONFIG_USER_ONLY
3443 /* Avoid overhead of an access check that always passes in user-mode */
3444 .accessfn
= aa64_zva_access
,
3447 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
3448 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
3449 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
3450 /* Cache ops: all NOPs since we don't emulate caches */
3451 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
3452 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3453 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3454 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
3455 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3456 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3457 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
3458 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
3459 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3460 .accessfn
= aa64_cacheop_access
},
3461 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
3462 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3463 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3464 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
3465 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3466 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3467 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
3468 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
3469 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3470 .accessfn
= aa64_cacheop_access
},
3471 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
3472 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3473 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3474 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
3475 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
3476 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3477 .accessfn
= aa64_cacheop_access
},
3478 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
3479 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
3480 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3481 .accessfn
= aa64_cacheop_access
},
3482 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
3483 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3484 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3485 /* TLBI operations */
3486 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
3487 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
3488 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3489 .writefn
= tlbi_aa64_vmalle1is_write
},
3490 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
3491 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
3492 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3493 .writefn
= tlbi_aa64_vae1is_write
},
3494 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
3495 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
3496 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3497 .writefn
= tlbi_aa64_vmalle1is_write
},
3498 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
3499 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
3500 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3501 .writefn
= tlbi_aa64_vae1is_write
},
3502 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
3503 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3504 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3505 .writefn
= tlbi_aa64_vae1is_write
},
3506 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
3507 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3508 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3509 .writefn
= tlbi_aa64_vae1is_write
},
3510 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
3511 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
3512 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3513 .writefn
= tlbi_aa64_vmalle1_write
},
3514 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
3515 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
3516 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3517 .writefn
= tlbi_aa64_vae1_write
},
3518 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
3519 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
3520 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3521 .writefn
= tlbi_aa64_vmalle1_write
},
3522 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
3523 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
3524 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3525 .writefn
= tlbi_aa64_vae1_write
},
3526 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
3527 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3528 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3529 .writefn
= tlbi_aa64_vae1_write
},
3530 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
3531 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3532 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3533 .writefn
= tlbi_aa64_vae1_write
},
3534 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
3535 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3536 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3537 .writefn
= tlbi_aa64_ipas2e1is_write
},
3538 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3539 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3540 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3541 .writefn
= tlbi_aa64_ipas2e1is_write
},
3542 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3543 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3544 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3545 .writefn
= tlbi_aa64_alle1is_write
},
3546 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3547 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3548 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3549 .writefn
= tlbi_aa64_alle1is_write
},
3550 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3551 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3552 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3553 .writefn
= tlbi_aa64_ipas2e1_write
},
3554 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3555 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3556 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3557 .writefn
= tlbi_aa64_ipas2e1_write
},
3558 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3559 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3560 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3561 .writefn
= tlbi_aa64_alle1_write
},
3562 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3563 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3564 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3565 .writefn
= tlbi_aa64_alle1is_write
},
3566 #ifndef CONFIG_USER_ONLY
3567 /* 64 bit address translation operations */
3568 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3569 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3570 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3571 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3572 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3573 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3574 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3575 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3576 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3577 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3578 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3579 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3580 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3581 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3582 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3583 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3584 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3585 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3586 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3587 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3588 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3589 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3590 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3591 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3592 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3593 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3594 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3595 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3596 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3597 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3598 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3599 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3600 .type
= ARM_CP_ALIAS
,
3601 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3602 .access
= PL1_RW
, .resetvalue
= 0,
3603 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3604 .writefn
= par_write
},
3606 /* TLB invalidate last level of translation table walk */
3607 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3608 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3609 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3610 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3611 .writefn
= tlbimvaa_is_write
},
3612 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3613 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3614 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3615 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3616 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3617 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3618 .writefn
= tlbimva_hyp_write
},
3619 { .name
= "TLBIMVALHIS",
3620 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3621 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3622 .writefn
= tlbimva_hyp_is_write
},
3623 { .name
= "TLBIIPAS2",
3624 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3625 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3626 .writefn
= tlbiipas2_write
},
3627 { .name
= "TLBIIPAS2IS",
3628 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3629 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3630 .writefn
= tlbiipas2_is_write
},
3631 { .name
= "TLBIIPAS2L",
3632 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3633 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3634 .writefn
= tlbiipas2_write
},
3635 { .name
= "TLBIIPAS2LIS",
3636 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3637 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3638 .writefn
= tlbiipas2_is_write
},
3639 /* 32 bit cache operations */
3640 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3641 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3642 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3643 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3644 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3645 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3646 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3647 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3648 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3649 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3650 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3651 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3652 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3653 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3654 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3655 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3656 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3657 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3658 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3659 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3660 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3661 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3662 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3663 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3664 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3665 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3666 /* MMU Domain access control / MPU write buffer control */
3667 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3668 .access
= PL1_RW
, .resetvalue
= 0,
3669 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3670 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3671 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3672 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3673 .type
= ARM_CP_ALIAS
,
3674 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3676 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3677 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3678 .type
= ARM_CP_ALIAS
,
3679 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3681 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
3682 /* We rely on the access checks not allowing the guest to write to the
3683 * state field when SPSel indicates that it's being used as the stack
3686 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3687 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3688 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3689 .type
= ARM_CP_ALIAS
,
3690 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3691 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3692 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3693 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3694 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3695 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3696 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3697 .type
= ARM_CP_NO_RAW
,
3698 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3699 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
3700 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
3701 .type
= ARM_CP_ALIAS
,
3702 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
3703 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
3704 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3705 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3706 .access
= PL2_RW
, .resetvalue
= 0,
3707 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3708 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3709 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3710 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3711 .access
= PL2_RW
, .resetvalue
= 0,
3712 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3713 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
3714 .type
= ARM_CP_ALIAS
,
3715 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
3717 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
3718 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
3719 .type
= ARM_CP_ALIAS
,
3720 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
3722 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
3723 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
3724 .type
= ARM_CP_ALIAS
,
3725 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
3727 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
3728 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
3729 .type
= ARM_CP_ALIAS
,
3730 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
3732 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
3733 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
3734 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
3736 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
3737 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
3738 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
3739 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3740 .writefn
= sdcr_write
,
3741 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
3745 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3746 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3747 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3748 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3750 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3751 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3752 .type
= ARM_CP_NO_RAW
,
3753 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3755 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3756 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3757 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3758 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3759 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3760 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3761 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3763 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3764 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3765 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3766 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3767 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3768 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3770 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3771 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3772 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3774 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3775 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3776 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3778 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3779 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3780 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3782 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3783 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3784 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3785 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3786 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3787 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3788 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3789 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3790 .cp
= 15, .opc1
= 6, .crm
= 2,
3791 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3792 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3793 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3794 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3795 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3796 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3797 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3798 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3799 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3800 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3801 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3802 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3803 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3804 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3805 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3806 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3808 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3809 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3810 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3811 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3812 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3813 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3814 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3815 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3817 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3818 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3819 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3820 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3821 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3823 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3824 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3825 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3826 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3827 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3828 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3829 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3830 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3831 .access
= PL2_RW
, .accessfn
= access_tda
,
3832 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3833 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3834 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3835 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3836 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3837 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3838 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3839 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3843 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3845 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3846 uint64_t valid_mask
= HCR_MASK
;
3848 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3849 valid_mask
&= ~HCR_HCD
;
3850 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
3851 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
3852 * However, if we're using the SMC PSCI conduit then QEMU is
3853 * effectively acting like EL3 firmware and so the guest at
3854 * EL2 should retain the ability to prevent EL1 from being
3855 * able to make SMC calls into the ersatz firmware, so in
3856 * that case HCR.TSC should be read/write.
3858 valid_mask
&= ~HCR_TSC
;
3861 /* Clear RES0 bits. */
3862 value
&= valid_mask
;
3864 /* These bits change the MMU setup:
3865 * HCR_VM enables stage 2 translation
3866 * HCR_PTW forbids certain page-table setups
3867 * HCR_DC Disables stage1 and enables stage2 translation
3869 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3870 tlb_flush(CPU(cpu
));
3872 raw_write(env
, ri
, value
);
3875 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3876 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3877 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3878 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3879 .writefn
= hcr_write
},
3880 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3881 .type
= ARM_CP_ALIAS
,
3882 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3884 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3885 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
3886 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3887 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3888 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
3889 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3890 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3891 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3892 .type
= ARM_CP_ALIAS
,
3893 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3895 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
3896 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3897 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3898 .access
= PL2_RW
, .writefn
= vbar_write
,
3899 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3901 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3902 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3903 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3904 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3905 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3906 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3907 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3908 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3909 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3910 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3911 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3913 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3914 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3915 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3916 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3917 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3918 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3919 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3921 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3922 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3923 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3924 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3926 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3927 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3928 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3930 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3931 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3932 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3934 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3935 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3937 /* no .writefn needed as this can't cause an ASID change;
3938 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3940 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3941 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3942 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3943 .type
= ARM_CP_ALIAS
,
3944 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3945 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3946 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3947 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3949 /* no .writefn needed as this can't cause an ASID change;
3950 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3952 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3953 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3954 .cp
= 15, .opc1
= 6, .crm
= 2,
3955 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3956 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3957 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
3958 .writefn
= vttbr_write
},
3959 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3960 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3961 .access
= PL2_RW
, .writefn
= vttbr_write
,
3962 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
3963 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3964 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3965 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3966 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
3967 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3968 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3969 .access
= PL2_RW
, .resetvalue
= 0,
3970 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
3971 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3972 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3973 .access
= PL2_RW
, .resetvalue
= 0,
3974 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3975 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3976 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3977 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3978 { .name
= "TLBIALLNSNH",
3979 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3980 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3981 .writefn
= tlbiall_nsnh_write
},
3982 { .name
= "TLBIALLNSNHIS",
3983 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3984 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3985 .writefn
= tlbiall_nsnh_is_write
},
3986 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3987 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3988 .writefn
= tlbiall_hyp_write
},
3989 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3990 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3991 .writefn
= tlbiall_hyp_is_write
},
3992 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3993 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3994 .writefn
= tlbimva_hyp_write
},
3995 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3996 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3997 .writefn
= tlbimva_hyp_is_write
},
3998 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
3999 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4000 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4001 .writefn
= tlbi_aa64_alle2_write
},
4002 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
4003 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4004 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4005 .writefn
= tlbi_aa64_vae2_write
},
4006 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
4007 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4008 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4009 .writefn
= tlbi_aa64_vae2_write
},
4010 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
4011 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4012 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4013 .writefn
= tlbi_aa64_alle2is_write
},
4014 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
4015 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4016 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4017 .writefn
= tlbi_aa64_vae2is_write
},
4018 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
4019 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4020 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4021 .writefn
= tlbi_aa64_vae2is_write
},
4022 #ifndef CONFIG_USER_ONLY
4023 /* Unlike the other EL2-related AT operations, these must
4024 * UNDEF from EL3 if EL2 is not implemented, which is why we
4025 * define them here rather than with the rest of the AT ops.
4027 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
4028 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4029 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4030 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4031 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
4032 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4033 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
4034 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
4035 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
4036 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
4037 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
4038 * to behave as if SCR.NS was 1.
4040 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
4042 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
4043 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
4045 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
4046 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4047 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4048 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
4049 * reset values as IMPDEF. We choose to reset to 3 to comply with
4050 * both ARMv7 and ARMv8.
4052 .access
= PL2_RW
, .resetvalue
= 3,
4053 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
4054 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4055 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4056 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
4057 .writefn
= gt_cntvoff_write
,
4058 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
4059 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4060 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
4061 .writefn
= gt_cntvoff_write
,
4062 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
4063 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4064 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4065 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4066 .type
= ARM_CP_IO
, .access
= PL2_RW
,
4067 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4068 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4069 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
4070 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
4071 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4072 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4073 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4074 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
4075 .resetfn
= gt_hyp_timer_reset
,
4076 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
4077 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4079 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4081 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
4083 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
4085 /* The only field of MDCR_EL2 that has a defined architectural reset value
4086 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
4087 * don't impelment any PMU event counters, so using zero as a reset
4088 * value for MDCR_EL2 is okay
4090 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4091 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4092 .access
= PL2_RW
, .resetvalue
= 0,
4093 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
4094 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
4095 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4096 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4097 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4098 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
4099 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4101 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4102 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4103 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4105 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
4109 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4112 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
4113 * At Secure EL1 it traps to EL3.
4115 if (arm_current_el(env
) == 3) {
4116 return CP_ACCESS_OK
;
4118 if (arm_is_secure_below_el3(env
)) {
4119 return CP_ACCESS_TRAP_EL3
;
4121 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
4123 return CP_ACCESS_OK
;
4125 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4128 static const ARMCPRegInfo el3_cp_reginfo
[] = {
4129 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
4130 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
4131 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
4132 .resetvalue
= 0, .writefn
= scr_write
},
4133 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
4134 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
4135 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4136 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
4137 .writefn
= scr_write
},
4138 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
4139 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
4140 .access
= PL3_RW
, .resetvalue
= 0,
4141 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
4143 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
4144 .access
= PL3_RW
, .resetvalue
= 0,
4145 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
4146 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4147 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4148 .writefn
= vbar_write
, .resetvalue
= 0,
4149 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
4150 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
4151 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
4152 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4153 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
4154 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
4155 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
4157 /* no .writefn needed as this can't cause an ASID change;
4158 * we must provide a .raw_writefn and .resetfn because we handle
4159 * reset and migration for the AArch32 TTBCR(S), which might be
4160 * using mask and base_mask.
4162 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
4163 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
4164 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
4165 .type
= ARM_CP_ALIAS
,
4166 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
4168 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
4169 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
4170 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
4171 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
4172 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
4173 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
4174 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
4175 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
4176 .type
= ARM_CP_ALIAS
,
4177 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
4179 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
4180 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4181 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
4182 .access
= PL3_RW
, .writefn
= vbar_write
,
4183 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
4185 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
4186 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
4187 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4188 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
4189 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
4190 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
4191 .access
= PL3_RW
, .resetvalue
= 0,
4192 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
4193 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
4194 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
4195 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4197 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
4198 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
4199 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4201 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
4202 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
4203 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4205 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
4206 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
4207 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4208 .writefn
= tlbi_aa64_alle3is_write
},
4209 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
4210 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
4211 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4212 .writefn
= tlbi_aa64_vae3is_write
},
4213 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
4214 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
4215 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4216 .writefn
= tlbi_aa64_vae3is_write
},
4217 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
4218 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
4219 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4220 .writefn
= tlbi_aa64_alle3_write
},
4221 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
4222 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
4223 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4224 .writefn
= tlbi_aa64_vae3_write
},
4225 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
4226 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
4227 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4228 .writefn
= tlbi_aa64_vae3_write
},
4232 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4235 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4236 * but the AArch32 CTR has its own reginfo struct)
4238 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
4239 return CP_ACCESS_TRAP
;
4241 return CP_ACCESS_OK
;
4244 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4247 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4248 * read via a bit in OSLSR_EL1.
4252 if (ri
->state
== ARM_CP_STATE_AA32
) {
4253 oslock
= (value
== 0xC5ACCE55);
4258 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
4261 static const ARMCPRegInfo debug_cp_reginfo
[] = {
4262 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4263 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4264 * unlike DBGDRAR it is never accessible from EL0.
4265 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4268 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
4269 .access
= PL0_R
, .accessfn
= access_tdra
,
4270 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4271 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
4272 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4273 .access
= PL1_R
, .accessfn
= access_tdra
,
4274 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4275 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4276 .access
= PL0_R
, .accessfn
= access_tdra
,
4277 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4278 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4279 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
4280 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4281 .access
= PL1_RW
, .accessfn
= access_tda
,
4282 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
4284 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4285 * We don't implement the configurable EL0 access.
4287 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
4288 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4289 .type
= ARM_CP_ALIAS
,
4290 .access
= PL1_R
, .accessfn
= access_tda
,
4291 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
4292 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
4293 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
4294 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4295 .accessfn
= access_tdosa
,
4296 .writefn
= oslar_write
},
4297 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
4298 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
4299 .access
= PL1_R
, .resetvalue
= 10,
4300 .accessfn
= access_tdosa
,
4301 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
4302 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4303 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4304 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
4305 .access
= PL1_RW
, .accessfn
= access_tdosa
,
4306 .type
= ARM_CP_NOP
},
4307 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4308 * implement vector catch debug events yet.
4311 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4312 .access
= PL1_RW
, .accessfn
= access_tda
,
4313 .type
= ARM_CP_NOP
},
4314 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4315 * to save and restore a 32-bit guest's DBGVCR)
4317 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
4318 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
4319 .access
= PL2_RW
, .accessfn
= access_tda
,
4320 .type
= ARM_CP_NOP
},
4321 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4322 * Channel but Linux may try to access this register. The 32-bit
4323 * alias is DBGDCCINT.
4325 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
4326 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4327 .access
= PL1_RW
, .accessfn
= access_tda
,
4328 .type
= ARM_CP_NOP
},
4332 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
4333 /* 64 bit access versions of the (dummy) debug registers */
4334 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
4335 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4336 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
4337 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4341 /* Return the exception level to which SVE-disabled exceptions should
4342 * be taken, or 0 if SVE is enabled.
4344 static int sve_exception_el(CPUARMState
*env
)
4346 #ifndef CONFIG_USER_ONLY
4347 unsigned current_el
= arm_current_el(env
);
4349 /* The CPACR.ZEN controls traps to EL1:
4350 * 0, 2 : trap EL0 and EL1 accesses
4351 * 1 : trap only EL0 accesses
4352 * 3 : trap no accesses
4354 switch (extract32(env
->cp15
.cpacr_el1
, 16, 2)) {
4356 if (current_el
<= 1) {
4357 /* Trap to PL1, which might be EL1 or EL3 */
4358 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
4365 if (current_el
== 0) {
4373 /* Similarly for CPACR.FPEN, after having checked ZEN. */
4374 switch (extract32(env
->cp15
.cpacr_el1
, 20, 2)) {
4376 if (current_el
<= 1) {
4377 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
4384 if (current_el
== 0) {
4392 /* CPTR_EL2. Check both TZ and TFP. */
4394 && (env
->cp15
.cptr_el
[2] & (CPTR_TFP
| CPTR_TZ
))
4395 && !arm_is_secure_below_el3(env
)) {
4399 /* CPTR_EL3. Check both EZ and TFP. */
4400 if (!(env
->cp15
.cptr_el
[3] & CPTR_EZ
)
4401 || (env
->cp15
.cptr_el
[3] & CPTR_TFP
)) {
4408 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4411 /* Bits other than [3:0] are RAZ/WI. */
4412 raw_write(env
, ri
, value
& 0xf);
4415 static const ARMCPRegInfo zcr_el1_reginfo
= {
4416 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
4417 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
4418 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
4419 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
4420 .writefn
= zcr_write
, .raw_writefn
= raw_write
4423 static const ARMCPRegInfo zcr_el2_reginfo
= {
4424 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
4425 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
4426 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
4427 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
4428 .writefn
= zcr_write
, .raw_writefn
= raw_write
4431 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
4432 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
4433 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
4434 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
4435 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
4438 static const ARMCPRegInfo zcr_el3_reginfo
= {
4439 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
4440 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
4441 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
4442 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
4443 .writefn
= zcr_write
, .raw_writefn
= raw_write
4446 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
4448 CPUARMState
*env
= &cpu
->env
;
4450 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
4451 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
4453 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
4455 if (env
->cpu_watchpoint
[n
]) {
4456 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
4457 env
->cpu_watchpoint
[n
] = NULL
;
4460 if (!extract64(wcr
, 0, 1)) {
4461 /* E bit clear : watchpoint disabled */
4465 switch (extract64(wcr
, 3, 2)) {
4467 /* LSC 00 is reserved and must behave as if the wp is disabled */
4470 flags
|= BP_MEM_READ
;
4473 flags
|= BP_MEM_WRITE
;
4476 flags
|= BP_MEM_ACCESS
;
4480 /* Attempts to use both MASK and BAS fields simultaneously are
4481 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4482 * thus generating a watchpoint for every byte in the masked region.
4484 mask
= extract64(wcr
, 24, 4);
4485 if (mask
== 1 || mask
== 2) {
4486 /* Reserved values of MASK; we must act as if the mask value was
4487 * some non-reserved value, or as if the watchpoint were disabled.
4488 * We choose the latter.
4492 /* Watchpoint covers an aligned area up to 2GB in size */
4494 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4495 * whether the watchpoint fires when the unmasked bits match; we opt
4496 * to generate the exceptions.
4500 /* Watchpoint covers bytes defined by the byte address select bits */
4501 int bas
= extract64(wcr
, 5, 8);
4505 /* This must act as if the watchpoint is disabled */
4509 if (extract64(wvr
, 2, 1)) {
4510 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4511 * ignored, and BAS[3:0] define which bytes to watch.
4515 /* The BAS bits are supposed to be programmed to indicate a contiguous
4516 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4517 * we fire for each byte in the word/doubleword addressed by the WVR.
4518 * We choose to ignore any non-zero bits after the first range of 1s.
4520 basstart
= ctz32(bas
);
4521 len
= cto32(bas
>> basstart
);
4525 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
4526 &env
->cpu_watchpoint
[n
]);
4529 void hw_watchpoint_update_all(ARMCPU
*cpu
)
4532 CPUARMState
*env
= &cpu
->env
;
4534 /* Completely clear out existing QEMU watchpoints and our array, to
4535 * avoid possible stale entries following migration load.
4537 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
4538 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
4540 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
4541 hw_watchpoint_update(cpu
, i
);
4545 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4548 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4551 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4552 * register reads and behaves as if values written are sign extended.
4553 * Bits [1:0] are RES0.
4555 value
= sextract64(value
, 0, 49) & ~3ULL;
4557 raw_write(env
, ri
, value
);
4558 hw_watchpoint_update(cpu
, i
);
4561 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4564 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4567 raw_write(env
, ri
, value
);
4568 hw_watchpoint_update(cpu
, i
);
4571 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
4573 CPUARMState
*env
= &cpu
->env
;
4574 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
4575 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
4580 if (env
->cpu_breakpoint
[n
]) {
4581 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
4582 env
->cpu_breakpoint
[n
] = NULL
;
4585 if (!extract64(bcr
, 0, 1)) {
4586 /* E bit clear : watchpoint disabled */
4590 bt
= extract64(bcr
, 20, 4);
4593 case 4: /* unlinked address mismatch (reserved if AArch64) */
4594 case 5: /* linked address mismatch (reserved if AArch64) */
4595 qemu_log_mask(LOG_UNIMP
,
4596 "arm: address mismatch breakpoint types not implemented\n");
4598 case 0: /* unlinked address match */
4599 case 1: /* linked address match */
4601 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4602 * we behave as if the register was sign extended. Bits [1:0] are
4603 * RES0. The BAS field is used to allow setting breakpoints on 16
4604 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4605 * a bp will fire if the addresses covered by the bp and the addresses
4606 * covered by the insn overlap but the insn doesn't start at the
4607 * start of the bp address range. We choose to require the insn and
4608 * the bp to have the same address. The constraints on writing to
4609 * BAS enforced in dbgbcr_write mean we have only four cases:
4610 * 0b0000 => no breakpoint
4611 * 0b0011 => breakpoint on addr
4612 * 0b1100 => breakpoint on addr + 2
4613 * 0b1111 => breakpoint on addr
4614 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4616 int bas
= extract64(bcr
, 5, 4);
4617 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
4626 case 2: /* unlinked context ID match */
4627 case 8: /* unlinked VMID match (reserved if no EL2) */
4628 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4629 qemu_log_mask(LOG_UNIMP
,
4630 "arm: unlinked context breakpoint types not implemented\n");
4632 case 9: /* linked VMID match (reserved if no EL2) */
4633 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4634 case 3: /* linked context ID match */
4636 /* We must generate no events for Linked context matches (unless
4637 * they are linked to by some other bp/wp, which is handled in
4638 * updates for the linking bp/wp). We choose to also generate no events
4639 * for reserved values.
4644 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
4647 void hw_breakpoint_update_all(ARMCPU
*cpu
)
4650 CPUARMState
*env
= &cpu
->env
;
4652 /* Completely clear out existing QEMU breakpoints and our array, to
4653 * avoid possible stale entries following migration load.
4655 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
4656 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
4658 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
4659 hw_breakpoint_update(cpu
, i
);
4663 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4666 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4669 raw_write(env
, ri
, value
);
4670 hw_breakpoint_update(cpu
, i
);
4673 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4676 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4679 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4682 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
4683 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
4685 raw_write(env
, ri
, value
);
4686 hw_breakpoint_update(cpu
, i
);
4689 static void define_debug_regs(ARMCPU
*cpu
)
4691 /* Define v7 and v8 architectural debug registers.
4692 * These are just dummy implementations for now.
4695 int wrps
, brps
, ctx_cmps
;
4696 ARMCPRegInfo dbgdidr
= {
4697 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
4698 .access
= PL0_R
, .accessfn
= access_tda
,
4699 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
4702 /* Note that all these register fields hold "number of Xs minus 1". */
4703 brps
= extract32(cpu
->dbgdidr
, 24, 4);
4704 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
4705 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
4707 assert(ctx_cmps
<= brps
);
4709 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4710 * of the debug registers such as number of breakpoints;
4711 * check that if they both exist then they agree.
4713 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
4714 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
4715 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
4716 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
4719 define_one_arm_cp_reg(cpu
, &dbgdidr
);
4720 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
4722 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
4723 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
4726 for (i
= 0; i
< brps
+ 1; i
++) {
4727 ARMCPRegInfo dbgregs
[] = {
4728 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
4729 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
4730 .access
= PL1_RW
, .accessfn
= access_tda
,
4731 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
4732 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
4734 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
4735 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
4736 .access
= PL1_RW
, .accessfn
= access_tda
,
4737 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
4738 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
4742 define_arm_cp_regs(cpu
, dbgregs
);
4745 for (i
= 0; i
< wrps
+ 1; i
++) {
4746 ARMCPRegInfo dbgregs
[] = {
4747 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
4748 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
4749 .access
= PL1_RW
, .accessfn
= access_tda
,
4750 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
4751 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
4753 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
4754 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
4755 .access
= PL1_RW
, .accessfn
= access_tda
,
4756 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
4757 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
4761 define_arm_cp_regs(cpu
, dbgregs
);
4765 /* We don't know until after realize whether there's a GICv3
4766 * attached, and that is what registers the gicv3 sysregs.
4767 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
4770 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4772 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4773 uint64_t pfr1
= cpu
->id_pfr1
;
4775 if (env
->gicv3state
) {
4781 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4783 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4784 uint64_t pfr0
= cpu
->id_aa64pfr0
;
4786 if (env
->gicv3state
) {
4792 void register_cp_regs_for_features(ARMCPU
*cpu
)
4794 /* Register all the coprocessor registers based on feature bits */
4795 CPUARMState
*env
= &cpu
->env
;
4796 if (arm_feature(env
, ARM_FEATURE_M
)) {
4797 /* M profile has no coprocessor registers */
4801 define_arm_cp_regs(cpu
, cp_reginfo
);
4802 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4803 /* Must go early as it is full of wildcards that may be
4804 * overridden by later definitions.
4806 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
4809 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4810 /* The ID registers all have impdef reset values */
4811 ARMCPRegInfo v6_idregs
[] = {
4812 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
4813 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4814 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4815 .resetvalue
= cpu
->id_pfr0
},
4816 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
4817 * the value of the GIC field until after we define these regs.
4819 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
4820 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
4821 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
4822 .readfn
= id_pfr1_read
,
4823 .writefn
= arm_cp_write_ignore
},
4824 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
4825 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
4826 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4827 .resetvalue
= cpu
->id_dfr0
},
4828 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
4829 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
4830 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4831 .resetvalue
= cpu
->id_afr0
},
4832 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
4833 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
4834 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4835 .resetvalue
= cpu
->id_mmfr0
},
4836 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
4837 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
4838 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4839 .resetvalue
= cpu
->id_mmfr1
},
4840 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
4841 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
4842 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4843 .resetvalue
= cpu
->id_mmfr2
},
4844 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
4845 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
4846 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4847 .resetvalue
= cpu
->id_mmfr3
},
4848 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
4849 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4850 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4851 .resetvalue
= cpu
->id_isar0
},
4852 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
4853 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
4854 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4855 .resetvalue
= cpu
->id_isar1
},
4856 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
4857 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4858 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4859 .resetvalue
= cpu
->id_isar2
},
4860 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4861 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4862 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4863 .resetvalue
= cpu
->id_isar3
},
4864 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4865 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4866 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4867 .resetvalue
= cpu
->id_isar4
},
4868 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4869 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4870 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4871 .resetvalue
= cpu
->id_isar5
},
4872 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
4873 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
4874 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4875 .resetvalue
= cpu
->id_mmfr4
},
4876 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
4877 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
4878 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4879 .resetvalue
= cpu
->id_isar6
},
4882 define_arm_cp_regs(cpu
, v6_idregs
);
4883 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4885 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4887 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4888 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4890 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4891 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
4892 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4894 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4895 /* v7 performance monitor control register: same implementor
4896 * field as main ID register, and we implement only the cycle
4899 #ifndef CONFIG_USER_ONLY
4900 ARMCPRegInfo pmcr
= {
4901 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4903 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4904 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4905 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4906 .raw_writefn
= raw_write
,
4908 ARMCPRegInfo pmcr64
= {
4909 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4910 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
4911 .access
= PL0_RW
, .accessfn
= pmreg_access
,
4913 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
4914 .resetvalue
= cpu
->midr
& 0xff000000,
4915 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
4917 define_one_arm_cp_reg(cpu
, &pmcr
);
4918 define_one_arm_cp_reg(cpu
, &pmcr64
);
4920 ARMCPRegInfo clidr
= {
4921 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
4922 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
4923 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
4925 define_one_arm_cp_reg(cpu
, &clidr
);
4926 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
4927 define_debug_regs(cpu
);
4929 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
4931 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4932 /* AArch64 ID registers, which all have impdef reset values.
4933 * Note that within the ID register ranges the unused slots
4934 * must all RAZ, not UNDEF; future architecture versions may
4935 * define new registers here.
4937 ARMCPRegInfo v8_idregs
[] = {
4938 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
4939 * know the right value for the GIC field until after we
4940 * define these regs.
4942 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4943 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
4944 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
4945 .readfn
= id_aa64pfr0_read
,
4946 .writefn
= arm_cp_write_ignore
},
4947 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4948 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
4949 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4950 .resetvalue
= cpu
->id_aa64pfr1
},
4951 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4952 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
4953 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4955 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4956 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
4957 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4959 { .name
= "ID_AA64PFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4960 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
4961 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4963 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4964 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
4965 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4967 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4968 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
4969 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4971 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4972 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
4973 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4975 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4976 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
4977 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4978 .resetvalue
= cpu
->id_aa64dfr0
},
4979 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4980 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
4981 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4982 .resetvalue
= cpu
->id_aa64dfr1
},
4983 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4984 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
4985 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4987 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4988 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
4989 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4991 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4992 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
4993 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4994 .resetvalue
= cpu
->id_aa64afr0
},
4995 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4996 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
4997 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4998 .resetvalue
= cpu
->id_aa64afr1
},
4999 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5000 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
5001 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5003 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5004 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
5005 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5007 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
5008 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
5009 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5010 .resetvalue
= cpu
->id_aa64isar0
},
5011 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
5012 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
5013 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5014 .resetvalue
= cpu
->id_aa64isar1
},
5015 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5016 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
5017 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5019 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5020 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
5021 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5023 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5024 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
5025 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5027 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5028 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
5029 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5031 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5032 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
5033 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5035 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5036 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
5037 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5039 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5040 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5041 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5042 .resetvalue
= cpu
->id_aa64mmfr0
},
5043 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5044 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
5045 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5046 .resetvalue
= cpu
->id_aa64mmfr1
},
5047 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5048 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
5049 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5051 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5052 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
5053 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5055 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5056 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
5057 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5059 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5060 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
5061 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5063 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5064 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
5065 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5067 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5068 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
5069 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5071 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
5072 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
5073 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5074 .resetvalue
= cpu
->mvfr0
},
5075 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
5076 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
5077 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5078 .resetvalue
= cpu
->mvfr1
},
5079 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
5080 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
5081 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5082 .resetvalue
= cpu
->mvfr2
},
5083 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5084 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
5085 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5087 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5088 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
5089 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5091 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5092 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
5093 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5095 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5096 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
5097 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5099 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
5100 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
5101 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5103 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
5104 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
5105 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5106 .resetvalue
= cpu
->pmceid0
},
5107 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
5108 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
5109 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5110 .resetvalue
= cpu
->pmceid0
},
5111 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
5112 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
5113 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5114 .resetvalue
= cpu
->pmceid1
},
5115 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
5116 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
5117 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
5118 .resetvalue
= cpu
->pmceid1
},
5121 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
5122 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
5123 !arm_feature(env
, ARM_FEATURE_EL2
)) {
5124 ARMCPRegInfo rvbar
= {
5125 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5126 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5127 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
5129 define_one_arm_cp_reg(cpu
, &rvbar
);
5131 define_arm_cp_regs(cpu
, v8_idregs
);
5132 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
5134 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
5135 uint64_t vmpidr_def
= mpidr_read_val(env
);
5136 ARMCPRegInfo vpidr_regs
[] = {
5137 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
5138 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5139 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5140 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
5141 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
5142 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
5143 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5144 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
5145 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
5146 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
5147 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5148 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5149 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
5150 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
5151 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
5152 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5154 .resetvalue
= vmpidr_def
,
5155 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
5158 define_arm_cp_regs(cpu
, vpidr_regs
);
5159 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
5160 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
5161 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
5162 ARMCPRegInfo rvbar
= {
5163 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
5164 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
5165 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
5167 define_one_arm_cp_reg(cpu
, &rvbar
);
5170 /* If EL2 is missing but higher ELs are enabled, we need to
5171 * register the no_el2 reginfos.
5173 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5174 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
5175 * of MIDR_EL1 and MPIDR_EL1.
5177 ARMCPRegInfo vpidr_regs
[] = {
5178 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5179 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5180 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5181 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
5182 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
5183 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5184 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5185 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5186 .type
= ARM_CP_NO_RAW
,
5187 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
5190 define_arm_cp_regs(cpu
, vpidr_regs
);
5191 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
5194 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5195 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
5196 ARMCPRegInfo el3_regs
[] = {
5197 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5198 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
5199 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
5200 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5201 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
5203 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5204 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
5205 .resetvalue
= cpu
->reset_sctlr
},
5209 define_arm_cp_regs(cpu
, el3_regs
);
5211 /* The behaviour of NSACR is sufficiently various that we don't
5212 * try to describe it in a single reginfo:
5213 * if EL3 is 64 bit, then trap to EL3 from S EL1,
5214 * reads as constant 0xc00 from NS EL1 and NS EL2
5215 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
5216 * if v7 without EL3, register doesn't exist
5217 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
5219 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5220 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5221 ARMCPRegInfo nsacr
= {
5222 .name
= "NSACR", .type
= ARM_CP_CONST
,
5223 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5224 .access
= PL1_RW
, .accessfn
= nsacr_access
,
5227 define_one_arm_cp_reg(cpu
, &nsacr
);
5229 ARMCPRegInfo nsacr
= {
5231 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5232 .access
= PL3_RW
| PL1_R
,
5234 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
5236 define_one_arm_cp_reg(cpu
, &nsacr
);
5239 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5240 ARMCPRegInfo nsacr
= {
5241 .name
= "NSACR", .type
= ARM_CP_CONST
,
5242 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5246 define_one_arm_cp_reg(cpu
, &nsacr
);
5250 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
5251 if (arm_feature(env
, ARM_FEATURE_V6
)) {
5252 /* PMSAv6 not implemented */
5253 assert(arm_feature(env
, ARM_FEATURE_V7
));
5254 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5255 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
5257 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
5260 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5261 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
5263 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5264 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
5266 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
5267 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
5269 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
5270 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
5272 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
5273 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
5275 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
5276 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
5278 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
5279 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
5281 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
5282 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
5284 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5285 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
5287 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5288 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
5290 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
5291 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
5293 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
5294 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
5296 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
5297 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
5298 * be read-only (ie write causes UNDEF exception).
5301 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
5302 /* Pre-v8 MIDR space.
5303 * Note that the MIDR isn't a simple constant register because
5304 * of the TI925 behaviour where writes to another register can
5305 * cause the MIDR value to change.
5307 * Unimplemented registers in the c15 0 0 0 space default to
5308 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
5309 * and friends override accordingly.
5312 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
5313 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
5314 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
5315 .readfn
= midr_read
,
5316 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5317 .type
= ARM_CP_OVERRIDE
},
5318 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5320 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
5321 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5323 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
5324 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5326 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
5327 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5329 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
5330 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5332 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
5333 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5336 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
5337 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5338 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
5339 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
5340 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5341 .readfn
= midr_read
},
5342 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5343 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5344 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5345 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5346 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5347 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
5348 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5349 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5350 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
5351 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
5354 ARMCPRegInfo id_cp_reginfo
[] = {
5355 /* These are common to v8 and pre-v8 */
5357 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
5358 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5359 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
5360 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
5361 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
5362 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5363 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5365 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
5366 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5369 /* TLBTR is specific to VMSA */
5370 ARMCPRegInfo id_tlbtr_reginfo
= {
5372 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
5373 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
5375 /* MPUIR is specific to PMSA V6+ */
5376 ARMCPRegInfo id_mpuir_reginfo
= {
5378 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5379 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5380 .resetvalue
= cpu
->pmsav7_dregion
<< 8
5382 ARMCPRegInfo crn0_wi_reginfo
= {
5383 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
5384 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
5385 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
5387 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
5388 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5390 /* Register the blanket "writes ignored" value first to cover the
5391 * whole space. Then update the specific ID registers to allow write
5392 * access, so that they ignore writes rather than causing them to
5395 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
5396 for (r
= id_pre_v8_midr_cp_reginfo
;
5397 r
->type
!= ARM_CP_SENTINEL
; r
++) {
5400 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5403 id_mpuir_reginfo
.access
= PL1_RW
;
5404 id_tlbtr_reginfo
.access
= PL1_RW
;
5406 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5407 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
5409 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
5411 define_arm_cp_regs(cpu
, id_cp_reginfo
);
5412 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
5413 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
5414 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5415 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
5419 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
5420 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
5423 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
5424 ARMCPRegInfo auxcr_reginfo
[] = {
5425 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5426 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
5427 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
5428 .resetvalue
= cpu
->reset_auxcr
},
5429 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5430 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
5431 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5433 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5434 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
5435 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5439 define_arm_cp_regs(cpu
, auxcr_reginfo
);
5442 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
5443 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5444 /* 32 bit view is [31:18] 0...0 [43:32]. */
5445 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
5446 | extract64(cpu
->reset_cbar
, 32, 12);
5447 ARMCPRegInfo cbar_reginfo
[] = {
5449 .type
= ARM_CP_CONST
,
5450 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5451 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
5452 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5453 .type
= ARM_CP_CONST
,
5454 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
5455 .access
= PL1_R
, .resetvalue
= cbar32
},
5458 /* We don't implement a r/w 64 bit CBAR currently */
5459 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
5460 define_arm_cp_regs(cpu
, cbar_reginfo
);
5462 ARMCPRegInfo cbar
= {
5464 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5465 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
5466 .fieldoffset
= offsetof(CPUARMState
,
5467 cp15
.c15_config_base_address
)
5469 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
5470 cbar
.access
= PL1_R
;
5471 cbar
.fieldoffset
= 0;
5472 cbar
.type
= ARM_CP_CONST
;
5474 define_one_arm_cp_reg(cpu
, &cbar
);
5478 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
5479 ARMCPRegInfo vbar_cp_reginfo
[] = {
5480 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
5481 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
5482 .access
= PL1_RW
, .writefn
= vbar_write
,
5483 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
5484 offsetof(CPUARMState
, cp15
.vbar_ns
) },
5488 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
5491 /* Generic registers whose values depend on the implementation */
5493 ARMCPRegInfo sctlr
= {
5494 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
5495 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5497 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
5498 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
5499 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
5500 .raw_writefn
= raw_write
,
5502 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5503 /* Normally we would always end the TB on an SCTLR write, but Linux
5504 * arch/arm/mach-pxa/sleep.S expects two instructions following
5505 * an MMU enable to execute from cache. Imitate this behaviour.
5507 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
5509 define_one_arm_cp_reg(cpu
, &sctlr
);
5512 if (arm_feature(env
, ARM_FEATURE_SVE
)) {
5513 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
5514 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
5515 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
5517 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
5519 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5520 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
5525 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
5527 CPUState
*cs
= CPU(cpu
);
5528 CPUARMState
*env
= &cpu
->env
;
5530 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5531 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
5532 aarch64_fpu_gdb_set_reg
,
5533 34, "aarch64-fpu.xml", 0);
5534 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
5535 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5536 51, "arm-neon.xml", 0);
5537 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
5538 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5539 35, "arm-vfp3.xml", 0);
5540 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
5541 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5542 19, "arm-vfp.xml", 0);
5544 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
5545 arm_gen_dynamic_xml(cs
),
5546 "system-registers.xml", 0);
5549 /* Sort alphabetically by type name, except for "any". */
5550 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5552 ObjectClass
*class_a
= (ObjectClass
*)a
;
5553 ObjectClass
*class_b
= (ObjectClass
*)b
;
5554 const char *name_a
, *name_b
;
5556 name_a
= object_class_get_name(class_a
);
5557 name_b
= object_class_get_name(class_b
);
5558 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
5560 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
5563 return strcmp(name_a
, name_b
);
5567 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
5569 ObjectClass
*oc
= data
;
5570 CPUListState
*s
= user_data
;
5571 const char *typename
;
5574 typename
= object_class_get_name(oc
);
5575 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5576 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
5581 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
5585 .cpu_fprintf
= cpu_fprintf
,
5589 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5590 list
= g_slist_sort(list
, arm_cpu_list_compare
);
5591 (*cpu_fprintf
)(f
, "Available CPUs:\n");
5592 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
5596 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
5598 ObjectClass
*oc
= data
;
5599 CpuDefinitionInfoList
**cpu_list
= user_data
;
5600 CpuDefinitionInfoList
*entry
;
5601 CpuDefinitionInfo
*info
;
5602 const char *typename
;
5604 typename
= object_class_get_name(oc
);
5605 info
= g_malloc0(sizeof(*info
));
5606 info
->name
= g_strndup(typename
,
5607 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5608 info
->q_typename
= g_strdup(typename
);
5610 entry
= g_malloc0(sizeof(*entry
));
5611 entry
->value
= info
;
5612 entry
->next
= *cpu_list
;
5616 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
5618 CpuDefinitionInfoList
*cpu_list
= NULL
;
5621 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5622 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
5628 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
5629 void *opaque
, int state
, int secstate
,
5630 int crm
, int opc1
, int opc2
,
5633 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5634 * add a single reginfo struct to the hash table.
5636 uint32_t *key
= g_new(uint32_t, 1);
5637 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
5638 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
5639 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
5641 r2
->name
= g_strdup(name
);
5642 /* Reset the secure state to the specific incoming state. This is
5643 * necessary as the register may have been defined with both states.
5645 r2
->secure
= secstate
;
5647 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5648 /* Register is banked (using both entries in array).
5649 * Overwriting fieldoffset as the array is only used to define
5650 * banked registers but later only fieldoffset is used.
5652 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
5655 if (state
== ARM_CP_STATE_AA32
) {
5656 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5657 /* If the register is banked then we don't need to migrate or
5658 * reset the 32-bit instance in certain cases:
5660 * 1) If the register has both 32-bit and 64-bit instances then we
5661 * can count on the 64-bit instance taking care of the
5663 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5664 * taking care of the secure bank. This requires that separate
5665 * 32 and 64-bit definitions are provided.
5667 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
5668 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
5669 r2
->type
|= ARM_CP_ALIAS
;
5671 } else if ((secstate
!= r
->secure
) && !ns
) {
5672 /* The register is not banked so we only want to allow migration of
5673 * the non-secure instance.
5675 r2
->type
|= ARM_CP_ALIAS
;
5678 if (r
->state
== ARM_CP_STATE_BOTH
) {
5679 /* We assume it is a cp15 register if the .cp field is left unset.
5685 #ifdef HOST_WORDS_BIGENDIAN
5686 if (r2
->fieldoffset
) {
5687 r2
->fieldoffset
+= sizeof(uint32_t);
5692 if (state
== ARM_CP_STATE_AA64
) {
5693 /* To allow abbreviation of ARMCPRegInfo
5694 * definitions, we treat cp == 0 as equivalent to
5695 * the value for "standard guest-visible sysreg".
5696 * STATE_BOTH definitions are also always "standard
5697 * sysreg" in their AArch64 view (the .cp value may
5698 * be non-zero for the benefit of the AArch32 view).
5700 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
5701 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
5703 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
5704 r2
->opc0
, opc1
, opc2
);
5706 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
5709 r2
->opaque
= opaque
;
5711 /* reginfo passed to helpers is correct for the actual access,
5712 * and is never ARM_CP_STATE_BOTH:
5715 /* Make sure reginfo passed to helpers for wildcarded regs
5716 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5721 /* By convention, for wildcarded registers only the first
5722 * entry is used for migration; the others are marked as
5723 * ALIAS so we don't try to transfer the register
5724 * multiple times. Special registers (ie NOP/WFI) are
5725 * never migratable and not even raw-accessible.
5727 if ((r
->type
& ARM_CP_SPECIAL
)) {
5728 r2
->type
|= ARM_CP_NO_RAW
;
5730 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
5731 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
5732 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
5733 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
5736 /* Check that raw accesses are either forbidden or handled. Note that
5737 * we can't assert this earlier because the setup of fieldoffset for
5738 * banked registers has to be done first.
5740 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
5741 assert(!raw_accessors_invalid(r2
));
5744 /* Overriding of an existing definition must be explicitly
5747 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
5748 ARMCPRegInfo
*oldreg
;
5749 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
5750 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
5751 fprintf(stderr
, "Register redefined: cp=%d %d bit "
5752 "crn=%d crm=%d opc1=%d opc2=%d, "
5753 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
5754 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
5755 oldreg
->name
, r2
->name
);
5756 g_assert_not_reached();
5759 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
5763 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
5764 const ARMCPRegInfo
*r
, void *opaque
)
5766 /* Define implementations of coprocessor registers.
5767 * We store these in a hashtable because typically
5768 * there are less than 150 registers in a space which
5769 * is 16*16*16*8*8 = 262144 in size.
5770 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5771 * If a register is defined twice then the second definition is
5772 * used, so this can be used to define some generic registers and
5773 * then override them with implementation specific variations.
5774 * At least one of the original and the second definition should
5775 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5776 * against accidental use.
5778 * The state field defines whether the register is to be
5779 * visible in the AArch32 or AArch64 execution state. If the
5780 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5781 * reginfo structure for the AArch32 view, which sees the lower
5782 * 32 bits of the 64 bit register.
5784 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5785 * be wildcarded. AArch64 registers are always considered to be 64
5786 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5787 * the register, if any.
5789 int crm
, opc1
, opc2
, state
;
5790 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
5791 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
5792 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
5793 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
5794 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
5795 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
5796 /* 64 bit registers have only CRm and Opc1 fields */
5797 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
5798 /* op0 only exists in the AArch64 encodings */
5799 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
5800 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5801 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
5802 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5803 * encodes a minimum access level for the register. We roll this
5804 * runtime check into our general permission check code, so check
5805 * here that the reginfo's specified permissions are strict enough
5806 * to encompass the generic architectural permission check.
5808 if (r
->state
!= ARM_CP_STATE_AA32
) {
5811 case 0: case 1: case 2:
5824 /* unallocated encoding, so not possible */
5832 /* min_EL EL1, secure mode only (we don't check the latter) */
5836 /* broken reginfo with out-of-range opc1 */
5840 /* assert our permissions are not too lax (stricter is fine) */
5841 assert((r
->access
& ~mask
) == 0);
5844 /* Check that the register definition has enough info to handle
5845 * reads and writes if they are permitted.
5847 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
5848 if (r
->access
& PL3_R
) {
5849 assert((r
->fieldoffset
||
5850 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5853 if (r
->access
& PL3_W
) {
5854 assert((r
->fieldoffset
||
5855 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5859 /* Bad type field probably means missing sentinel at end of reg list */
5860 assert(cptype_valid(r
->type
));
5861 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
5862 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
5863 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
5864 for (state
= ARM_CP_STATE_AA32
;
5865 state
<= ARM_CP_STATE_AA64
; state
++) {
5866 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
5869 if (state
== ARM_CP_STATE_AA32
) {
5870 /* Under AArch32 CP registers can be common
5871 * (same for secure and non-secure world) or banked.
5875 switch (r
->secure
) {
5876 case ARM_CP_SECSTATE_S
:
5877 case ARM_CP_SECSTATE_NS
:
5878 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5879 r
->secure
, crm
, opc1
, opc2
,
5883 name
= g_strdup_printf("%s_S", r
->name
);
5884 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5886 crm
, opc1
, opc2
, name
);
5888 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5890 crm
, opc1
, opc2
, r
->name
);
5894 /* AArch64 registers get mapped to non-secure instance
5896 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5898 crm
, opc1
, opc2
, r
->name
);
5906 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
5907 const ARMCPRegInfo
*regs
, void *opaque
)
5909 /* Define a whole list of registers */
5910 const ARMCPRegInfo
*r
;
5911 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5912 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
5916 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
5918 return g_hash_table_lookup(cpregs
, &encoded_cp
);
5921 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5924 /* Helper coprocessor write function for write-ignore registers */
5927 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5929 /* Helper coprocessor write function for read-as-zero registers */
5933 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
5935 /* Helper coprocessor reset function for do-nothing-on-reset registers */
5938 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
5940 /* Return true if it is not valid for us to switch to
5941 * this CPU mode (ie all the UNPREDICTABLE cases in
5942 * the ARM ARM CPSRWriteByInstr pseudocode).
5945 /* Changes to or from Hyp via MSR and CPS are illegal. */
5946 if (write_type
== CPSRWriteByInstr
&&
5947 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
5948 mode
== ARM_CPU_MODE_HYP
)) {
5953 case ARM_CPU_MODE_USR
:
5955 case ARM_CPU_MODE_SYS
:
5956 case ARM_CPU_MODE_SVC
:
5957 case ARM_CPU_MODE_ABT
:
5958 case ARM_CPU_MODE_UND
:
5959 case ARM_CPU_MODE_IRQ
:
5960 case ARM_CPU_MODE_FIQ
:
5961 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5962 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5964 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5965 * and CPS are treated as illegal mode changes.
5967 if (write_type
== CPSRWriteByInstr
&&
5968 (env
->cp15
.hcr_el2
& HCR_TGE
) &&
5969 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
5970 !arm_is_secure_below_el3(env
)) {
5974 case ARM_CPU_MODE_HYP
:
5975 return !arm_feature(env
, ARM_FEATURE_EL2
)
5976 || arm_current_el(env
) < 2 || arm_is_secure(env
);
5977 case ARM_CPU_MODE_MON
:
5978 return arm_current_el(env
) < 3;
5984 uint32_t cpsr_read(CPUARMState
*env
)
5987 ZF
= (env
->ZF
== 0);
5988 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
5989 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
5990 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
5991 | ((env
->condexec_bits
& 0xfc) << 8)
5992 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
5995 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
5996 CPSRWriteType write_type
)
5998 uint32_t changed_daif
;
6000 if (mask
& CPSR_NZCV
) {
6001 env
->ZF
= (~val
) & CPSR_Z
;
6003 env
->CF
= (val
>> 29) & 1;
6004 env
->VF
= (val
<< 3) & 0x80000000;
6007 env
->QF
= ((val
& CPSR_Q
) != 0);
6009 env
->thumb
= ((val
& CPSR_T
) != 0);
6010 if (mask
& CPSR_IT_0_1
) {
6011 env
->condexec_bits
&= ~3;
6012 env
->condexec_bits
|= (val
>> 25) & 3;
6014 if (mask
& CPSR_IT_2_7
) {
6015 env
->condexec_bits
&= 3;
6016 env
->condexec_bits
|= (val
>> 8) & 0xfc;
6018 if (mask
& CPSR_GE
) {
6019 env
->GE
= (val
>> 16) & 0xf;
6022 /* In a V7 implementation that includes the security extensions but does
6023 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
6024 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
6025 * bits respectively.
6027 * In a V8 implementation, it is permitted for privileged software to
6028 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
6030 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
6031 arm_feature(env
, ARM_FEATURE_EL3
) &&
6032 !arm_feature(env
, ARM_FEATURE_EL2
) &&
6033 !arm_is_secure(env
)) {
6035 changed_daif
= (env
->daif
^ val
) & mask
;
6037 if (changed_daif
& CPSR_A
) {
6038 /* Check to see if we are allowed to change the masking of async
6039 * abort exceptions from a non-secure state.
6041 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
6042 qemu_log_mask(LOG_GUEST_ERROR
,
6043 "Ignoring attempt to switch CPSR_A flag from "
6044 "non-secure world with SCR.AW bit clear\n");
6049 if (changed_daif
& CPSR_F
) {
6050 /* Check to see if we are allowed to change the masking of FIQ
6051 * exceptions from a non-secure state.
6053 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
6054 qemu_log_mask(LOG_GUEST_ERROR
,
6055 "Ignoring attempt to switch CPSR_F flag from "
6056 "non-secure world with SCR.FW bit clear\n");
6060 /* Check whether non-maskable FIQ (NMFI) support is enabled.
6061 * If this bit is set software is not allowed to mask
6062 * FIQs, but is allowed to set CPSR_F to 0.
6064 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
6066 qemu_log_mask(LOG_GUEST_ERROR
,
6067 "Ignoring attempt to enable CPSR_F flag "
6068 "(non-maskable FIQ [NMFI] support enabled)\n");
6074 env
->daif
&= ~(CPSR_AIF
& mask
);
6075 env
->daif
|= val
& CPSR_AIF
& mask
;
6077 if (write_type
!= CPSRWriteRaw
&&
6078 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
6079 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
6080 /* Note that we can only get here in USR mode if this is a
6081 * gdb stub write; for this case we follow the architectural
6082 * behaviour for guest writes in USR mode of ignoring an attempt
6083 * to switch mode. (Those are caught by translate.c for writes
6084 * triggered by guest instructions.)
6087 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
6088 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
6089 * v7, and has defined behaviour in v8:
6090 * + leave CPSR.M untouched
6091 * + allow changes to the other CPSR fields
6093 * For user changes via the GDB stub, we don't set PSTATE.IL,
6094 * as this would be unnecessarily harsh for a user error.
6097 if (write_type
!= CPSRWriteByGDBStub
&&
6098 arm_feature(env
, ARM_FEATURE_V8
)) {
6103 switch_mode(env
, val
& CPSR_M
);
6106 mask
&= ~CACHED_CPSR_BITS
;
6107 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
6110 /* Sign/zero extend */
6111 uint32_t HELPER(sxtb16
)(uint32_t x
)
6114 res
= (uint16_t)(int8_t)x
;
6115 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
6119 uint32_t HELPER(uxtb16
)(uint32_t x
)
6122 res
= (uint16_t)(uint8_t)x
;
6123 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
6127 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
6131 if (num
== INT_MIN
&& den
== -1)
6136 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
6143 uint32_t HELPER(rbit
)(uint32_t x
)
6148 #if defined(CONFIG_USER_ONLY)
6150 /* These should probably raise undefined insn exceptions. */
6151 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
6153 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6155 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
6158 uint32_t QEMU_NORETURN
HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
6160 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6162 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
6165 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
6167 /* translate.c should never generate calls here in user-only mode */
6168 g_assert_not_reached();
6171 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
6173 /* translate.c should never generate calls here in user-only mode */
6174 g_assert_not_reached();
6177 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
6179 /* The TT instructions can be used by unprivileged code, but in
6180 * user-only emulation we don't have the MPU.
6181 * Luckily since we know we are NonSecure unprivileged (and that in
6182 * turn means that the A flag wasn't specified), all the bits in the
6183 * register must be zero:
6184 * IREGION: 0 because IRVALID is 0
6185 * IRVALID: 0 because NS
6187 * NSRW: 0 because NS
6189 * RW: 0 because unpriv and A flag not set
6190 * R: 0 because unpriv and A flag not set
6191 * SRVALID: 0 because NS
6192 * MRVALID: 0 because unpriv and A flag not set
6193 * SREGION: 0 becaus SRVALID is 0
6194 * MREGION: 0 because MRVALID is 0
6199 void switch_mode(CPUARMState
*env
, int mode
)
6201 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6203 if (mode
!= ARM_CPU_MODE_USR
) {
6204 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
6208 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6209 uint32_t cur_el
, bool secure
)
6214 void aarch64_sync_64_to_32(CPUARMState
*env
)
6216 g_assert_not_reached();
6221 void switch_mode(CPUARMState
*env
, int mode
)
6226 old_mode
= env
->uncached_cpsr
& CPSR_M
;
6227 if (mode
== old_mode
)
6230 if (old_mode
== ARM_CPU_MODE_FIQ
) {
6231 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
6232 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
6233 } else if (mode
== ARM_CPU_MODE_FIQ
) {
6234 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
6235 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
6238 i
= bank_number(old_mode
);
6239 env
->banked_r13
[i
] = env
->regs
[13];
6240 env
->banked_r14
[i
] = env
->regs
[14];
6241 env
->banked_spsr
[i
] = env
->spsr
;
6243 i
= bank_number(mode
);
6244 env
->regs
[13] = env
->banked_r13
[i
];
6245 env
->regs
[14] = env
->banked_r14
[i
];
6246 env
->spsr
= env
->banked_spsr
[i
];
6249 /* Physical Interrupt Target EL Lookup Table
6251 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
6253 * The below multi-dimensional table is used for looking up the target
6254 * exception level given numerous condition criteria. Specifically, the
6255 * target EL is based on SCR and HCR routing controls as well as the
6256 * currently executing EL and secure state.
6259 * target_el_table[2][2][2][2][2][4]
6260 * | | | | | +--- Current EL
6261 * | | | | +------ Non-secure(0)/Secure(1)
6262 * | | | +--------- HCR mask override
6263 * | | +------------ SCR exec state control
6264 * | +--------------- SCR mask override
6265 * +------------------ 32-bit(0)/64-bit(1) EL3
6267 * The table values are as such:
6271 * The ARM ARM target EL table includes entries indicating that an "exception
6272 * is not taken". The two cases where this is applicable are:
6273 * 1) An exception is taken from EL3 but the SCR does not have the exception
6275 * 2) An exception is taken from EL2 but the HCR does not have the exception
6277 * In these two cases, the below table contain a target of EL1. This value is
6278 * returned as it is expected that the consumer of the table data will check
6279 * for "target EL >= current EL" to ensure the exception is not taken.
6283 * BIT IRQ IMO Non-secure Secure
6284 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
6286 static const int8_t target_el_table
[2][2][2][2][2][4] = {
6287 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6288 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
6289 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6290 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
6291 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6292 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
6293 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6294 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
6295 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
6296 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
6297 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
6298 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
6299 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6300 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
6301 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6302 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
6306 * Determine the target EL for physical exceptions
6308 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6309 uint32_t cur_el
, bool secure
)
6311 CPUARMState
*env
= cs
->env_ptr
;
6316 /* Is the highest EL AArch64? */
6317 int is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
6319 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6320 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
6322 /* Either EL2 is the highest EL (and so the EL2 register width
6323 * is given by is64); or there is no EL2 or EL3, in which case
6324 * the value of 'rw' does not affect the table lookup anyway.
6331 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
6332 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
6335 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
6336 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
6339 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
6340 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
6344 /* If HCR.TGE is set then HCR is treated as being 1 */
6345 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
6347 /* Perform a table-lookup for the target EL given the current state */
6348 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
6350 assert(target_el
> 0);
6355 static bool v7m_stack_write(ARMCPU
*cpu
, uint32_t addr
, uint32_t value
,
6356 ARMMMUIdx mmu_idx
, bool ignfault
)
6358 CPUState
*cs
= CPU(cpu
);
6359 CPUARMState
*env
= &cpu
->env
;
6360 MemTxAttrs attrs
= {};
6362 target_ulong page_size
;
6366 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
6370 if (get_phys_addr(env
, addr
, MMU_DATA_STORE
, mmu_idx
, &physaddr
,
6371 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
6372 /* MPU/SAU lookup failed */
6373 if (fi
.type
== ARMFault_QEMU_SFault
) {
6374 qemu_log_mask(CPU_LOG_INT
,
6375 "...SecureFault with SFSR.AUVIOL during stacking\n");
6376 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
6377 env
->v7m
.sfar
= addr
;
6378 exc
= ARMV7M_EXCP_SECURE
;
6381 qemu_log_mask(CPU_LOG_INT
, "...MemManageFault with CFSR.MSTKERR\n");
6382 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MSTKERR_MASK
;
6383 exc
= ARMV7M_EXCP_MEM
;
6384 exc_secure
= secure
;
6388 address_space_stl_le(arm_addressspace(cs
, attrs
), physaddr
, value
,
6390 if (txres
!= MEMTX_OK
) {
6391 /* BusFault trying to write the data */
6392 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.STKERR\n");
6393 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_STKERR_MASK
;
6394 exc
= ARMV7M_EXCP_BUS
;
6401 /* By pending the exception at this point we are making
6402 * the IMPDEF choice "overridden exceptions pended" (see the
6403 * MergeExcInfo() pseudocode). The other choice would be to not
6404 * pend them now and then make a choice about which to throw away
6405 * later if we have two derived exceptions.
6406 * The only case when we must not pend the exception but instead
6407 * throw it away is if we are doing the push of the callee registers
6408 * and we've already generated a derived exception. Even in this
6409 * case we will still update the fault status registers.
6412 armv7m_nvic_set_pending_derived(env
->nvic
, exc
, exc_secure
);
6417 static bool v7m_stack_read(ARMCPU
*cpu
, uint32_t *dest
, uint32_t addr
,
6420 CPUState
*cs
= CPU(cpu
);
6421 CPUARMState
*env
= &cpu
->env
;
6422 MemTxAttrs attrs
= {};
6424 target_ulong page_size
;
6428 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
6433 if (get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &physaddr
,
6434 &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
6435 /* MPU/SAU lookup failed */
6436 if (fi
.type
== ARMFault_QEMU_SFault
) {
6437 qemu_log_mask(CPU_LOG_INT
,
6438 "...SecureFault with SFSR.AUVIOL during unstack\n");
6439 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
6440 env
->v7m
.sfar
= addr
;
6441 exc
= ARMV7M_EXCP_SECURE
;
6444 qemu_log_mask(CPU_LOG_INT
,
6445 "...MemManageFault with CFSR.MUNSTKERR\n");
6446 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MUNSTKERR_MASK
;
6447 exc
= ARMV7M_EXCP_MEM
;
6448 exc_secure
= secure
;
6453 value
= address_space_ldl(arm_addressspace(cs
, attrs
), physaddr
,
6455 if (txres
!= MEMTX_OK
) {
6456 /* BusFault trying to read the data */
6457 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.UNSTKERR\n");
6458 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_UNSTKERR_MASK
;
6459 exc
= ARMV7M_EXCP_BUS
;
6468 /* By pending the exception at this point we are making
6469 * the IMPDEF choice "overridden exceptions pended" (see the
6470 * MergeExcInfo() pseudocode). The other choice would be to not
6471 * pend them now and then make a choice about which to throw away
6472 * later if we have two derived exceptions.
6474 armv7m_nvic_set_pending(env
->nvic
, exc
, exc_secure
);
6478 /* Return true if we're using the process stack pointer (not the MSP) */
6479 static bool v7m_using_psp(CPUARMState
*env
)
6481 /* Handler mode always uses the main stack; for thread mode
6482 * the CONTROL.SPSEL bit determines the answer.
6483 * Note that in v7M it is not possible to be in Handler mode with
6484 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
6486 return !arm_v7m_is_handler_mode(env
) &&
6487 env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
;
6490 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
6491 * This may change the current stack pointer between Main and Process
6492 * stack pointers if it is done for the CONTROL register for the current
6495 static void write_v7m_control_spsel_for_secstate(CPUARMState
*env
,
6499 bool old_is_psp
= v7m_using_psp(env
);
6501 env
->v7m
.control
[secstate
] =
6502 deposit32(env
->v7m
.control
[secstate
],
6503 R_V7M_CONTROL_SPSEL_SHIFT
,
6504 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
6506 if (secstate
== env
->v7m
.secure
) {
6507 bool new_is_psp
= v7m_using_psp(env
);
6510 if (old_is_psp
!= new_is_psp
) {
6511 tmp
= env
->v7m
.other_sp
;
6512 env
->v7m
.other_sp
= env
->regs
[13];
6513 env
->regs
[13] = tmp
;
6518 /* Write to v7M CONTROL.SPSEL bit. This may change the current
6519 * stack pointer between Main and Process stack pointers.
6521 static void write_v7m_control_spsel(CPUARMState
*env
, bool new_spsel
)
6523 write_v7m_control_spsel_for_secstate(env
, new_spsel
, env
->v7m
.secure
);
6526 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
)
6528 /* Write a new value to v7m.exception, thus transitioning into or out
6529 * of Handler mode; this may result in a change of active stack pointer.
6531 bool new_is_psp
, old_is_psp
= v7m_using_psp(env
);
6534 env
->v7m
.exception
= new_exc
;
6536 new_is_psp
= v7m_using_psp(env
);
6538 if (old_is_psp
!= new_is_psp
) {
6539 tmp
= env
->v7m
.other_sp
;
6540 env
->v7m
.other_sp
= env
->regs
[13];
6541 env
->regs
[13] = tmp
;
6545 /* Switch M profile security state between NS and S */
6546 static void switch_v7m_security_state(CPUARMState
*env
, bool new_secstate
)
6548 uint32_t new_ss_msp
, new_ss_psp
;
6550 if (env
->v7m
.secure
== new_secstate
) {
6554 /* All the banked state is accessed by looking at env->v7m.secure
6555 * except for the stack pointer; rearrange the SP appropriately.
6557 new_ss_msp
= env
->v7m
.other_ss_msp
;
6558 new_ss_psp
= env
->v7m
.other_ss_psp
;
6560 if (v7m_using_psp(env
)) {
6561 env
->v7m
.other_ss_psp
= env
->regs
[13];
6562 env
->v7m
.other_ss_msp
= env
->v7m
.other_sp
;
6564 env
->v7m
.other_ss_msp
= env
->regs
[13];
6565 env
->v7m
.other_ss_psp
= env
->v7m
.other_sp
;
6568 env
->v7m
.secure
= new_secstate
;
6570 if (v7m_using_psp(env
)) {
6571 env
->regs
[13] = new_ss_psp
;
6572 env
->v7m
.other_sp
= new_ss_msp
;
6574 env
->regs
[13] = new_ss_msp
;
6575 env
->v7m
.other_sp
= new_ss_psp
;
6579 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
6582 * - if the return value is a magic value, do exception return (like BX)
6583 * - otherwise bit 0 of the return value is the target security state
6587 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6588 /* Covers FNC_RETURN and EXC_RETURN magic */
6589 min_magic
= FNC_RETURN_MIN_MAGIC
;
6591 /* EXC_RETURN magic only */
6592 min_magic
= EXC_RETURN_MIN_MAGIC
;
6595 if (dest
>= min_magic
) {
6596 /* This is an exception return magic value; put it where
6597 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
6598 * Note that if we ever add gen_ss_advance() singlestep support to
6599 * M profile this should count as an "instruction execution complete"
6600 * event (compare gen_bx_excret_final_code()).
6602 env
->regs
[15] = dest
& ~1;
6603 env
->thumb
= dest
& 1;
6604 HELPER(exception_internal
)(env
, EXCP_EXCEPTION_EXIT
);
6608 /* translate.c should have made BXNS UNDEF unless we're secure */
6609 assert(env
->v7m
.secure
);
6611 switch_v7m_security_state(env
, dest
& 1);
6613 env
->regs
[15] = dest
& ~1;
6616 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
6618 /* Handle v7M BLXNS:
6619 * - bit 0 of the destination address is the target security state
6622 /* At this point regs[15] is the address just after the BLXNS */
6623 uint32_t nextinst
= env
->regs
[15] | 1;
6624 uint32_t sp
= env
->regs
[13] - 8;
6627 /* translate.c will have made BLXNS UNDEF unless we're secure */
6628 assert(env
->v7m
.secure
);
6631 /* target is Secure, so this is just a normal BLX,
6632 * except that the low bit doesn't indicate Thumb/not.
6634 env
->regs
[14] = nextinst
;
6636 env
->regs
[15] = dest
& ~1;
6640 /* Target is non-secure: first push a stack frame */
6641 if (!QEMU_IS_ALIGNED(sp
, 8)) {
6642 qemu_log_mask(LOG_GUEST_ERROR
,
6643 "BLXNS with misaligned SP is UNPREDICTABLE\n");
6646 saved_psr
= env
->v7m
.exception
;
6647 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
) {
6648 saved_psr
|= XPSR_SFPA
;
6651 /* Note that these stores can throw exceptions on MPU faults */
6652 cpu_stl_data(env
, sp
, nextinst
);
6653 cpu_stl_data(env
, sp
+ 4, saved_psr
);
6656 env
->regs
[14] = 0xfeffffff;
6657 if (arm_v7m_is_handler_mode(env
)) {
6658 /* Write a dummy value to IPSR, to avoid leaking the current secure
6659 * exception number to non-secure code. This is guaranteed not
6660 * to cause write_v7m_exception() to actually change stacks.
6662 write_v7m_exception(env
, 1);
6664 switch_v7m_security_state(env
, 0);
6666 env
->regs
[15] = dest
;
6669 static uint32_t *get_v7m_sp_ptr(CPUARMState
*env
, bool secure
, bool threadmode
,
6672 /* Return a pointer to the location where we currently store the
6673 * stack pointer for the requested security state and thread mode.
6674 * This pointer will become invalid if the CPU state is updated
6675 * such that the stack pointers are switched around (eg changing
6676 * the SPSEL control bit).
6677 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
6678 * Unlike that pseudocode, we require the caller to pass us in the
6679 * SPSEL control bit value; this is because we also use this
6680 * function in handling of pushing of the callee-saves registers
6681 * part of the v8M stack frame (pseudocode PushCalleeStack()),
6682 * and in the tailchain codepath the SPSEL bit comes from the exception
6683 * return magic LR value from the previous exception. The pseudocode
6684 * opencodes the stack-selection in PushCalleeStack(), but we prefer
6685 * to make this utility function generic enough to do the job.
6687 bool want_psp
= threadmode
&& spsel
;
6689 if (secure
== env
->v7m
.secure
) {
6690 if (want_psp
== v7m_using_psp(env
)) {
6691 return &env
->regs
[13];
6693 return &env
->v7m
.other_sp
;
6697 return &env
->v7m
.other_ss_psp
;
6699 return &env
->v7m
.other_ss_msp
;
6704 static bool arm_v7m_load_vector(ARMCPU
*cpu
, int exc
, bool targets_secure
,
6707 CPUState
*cs
= CPU(cpu
);
6708 CPUARMState
*env
= &cpu
->env
;
6710 uint32_t addr
= env
->v7m
.vecbase
[targets_secure
] + exc
* 4;
6711 uint32_t vector_entry
;
6712 MemTxAttrs attrs
= {};
6716 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targets_secure
, true);
6718 /* We don't do a get_phys_addr() here because the rules for vector
6719 * loads are special: they always use the default memory map, and
6720 * the default memory map permits reads from all addresses.
6721 * Since there's no easy way to pass through to pmsav8_mpu_lookup()
6722 * that we want this special case which would always say "yes",
6723 * we just do the SAU lookup here followed by a direct physical load.
6725 attrs
.secure
= targets_secure
;
6728 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6729 V8M_SAttributes sattrs
= {};
6731 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
6733 attrs
.secure
= false;
6734 } else if (!targets_secure
) {
6735 /* NS access to S memory */
6740 vector_entry
= address_space_ldl(arm_addressspace(cs
, attrs
), addr
,
6742 if (result
!= MEMTX_OK
) {
6745 *pvec
= vector_entry
;
6749 /* All vector table fetch fails are reported as HardFault, with
6750 * HFSR.VECTTBL and .FORCED set. (FORCED is set because
6751 * technically the underlying exception is a MemManage or BusFault
6752 * that is escalated to HardFault.) This is a terminal exception,
6753 * so we will either take the HardFault immediately or else enter
6754 * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
6756 exc_secure
= targets_secure
||
6757 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
6758 env
->v7m
.hfsr
|= R_V7M_HFSR_VECTTBL_MASK
| R_V7M_HFSR_FORCED_MASK
;
6759 armv7m_nvic_set_pending_derived(env
->nvic
, ARMV7M_EXCP_HARD
, exc_secure
);
6763 static bool v7m_push_callee_stack(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
6766 /* For v8M, push the callee-saves register part of the stack frame.
6767 * Compare the v8M pseudocode PushCalleeStack().
6768 * In the tailchaining case this may not be the current stack.
6770 CPUARMState
*env
= &cpu
->env
;
6771 uint32_t *frame_sp_p
;
6777 bool mode
= lr
& R_V7M_EXCRET_MODE_MASK
;
6778 bool priv
= !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_NPRIV_MASK
) ||
6781 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, M_REG_S
, priv
);
6782 frame_sp_p
= get_v7m_sp_ptr(env
, M_REG_S
, mode
,
6783 lr
& R_V7M_EXCRET_SPSEL_MASK
);
6785 mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
6786 frame_sp_p
= &env
->regs
[13];
6789 frameptr
= *frame_sp_p
- 0x28;
6791 /* Write as much of the stack frame as we can. A write failure may
6792 * cause us to pend a derived exception.
6795 v7m_stack_write(cpu
, frameptr
, 0xfefa125b, mmu_idx
, ignore_faults
) &&
6796 v7m_stack_write(cpu
, frameptr
+ 0x8, env
->regs
[4], mmu_idx
,
6798 v7m_stack_write(cpu
, frameptr
+ 0xc, env
->regs
[5], mmu_idx
,
6800 v7m_stack_write(cpu
, frameptr
+ 0x10, env
->regs
[6], mmu_idx
,
6802 v7m_stack_write(cpu
, frameptr
+ 0x14, env
->regs
[7], mmu_idx
,
6804 v7m_stack_write(cpu
, frameptr
+ 0x18, env
->regs
[8], mmu_idx
,
6806 v7m_stack_write(cpu
, frameptr
+ 0x1c, env
->regs
[9], mmu_idx
,
6808 v7m_stack_write(cpu
, frameptr
+ 0x20, env
->regs
[10], mmu_idx
,
6810 v7m_stack_write(cpu
, frameptr
+ 0x24, env
->regs
[11], mmu_idx
,
6813 /* Update SP regardless of whether any of the stack accesses failed.
6814 * When we implement v8M stack limit checking then this attempt to
6815 * update SP might also fail and result in a derived exception.
6817 *frame_sp_p
= frameptr
;
6822 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
6823 bool ignore_stackfaults
)
6825 /* Do the "take the exception" parts of exception entry,
6826 * but not the pushing of state to the stack. This is
6827 * similar to the pseudocode ExceptionTaken() function.
6829 CPUARMState
*env
= &cpu
->env
;
6831 bool targets_secure
;
6833 bool push_failed
= false;
6835 armv7m_nvic_get_pending_irq_info(env
->nvic
, &exc
, &targets_secure
);
6837 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6838 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
6839 (lr
& R_V7M_EXCRET_S_MASK
)) {
6840 /* The background code (the owner of the registers in the
6841 * exception frame) is Secure. This means it may either already
6842 * have or now needs to push callee-saves registers.
6844 if (targets_secure
) {
6845 if (dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
)) {
6846 /* We took an exception from Secure to NonSecure
6847 * (which means the callee-saved registers got stacked)
6848 * and are now tailchaining to a Secure exception.
6849 * Clear DCRS so eventual return from this Secure
6850 * exception unstacks the callee-saved registers.
6852 lr
&= ~R_V7M_EXCRET_DCRS_MASK
;
6855 /* We're going to a non-secure exception; push the
6856 * callee-saves registers to the stack now, if they're
6857 * not already saved.
6859 if (lr
& R_V7M_EXCRET_DCRS_MASK
&&
6860 !(dotailchain
&& (lr
& R_V7M_EXCRET_ES_MASK
))) {
6861 push_failed
= v7m_push_callee_stack(cpu
, lr
, dotailchain
,
6862 ignore_stackfaults
);
6864 lr
|= R_V7M_EXCRET_DCRS_MASK
;
6868 lr
&= ~R_V7M_EXCRET_ES_MASK
;
6869 if (targets_secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6870 lr
|= R_V7M_EXCRET_ES_MASK
;
6872 lr
&= ~R_V7M_EXCRET_SPSEL_MASK
;
6873 if (env
->v7m
.control
[targets_secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
6874 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
6877 /* Clear registers if necessary to prevent non-secure exception
6878 * code being able to see register values from secure code.
6879 * Where register values become architecturally UNKNOWN we leave
6880 * them with their previous values.
6882 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6883 if (!targets_secure
) {
6884 /* Always clear the caller-saved registers (they have been
6885 * pushed to the stack earlier in v7m_push_stack()).
6886 * Clear callee-saved registers if the background code is
6887 * Secure (in which case these regs were saved in
6888 * v7m_push_callee_stack()).
6892 for (i
= 0; i
< 13; i
++) {
6893 /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
6894 if (i
< 4 || i
> 11 || (lr
& R_V7M_EXCRET_S_MASK
)) {
6899 xpsr_write(env
, 0, XPSR_NZCV
| XPSR_Q
| XPSR_GE
| XPSR_IT
);
6904 if (push_failed
&& !ignore_stackfaults
) {
6905 /* Derived exception on callee-saves register stacking:
6906 * we might now want to take a different exception which
6907 * targets a different security state, so try again from the top.
6909 v7m_exception_taken(cpu
, lr
, true, true);
6913 if (!arm_v7m_load_vector(cpu
, exc
, targets_secure
, &addr
)) {
6914 /* Vector load failed: derived exception */
6915 v7m_exception_taken(cpu
, lr
, true, true);
6919 /* Now we've done everything that might cause a derived exception
6920 * we can go ahead and activate whichever exception we're going to
6921 * take (which might now be the derived exception).
6923 armv7m_nvic_acknowledge_irq(env
->nvic
);
6925 /* Switch to target security state -- must do this before writing SPSEL */
6926 switch_v7m_security_state(env
, targets_secure
);
6927 write_v7m_control_spsel(env
, 0);
6928 arm_clear_exclusive(env
);
6930 env
->condexec_bits
= 0;
6932 env
->regs
[15] = addr
& 0xfffffffe;
6933 env
->thumb
= addr
& 1;
6936 static bool v7m_push_stack(ARMCPU
*cpu
)
6938 /* Do the "set up stack frame" part of exception entry,
6939 * similar to pseudocode PushStack().
6940 * Return true if we generate a derived exception (and so
6941 * should ignore further stack faults trying to process
6942 * that derived exception.)
6945 CPUARMState
*env
= &cpu
->env
;
6946 uint32_t xpsr
= xpsr_read(env
);
6947 uint32_t frameptr
= env
->regs
[13];
6948 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
6950 /* Align stack pointer if the guest wants that */
6951 if ((frameptr
& 4) &&
6952 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
6954 xpsr
|= XPSR_SPREALIGN
;
6959 /* Write as much of the stack frame as we can. If we fail a stack
6960 * write this will result in a derived exception being pended
6961 * (which may be taken in preference to the one we started with
6962 * if it has higher priority).
6965 v7m_stack_write(cpu
, frameptr
, env
->regs
[0], mmu_idx
, false) &&
6966 v7m_stack_write(cpu
, frameptr
+ 4, env
->regs
[1], mmu_idx
, false) &&
6967 v7m_stack_write(cpu
, frameptr
+ 8, env
->regs
[2], mmu_idx
, false) &&
6968 v7m_stack_write(cpu
, frameptr
+ 12, env
->regs
[3], mmu_idx
, false) &&
6969 v7m_stack_write(cpu
, frameptr
+ 16, env
->regs
[12], mmu_idx
, false) &&
6970 v7m_stack_write(cpu
, frameptr
+ 20, env
->regs
[14], mmu_idx
, false) &&
6971 v7m_stack_write(cpu
, frameptr
+ 24, env
->regs
[15], mmu_idx
, false) &&
6972 v7m_stack_write(cpu
, frameptr
+ 28, xpsr
, mmu_idx
, false);
6974 /* Update SP regardless of whether any of the stack accesses failed.
6975 * When we implement v8M stack limit checking then this attempt to
6976 * update SP might also fail and result in a derived exception.
6978 env
->regs
[13] = frameptr
;
6983 static void do_v7m_exception_exit(ARMCPU
*cpu
)
6985 CPUARMState
*env
= &cpu
->env
;
6988 bool ufault
= false;
6989 bool sfault
= false;
6990 bool return_to_sp_process
;
6991 bool return_to_handler
;
6992 bool rettobase
= false;
6993 bool exc_secure
= false;
6994 bool return_to_secure
;
6996 /* If we're not in Handler mode then jumps to magic exception-exit
6997 * addresses don't have magic behaviour. However for the v8M
6998 * security extensions the magic secure-function-return has to
6999 * work in thread mode too, so to avoid doing an extra check in
7000 * the generated code we allow exception-exit magic to also cause the
7001 * internal exception and bring us here in thread mode. Correct code
7002 * will never try to do this (the following insn fetch will always
7003 * fault) so we the overhead of having taken an unnecessary exception
7006 if (!arm_v7m_is_handler_mode(env
)) {
7010 /* In the spec pseudocode ExceptionReturn() is called directly
7011 * from BXWritePC() and gets the full target PC value including
7012 * bit zero. In QEMU's implementation we treat it as a normal
7013 * jump-to-register (which is then caught later on), and so split
7014 * the target value up between env->regs[15] and env->thumb in
7015 * gen_bx(). Reconstitute it.
7017 excret
= env
->regs
[15];
7022 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
7023 " previous exception %d\n",
7024 excret
, env
->v7m
.exception
);
7026 if ((excret
& R_V7M_EXCRET_RES1_MASK
) != R_V7M_EXCRET_RES1_MASK
) {
7027 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
7028 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n",
7032 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7033 /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
7034 * we pick which FAULTMASK to clear.
7036 if (!env
->v7m
.secure
&&
7037 ((excret
& R_V7M_EXCRET_ES_MASK
) ||
7038 !(excret
& R_V7M_EXCRET_DCRS_MASK
))) {
7040 /* For all other purposes, treat ES as 0 (R_HXSR) */
7041 excret
&= ~R_V7M_EXCRET_ES_MASK
;
7045 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
7046 /* Auto-clear FAULTMASK on return from other than NMI.
7047 * If the security extension is implemented then this only
7048 * happens if the raw execution priority is >= 0; the
7049 * value of the ES bit in the exception return value indicates
7050 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
7052 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7053 exc_secure
= excret
& R_V7M_EXCRET_ES_MASK
;
7054 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
7055 env
->v7m
.faultmask
[exc_secure
] = 0;
7058 env
->v7m
.faultmask
[M_REG_NS
] = 0;
7062 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
,
7065 /* attempt to exit an exception that isn't active */
7069 /* still an irq active now */
7072 /* we returned to base exception level, no nesting.
7073 * (In the pseudocode this is written using "NestedActivation != 1"
7074 * where we have 'rettobase == false'.)
7079 g_assert_not_reached();
7082 return_to_handler
= !(excret
& R_V7M_EXCRET_MODE_MASK
);
7083 return_to_sp_process
= excret
& R_V7M_EXCRET_SPSEL_MASK
;
7084 return_to_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
7085 (excret
& R_V7M_EXCRET_S_MASK
);
7087 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7088 if (!arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
7089 /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
7090 * we choose to take the UsageFault.
7092 if ((excret
& R_V7M_EXCRET_S_MASK
) ||
7093 (excret
& R_V7M_EXCRET_ES_MASK
) ||
7094 !(excret
& R_V7M_EXCRET_DCRS_MASK
)) {
7098 if (excret
& R_V7M_EXCRET_RES0_MASK
) {
7102 /* For v7M we only recognize certain combinations of the low bits */
7103 switch (excret
& 0xf) {
7104 case 1: /* Return to Handler */
7106 case 13: /* Return to Thread using Process stack */
7107 case 9: /* Return to Thread using Main stack */
7108 /* We only need to check NONBASETHRDENA for v7M, because in
7109 * v8M this bit does not exist (it is RES1).
7112 !(env
->v7m
.ccr
[env
->v7m
.secure
] &
7113 R_V7M_CCR_NONBASETHRDENA_MASK
)) {
7123 env
->v7m
.sfsr
|= R_V7M_SFSR_INVER_MASK
;
7124 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7125 v7m_exception_taken(cpu
, excret
, true, false);
7126 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
7127 "stackframe: failed EXC_RETURN.ES validity check\n");
7132 /* Bad exception return: instead of popping the exception
7133 * stack, directly take a usage fault on the current stack.
7135 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7136 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7137 v7m_exception_taken(cpu
, excret
, true, false);
7138 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
7139 "stackframe: failed exception return integrity check\n");
7143 /* Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
7144 * Handler mode (and will be until we write the new XPSR.Interrupt
7145 * field) this does not switch around the current stack pointer.
7147 write_v7m_control_spsel_for_secstate(env
, return_to_sp_process
, exc_secure
);
7149 switch_v7m_security_state(env
, return_to_secure
);
7152 /* The stack pointer we should be reading the exception frame from
7153 * depends on bits in the magic exception return type value (and
7154 * for v8M isn't necessarily the stack pointer we will eventually
7155 * end up resuming execution with). Get a pointer to the location
7156 * in the CPU state struct where the SP we need is currently being
7157 * stored; we will use and modify it in place.
7158 * We use this limited C variable scope so we don't accidentally
7159 * use 'frame_sp_p' after we do something that makes it invalid.
7161 uint32_t *frame_sp_p
= get_v7m_sp_ptr(env
,
7164 return_to_sp_process
);
7165 uint32_t frameptr
= *frame_sp_p
;
7168 bool return_to_priv
= return_to_handler
||
7169 !(env
->v7m
.control
[return_to_secure
] & R_V7M_CONTROL_NPRIV_MASK
);
7171 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, return_to_secure
,
7174 if (!QEMU_IS_ALIGNED(frameptr
, 8) &&
7175 arm_feature(env
, ARM_FEATURE_V8
)) {
7176 qemu_log_mask(LOG_GUEST_ERROR
,
7177 "M profile exception return with non-8-aligned SP "
7178 "for destination state is UNPREDICTABLE\n");
7181 /* Do we need to pop callee-saved registers? */
7182 if (return_to_secure
&&
7183 ((excret
& R_V7M_EXCRET_ES_MASK
) == 0 ||
7184 (excret
& R_V7M_EXCRET_DCRS_MASK
) == 0)) {
7185 uint32_t expected_sig
= 0xfefa125b;
7186 uint32_t actual_sig
;
7188 pop_ok
= v7m_stack_read(cpu
, &actual_sig
, frameptr
, mmu_idx
);
7190 if (pop_ok
&& expected_sig
!= actual_sig
) {
7191 /* Take a SecureFault on the current stack */
7192 env
->v7m
.sfsr
|= R_V7M_SFSR_INVIS_MASK
;
7193 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7194 v7m_exception_taken(cpu
, excret
, true, false);
7195 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
7196 "stackframe: failed exception return integrity "
7197 "signature check\n");
7202 v7m_stack_read(cpu
, &env
->regs
[4], frameptr
+ 0x8, mmu_idx
) &&
7203 v7m_stack_read(cpu
, &env
->regs
[4], frameptr
+ 0x8, mmu_idx
) &&
7204 v7m_stack_read(cpu
, &env
->regs
[5], frameptr
+ 0xc, mmu_idx
) &&
7205 v7m_stack_read(cpu
, &env
->regs
[6], frameptr
+ 0x10, mmu_idx
) &&
7206 v7m_stack_read(cpu
, &env
->regs
[7], frameptr
+ 0x14, mmu_idx
) &&
7207 v7m_stack_read(cpu
, &env
->regs
[8], frameptr
+ 0x18, mmu_idx
) &&
7208 v7m_stack_read(cpu
, &env
->regs
[9], frameptr
+ 0x1c, mmu_idx
) &&
7209 v7m_stack_read(cpu
, &env
->regs
[10], frameptr
+ 0x20, mmu_idx
) &&
7210 v7m_stack_read(cpu
, &env
->regs
[11], frameptr
+ 0x24, mmu_idx
);
7217 v7m_stack_read(cpu
, &env
->regs
[0], frameptr
, mmu_idx
) &&
7218 v7m_stack_read(cpu
, &env
->regs
[1], frameptr
+ 0x4, mmu_idx
) &&
7219 v7m_stack_read(cpu
, &env
->regs
[2], frameptr
+ 0x8, mmu_idx
) &&
7220 v7m_stack_read(cpu
, &env
->regs
[3], frameptr
+ 0xc, mmu_idx
) &&
7221 v7m_stack_read(cpu
, &env
->regs
[12], frameptr
+ 0x10, mmu_idx
) &&
7222 v7m_stack_read(cpu
, &env
->regs
[14], frameptr
+ 0x14, mmu_idx
) &&
7223 v7m_stack_read(cpu
, &env
->regs
[15], frameptr
+ 0x18, mmu_idx
) &&
7224 v7m_stack_read(cpu
, &xpsr
, frameptr
+ 0x1c, mmu_idx
);
7227 /* v7m_stack_read() pended a fault, so take it (as a tail
7228 * chained exception on the same stack frame)
7230 v7m_exception_taken(cpu
, excret
, true, false);
7234 /* Returning from an exception with a PC with bit 0 set is defined
7235 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
7236 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
7237 * the lsbit, and there are several RTOSes out there which incorrectly
7238 * assume the r15 in the stack frame should be a Thumb-style "lsbit
7239 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
7240 * complain about the badly behaved guest.
7242 if (env
->regs
[15] & 1) {
7243 env
->regs
[15] &= ~1U;
7244 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7245 qemu_log_mask(LOG_GUEST_ERROR
,
7246 "M profile return from interrupt with misaligned "
7247 "PC is UNPREDICTABLE on v7M\n");
7251 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7252 /* For v8M we have to check whether the xPSR exception field
7253 * matches the EXCRET value for return to handler/thread
7254 * before we commit to changing the SP and xPSR.
7256 bool will_be_handler
= (xpsr
& XPSR_EXCP
) != 0;
7257 if (return_to_handler
!= will_be_handler
) {
7258 /* Take an INVPC UsageFault on the current stack.
7259 * By this point we will have switched to the security state
7260 * for the background state, so this UsageFault will target
7263 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
7265 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7266 v7m_exception_taken(cpu
, excret
, true, false);
7267 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
7268 "stackframe: failed exception return integrity "
7274 /* Commit to consuming the stack frame */
7276 /* Undo stack alignment (the SPREALIGN bit indicates that the original
7277 * pre-exception SP was not 8-aligned and we added a padding word to
7278 * align it, so we undo this by ORing in the bit that increases it
7279 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
7280 * would work too but a logical OR is how the pseudocode specifies it.)
7282 if (xpsr
& XPSR_SPREALIGN
) {
7285 *frame_sp_p
= frameptr
;
7287 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
7288 xpsr_write(env
, xpsr
, ~XPSR_SPREALIGN
);
7290 /* The restored xPSR exception field will be zero if we're
7291 * resuming in Thread mode. If that doesn't match what the
7292 * exception return excret specified then this is a UsageFault.
7293 * v7M requires we make this check here; v8M did it earlier.
7295 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
7296 /* Take an INVPC UsageFault by pushing the stack again;
7297 * we know we're v7M so this is never a Secure UsageFault.
7299 bool ignore_stackfaults
;
7301 assert(!arm_feature(env
, ARM_FEATURE_V8
));
7302 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, false);
7303 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7304 ignore_stackfaults
= v7m_push_stack(cpu
);
7305 v7m_exception_taken(cpu
, excret
, false, ignore_stackfaults
);
7306 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
7307 "failed exception return integrity check\n");
7311 /* Otherwise, we have a successful exception exit. */
7312 arm_clear_exclusive(env
);
7313 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
7316 static bool do_v7m_function_return(ARMCPU
*cpu
)
7318 /* v8M security extensions magic function return.
7320 * (1) throw an exception (longjump)
7321 * (2) return true if we successfully handled the function return
7322 * (3) return false if we failed a consistency check and have
7323 * pended a UsageFault that needs to be taken now
7325 * At this point the magic return value is split between env->regs[15]
7326 * and env->thumb. We don't bother to reconstitute it because we don't
7327 * need it (all values are handled the same way).
7329 CPUARMState
*env
= &cpu
->env
;
7330 uint32_t newpc
, newpsr
, newpsr_exc
;
7332 qemu_log_mask(CPU_LOG_INT
, "...really v7M secure function return\n");
7335 bool threadmode
, spsel
;
7338 uint32_t *frame_sp_p
;
7341 /* Pull the return address and IPSR from the Secure stack */
7342 threadmode
= !arm_v7m_is_handler_mode(env
);
7343 spsel
= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SPSEL_MASK
;
7345 frame_sp_p
= get_v7m_sp_ptr(env
, true, threadmode
, spsel
);
7346 frameptr
= *frame_sp_p
;
7348 /* These loads may throw an exception (for MPU faults). We want to
7349 * do them as secure, so work out what MMU index that is.
7351 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
7352 oi
= make_memop_idx(MO_LE
, arm_to_core_mmu_idx(mmu_idx
));
7353 newpc
= helper_le_ldul_mmu(env
, frameptr
, oi
, 0);
7354 newpsr
= helper_le_ldul_mmu(env
, frameptr
+ 4, oi
, 0);
7356 /* Consistency checks on new IPSR */
7357 newpsr_exc
= newpsr
& XPSR_EXCP
;
7358 if (!((env
->v7m
.exception
== 0 && newpsr_exc
== 0) ||
7359 (env
->v7m
.exception
== 1 && newpsr_exc
!= 0))) {
7360 /* Pend the fault and tell our caller to take it */
7361 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
7362 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
7364 qemu_log_mask(CPU_LOG_INT
,
7365 "...taking INVPC UsageFault: "
7366 "IPSR consistency check failed\n");
7370 *frame_sp_p
= frameptr
+ 8;
7373 /* This invalidates frame_sp_p */
7374 switch_v7m_security_state(env
, true);
7375 env
->v7m
.exception
= newpsr_exc
;
7376 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
7377 if (newpsr
& XPSR_SFPA
) {
7378 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_SFPA_MASK
;
7380 xpsr_write(env
, 0, XPSR_IT
);
7381 env
->thumb
= newpc
& 1;
7382 env
->regs
[15] = newpc
& ~1;
7384 qemu_log_mask(CPU_LOG_INT
, "...function return successful\n");
7388 static void arm_log_exception(int idx
)
7390 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
7391 const char *exc
= NULL
;
7392 static const char * const excnames
[] = {
7393 [EXCP_UDEF
] = "Undefined Instruction",
7395 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
7396 [EXCP_DATA_ABORT
] = "Data Abort",
7399 [EXCP_BKPT
] = "Breakpoint",
7400 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
7401 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
7402 [EXCP_HVC
] = "Hypervisor Call",
7403 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
7404 [EXCP_SMC
] = "Secure Monitor Call",
7405 [EXCP_VIRQ
] = "Virtual IRQ",
7406 [EXCP_VFIQ
] = "Virtual FIQ",
7407 [EXCP_SEMIHOST
] = "Semihosting call",
7408 [EXCP_NOCP
] = "v7M NOCP UsageFault",
7409 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
7412 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
7413 exc
= excnames
[idx
];
7418 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
7422 static bool v7m_read_half_insn(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
7423 uint32_t addr
, uint16_t *insn
)
7425 /* Load a 16-bit portion of a v7M instruction, returning true on success,
7426 * or false on failure (in which case we will have pended the appropriate
7428 * We need to do the instruction fetch's MPU and SAU checks
7429 * like this because there is no MMU index that would allow
7430 * doing the load with a single function call. Instead we must
7431 * first check that the security attributes permit the load
7432 * and that they don't mismatch on the two halves of the instruction,
7433 * and then we do the load as a secure load (ie using the security
7434 * attributes of the address, not the CPU, as architecturally required).
7436 CPUState
*cs
= CPU(cpu
);
7437 CPUARMState
*env
= &cpu
->env
;
7438 V8M_SAttributes sattrs
= {};
7439 MemTxAttrs attrs
= {};
7440 ARMMMUFaultInfo fi
= {};
7442 target_ulong page_size
;
7446 v8m_security_lookup(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &sattrs
);
7447 if (!sattrs
.nsc
|| sattrs
.ns
) {
7448 /* This must be the second half of the insn, and it straddles a
7449 * region boundary with the second half not being S&NSC.
7451 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7452 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7453 qemu_log_mask(CPU_LOG_INT
,
7454 "...really SecureFault with SFSR.INVEP\n");
7457 if (get_phys_addr(env
, addr
, MMU_INST_FETCH
, mmu_idx
,
7458 &physaddr
, &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
7459 /* the MPU lookup failed */
7460 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7461 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, env
->v7m
.secure
);
7462 qemu_log_mask(CPU_LOG_INT
, "...really MemManage with CFSR.IACCVIOL\n");
7465 *insn
= address_space_lduw_le(arm_addressspace(cs
, attrs
), physaddr
,
7467 if (txres
!= MEMTX_OK
) {
7468 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7469 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7470 qemu_log_mask(CPU_LOG_INT
, "...really BusFault with CFSR.IBUSERR\n");
7476 static bool v7m_handle_execute_nsc(ARMCPU
*cpu
)
7478 /* Check whether this attempt to execute code in a Secure & NS-Callable
7479 * memory region is for an SG instruction; if so, then emulate the
7480 * effect of the SG instruction and return true. Otherwise pend
7481 * the correct kind of exception and return false.
7483 CPUARMState
*env
= &cpu
->env
;
7487 /* We should never get here unless get_phys_addr_pmsav8() caused
7488 * an exception for NS executing in S&NSC memory.
7490 assert(!env
->v7m
.secure
);
7491 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7493 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
7494 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
7496 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15], &insn
)) {
7504 if (insn
!= 0xe97f) {
7505 /* Not an SG instruction first half (we choose the IMPDEF
7506 * early-SG-check option).
7511 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15] + 2, &insn
)) {
7515 if (insn
!= 0xe97f) {
7516 /* Not an SG instruction second half (yes, both halves of the SG
7517 * insn have the same hex value)
7522 /* OK, we have confirmed that we really have an SG instruction.
7523 * We know we're NS in S memory so don't need to repeat those checks.
7525 qemu_log_mask(CPU_LOG_INT
, "...really an SG instruction at 0x%08" PRIx32
7526 ", executing it\n", env
->regs
[15]);
7527 env
->regs
[14] &= ~1;
7528 switch_v7m_security_state(env
, true);
7529 xpsr_write(env
, 0, XPSR_IT
);
7534 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7535 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7536 qemu_log_mask(CPU_LOG_INT
,
7537 "...really SecureFault with SFSR.INVEP\n");
7541 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
7543 ARMCPU
*cpu
= ARM_CPU(cs
);
7544 CPUARMState
*env
= &cpu
->env
;
7546 bool ignore_stackfaults
;
7548 arm_log_exception(cs
->exception_index
);
7550 /* For exceptions we just mark as pending on the NVIC, and let that
7552 switch (cs
->exception_index
) {
7554 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7555 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNDEFINSTR_MASK
;
7558 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7559 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_NOCP_MASK
;
7562 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7563 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVSTATE_MASK
;
7566 /* The PC already points to the next instruction. */
7567 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
, env
->v7m
.secure
);
7569 case EXCP_PREFETCH_ABORT
:
7570 case EXCP_DATA_ABORT
:
7571 /* Note that for M profile we don't have a guest facing FSR, but
7572 * the env->exception.fsr will be populated by the code that
7573 * raises the fault, in the A profile short-descriptor format.
7575 switch (env
->exception
.fsr
& 0xf) {
7576 case M_FAKE_FSR_NSC_EXEC
:
7577 /* Exception generated when we try to execute code at an address
7578 * which is marked as Secure & Non-Secure Callable and the CPU
7579 * is in the Non-Secure state. The only instruction which can
7580 * be executed like this is SG (and that only if both halves of
7581 * the SG instruction have the same security attributes.)
7582 * Everything else must generate an INVEP SecureFault, so we
7583 * emulate the SG instruction here.
7585 if (v7m_handle_execute_nsc(cpu
)) {
7589 case M_FAKE_FSR_SFAULT
:
7590 /* Various flavours of SecureFault for attempts to execute or
7591 * access data in the wrong security state.
7593 switch (cs
->exception_index
) {
7594 case EXCP_PREFETCH_ABORT
:
7595 if (env
->v7m
.secure
) {
7596 env
->v7m
.sfsr
|= R_V7M_SFSR_INVTRAN_MASK
;
7597 qemu_log_mask(CPU_LOG_INT
,
7598 "...really SecureFault with SFSR.INVTRAN\n");
7600 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7601 qemu_log_mask(CPU_LOG_INT
,
7602 "...really SecureFault with SFSR.INVEP\n");
7605 case EXCP_DATA_ABORT
:
7606 /* This must be an NS access to S memory */
7607 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
7608 qemu_log_mask(CPU_LOG_INT
,
7609 "...really SecureFault with SFSR.AUVIOL\n");
7612 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7614 case 0x8: /* External Abort */
7615 switch (cs
->exception_index
) {
7616 case EXCP_PREFETCH_ABORT
:
7617 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7618 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IBUSERR\n");
7620 case EXCP_DATA_ABORT
:
7621 env
->v7m
.cfsr
[M_REG_NS
] |=
7622 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
7623 env
->v7m
.bfar
= env
->exception
.vaddress
;
7624 qemu_log_mask(CPU_LOG_INT
,
7625 "...with CFSR.PRECISERR and BFAR 0x%x\n",
7629 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7632 /* All other FSR values are either MPU faults or "can't happen
7633 * for M profile" cases.
7635 switch (cs
->exception_index
) {
7636 case EXCP_PREFETCH_ABORT
:
7637 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7638 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
7640 case EXCP_DATA_ABORT
:
7641 env
->v7m
.cfsr
[env
->v7m
.secure
] |=
7642 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
7643 env
->v7m
.mmfar
[env
->v7m
.secure
] = env
->exception
.vaddress
;
7644 qemu_log_mask(CPU_LOG_INT
,
7645 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
7646 env
->v7m
.mmfar
[env
->v7m
.secure
]);
7649 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
,
7655 if (semihosting_enabled()) {
7657 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
7660 qemu_log_mask(CPU_LOG_INT
,
7661 "...handling as semihosting call 0x%x\n",
7663 env
->regs
[0] = do_arm_semihosting(env
);
7667 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
, false);
7671 case EXCP_EXCEPTION_EXIT
:
7672 if (env
->regs
[15] < EXC_RETURN_MIN_MAGIC
) {
7673 /* Must be v8M security extension function return */
7674 assert(env
->regs
[15] >= FNC_RETURN_MIN_MAGIC
);
7675 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7676 if (do_v7m_function_return(cpu
)) {
7680 do_v7m_exception_exit(cpu
);
7685 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7686 return; /* Never happens. Keep compiler happy. */
7689 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7690 lr
= R_V7M_EXCRET_RES1_MASK
|
7691 R_V7M_EXCRET_DCRS_MASK
|
7692 R_V7M_EXCRET_FTYPE_MASK
;
7693 /* The S bit indicates whether we should return to Secure
7694 * or NonSecure (ie our current state).
7695 * The ES bit indicates whether we're taking this exception
7696 * to Secure or NonSecure (ie our target state). We set it
7697 * later, in v7m_exception_taken().
7698 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
7699 * This corresponds to the ARM ARM pseudocode for v8M setting
7700 * some LR bits in PushStack() and some in ExceptionTaken();
7701 * the distinction matters for the tailchain cases where we
7702 * can take an exception without pushing the stack.
7704 if (env
->v7m
.secure
) {
7705 lr
|= R_V7M_EXCRET_S_MASK
;
7708 lr
= R_V7M_EXCRET_RES1_MASK
|
7709 R_V7M_EXCRET_S_MASK
|
7710 R_V7M_EXCRET_DCRS_MASK
|
7711 R_V7M_EXCRET_FTYPE_MASK
|
7712 R_V7M_EXCRET_ES_MASK
;
7713 if (env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
) {
7714 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
7717 if (!arm_v7m_is_handler_mode(env
)) {
7718 lr
|= R_V7M_EXCRET_MODE_MASK
;
7721 ignore_stackfaults
= v7m_push_stack(cpu
);
7722 v7m_exception_taken(cpu
, lr
, false, ignore_stackfaults
);
7723 qemu_log_mask(CPU_LOG_INT
, "... as %d\n", env
->v7m
.exception
);
7726 /* Function used to synchronize QEMU's AArch64 register set with AArch32
7727 * register set. This is necessary when switching between AArch32 and AArch64
7730 void aarch64_sync_32_to_64(CPUARMState
*env
)
7733 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7735 /* We can blanket copy R[0:7] to X[0:7] */
7736 for (i
= 0; i
< 8; i
++) {
7737 env
->xregs
[i
] = env
->regs
[i
];
7740 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
7741 * Otherwise, they come from the banked user regs.
7743 if (mode
== ARM_CPU_MODE_FIQ
) {
7744 for (i
= 8; i
< 13; i
++) {
7745 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
7748 for (i
= 8; i
< 13; i
++) {
7749 env
->xregs
[i
] = env
->regs
[i
];
7753 /* Registers x13-x23 are the various mode SP and FP registers. Registers
7754 * r13 and r14 are only copied if we are in that mode, otherwise we copy
7755 * from the mode banked register.
7757 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7758 env
->xregs
[13] = env
->regs
[13];
7759 env
->xregs
[14] = env
->regs
[14];
7761 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
7762 /* HYP is an exception in that it is copied from r14 */
7763 if (mode
== ARM_CPU_MODE_HYP
) {
7764 env
->xregs
[14] = env
->regs
[14];
7766 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
7770 if (mode
== ARM_CPU_MODE_HYP
) {
7771 env
->xregs
[15] = env
->regs
[13];
7773 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
7776 if (mode
== ARM_CPU_MODE_IRQ
) {
7777 env
->xregs
[16] = env
->regs
[14];
7778 env
->xregs
[17] = env
->regs
[13];
7780 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
7781 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
7784 if (mode
== ARM_CPU_MODE_SVC
) {
7785 env
->xregs
[18] = env
->regs
[14];
7786 env
->xregs
[19] = env
->regs
[13];
7788 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
7789 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
7792 if (mode
== ARM_CPU_MODE_ABT
) {
7793 env
->xregs
[20] = env
->regs
[14];
7794 env
->xregs
[21] = env
->regs
[13];
7796 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
7797 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
7800 if (mode
== ARM_CPU_MODE_UND
) {
7801 env
->xregs
[22] = env
->regs
[14];
7802 env
->xregs
[23] = env
->regs
[13];
7804 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
7805 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
7808 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7809 * mode, then we can copy from r8-r14. Otherwise, we copy from the
7810 * FIQ bank for r8-r14.
7812 if (mode
== ARM_CPU_MODE_FIQ
) {
7813 for (i
= 24; i
< 31; i
++) {
7814 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
7817 for (i
= 24; i
< 29; i
++) {
7818 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
7820 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
7821 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
7824 env
->pc
= env
->regs
[15];
7827 /* Function used to synchronize QEMU's AArch32 register set with AArch64
7828 * register set. This is necessary when switching between AArch32 and AArch64
7831 void aarch64_sync_64_to_32(CPUARMState
*env
)
7834 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7836 /* We can blanket copy X[0:7] to R[0:7] */
7837 for (i
= 0; i
< 8; i
++) {
7838 env
->regs
[i
] = env
->xregs
[i
];
7841 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
7842 * Otherwise, we copy x8-x12 into the banked user regs.
7844 if (mode
== ARM_CPU_MODE_FIQ
) {
7845 for (i
= 8; i
< 13; i
++) {
7846 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
7849 for (i
= 8; i
< 13; i
++) {
7850 env
->regs
[i
] = env
->xregs
[i
];
7854 /* Registers r13 & r14 depend on the current mode.
7855 * If we are in a given mode, we copy the corresponding x registers to r13
7856 * and r14. Otherwise, we copy the x register to the banked r13 and r14
7859 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7860 env
->regs
[13] = env
->xregs
[13];
7861 env
->regs
[14] = env
->xregs
[14];
7863 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
7865 /* HYP is an exception in that it does not have its own banked r14 but
7866 * shares the USR r14
7868 if (mode
== ARM_CPU_MODE_HYP
) {
7869 env
->regs
[14] = env
->xregs
[14];
7871 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
7875 if (mode
== ARM_CPU_MODE_HYP
) {
7876 env
->regs
[13] = env
->xregs
[15];
7878 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
7881 if (mode
== ARM_CPU_MODE_IRQ
) {
7882 env
->regs
[14] = env
->xregs
[16];
7883 env
->regs
[13] = env
->xregs
[17];
7885 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
7886 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
7889 if (mode
== ARM_CPU_MODE_SVC
) {
7890 env
->regs
[14] = env
->xregs
[18];
7891 env
->regs
[13] = env
->xregs
[19];
7893 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
7894 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
7897 if (mode
== ARM_CPU_MODE_ABT
) {
7898 env
->regs
[14] = env
->xregs
[20];
7899 env
->regs
[13] = env
->xregs
[21];
7901 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
7902 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
7905 if (mode
== ARM_CPU_MODE_UND
) {
7906 env
->regs
[14] = env
->xregs
[22];
7907 env
->regs
[13] = env
->xregs
[23];
7909 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
7910 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
7913 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7914 * mode, then we can copy to r8-r14. Otherwise, we copy to the
7915 * FIQ bank for r8-r14.
7917 if (mode
== ARM_CPU_MODE_FIQ
) {
7918 for (i
= 24; i
< 31; i
++) {
7919 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
7922 for (i
= 24; i
< 29; i
++) {
7923 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
7925 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
7926 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
7929 env
->regs
[15] = env
->pc
;
7932 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
7934 ARMCPU
*cpu
= ARM_CPU(cs
);
7935 CPUARMState
*env
= &cpu
->env
;
7942 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
7943 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
7945 case EC_BREAKPOINT_SAME_EL
:
7949 case EC_WATCHPOINT_SAME_EL
:
7955 case EC_VECTORCATCH
:
7964 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
7967 /* TODO: Vectored interrupt controller. */
7968 switch (cs
->exception_index
) {
7970 new_mode
= ARM_CPU_MODE_UND
;
7979 new_mode
= ARM_CPU_MODE_SVC
;
7982 /* The PC already points to the next instruction. */
7986 /* Fall through to prefetch abort. */
7987 case EXCP_PREFETCH_ABORT
:
7988 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
7989 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
7990 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
7991 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
7992 new_mode
= ARM_CPU_MODE_ABT
;
7994 mask
= CPSR_A
| CPSR_I
;
7997 case EXCP_DATA_ABORT
:
7998 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
7999 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
8000 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
8002 (uint32_t)env
->exception
.vaddress
);
8003 new_mode
= ARM_CPU_MODE_ABT
;
8005 mask
= CPSR_A
| CPSR_I
;
8009 new_mode
= ARM_CPU_MODE_IRQ
;
8011 /* Disable IRQ and imprecise data aborts. */
8012 mask
= CPSR_A
| CPSR_I
;
8014 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
8015 /* IRQ routed to monitor mode */
8016 new_mode
= ARM_CPU_MODE_MON
;
8021 new_mode
= ARM_CPU_MODE_FIQ
;
8023 /* Disable FIQ, IRQ and imprecise data aborts. */
8024 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8025 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
8026 /* FIQ routed to monitor mode */
8027 new_mode
= ARM_CPU_MODE_MON
;
8032 new_mode
= ARM_CPU_MODE_IRQ
;
8034 /* Disable IRQ and imprecise data aborts. */
8035 mask
= CPSR_A
| CPSR_I
;
8039 new_mode
= ARM_CPU_MODE_FIQ
;
8041 /* Disable FIQ, IRQ and imprecise data aborts. */
8042 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8046 new_mode
= ARM_CPU_MODE_MON
;
8048 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8052 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8053 return; /* Never happens. Keep compiler happy. */
8056 if (new_mode
== ARM_CPU_MODE_MON
) {
8057 addr
+= env
->cp15
.mvbar
;
8058 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
8059 /* High vectors. When enabled, base address cannot be remapped. */
8062 /* ARM v7 architectures provide a vector base address register to remap
8063 * the interrupt vector table.
8064 * This register is only followed in non-monitor mode, and is banked.
8065 * Note: only bits 31:5 are valid.
8067 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
8070 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
8071 env
->cp15
.scr_el3
&= ~SCR_NS
;
8074 switch_mode (env
, new_mode
);
8075 /* For exceptions taken to AArch32 we must clear the SS bit in both
8076 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
8078 env
->uncached_cpsr
&= ~PSTATE_SS
;
8079 env
->spsr
= cpsr_read(env
);
8080 /* Clear IT bits. */
8081 env
->condexec_bits
= 0;
8082 /* Switch to the new mode, and to the correct instruction set. */
8083 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
8084 /* Set new mode endianness */
8085 env
->uncached_cpsr
&= ~CPSR_E
;
8086 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
8087 env
->uncached_cpsr
|= CPSR_E
;
8090 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
8091 * and we should just guard the thumb mode on V4 */
8092 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
8093 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
8095 env
->regs
[14] = env
->regs
[15] + offset
;
8096 env
->regs
[15] = addr
;
8099 /* Handle exception entry to a target EL which is using AArch64 */
8100 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
8102 ARMCPU
*cpu
= ARM_CPU(cs
);
8103 CPUARMState
*env
= &cpu
->env
;
8104 unsigned int new_el
= env
->exception
.target_el
;
8105 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
8106 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
8108 if (arm_current_el(env
) < new_el
) {
8109 /* Entry vector offset depends on whether the implemented EL
8110 * immediately lower than the target level is using AArch32 or AArch64
8116 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
8119 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
8122 is_aa64
= is_a64(env
);
8125 g_assert_not_reached();
8133 } else if (pstate_read(env
) & PSTATE_SP
) {
8137 switch (cs
->exception_index
) {
8138 case EXCP_PREFETCH_ABORT
:
8139 case EXCP_DATA_ABORT
:
8140 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
8141 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
8142 env
->cp15
.far_el
[new_el
]);
8150 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
8161 qemu_log_mask(CPU_LOG_INT
,
8162 "...handling as semihosting call 0x%" PRIx64
"\n",
8164 env
->xregs
[0] = do_arm_semihosting(env
);
8167 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8171 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
8172 aarch64_save_sp(env
, arm_current_el(env
));
8173 env
->elr_el
[new_el
] = env
->pc
;
8175 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
8176 env
->elr_el
[new_el
] = env
->regs
[15];
8178 aarch64_sync_32_to_64(env
);
8180 env
->condexec_bits
= 0;
8182 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
8183 env
->elr_el
[new_el
]);
8185 pstate_write(env
, PSTATE_DAIF
| new_mode
);
8187 aarch64_restore_sp(env
, new_el
);
8191 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
8192 new_el
, env
->pc
, pstate_read(env
));
8195 static inline bool check_for_semihosting(CPUState
*cs
)
8197 /* Check whether this exception is a semihosting call; if so
8198 * then handle it and return true; otherwise return false.
8200 ARMCPU
*cpu
= ARM_CPU(cs
);
8201 CPUARMState
*env
= &cpu
->env
;
8204 if (cs
->exception_index
== EXCP_SEMIHOST
) {
8205 /* This is always the 64-bit semihosting exception.
8206 * The "is this usermode" and "is semihosting enabled"
8207 * checks have been done at translate time.
8209 qemu_log_mask(CPU_LOG_INT
,
8210 "...handling as semihosting call 0x%" PRIx64
"\n",
8212 env
->xregs
[0] = do_arm_semihosting(env
);
8219 /* Only intercept calls from privileged modes, to provide some
8220 * semblance of security.
8222 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
8223 (!semihosting_enabled() ||
8224 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
8228 switch (cs
->exception_index
) {
8230 /* This is always a semihosting call; the "is this usermode"
8231 * and "is semihosting enabled" checks have been done at
8236 /* Check for semihosting interrupt. */
8238 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
8244 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
8246 if (imm
== 0x123456) {
8252 /* See if this is a semihosting syscall. */
8254 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
8266 qemu_log_mask(CPU_LOG_INT
,
8267 "...handling as semihosting call 0x%x\n",
8269 env
->regs
[0] = do_arm_semihosting(env
);
8274 /* Handle a CPU exception for A and R profile CPUs.
8275 * Do any appropriate logging, handle PSCI calls, and then hand off
8276 * to the AArch64-entry or AArch32-entry function depending on the
8277 * target exception level's register width.
8279 void arm_cpu_do_interrupt(CPUState
*cs
)
8281 ARMCPU
*cpu
= ARM_CPU(cs
);
8282 CPUARMState
*env
= &cpu
->env
;
8283 unsigned int new_el
= env
->exception
.target_el
;
8285 assert(!arm_feature(env
, ARM_FEATURE_M
));
8287 arm_log_exception(cs
->exception_index
);
8288 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
8290 if (qemu_loglevel_mask(CPU_LOG_INT
)
8291 && !excp_is_internal(cs
->exception_index
)) {
8292 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
8293 env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
,
8294 env
->exception
.syndrome
);
8297 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
8298 arm_handle_psci_call(cpu
);
8299 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
8303 /* Semihosting semantics depend on the register width of the
8304 * code that caused the exception, not the target exception level,
8305 * so must be handled here.
8307 if (check_for_semihosting(cs
)) {
8311 /* Hooks may change global state so BQL should be held, also the
8312 * BQL needs to be held for any modification of
8313 * cs->interrupt_request.
8315 g_assert(qemu_mutex_iothread_locked());
8317 arm_call_pre_el_change_hook(cpu
);
8319 assert(!excp_is_internal(cs
->exception_index
));
8320 if (arm_el_is_aa64(env
, new_el
)) {
8321 arm_cpu_do_interrupt_aarch64(cs
);
8323 arm_cpu_do_interrupt_aarch32(cs
);
8326 arm_call_el_change_hook(cpu
);
8328 if (!kvm_enabled()) {
8329 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
8333 /* Return the exception level which controls this address translation regime */
8334 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8337 case ARMMMUIdx_S2NS
:
8338 case ARMMMUIdx_S1E2
:
8340 case ARMMMUIdx_S1E3
:
8342 case ARMMMUIdx_S1SE0
:
8343 return arm_el_is_aa64(env
, 3) ? 1 : 3;
8344 case ARMMMUIdx_S1SE1
:
8345 case ARMMMUIdx_S1NSE0
:
8346 case ARMMMUIdx_S1NSE1
:
8347 case ARMMMUIdx_MPrivNegPri
:
8348 case ARMMMUIdx_MUserNegPri
:
8349 case ARMMMUIdx_MPriv
:
8350 case ARMMMUIdx_MUser
:
8351 case ARMMMUIdx_MSPrivNegPri
:
8352 case ARMMMUIdx_MSUserNegPri
:
8353 case ARMMMUIdx_MSPriv
:
8354 case ARMMMUIdx_MSUser
:
8357 g_assert_not_reached();
8361 /* Return the SCTLR value which controls this address translation regime */
8362 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8364 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
8367 /* Return true if the specified stage of address translation is disabled */
8368 static inline bool regime_translation_disabled(CPUARMState
*env
,
8371 if (arm_feature(env
, ARM_FEATURE_M
)) {
8372 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
8373 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
8374 case R_V7M_MPU_CTRL_ENABLE_MASK
:
8375 /* Enabled, but not for HardFault and NMI */
8376 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
8377 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
8378 /* Enabled for all cases */
8382 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
8383 * we warned about that in armv7m_nvic.c when the guest set it.
8389 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8390 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
8392 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
8395 static inline bool regime_translation_big_endian(CPUARMState
*env
,
8398 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
8401 /* Return the TCR controlling this translation regime */
8402 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8404 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8405 return &env
->cp15
.vtcr_el2
;
8407 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
8410 /* Convert a possible stage1+2 MMU index into the appropriate
8413 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
8415 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
8416 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
8421 /* Returns TBI0 value for current regime el */
8422 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8427 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8428 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8430 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8432 tcr
= regime_tcr(env
, mmu_idx
);
8433 el
= regime_el(env
, mmu_idx
);
8436 return extract64(tcr
->raw_tcr
, 20, 1);
8438 return extract64(tcr
->raw_tcr
, 37, 1);
8442 /* Returns TBI1 value for current regime el */
8443 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8448 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8449 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8451 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8453 tcr
= regime_tcr(env
, mmu_idx
);
8454 el
= regime_el(env
, mmu_idx
);
8459 return extract64(tcr
->raw_tcr
, 38, 1);
8463 /* Return the TTBR associated with this translation regime */
8464 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8467 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8468 return env
->cp15
.vttbr_el2
;
8471 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
8473 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
8477 /* Return true if the translation regime is using LPAE format page tables */
8478 static inline bool regime_using_lpae_format(CPUARMState
*env
,
8481 int el
= regime_el(env
, mmu_idx
);
8482 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
8485 if (arm_feature(env
, ARM_FEATURE_LPAE
)
8486 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
8492 /* Returns true if the stage 1 translation regime is using LPAE format page
8493 * tables. Used when raising alignment exceptions, whose FSR changes depending
8494 * on whether the long or short descriptor format is in use. */
8495 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8497 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8499 return regime_using_lpae_format(env
, mmu_idx
);
8502 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8505 case ARMMMUIdx_S1SE0
:
8506 case ARMMMUIdx_S1NSE0
:
8507 case ARMMMUIdx_MUser
:
8508 case ARMMMUIdx_MSUser
:
8509 case ARMMMUIdx_MUserNegPri
:
8510 case ARMMMUIdx_MSUserNegPri
:
8514 case ARMMMUIdx_S12NSE0
:
8515 case ARMMMUIdx_S12NSE1
:
8516 g_assert_not_reached();
8520 /* Translate section/page access permissions to page
8521 * R/W protection flags
8524 * @mmu_idx: MMU index indicating required translation regime
8525 * @ap: The 3-bit access permissions (AP[2:0])
8526 * @domain_prot: The 2-bit domain access permissions
8528 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8529 int ap
, int domain_prot
)
8531 bool is_user
= regime_is_user(env
, mmu_idx
);
8533 if (domain_prot
== 3) {
8534 return PAGE_READ
| PAGE_WRITE
;
8539 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8542 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
8544 return is_user
? 0 : PAGE_READ
;
8551 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8556 return PAGE_READ
| PAGE_WRITE
;
8559 return PAGE_READ
| PAGE_WRITE
;
8560 case 4: /* Reserved. */
8563 return is_user
? 0 : PAGE_READ
;
8567 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
8572 g_assert_not_reached();
8576 /* Translate section/page access permissions to page
8577 * R/W protection flags.
8579 * @ap: The 2-bit simple AP (AP[2:1])
8580 * @is_user: TRUE if accessing from PL0
8582 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
8586 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8588 return PAGE_READ
| PAGE_WRITE
;
8590 return is_user
? 0 : PAGE_READ
;
8594 g_assert_not_reached();
8599 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
8601 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
8604 /* Translate S2 section/page access permissions to protection flags
8607 * @s2ap: The 2-bit stage2 access permissions (S2AP)
8608 * @xn: XN (execute-never) bit
8610 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
8621 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
8628 /* Translate section/page access permissions to protection flags
8631 * @mmu_idx: MMU index indicating required translation regime
8632 * @is_aa64: TRUE if AArch64
8633 * @ap: The 2-bit simple AP (AP[2:1])
8634 * @ns: NS (non-secure) bit
8635 * @xn: XN (execute-never) bit
8636 * @pxn: PXN (privileged execute-never) bit
8638 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
8639 int ap
, int ns
, int xn
, int pxn
)
8641 bool is_user
= regime_is_user(env
, mmu_idx
);
8642 int prot_rw
, user_rw
;
8646 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
8648 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
8652 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
8655 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
8659 /* TODO have_wxn should be replaced with
8660 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
8661 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
8662 * compatible processors have EL2, which is required for [U]WXN.
8664 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
8667 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
8671 switch (regime_el(env
, mmu_idx
)) {
8674 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
8681 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8682 switch (regime_el(env
, mmu_idx
)) {
8686 xn
= xn
|| !(user_rw
& PAGE_READ
);
8690 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
8692 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
8693 (uwxn
&& (user_rw
& PAGE_WRITE
));
8703 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
8706 return prot_rw
| PAGE_EXEC
;
8709 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8710 uint32_t *table
, uint32_t address
)
8712 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
8713 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8715 if (address
& tcr
->mask
) {
8716 if (tcr
->raw_tcr
& TTBCR_PD1
) {
8717 /* Translation table walk disabled for TTBR1 */
8720 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
8722 if (tcr
->raw_tcr
& TTBCR_PD0
) {
8723 /* Translation table walk disabled for TTBR0 */
8726 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
8728 *table
|= (address
>> 18) & 0x3ffc;
8732 /* Translate a S1 pagetable walk through S2 if needed. */
8733 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8734 hwaddr addr
, MemTxAttrs txattrs
,
8735 ARMMMUFaultInfo
*fi
)
8737 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
8738 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
8739 target_ulong s2size
;
8744 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
8745 &txattrs
, &s2prot
, &s2size
, fi
, NULL
);
8747 assert(fi
->type
!= ARMFault_None
);
8758 /* All loads done in the course of a page table walk go through here. */
8759 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8760 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
8762 ARMCPU
*cpu
= ARM_CPU(cs
);
8763 CPUARMState
*env
= &cpu
->env
;
8764 MemTxAttrs attrs
= {};
8765 MemTxResult result
= MEMTX_OK
;
8769 attrs
.secure
= is_secure
;
8770 as
= arm_addressspace(cs
, attrs
);
8771 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
8775 if (regime_translation_big_endian(env
, mmu_idx
)) {
8776 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
8778 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
8780 if (result
== MEMTX_OK
) {
8783 fi
->type
= ARMFault_SyncExternalOnWalk
;
8784 fi
->ea
= arm_extabort_type(result
);
8788 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8789 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
8791 ARMCPU
*cpu
= ARM_CPU(cs
);
8792 CPUARMState
*env
= &cpu
->env
;
8793 MemTxAttrs attrs
= {};
8794 MemTxResult result
= MEMTX_OK
;
8798 attrs
.secure
= is_secure
;
8799 as
= arm_addressspace(cs
, attrs
);
8800 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
8804 if (regime_translation_big_endian(env
, mmu_idx
)) {
8805 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
8807 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
8809 if (result
== MEMTX_OK
) {
8812 fi
->type
= ARMFault_SyncExternalOnWalk
;
8813 fi
->ea
= arm_extabort_type(result
);
8817 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
8818 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8819 hwaddr
*phys_ptr
, int *prot
,
8820 target_ulong
*page_size
,
8821 ARMMMUFaultInfo
*fi
)
8823 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
8834 /* Pagetable walk. */
8835 /* Lookup l1 descriptor. */
8836 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8837 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8838 fi
->type
= ARMFault_Translation
;
8841 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8843 if (fi
->type
!= ARMFault_None
) {
8847 domain
= (desc
>> 5) & 0x0f;
8848 if (regime_el(env
, mmu_idx
) == 1) {
8849 dacr
= env
->cp15
.dacr_ns
;
8851 dacr
= env
->cp15
.dacr_s
;
8853 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8855 /* Section translation fault. */
8856 fi
->type
= ARMFault_Translation
;
8862 if (domain_prot
== 0 || domain_prot
== 2) {
8863 fi
->type
= ARMFault_Domain
;
8868 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
8869 ap
= (desc
>> 10) & 3;
8870 *page_size
= 1024 * 1024;
8872 /* Lookup l2 entry. */
8874 /* Coarse pagetable. */
8875 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
8877 /* Fine pagetable. */
8878 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
8880 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8882 if (fi
->type
!= ARMFault_None
) {
8886 case 0: /* Page translation fault. */
8887 fi
->type
= ARMFault_Translation
;
8889 case 1: /* 64k page. */
8890 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
8891 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
8892 *page_size
= 0x10000;
8894 case 2: /* 4k page. */
8895 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8896 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
8897 *page_size
= 0x1000;
8899 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
8901 /* ARMv6/XScale extended small page format */
8902 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
8903 || arm_feature(env
, ARM_FEATURE_V6
)) {
8904 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8905 *page_size
= 0x1000;
8907 /* UNPREDICTABLE in ARMv5; we choose to take a
8908 * page translation fault.
8910 fi
->type
= ARMFault_Translation
;
8914 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
8917 ap
= (desc
>> 4) & 3;
8920 /* Never happens, but compiler isn't smart enough to tell. */
8924 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
8925 *prot
|= *prot
? PAGE_EXEC
: 0;
8926 if (!(*prot
& (1 << access_type
))) {
8927 /* Access permission fault. */
8928 fi
->type
= ARMFault_Permission
;
8931 *phys_ptr
= phys_addr
;
8934 fi
->domain
= domain
;
8939 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
8940 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8941 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
8942 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
8944 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
8958 /* Pagetable walk. */
8959 /* Lookup l1 descriptor. */
8960 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8961 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8962 fi
->type
= ARMFault_Translation
;
8965 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8967 if (fi
->type
!= ARMFault_None
) {
8971 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
8972 /* Section translation fault, or attempt to use the encoding
8973 * which is Reserved on implementations without PXN.
8975 fi
->type
= ARMFault_Translation
;
8978 if ((type
== 1) || !(desc
& (1 << 18))) {
8979 /* Page or Section. */
8980 domain
= (desc
>> 5) & 0x0f;
8982 if (regime_el(env
, mmu_idx
) == 1) {
8983 dacr
= env
->cp15
.dacr_ns
;
8985 dacr
= env
->cp15
.dacr_s
;
8990 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8991 if (domain_prot
== 0 || domain_prot
== 2) {
8992 /* Section or Page domain fault */
8993 fi
->type
= ARMFault_Domain
;
8997 if (desc
& (1 << 18)) {
8999 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
9000 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
9001 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
9002 *page_size
= 0x1000000;
9005 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9006 *page_size
= 0x100000;
9008 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
9009 xn
= desc
& (1 << 4);
9011 ns
= extract32(desc
, 19, 1);
9013 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
9014 pxn
= (desc
>> 2) & 1;
9016 ns
= extract32(desc
, 3, 1);
9017 /* Lookup l2 entry. */
9018 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9019 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9021 if (fi
->type
!= ARMFault_None
) {
9024 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
9026 case 0: /* Page translation fault. */
9027 fi
->type
= ARMFault_Translation
;
9029 case 1: /* 64k page. */
9030 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9031 xn
= desc
& (1 << 15);
9032 *page_size
= 0x10000;
9034 case 2: case 3: /* 4k page. */
9035 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9037 *page_size
= 0x1000;
9040 /* Never happens, but compiler isn't smart enough to tell. */
9044 if (domain_prot
== 3) {
9045 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9047 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
9050 if (xn
&& access_type
== MMU_INST_FETCH
) {
9051 fi
->type
= ARMFault_Permission
;
9055 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
9056 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
9057 /* The simplified model uses AP[0] as an access control bit. */
9058 if ((ap
& 1) == 0) {
9059 /* Access flag fault. */
9060 fi
->type
= ARMFault_AccessFlag
;
9063 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
9065 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9070 if (!(*prot
& (1 << access_type
))) {
9071 /* Access permission fault. */
9072 fi
->type
= ARMFault_Permission
;
9077 /* The NS bit will (as required by the architecture) have no effect if
9078 * the CPU doesn't support TZ or this is a non-secure translation
9079 * regime, because the attribute will already be non-secure.
9081 attrs
->secure
= false;
9083 *phys_ptr
= phys_addr
;
9086 fi
->domain
= domain
;
9092 * check_s2_mmu_setup
9094 * @is_aa64: True if the translation regime is in AArch64 state
9095 * @startlevel: Suggested starting level
9096 * @inputsize: Bitsize of IPAs
9097 * @stride: Page-table stride (See the ARM ARM)
9099 * Returns true if the suggested S2 translation parameters are OK and
9102 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
9103 int inputsize
, int stride
)
9105 const int grainsize
= stride
+ 3;
9108 /* Negative levels are never allowed. */
9113 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
9114 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
9119 CPUARMState
*env
= &cpu
->env
;
9120 unsigned int pamax
= arm_pamax(cpu
);
9123 case 13: /* 64KB Pages. */
9124 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
9128 case 11: /* 16KB Pages. */
9129 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
9133 case 9: /* 4KB Pages. */
9134 if (level
== 0 && pamax
<= 42) {
9139 g_assert_not_reached();
9142 /* Inputsize checks. */
9143 if (inputsize
> pamax
&&
9144 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
9145 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
9149 /* AArch32 only supports 4KB pages. Assert on that. */
9150 assert(stride
== 9);
9159 /* Translate from the 4-bit stage 2 representation of
9160 * memory attributes (without cache-allocation hints) to
9161 * the 8-bit representation of the stage 1 MAIR registers
9162 * (which includes allocation hints).
9164 * ref: shared/translation/attrs/S2AttrDecode()
9165 * .../S2ConvertAttrsHints()
9167 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
9169 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
9170 uint8_t loattr
= extract32(s2attrs
, 0, 2);
9171 uint8_t hihint
= 0, lohint
= 0;
9173 if (hiattr
!= 0) { /* normal memory */
9174 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
9175 hiattr
= loattr
= 1; /* non-cacheable */
9177 if (hiattr
!= 1) { /* Write-through or write-back */
9178 hihint
= 3; /* RW allocate */
9180 if (loattr
!= 1) { /* Write-through or write-back */
9181 lohint
= 3; /* RW allocate */
9186 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
9189 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
9190 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9191 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
9192 target_ulong
*page_size_ptr
,
9193 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
9195 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9196 CPUState
*cs
= CPU(cpu
);
9197 /* Read an LPAE long-descriptor translation table. */
9198 ARMFaultType fault_type
= ARMFault_Translation
;
9205 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
9206 uint32_t tableattrs
;
9207 target_ulong page_size
;
9213 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
9214 int ap
, ns
, xn
, pxn
;
9215 uint32_t el
= regime_el(env
, mmu_idx
);
9216 bool ttbr1_valid
= true;
9217 uint64_t descaddrmask
;
9218 bool aarch64
= arm_el_is_aa64(env
, el
);
9221 * This code does not handle the different format TCR for VTCR_EL2.
9222 * This code also does not support shareability levels.
9223 * Attribute and permission bit handling should also be checked when adding
9224 * support for those page table walks.
9230 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9231 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
9234 if (extract64(address
, 55, 1)) {
9235 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
9237 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
9242 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
9246 ttbr1_valid
= false;
9251 /* There is no TTBR1 for EL2 */
9253 ttbr1_valid
= false;
9257 /* Determine whether this address is in the region controlled by
9258 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
9259 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
9260 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
9263 /* AArch64 translation. */
9264 t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
9265 t0sz
= MIN(t0sz
, 39);
9266 t0sz
= MAX(t0sz
, 16);
9267 } else if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9268 /* AArch32 stage 1 translation. */
9269 t0sz
= extract32(tcr
->raw_tcr
, 0, 3);
9271 /* AArch32 stage 2 translation. */
9272 bool sext
= extract32(tcr
->raw_tcr
, 4, 1);
9273 bool sign
= extract32(tcr
->raw_tcr
, 3, 1);
9274 /* Address size is 40-bit for a stage 2 translation,
9275 * and t0sz can be negative (from -8 to 7),
9276 * so we need to adjust it to use the TTBR selecting logic below.
9279 t0sz
= sextract32(tcr
->raw_tcr
, 0, 4) + 8;
9281 /* If the sign-extend bit is not the same as t0sz[3], the result
9282 * is unpredictable. Flag this as a guest error. */
9284 qemu_log_mask(LOG_GUEST_ERROR
,
9285 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
9288 t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
9290 t1sz
= MIN(t1sz
, 39);
9291 t1sz
= MAX(t1sz
, 16);
9293 if (t0sz
&& !extract64(address
, addrsize
- t0sz
, t0sz
- tbi
)) {
9294 /* there is a ttbr0 region and we are in it (high bits all zero) */
9296 } else if (ttbr1_valid
&& t1sz
&&
9297 !extract64(~address
, addrsize
- t1sz
, t1sz
- tbi
)) {
9298 /* there is a ttbr1 region and we are in it (high bits all one) */
9301 /* ttbr0 region is "everything not in the ttbr1 region" */
9303 } else if (!t1sz
&& ttbr1_valid
) {
9304 /* ttbr1 region is "everything not in the ttbr0 region" */
9307 /* in the gap between the two regions, this is a Translation fault */
9308 fault_type
= ARMFault_Translation
;
9312 /* Note that QEMU ignores shareability and cacheability attributes,
9313 * so we don't need to do anything with the SH, ORGN, IRGN fields
9314 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
9315 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
9316 * implement any ASID-like capability so we can ignore it (instead
9317 * we will always flush the TLB any time the ASID is changed).
9319 if (ttbr_select
== 0) {
9320 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
9322 epd
= extract32(tcr
->raw_tcr
, 7, 1);
9324 inputsize
= addrsize
- t0sz
;
9326 tg
= extract32(tcr
->raw_tcr
, 14, 2);
9327 if (tg
== 1) { /* 64KB pages */
9330 if (tg
== 2) { /* 16KB pages */
9334 /* We should only be here if TTBR1 is valid */
9335 assert(ttbr1_valid
);
9337 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
9338 epd
= extract32(tcr
->raw_tcr
, 23, 1);
9339 inputsize
= addrsize
- t1sz
;
9341 tg
= extract32(tcr
->raw_tcr
, 30, 2);
9342 if (tg
== 3) { /* 64KB pages */
9345 if (tg
== 1) { /* 16KB pages */
9350 /* Here we should have set up all the parameters for the translation:
9351 * inputsize, ttbr, epd, stride, tbi
9355 /* Translation table walk disabled => Translation fault on TLB miss
9356 * Note: This is always 0 on 64-bit EL2 and EL3.
9361 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9362 /* The starting level depends on the virtual address size (which can
9363 * be up to 48 bits) and the translation granule size. It indicates
9364 * the number of strides (stride bits at a time) needed to
9365 * consume the bits of the input address. In the pseudocode this is:
9366 * level = 4 - RoundUp((inputsize - grainsize) / stride)
9367 * where their 'inputsize' is our 'inputsize', 'grainsize' is
9368 * our 'stride + 3' and 'stride' is our 'stride'.
9369 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
9370 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
9371 * = 4 - (inputsize - 4) / stride;
9373 level
= 4 - (inputsize
- 4) / stride
;
9375 /* For stage 2 translations the starting level is specified by the
9376 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
9378 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
9379 uint32_t startlevel
;
9382 if (!aarch64
|| stride
== 9) {
9383 /* AArch32 or 4KB pages */
9384 startlevel
= 2 - sl0
;
9386 /* 16KB or 64KB pages */
9387 startlevel
= 3 - sl0
;
9390 /* Check that the starting level is valid. */
9391 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
9394 fault_type
= ARMFault_Translation
;
9400 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
9401 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
9403 /* Now we can extract the actual base address from the TTBR */
9404 descaddr
= extract64(ttbr
, 0, 48);
9405 descaddr
&= ~indexmask
;
9407 /* The address field in the descriptor goes up to bit 39 for ARMv7
9408 * but up to bit 47 for ARMv8, but we use the descaddrmask
9409 * up to bit 39 for AArch32, because we don't need other bits in that case
9410 * to construct next descriptor address (anyway they should be all zeroes).
9412 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
9413 ~indexmask_grainsize
;
9415 /* Secure accesses start with the page table in secure memory and
9416 * can be downgraded to non-secure at any step. Non-secure accesses
9417 * remain non-secure. We implement this by just ORing in the NSTable/NS
9418 * bits at each step.
9420 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
9422 uint64_t descriptor
;
9425 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
9427 nstable
= extract32(tableattrs
, 4, 1);
9428 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
9429 if (fi
->type
!= ARMFault_None
) {
9433 if (!(descriptor
& 1) ||
9434 (!(descriptor
& 2) && (level
== 3))) {
9435 /* Invalid, or the Reserved level 3 encoding */
9438 descaddr
= descriptor
& descaddrmask
;
9440 if ((descriptor
& 2) && (level
< 3)) {
9441 /* Table entry. The top five bits are attributes which may
9442 * propagate down through lower levels of the table (and
9443 * which are all arranged so that 0 means "no effect", so
9444 * we can gather them up by ORing in the bits at each level).
9446 tableattrs
|= extract64(descriptor
, 59, 5);
9448 indexmask
= indexmask_grainsize
;
9451 /* Block entry at level 1 or 2, or page entry at level 3.
9452 * These are basically the same thing, although the number
9453 * of bits we pull in from the vaddr varies.
9455 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
9456 descaddr
|= (address
& (page_size
- 1));
9457 /* Extract attributes from the descriptor */
9458 attrs
= extract64(descriptor
, 2, 10)
9459 | (extract64(descriptor
, 52, 12) << 10);
9461 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9462 /* Stage 2 table descriptors do not include any attribute fields */
9465 /* Merge in attributes from table descriptors */
9466 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
9467 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
9468 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
9469 * means "force PL1 access only", which means forcing AP[1] to 0.
9471 if (extract32(tableattrs
, 2, 1)) {
9474 attrs
|= nstable
<< 3; /* NS */
9477 /* Here descaddr is the final physical address, and attributes
9480 fault_type
= ARMFault_AccessFlag
;
9481 if ((attrs
& (1 << 8)) == 0) {
9486 ap
= extract32(attrs
, 4, 2);
9487 xn
= extract32(attrs
, 12, 1);
9489 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9491 *prot
= get_S2prot(env
, ap
, xn
);
9493 ns
= extract32(attrs
, 3, 1);
9494 pxn
= extract32(attrs
, 11, 1);
9495 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
9498 fault_type
= ARMFault_Permission
;
9499 if (!(*prot
& (1 << access_type
))) {
9504 /* The NS bit will (as required by the architecture) have no effect if
9505 * the CPU doesn't support TZ or this is a non-secure translation
9506 * regime, because the attribute will already be non-secure.
9508 txattrs
->secure
= false;
9511 if (cacheattrs
!= NULL
) {
9512 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9513 cacheattrs
->attrs
= convert_stage2_attrs(env
,
9514 extract32(attrs
, 0, 4));
9516 /* Index into MAIR registers for cache attributes */
9517 uint8_t attrindx
= extract32(attrs
, 0, 3);
9518 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
9519 assert(attrindx
<= 7);
9520 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
9522 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
9525 *phys_ptr
= descaddr
;
9526 *page_size_ptr
= page_size
;
9530 fi
->type
= fault_type
;
9532 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
9533 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
9537 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
9539 int32_t address
, int *prot
)
9541 if (!arm_feature(env
, ARM_FEATURE_M
)) {
9542 *prot
= PAGE_READ
| PAGE_WRITE
;
9544 case 0xF0000000 ... 0xFFFFFFFF:
9545 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
9546 /* hivecs execing is ok */
9550 case 0x00000000 ... 0x7FFFFFFF:
9555 /* Default system address map for M profile cores.
9556 * The architecture specifies which regions are execute-never;
9557 * at the MPU level no other checks are defined.
9560 case 0x00000000 ... 0x1fffffff: /* ROM */
9561 case 0x20000000 ... 0x3fffffff: /* SRAM */
9562 case 0x60000000 ... 0x7fffffff: /* RAM */
9563 case 0x80000000 ... 0x9fffffff: /* RAM */
9564 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9566 case 0x40000000 ... 0x5fffffff: /* Peripheral */
9567 case 0xa0000000 ... 0xbfffffff: /* Device */
9568 case 0xc0000000 ... 0xdfffffff: /* Device */
9569 case 0xe0000000 ... 0xffffffff: /* System */
9570 *prot
= PAGE_READ
| PAGE_WRITE
;
9573 g_assert_not_reached();
9578 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
9579 ARMMMUIdx mmu_idx
, bool is_user
)
9581 /* Return true if we should use the default memory map as a
9582 * "background" region if there are no hits against any MPU regions.
9584 CPUARMState
*env
= &cpu
->env
;
9590 if (arm_feature(env
, ARM_FEATURE_M
)) {
9591 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
9592 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
9594 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
9598 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
9600 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
9601 return arm_feature(env
, ARM_FEATURE_M
) &&
9602 extract32(address
, 20, 12) == 0xe00;
9605 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
9607 /* True if address is in the M profile system region
9608 * 0xe0000000 - 0xffffffff
9610 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
9613 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
9614 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9615 hwaddr
*phys_ptr
, int *prot
,
9616 target_ulong
*page_size
,
9617 ARMMMUFaultInfo
*fi
)
9619 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9621 bool is_user
= regime_is_user(env
, mmu_idx
);
9623 *phys_ptr
= address
;
9624 *page_size
= TARGET_PAGE_SIZE
;
9627 if (regime_translation_disabled(env
, mmu_idx
) ||
9628 m_is_ppb_region(env
, address
)) {
9629 /* MPU disabled or M profile PPB access: use default memory map.
9630 * The other case which uses the default memory map in the
9631 * v7M ARM ARM pseudocode is exception vector reads from the vector
9632 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
9633 * which always does a direct read using address_space_ldl(), rather
9634 * than going via this function, so we don't need to check that here.
9636 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9637 } else { /* MPU enabled */
9638 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9640 uint32_t base
= env
->pmsav7
.drbar
[n
];
9641 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
9645 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
9650 qemu_log_mask(LOG_GUEST_ERROR
,
9651 "DRSR[%d]: Rsize field cannot be 0\n", n
);
9655 rmask
= (1ull << rsize
) - 1;
9658 qemu_log_mask(LOG_GUEST_ERROR
,
9659 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
9660 "to DRSR region size, mask = 0x%" PRIx32
"\n",
9665 if (address
< base
|| address
> base
+ rmask
) {
9667 * Address not in this region. We must check whether the
9668 * region covers addresses in the same page as our address.
9669 * In that case we must not report a size that covers the
9670 * whole page for a subsequent hit against a different MPU
9671 * region or the background region, because it would result in
9672 * incorrect TLB hits for subsequent accesses to addresses that
9673 * are in this MPU region.
9675 if (ranges_overlap(base
, rmask
,
9676 address
& TARGET_PAGE_MASK
,
9677 TARGET_PAGE_SIZE
)) {
9683 /* Region matched */
9685 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
9687 uint32_t srdis_mask
;
9689 rsize
-= 3; /* sub region size (power of 2) */
9690 snd
= ((address
- base
) >> rsize
) & 0x7;
9691 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
9693 srdis_mask
= srdis
? 0x3 : 0x0;
9694 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
9695 /* This will check in groups of 2, 4 and then 8, whether
9696 * the subregion bits are consistent. rsize is incremented
9697 * back up to give the region size, considering consistent
9698 * adjacent subregions as one region. Stop testing if rsize
9699 * is already big enough for an entire QEMU page.
9701 int snd_rounded
= snd
& ~(i
- 1);
9702 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
9703 snd_rounded
+ 8, i
);
9704 if (srdis_mask
^ srdis_multi
) {
9707 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
9714 if (rsize
< TARGET_PAGE_BITS
) {
9715 *page_size
= 1 << rsize
;
9720 if (n
== -1) { /* no hits */
9721 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9722 /* background fault */
9723 fi
->type
= ARMFault_Background
;
9726 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9727 } else { /* a MPU hit! */
9728 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
9729 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
9731 if (m_is_system_region(env
, address
)) {
9732 /* System space is always execute never */
9736 if (is_user
) { /* User mode AP bit decoding */
9741 break; /* no access */
9743 *prot
|= PAGE_WRITE
;
9747 *prot
|= PAGE_READ
| PAGE_EXEC
;
9750 /* for v7M, same as 6; for R profile a reserved value */
9751 if (arm_feature(env
, ARM_FEATURE_M
)) {
9752 *prot
|= PAGE_READ
| PAGE_EXEC
;
9757 qemu_log_mask(LOG_GUEST_ERROR
,
9758 "DRACR[%d]: Bad value for AP bits: 0x%"
9759 PRIx32
"\n", n
, ap
);
9761 } else { /* Priv. mode AP bits decoding */
9764 break; /* no access */
9768 *prot
|= PAGE_WRITE
;
9772 *prot
|= PAGE_READ
| PAGE_EXEC
;
9775 /* for v7M, same as 6; for R profile a reserved value */
9776 if (arm_feature(env
, ARM_FEATURE_M
)) {
9777 *prot
|= PAGE_READ
| PAGE_EXEC
;
9782 qemu_log_mask(LOG_GUEST_ERROR
,
9783 "DRACR[%d]: Bad value for AP bits: 0x%"
9784 PRIx32
"\n", n
, ap
);
9790 *prot
&= ~PAGE_EXEC
;
9795 fi
->type
= ARMFault_Permission
;
9798 * Core QEMU code can't handle execution from small pages yet, so
9799 * don't try it. This way we'll get an MPU exception, rather than
9800 * eventually causing QEMU to exit in get_page_addr_code().
9802 if (*page_size
< TARGET_PAGE_SIZE
&& (*prot
& PAGE_EXEC
)) {
9803 qemu_log_mask(LOG_UNIMP
,
9804 "MPU: No support for execution from regions "
9805 "smaller than 1K\n");
9806 *prot
&= ~PAGE_EXEC
;
9808 return !(*prot
& (1 << access_type
));
9811 static bool v8m_is_sau_exempt(CPUARMState
*env
,
9812 uint32_t address
, MMUAccessType access_type
)
9814 /* The architecture specifies that certain address ranges are
9815 * exempt from v8M SAU/IDAU checks.
9818 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
9819 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
9820 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
9821 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
9822 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
9823 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
9826 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
9827 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9828 V8M_SAttributes
*sattrs
)
9830 /* Look up the security attributes for this address. Compare the
9831 * pseudocode SecurityCheck() function.
9832 * We assume the caller has zero-initialized *sattrs.
9834 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9836 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
9837 int idau_region
= IREGION_NOTVALID
;
9838 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
9839 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
9842 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
9843 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
9845 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
9849 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
9850 /* 0xf0000000..0xffffffff is always S for insn fetches */
9854 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
9855 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
9859 if (idau_region
!= IREGION_NOTVALID
) {
9860 sattrs
->irvalid
= true;
9861 sattrs
->iregion
= idau_region
;
9864 switch (env
->sau
.ctrl
& 3) {
9865 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
9867 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
9870 default: /* SAU.ENABLE == 1 */
9871 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
9872 if (env
->sau
.rlar
[r
] & 1) {
9873 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
9874 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
9876 if (base
<= address
&& limit
>= address
) {
9877 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
9878 sattrs
->subpage
= true;
9880 if (sattrs
->srvalid
) {
9881 /* If we hit in more than one region then we must report
9882 * as Secure, not NS-Callable, with no valid region
9886 sattrs
->nsc
= false;
9887 sattrs
->sregion
= 0;
9888 sattrs
->srvalid
= false;
9891 if (env
->sau
.rlar
[r
] & 2) {
9896 sattrs
->srvalid
= true;
9897 sattrs
->sregion
= r
;
9901 * Address not in this region. We must check whether the
9902 * region covers addresses in the same page as our address.
9903 * In that case we must not report a size that covers the
9904 * whole page for a subsequent hit against a different MPU
9905 * region or the background region, because it would result
9906 * in incorrect TLB hits for subsequent accesses to
9907 * addresses that are in this MPU region.
9909 if (limit
>= base
&&
9910 ranges_overlap(base
, limit
- base
+ 1,
9912 TARGET_PAGE_SIZE
)) {
9913 sattrs
->subpage
= true;
9919 /* The IDAU will override the SAU lookup results if it specifies
9920 * higher security than the SAU does.
9923 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
9925 sattrs
->nsc
= idau_nsc
;
9932 static bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
9933 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9934 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
9935 int *prot
, bool *is_subpage
,
9936 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
9938 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
9939 * that a full phys-to-virt translation does).
9940 * mregion is (if not NULL) set to the region number which matched,
9941 * or -1 if no region number is returned (MPU off, address did not
9942 * hit a region, address hit in multiple regions).
9943 * We set is_subpage to true if the region hit doesn't cover the
9944 * entire TARGET_PAGE the address is within.
9946 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9947 bool is_user
= regime_is_user(env
, mmu_idx
);
9948 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
9950 int matchregion
= -1;
9952 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
9953 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
9955 *is_subpage
= false;
9956 *phys_ptr
= address
;
9962 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
9963 * was an exception vector read from the vector table (which is always
9964 * done using the default system address map), because those accesses
9965 * are done in arm_v7m_load_vector(), which always does a direct
9966 * read using address_space_ldl(), rather than going via this function.
9968 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
9970 } else if (m_is_ppb_region(env
, address
)) {
9972 } else if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9975 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9977 /* Note that the base address is bits [31:5] from the register
9978 * with bits [4:0] all zeroes, but the limit address is bits
9979 * [31:5] from the register with bits [4:0] all ones.
9981 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
9982 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
9984 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
9985 /* Region disabled */
9989 if (address
< base
|| address
> limit
) {
9991 * Address not in this region. We must check whether the
9992 * region covers addresses in the same page as our address.
9993 * In that case we must not report a size that covers the
9994 * whole page for a subsequent hit against a different MPU
9995 * region or the background region, because it would result in
9996 * incorrect TLB hits for subsequent accesses to addresses that
9997 * are in this MPU region.
9999 if (limit
>= base
&&
10000 ranges_overlap(base
, limit
- base
+ 1,
10002 TARGET_PAGE_SIZE
)) {
10003 *is_subpage
= true;
10008 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
10009 *is_subpage
= true;
10013 /* Multiple regions match -- always a failure (unlike
10014 * PMSAv7 where highest-numbered-region wins)
10016 fi
->type
= ARMFault_Permission
;
10027 /* background fault */
10028 fi
->type
= ARMFault_Background
;
10032 if (matchregion
== -1) {
10033 /* hit using the background region */
10034 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10036 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
10037 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
10039 if (m_is_system_region(env
, address
)) {
10040 /* System space is always execute never */
10044 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
10045 if (*prot
&& !xn
) {
10046 *prot
|= PAGE_EXEC
;
10048 /* We don't need to look the attribute up in the MAIR0/MAIR1
10049 * registers because that only tells us about cacheability.
10052 *mregion
= matchregion
;
10056 fi
->type
= ARMFault_Permission
;
10059 * Core QEMU code can't handle execution from small pages yet, so
10060 * don't try it. This means any attempted execution will generate
10061 * an MPU exception, rather than eventually causing QEMU to exit in
10062 * get_page_addr_code().
10064 if (*is_subpage
&& (*prot
& PAGE_EXEC
)) {
10065 qemu_log_mask(LOG_UNIMP
,
10066 "MPU: No support for execution from regions "
10067 "smaller than 1K\n");
10068 *prot
&= ~PAGE_EXEC
;
10070 return !(*prot
& (1 << access_type
));
10074 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
10075 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10076 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
10077 int *prot
, target_ulong
*page_size
,
10078 ARMMMUFaultInfo
*fi
)
10080 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
10081 V8M_SAttributes sattrs
= {};
10083 bool mpu_is_subpage
;
10085 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10086 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
10087 if (access_type
== MMU_INST_FETCH
) {
10088 /* Instruction fetches always use the MMU bank and the
10089 * transaction attribute determined by the fetch address,
10090 * regardless of CPU state. This is painful for QEMU
10091 * to handle, because it would mean we need to encode
10092 * into the mmu_idx not just the (user, negpri) information
10093 * for the current security state but also that for the
10094 * other security state, which would balloon the number
10095 * of mmu_idx values needed alarmingly.
10096 * Fortunately we can avoid this because it's not actually
10097 * possible to arbitrarily execute code from memory with
10098 * the wrong security attribute: it will always generate
10099 * an exception of some kind or another, apart from the
10100 * special case of an NS CPU executing an SG instruction
10101 * in S&NSC memory. So we always just fail the translation
10102 * here and sort things out in the exception handler
10103 * (including possibly emulating an SG instruction).
10105 if (sattrs
.ns
!= !secure
) {
10107 fi
->type
= ARMFault_QEMU_NSCExec
;
10109 fi
->type
= ARMFault_QEMU_SFault
;
10111 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
10112 *phys_ptr
= address
;
10117 /* For data accesses we always use the MMU bank indicated
10118 * by the current CPU state, but the security attributes
10119 * might downgrade a secure access to nonsecure.
10122 txattrs
->secure
= false;
10123 } else if (!secure
) {
10124 /* NS access to S memory must fault.
10125 * Architecturally we should first check whether the
10126 * MPU information for this address indicates that we
10127 * are doing an unaligned access to Device memory, which
10128 * should generate a UsageFault instead. QEMU does not
10129 * currently check for that kind of unaligned access though.
10130 * If we added it we would need to do so as a special case
10131 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
10133 fi
->type
= ARMFault_QEMU_SFault
;
10134 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
10135 *phys_ptr
= address
;
10142 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
10143 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
10145 * TODO: this is a temporary hack to ignore the fact that the SAU region
10146 * is smaller than a page if this is an executable region. We never
10147 * supported small MPU regions, but we did (accidentally) allow small
10148 * SAU regions, and if we now made small SAU regions not be executable
10149 * then this would break previously working guest code. We can't
10150 * remove this until/unless we implement support for execution from
10153 if (*prot
& PAGE_EXEC
) {
10154 sattrs
.subpage
= false;
10156 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
10160 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
10161 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10162 hwaddr
*phys_ptr
, int *prot
,
10163 ARMMMUFaultInfo
*fi
)
10168 bool is_user
= regime_is_user(env
, mmu_idx
);
10170 if (regime_translation_disabled(env
, mmu_idx
)) {
10171 /* MPU disabled. */
10172 *phys_ptr
= address
;
10173 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10177 *phys_ptr
= address
;
10178 for (n
= 7; n
>= 0; n
--) {
10179 base
= env
->cp15
.c6_region
[n
];
10180 if ((base
& 1) == 0) {
10183 mask
= 1 << ((base
>> 1) & 0x1f);
10184 /* Keep this shift separate from the above to avoid an
10185 (undefined) << 32. */
10186 mask
= (mask
<< 1) - 1;
10187 if (((base
^ address
) & ~mask
) == 0) {
10192 fi
->type
= ARMFault_Background
;
10196 if (access_type
== MMU_INST_FETCH
) {
10197 mask
= env
->cp15
.pmsav5_insn_ap
;
10199 mask
= env
->cp15
.pmsav5_data_ap
;
10201 mask
= (mask
>> (n
* 4)) & 0xf;
10204 fi
->type
= ARMFault_Permission
;
10209 fi
->type
= ARMFault_Permission
;
10213 *prot
= PAGE_READ
| PAGE_WRITE
;
10218 *prot
|= PAGE_WRITE
;
10222 *prot
= PAGE_READ
| PAGE_WRITE
;
10226 fi
->type
= ARMFault_Permission
;
10236 /* Bad permission. */
10237 fi
->type
= ARMFault_Permission
;
10241 *prot
|= PAGE_EXEC
;
10245 /* Combine either inner or outer cacheability attributes for normal
10246 * memory, according to table D4-42 and pseudocode procedure
10247 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
10249 * NB: only stage 1 includes allocation hints (RW bits), leading to
10252 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
10254 if (s1
== 4 || s2
== 4) {
10255 /* non-cacheable has precedence */
10257 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
10258 /* stage 1 write-through takes precedence */
10260 } else if (extract32(s2
, 2, 2) == 2) {
10261 /* stage 2 write-through takes precedence, but the allocation hint
10262 * is still taken from stage 1
10264 return (2 << 2) | extract32(s1
, 0, 2);
10265 } else { /* write-back */
10270 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
10271 * and CombineS1S2Desc()
10273 * @s1: Attributes from stage 1 walk
10274 * @s2: Attributes from stage 2 walk
10276 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
10278 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
10279 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
10282 /* Combine shareability attributes (table D4-43) */
10283 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
10284 /* if either are outer-shareable, the result is outer-shareable */
10285 ret
.shareability
= 2;
10286 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
10287 /* if either are inner-shareable, the result is inner-shareable */
10288 ret
.shareability
= 3;
10290 /* both non-shareable */
10291 ret
.shareability
= 0;
10294 /* Combine memory type and cacheability attributes */
10295 if (s1hi
== 0 || s2hi
== 0) {
10296 /* Device has precedence over normal */
10297 if (s1lo
== 0 || s2lo
== 0) {
10298 /* nGnRnE has precedence over anything */
10300 } else if (s1lo
== 4 || s2lo
== 4) {
10301 /* non-Reordering has precedence over Reordering */
10302 ret
.attrs
= 4; /* nGnRE */
10303 } else if (s1lo
== 8 || s2lo
== 8) {
10304 /* non-Gathering has precedence over Gathering */
10305 ret
.attrs
= 8; /* nGRE */
10307 ret
.attrs
= 0xc; /* GRE */
10310 /* Any location for which the resultant memory type is any
10311 * type of Device memory is always treated as Outer Shareable.
10313 ret
.shareability
= 2;
10314 } else { /* Normal memory */
10315 /* Outer/inner cacheability combine independently */
10316 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
10317 | combine_cacheattr_nibble(s1lo
, s2lo
);
10319 if (ret
.attrs
== 0x44) {
10320 /* Any location for which the resultant memory type is Normal
10321 * Inner Non-cacheable, Outer Non-cacheable is always treated
10322 * as Outer Shareable.
10324 ret
.shareability
= 2;
10332 /* get_phys_addr - get the physical address for this virtual address
10334 * Find the physical address corresponding to the given virtual address,
10335 * by doing a translation table walk on MMU based systems or using the
10336 * MPU state on MPU based systems.
10338 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10339 * prot and page_size may not be filled in, and the populated fsr value provides
10340 * information on why the translation aborted, in the format of a
10341 * DFSR/IFSR fault register, with the following caveats:
10342 * * we honour the short vs long DFSR format differences.
10343 * * the WnR bit is never set (the caller must do this).
10344 * * for PSMAv5 based systems we don't bother to return a full FSR format
10347 * @env: CPUARMState
10348 * @address: virtual address to get physical address for
10349 * @access_type: 0 for read, 1 for write, 2 for execute
10350 * @mmu_idx: MMU index indicating required translation regime
10351 * @phys_ptr: set to the physical address corresponding to the virtual address
10352 * @attrs: set to the memory transaction attributes to use
10353 * @prot: set to the permissions for the page containing phys_ptr
10354 * @page_size: set to the size of the page containing phys_ptr
10355 * @fi: set to fault info if the translation fails
10356 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10358 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
10359 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10360 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10361 target_ulong
*page_size
,
10362 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10364 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
10365 /* Call ourselves recursively to do the stage 1 and then stage 2
10368 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
10372 ARMCacheAttrs cacheattrs2
= {};
10374 ret
= get_phys_addr(env
, address
, access_type
,
10375 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
10376 prot
, page_size
, fi
, cacheattrs
);
10378 /* If S1 fails or S2 is disabled, return early. */
10379 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
10384 /* S1 is done. Now do S2 translation. */
10385 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
10386 phys_ptr
, attrs
, &s2_prot
,
10388 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
10390 /* Combine the S1 and S2 perms. */
10393 /* Combine the S1 and S2 cache attributes, if needed */
10394 if (!ret
&& cacheattrs
!= NULL
) {
10395 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
10401 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
10403 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10407 /* The page table entries may downgrade secure to non-secure, but
10408 * cannot upgrade an non-secure translation regime's attributes
10411 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
10412 attrs
->user
= regime_is_user(env
, mmu_idx
);
10414 /* Fast Context Switch Extension. This doesn't exist at all in v8.
10415 * In v7 and earlier it affects all stage 1 translations.
10417 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
10418 && !arm_feature(env
, ARM_FEATURE_V8
)) {
10419 if (regime_el(env
, mmu_idx
) == 3) {
10420 address
+= env
->cp15
.fcseidr_s
;
10422 address
+= env
->cp15
.fcseidr_ns
;
10426 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
10428 *page_size
= TARGET_PAGE_SIZE
;
10430 if (arm_feature(env
, ARM_FEATURE_V8
)) {
10432 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
10433 phys_ptr
, attrs
, prot
, page_size
, fi
);
10434 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10436 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
10437 phys_ptr
, prot
, page_size
, fi
);
10440 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
10441 phys_ptr
, prot
, fi
);
10443 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
10444 " mmu_idx %u -> %s (prot %c%c%c)\n",
10445 access_type
== MMU_DATA_LOAD
? "reading" :
10446 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
10447 (uint32_t)address
, mmu_idx
,
10448 ret
? "Miss" : "Hit",
10449 *prot
& PAGE_READ
? 'r' : '-',
10450 *prot
& PAGE_WRITE
? 'w' : '-',
10451 *prot
& PAGE_EXEC
? 'x' : '-');
10456 /* Definitely a real MMU, not an MPU */
10458 if (regime_translation_disabled(env
, mmu_idx
)) {
10459 /* MMU disabled. */
10460 *phys_ptr
= address
;
10461 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10462 *page_size
= TARGET_PAGE_SIZE
;
10466 if (regime_using_lpae_format(env
, mmu_idx
)) {
10467 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
10468 phys_ptr
, attrs
, prot
, page_size
,
10470 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
10471 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
10472 phys_ptr
, attrs
, prot
, page_size
, fi
);
10474 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
10475 phys_ptr
, prot
, page_size
, fi
);
10479 /* Walk the page table and (if the mapping exists) add the page
10480 * to the TLB. Return false on success, or true on failure. Populate
10481 * fsr with ARM DFSR/IFSR fault register format value on failure.
10483 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
10484 MMUAccessType access_type
, int mmu_idx
,
10485 ARMMMUFaultInfo
*fi
)
10487 ARMCPU
*cpu
= ARM_CPU(cs
);
10488 CPUARMState
*env
= &cpu
->env
;
10490 target_ulong page_size
;
10493 MemTxAttrs attrs
= {};
10495 ret
= get_phys_addr(env
, address
, access_type
,
10496 core_to_arm_mmu_idx(env
, mmu_idx
), &phys_addr
,
10497 &attrs
, &prot
, &page_size
, fi
, NULL
);
10500 * Map a single [sub]page. Regions smaller than our declared
10501 * target page size are handled specially, so for those we
10502 * pass in the exact addresses.
10504 if (page_size
>= TARGET_PAGE_SIZE
) {
10505 phys_addr
&= TARGET_PAGE_MASK
;
10506 address
&= TARGET_PAGE_MASK
;
10508 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
10509 prot
, mmu_idx
, page_size
);
10516 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
10519 ARMCPU
*cpu
= ARM_CPU(cs
);
10520 CPUARMState
*env
= &cpu
->env
;
10522 target_ulong page_size
;
10525 ARMMMUFaultInfo fi
= {};
10526 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
10528 *attrs
= (MemTxAttrs
) {};
10530 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
10531 attrs
, &prot
, &page_size
, &fi
, NULL
);
10539 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
10542 unsigned el
= arm_current_el(env
);
10544 /* First handle registers which unprivileged can read */
10547 case 0 ... 7: /* xPSR sub-fields */
10549 if ((reg
& 1) && el
) {
10550 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
10553 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
10555 /* EPSR reads as zero */
10556 return xpsr_read(env
) & mask
;
10558 case 20: /* CONTROL */
10559 return env
->v7m
.control
[env
->v7m
.secure
];
10560 case 0x94: /* CONTROL_NS */
10561 /* We have to handle this here because unprivileged Secure code
10562 * can read the NS CONTROL register.
10564 if (!env
->v7m
.secure
) {
10567 return env
->v7m
.control
[M_REG_NS
];
10571 return 0; /* unprivileged reads others as zero */
10574 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10576 case 0x88: /* MSP_NS */
10577 if (!env
->v7m
.secure
) {
10580 return env
->v7m
.other_ss_msp
;
10581 case 0x89: /* PSP_NS */
10582 if (!env
->v7m
.secure
) {
10585 return env
->v7m
.other_ss_psp
;
10586 case 0x8a: /* MSPLIM_NS */
10587 if (!env
->v7m
.secure
) {
10590 return env
->v7m
.msplim
[M_REG_NS
];
10591 case 0x8b: /* PSPLIM_NS */
10592 if (!env
->v7m
.secure
) {
10595 return env
->v7m
.psplim
[M_REG_NS
];
10596 case 0x90: /* PRIMASK_NS */
10597 if (!env
->v7m
.secure
) {
10600 return env
->v7m
.primask
[M_REG_NS
];
10601 case 0x91: /* BASEPRI_NS */
10602 if (!env
->v7m
.secure
) {
10605 return env
->v7m
.basepri
[M_REG_NS
];
10606 case 0x93: /* FAULTMASK_NS */
10607 if (!env
->v7m
.secure
) {
10610 return env
->v7m
.faultmask
[M_REG_NS
];
10611 case 0x98: /* SP_NS */
10613 /* This gives the non-secure SP selected based on whether we're
10614 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10616 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
10618 if (!env
->v7m
.secure
) {
10621 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
10622 return env
->v7m
.other_ss_psp
;
10624 return env
->v7m
.other_ss_msp
;
10634 return v7m_using_psp(env
) ? env
->v7m
.other_sp
: env
->regs
[13];
10636 return v7m_using_psp(env
) ? env
->regs
[13] : env
->v7m
.other_sp
;
10637 case 10: /* MSPLIM */
10638 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10641 return env
->v7m
.msplim
[env
->v7m
.secure
];
10642 case 11: /* PSPLIM */
10643 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10646 return env
->v7m
.psplim
[env
->v7m
.secure
];
10647 case 16: /* PRIMASK */
10648 return env
->v7m
.primask
[env
->v7m
.secure
];
10649 case 17: /* BASEPRI */
10650 case 18: /* BASEPRI_MAX */
10651 return env
->v7m
.basepri
[env
->v7m
.secure
];
10652 case 19: /* FAULTMASK */
10653 return env
->v7m
.faultmask
[env
->v7m
.secure
];
10656 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
10657 " register %d\n", reg
);
10662 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
10664 /* We're passed bits [11..0] of the instruction; extract
10665 * SYSm and the mask bits.
10666 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
10667 * we choose to treat them as if the mask bits were valid.
10668 * NB that the pseudocode 'mask' variable is bits [11..10],
10669 * whereas ours is [11..8].
10671 uint32_t mask
= extract32(maskreg
, 8, 4);
10672 uint32_t reg
= extract32(maskreg
, 0, 8);
10674 if (arm_current_el(env
) == 0 && reg
> 7) {
10675 /* only xPSR sub-fields may be written by unprivileged */
10679 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10681 case 0x88: /* MSP_NS */
10682 if (!env
->v7m
.secure
) {
10685 env
->v7m
.other_ss_msp
= val
;
10687 case 0x89: /* PSP_NS */
10688 if (!env
->v7m
.secure
) {
10691 env
->v7m
.other_ss_psp
= val
;
10693 case 0x8a: /* MSPLIM_NS */
10694 if (!env
->v7m
.secure
) {
10697 env
->v7m
.msplim
[M_REG_NS
] = val
& ~7;
10699 case 0x8b: /* PSPLIM_NS */
10700 if (!env
->v7m
.secure
) {
10703 env
->v7m
.psplim
[M_REG_NS
] = val
& ~7;
10705 case 0x90: /* PRIMASK_NS */
10706 if (!env
->v7m
.secure
) {
10709 env
->v7m
.primask
[M_REG_NS
] = val
& 1;
10711 case 0x91: /* BASEPRI_NS */
10712 if (!env
->v7m
.secure
) {
10715 env
->v7m
.basepri
[M_REG_NS
] = val
& 0xff;
10717 case 0x93: /* FAULTMASK_NS */
10718 if (!env
->v7m
.secure
) {
10721 env
->v7m
.faultmask
[M_REG_NS
] = val
& 1;
10723 case 0x94: /* CONTROL_NS */
10724 if (!env
->v7m
.secure
) {
10727 write_v7m_control_spsel_for_secstate(env
,
10728 val
& R_V7M_CONTROL_SPSEL_MASK
,
10730 env
->v7m
.control
[M_REG_NS
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
10731 env
->v7m
.control
[M_REG_NS
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
10733 case 0x98: /* SP_NS */
10735 /* This gives the non-secure SP selected based on whether we're
10736 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10738 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
10740 if (!env
->v7m
.secure
) {
10743 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
10744 env
->v7m
.other_ss_psp
= val
;
10746 env
->v7m
.other_ss_msp
= val
;
10756 case 0 ... 7: /* xPSR sub-fields */
10757 /* only APSR is actually writable */
10759 uint32_t apsrmask
= 0;
10762 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
10764 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
10765 apsrmask
|= XPSR_GE
;
10767 xpsr_write(env
, val
, apsrmask
);
10771 if (v7m_using_psp(env
)) {
10772 env
->v7m
.other_sp
= val
;
10774 env
->regs
[13] = val
;
10778 if (v7m_using_psp(env
)) {
10779 env
->regs
[13] = val
;
10781 env
->v7m
.other_sp
= val
;
10784 case 10: /* MSPLIM */
10785 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10788 env
->v7m
.msplim
[env
->v7m
.secure
] = val
& ~7;
10790 case 11: /* PSPLIM */
10791 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10794 env
->v7m
.psplim
[env
->v7m
.secure
] = val
& ~7;
10796 case 16: /* PRIMASK */
10797 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
10799 case 17: /* BASEPRI */
10800 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
10802 case 18: /* BASEPRI_MAX */
10804 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
10805 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
10806 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
10809 case 19: /* FAULTMASK */
10810 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
10812 case 20: /* CONTROL */
10813 /* Writing to the SPSEL bit only has an effect if we are in
10814 * thread mode; other bits can be updated by any privileged code.
10815 * write_v7m_control_spsel() deals with updating the SPSEL bit in
10816 * env->v7m.control, so we only need update the others.
10817 * For v7M, we must just ignore explicit writes to SPSEL in handler
10818 * mode; for v8M the write is permitted but will have no effect.
10820 if (arm_feature(env
, ARM_FEATURE_V8
) ||
10821 !arm_v7m_is_handler_mode(env
)) {
10822 write_v7m_control_spsel(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
10824 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
10825 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
10829 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
10830 " register %d\n", reg
);
10835 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
10837 /* Implement the TT instruction. op is bits [7:6] of the insn. */
10838 bool forceunpriv
= op
& 1;
10840 V8M_SAttributes sattrs
= {};
10842 bool r
, rw
, nsr
, nsrw
, mrvalid
;
10844 ARMMMUFaultInfo fi
= {};
10845 MemTxAttrs attrs
= {};
10850 bool targetsec
= env
->v7m
.secure
;
10853 /* Work out what the security state and privilege level we're
10854 * interested in is...
10857 targetsec
= !targetsec
;
10861 targetpriv
= false;
10863 targetpriv
= arm_v7m_is_handler_mode(env
) ||
10864 !(env
->v7m
.control
[targetsec
] & R_V7M_CONTROL_NPRIV_MASK
);
10867 /* ...and then figure out which MMU index this is */
10868 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targetsec
, targetpriv
);
10870 /* We know that the MPU and SAU don't care about the access type
10871 * for our purposes beyond that we don't want to claim to be
10872 * an insn fetch, so we arbitrarily call this a read.
10875 /* MPU region info only available for privileged or if
10876 * inspecting the other MPU state.
10878 if (arm_current_el(env
) != 0 || alt
) {
10879 /* We can ignore the return value as prot is always set */
10880 pmsav8_mpu_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
,
10881 &phys_addr
, &attrs
, &prot
, &is_subpage
,
10883 if (mregion
== -1) {
10889 r
= prot
& PAGE_READ
;
10890 rw
= prot
& PAGE_WRITE
;
10898 if (env
->v7m
.secure
) {
10899 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
10900 nsr
= sattrs
.ns
&& r
;
10901 nsrw
= sattrs
.ns
&& rw
;
10908 tt_resp
= (sattrs
.iregion
<< 24) |
10909 (sattrs
.irvalid
<< 23) |
10910 ((!sattrs
.ns
) << 22) |
10915 (sattrs
.srvalid
<< 17) |
10917 (sattrs
.sregion
<< 8) |
10925 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
10927 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
10928 * Note that we do not implement the (architecturally mandated)
10929 * alignment fault for attempts to use this on Device memory
10930 * (which matches the usual QEMU behaviour of not implementing either
10931 * alignment faults or any memory attribute handling).
10934 ARMCPU
*cpu
= arm_env_get_cpu(env
);
10935 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
10936 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
10938 #ifndef CONFIG_USER_ONLY
10940 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
10941 * the block size so we might have to do more than one TLB lookup.
10942 * We know that in fact for any v8 CPU the page size is at least 4K
10943 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
10944 * 1K as an artefact of legacy v5 subpage support being present in the
10945 * same QEMU executable.
10947 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
10948 void *hostaddr
[maxidx
];
10950 unsigned mmu_idx
= cpu_mmu_index(env
, false);
10951 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
10953 for (try = 0; try < 2; try++) {
10955 for (i
= 0; i
< maxidx
; i
++) {
10956 hostaddr
[i
] = tlb_vaddr_to_host(env
,
10957 vaddr
+ TARGET_PAGE_SIZE
* i
,
10959 if (!hostaddr
[i
]) {
10964 /* If it's all in the TLB it's fair game for just writing to;
10965 * we know we don't need to update dirty status, etc.
10967 for (i
= 0; i
< maxidx
- 1; i
++) {
10968 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
10970 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
10973 /* OK, try a store and see if we can populate the tlb. This
10974 * might cause an exception if the memory isn't writable,
10975 * in which case we will longjmp out of here. We must for
10976 * this purpose use the actual register value passed to us
10977 * so that we get the fault address right.
10979 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
10980 /* Now we can populate the other TLB entries, if any */
10981 for (i
= 0; i
< maxidx
; i
++) {
10982 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
10983 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
10984 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
10989 /* Slow path (probably attempt to do this to an I/O device or
10990 * similar, or clearing of a block of code we have translations
10991 * cached for). Just do a series of byte writes as the architecture
10992 * demands. It's not worth trying to use a cpu_physical_memory_map(),
10993 * memset(), unmap() sequence here because:
10994 * + we'd need to account for the blocksize being larger than a page
10995 * + the direct-RAM access case is almost always going to be dealt
10996 * with in the fastpath code above, so there's no speed benefit
10997 * + we would have to deal with the map returning NULL because the
10998 * bounce buffer was in use
11000 for (i
= 0; i
< blocklen
; i
++) {
11001 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
11005 memset(g2h(vaddr
), 0, blocklen
);
11009 /* Note that signed overflow is undefined in C. The following routines are
11010 careful to use unsigned types where modulo arithmetic is required.
11011 Failure to do so _will_ break on newer gcc. */
11013 /* Signed saturating arithmetic. */
11015 /* Perform 16-bit signed saturating addition. */
11016 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11021 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11030 /* Perform 8-bit signed saturating addition. */
11031 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11036 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11045 /* Perform 16-bit signed saturating subtraction. */
11046 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11051 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11060 /* Perform 8-bit signed saturating subtraction. */
11061 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11066 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11075 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11076 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11077 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11078 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11081 #include "op_addsub.h"
11083 /* Unsigned saturating arithmetic. */
11084 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11093 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11101 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11110 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11118 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11119 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11120 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11121 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11124 #include "op_addsub.h"
11126 /* Signed modulo arithmetic. */
11127 #define SARITH16(a, b, n, op) do { \
11129 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11130 RESULT(sum, n, 16); \
11132 ge |= 3 << (n * 2); \
11135 #define SARITH8(a, b, n, op) do { \
11137 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11138 RESULT(sum, n, 8); \
11144 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11145 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11146 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11147 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11151 #include "op_addsub.h"
11153 /* Unsigned modulo arithmetic. */
11154 #define ADD16(a, b, n) do { \
11156 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11157 RESULT(sum, n, 16); \
11158 if ((sum >> 16) == 1) \
11159 ge |= 3 << (n * 2); \
11162 #define ADD8(a, b, n) do { \
11164 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11165 RESULT(sum, n, 8); \
11166 if ((sum >> 8) == 1) \
11170 #define SUB16(a, b, n) do { \
11172 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11173 RESULT(sum, n, 16); \
11174 if ((sum >> 16) == 0) \
11175 ge |= 3 << (n * 2); \
11178 #define SUB8(a, b, n) do { \
11180 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11181 RESULT(sum, n, 8); \
11182 if ((sum >> 8) == 0) \
11189 #include "op_addsub.h"
11191 /* Halved signed arithmetic. */
11192 #define ADD16(a, b, n) \
11193 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11194 #define SUB16(a, b, n) \
11195 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11196 #define ADD8(a, b, n) \
11197 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11198 #define SUB8(a, b, n) \
11199 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11202 #include "op_addsub.h"
11204 /* Halved unsigned arithmetic. */
11205 #define ADD16(a, b, n) \
11206 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11207 #define SUB16(a, b, n) \
11208 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11209 #define ADD8(a, b, n) \
11210 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11211 #define SUB8(a, b, n) \
11212 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11215 #include "op_addsub.h"
11217 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11225 /* Unsigned sum of absolute byte differences. */
11226 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11229 sum
= do_usad(a
, b
);
11230 sum
+= do_usad(a
>> 8, b
>> 8);
11231 sum
+= do_usad(a
>> 16, b
>>16);
11232 sum
+= do_usad(a
>> 24, b
>> 24);
11236 /* For ARMv6 SEL instruction. */
11237 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11249 mask
|= 0xff000000;
11250 return (a
& mask
) | (b
& ~mask
);
11253 /* VFP support. We follow the convention used for VFP instructions:
11254 Single precision routines have a "s" suffix, double precision a
11257 /* Convert host exception flags to vfp form. */
11258 static inline int vfp_exceptbits_from_host(int host_bits
)
11260 int target_bits
= 0;
11262 if (host_bits
& float_flag_invalid
)
11264 if (host_bits
& float_flag_divbyzero
)
11266 if (host_bits
& float_flag_overflow
)
11268 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
11270 if (host_bits
& float_flag_inexact
)
11271 target_bits
|= 0x10;
11272 if (host_bits
& float_flag_input_denormal
)
11273 target_bits
|= 0x80;
11274 return target_bits
;
11277 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
11282 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
11283 | (env
->vfp
.vec_len
<< 16)
11284 | (env
->vfp
.vec_stride
<< 20);
11285 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
11286 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
11287 i
|= get_float_exception_flags(&env
->vfp
.fp_status_f16
);
11288 fpscr
|= vfp_exceptbits_from_host(i
);
11292 uint32_t vfp_get_fpscr(CPUARMState
*env
)
11294 return HELPER(vfp_get_fpscr
)(env
);
11297 /* Convert vfp exception flags to target form. */
11298 static inline int vfp_exceptbits_to_host(int target_bits
)
11302 if (target_bits
& 1)
11303 host_bits
|= float_flag_invalid
;
11304 if (target_bits
& 2)
11305 host_bits
|= float_flag_divbyzero
;
11306 if (target_bits
& 4)
11307 host_bits
|= float_flag_overflow
;
11308 if (target_bits
& 8)
11309 host_bits
|= float_flag_underflow
;
11310 if (target_bits
& 0x10)
11311 host_bits
|= float_flag_inexact
;
11312 if (target_bits
& 0x80)
11313 host_bits
|= float_flag_input_denormal
;
11317 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
11322 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
11323 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
11324 env
->vfp
.vec_len
= (val
>> 16) & 7;
11325 env
->vfp
.vec_stride
= (val
>> 20) & 3;
11328 if (changed
& (3 << 22)) {
11329 i
= (val
>> 22) & 3;
11331 case FPROUNDING_TIEEVEN
:
11332 i
= float_round_nearest_even
;
11334 case FPROUNDING_POSINF
:
11335 i
= float_round_up
;
11337 case FPROUNDING_NEGINF
:
11338 i
= float_round_down
;
11340 case FPROUNDING_ZERO
:
11341 i
= float_round_to_zero
;
11344 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
11345 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
11347 if (changed
& FPCR_FZ16
) {
11348 bool ftz_enabled
= val
& FPCR_FZ16
;
11349 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
11350 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
11352 if (changed
& FPCR_FZ
) {
11353 bool ftz_enabled
= val
& FPCR_FZ
;
11354 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
11355 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
11357 if (changed
& FPCR_DN
) {
11358 bool dnan_enabled
= val
& FPCR_DN
;
11359 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
11360 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
11363 /* The exception flags are ORed together when we read fpscr so we
11364 * only need to preserve the current state in one of our
11365 * float_status values.
11367 i
= vfp_exceptbits_to_host(val
);
11368 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
11369 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
11370 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
11373 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
11375 HELPER(vfp_set_fpscr
)(env
, val
);
11378 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
11380 #define VFP_BINOP(name) \
11381 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
11383 float_status *fpst = fpstp; \
11384 return float32_ ## name(a, b, fpst); \
11386 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
11388 float_status *fpst = fpstp; \
11389 return float64_ ## name(a, b, fpst); \
11401 float32
VFP_HELPER(neg
, s
)(float32 a
)
11403 return float32_chs(a
);
11406 float64
VFP_HELPER(neg
, d
)(float64 a
)
11408 return float64_chs(a
);
11411 float32
VFP_HELPER(abs
, s
)(float32 a
)
11413 return float32_abs(a
);
11416 float64
VFP_HELPER(abs
, d
)(float64 a
)
11418 return float64_abs(a
);
11421 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
11423 return float32_sqrt(a
, &env
->vfp
.fp_status
);
11426 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
11428 return float64_sqrt(a
, &env
->vfp
.fp_status
);
11431 /* XXX: check quiet/signaling case */
11432 #define DO_VFP_cmp(p, type) \
11433 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
11436 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
11437 case 0: flags = 0x6; break; \
11438 case -1: flags = 0x8; break; \
11439 case 1: flags = 0x2; break; \
11440 default: case 2: flags = 0x3; break; \
11442 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
11443 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
11445 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
11448 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
11449 case 0: flags = 0x6; break; \
11450 case -1: flags = 0x8; break; \
11451 case 1: flags = 0x2; break; \
11452 default: case 2: flags = 0x3; break; \
11454 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
11455 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
11457 DO_VFP_cmp(s
, float32
)
11458 DO_VFP_cmp(d
, float64
)
11461 /* Integer to float and float to integer conversions */
11463 #define CONV_ITOF(name, ftype, fsz, sign) \
11464 ftype HELPER(name)(uint32_t x, void *fpstp) \
11466 float_status *fpst = fpstp; \
11467 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
11470 #define CONV_FTOI(name, ftype, fsz, sign, round) \
11471 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
11473 float_status *fpst = fpstp; \
11474 if (float##fsz##_is_any_nan(x)) { \
11475 float_raise(float_flag_invalid, fpst); \
11478 return float##fsz##_to_##sign##int32##round(x, fpst); \
11481 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
11482 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
11483 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
11484 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
11486 FLOAT_CONVS(si
, h
, uint32_t, 16, )
11487 FLOAT_CONVS(si
, s
, float32
, 32, )
11488 FLOAT_CONVS(si
, d
, float64
, 64, )
11489 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
11490 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
11491 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
11497 /* floating point conversion */
11498 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
11500 return float32_to_float64(x
, &env
->vfp
.fp_status
);
11503 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
11505 return float64_to_float32(x
, &env
->vfp
.fp_status
);
11508 /* VFP3 fixed point conversion. */
11509 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11510 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
11513 float_status *fpst = fpstp; \
11515 tmp = itype##_to_##float##fsz(x, fpst); \
11516 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
11519 /* Notice that we want only input-denormal exception flags from the
11520 * scalbn operation: the other possible flags (overflow+inexact if
11521 * we overflow to infinity, output-denormal) aren't correct for the
11522 * complete scale-and-convert operation.
11524 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
11525 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
11529 float_status *fpst = fpstp; \
11530 int old_exc_flags = get_float_exception_flags(fpst); \
11532 if (float##fsz##_is_any_nan(x)) { \
11533 float_raise(float_flag_invalid, fpst); \
11536 tmp = float##fsz##_scalbn(x, shift, fpst); \
11537 old_exc_flags |= get_float_exception_flags(fpst) \
11538 & float_flag_input_denormal; \
11539 set_float_exception_flags(old_exc_flags, fpst); \
11540 return float##fsz##_to_##itype##round(tmp, fpst); \
11543 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
11544 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11545 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
11546 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
11548 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
11549 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
11550 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
11552 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
11553 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
11554 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
11555 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
11556 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
11557 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
11558 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
11559 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
11560 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
11561 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
11562 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
11563 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
11565 #undef VFP_CONV_FIX
11566 #undef VFP_CONV_FIX_FLOAT
11567 #undef VFP_CONV_FLOAT_FIX_ROUND
11568 #undef VFP_CONV_FIX_A64
11570 /* Conversion to/from f16 can overflow to infinity before/after scaling.
11571 * Therefore we convert to f64, scale, and then convert f64 to f16; or
11572 * vice versa for conversion to integer.
11574 * For 16- and 32-bit integers, the conversion to f64 never rounds.
11575 * For 64-bit integers, any integer that would cause rounding will also
11576 * overflow to f16 infinity, so there is no double rounding problem.
11579 static float16
do_postscale_fp16(float64 f
, int shift
, float_status
*fpst
)
11581 return float64_to_float16(float64_scalbn(f
, -shift
, fpst
), true, fpst
);
11584 uint32_t HELPER(vfp_sltoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11586 return do_postscale_fp16(int32_to_float64(x
, fpst
), shift
, fpst
);
11589 uint32_t HELPER(vfp_ultoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11591 return do_postscale_fp16(uint32_to_float64(x
, fpst
), shift
, fpst
);
11594 uint32_t HELPER(vfp_sqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
11596 return do_postscale_fp16(int64_to_float64(x
, fpst
), shift
, fpst
);
11599 uint32_t HELPER(vfp_uqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
11601 return do_postscale_fp16(uint64_to_float64(x
, fpst
), shift
, fpst
);
11604 static float64
do_prescale_fp16(float16 f
, int shift
, float_status
*fpst
)
11606 if (unlikely(float16_is_any_nan(f
))) {
11607 float_raise(float_flag_invalid
, fpst
);
11610 int old_exc_flags
= get_float_exception_flags(fpst
);
11613 ret
= float16_to_float64(f
, true, fpst
);
11614 ret
= float64_scalbn(ret
, shift
, fpst
);
11615 old_exc_flags
|= get_float_exception_flags(fpst
)
11616 & float_flag_input_denormal
;
11617 set_float_exception_flags(old_exc_flags
, fpst
);
11623 uint32_t HELPER(vfp_toshh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11625 return float64_to_int16(do_prescale_fp16(x
, shift
, fpst
), fpst
);
11628 uint32_t HELPER(vfp_touhh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11630 return float64_to_uint16(do_prescale_fp16(x
, shift
, fpst
), fpst
);
11633 uint32_t HELPER(vfp_toslh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11635 return float64_to_int32(do_prescale_fp16(x
, shift
, fpst
), fpst
);
11638 uint32_t HELPER(vfp_toulh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11640 return float64_to_uint32(do_prescale_fp16(x
, shift
, fpst
), fpst
);
11643 uint64_t HELPER(vfp_tosqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11645 return float64_to_int64(do_prescale_fp16(x
, shift
, fpst
), fpst
);
11648 uint64_t HELPER(vfp_touqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
11650 return float64_to_uint64(do_prescale_fp16(x
, shift
, fpst
), fpst
);
11653 /* Set the current fp rounding mode and return the old one.
11654 * The argument is a softfloat float_round_ value.
11656 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
11658 float_status
*fp_status
= fpstp
;
11660 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
11661 set_float_rounding_mode(rmode
, fp_status
);
11666 /* Set the current fp rounding mode in the standard fp status and return
11667 * the old one. This is for NEON instructions that need to change the
11668 * rounding mode but wish to use the standard FPSCR values for everything
11669 * else. Always set the rounding mode back to the correct value after
11671 * The argument is a softfloat float_round_ value.
11673 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
11675 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
11677 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
11678 set_float_rounding_mode(rmode
, fp_status
);
11683 /* Half precision conversions. */
11684 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
11686 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11687 * it would affect flushing input denormals.
11689 float_status
*fpst
= fpstp
;
11690 flag save
= get_flush_inputs_to_zero(fpst
);
11691 set_flush_inputs_to_zero(false, fpst
);
11692 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
11693 set_flush_inputs_to_zero(save
, fpst
);
11697 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
11699 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11700 * it would affect flushing output denormals.
11702 float_status
*fpst
= fpstp
;
11703 flag save
= get_flush_to_zero(fpst
);
11704 set_flush_to_zero(false, fpst
);
11705 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
11706 set_flush_to_zero(save
, fpst
);
11710 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
11712 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11713 * it would affect flushing input denormals.
11715 float_status
*fpst
= fpstp
;
11716 flag save
= get_flush_inputs_to_zero(fpst
);
11717 set_flush_inputs_to_zero(false, fpst
);
11718 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
11719 set_flush_inputs_to_zero(save
, fpst
);
11723 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
11725 /* Squash FZ16 to 0 for the duration of conversion. In this case,
11726 * it would affect flushing output denormals.
11728 float_status
*fpst
= fpstp
;
11729 flag save
= get_flush_to_zero(fpst
);
11730 set_flush_to_zero(false, fpst
);
11731 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
11732 set_flush_to_zero(save
, fpst
);
11736 #define float32_two make_float32(0x40000000)
11737 #define float32_three make_float32(0x40400000)
11738 #define float32_one_point_five make_float32(0x3fc00000)
11740 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
11742 float_status
*s
= &env
->vfp
.standard_fp_status
;
11743 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
11744 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
11745 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
11746 float_raise(float_flag_input_denormal
, s
);
11748 return float32_two
;
11750 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
11753 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
11755 float_status
*s
= &env
->vfp
.standard_fp_status
;
11757 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
11758 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
11759 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
11760 float_raise(float_flag_input_denormal
, s
);
11762 return float32_one_point_five
;
11764 product
= float32_mul(a
, b
, s
);
11765 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
11768 /* NEON helpers. */
11770 /* Constants 256 and 512 are used in some helpers; we avoid relying on
11771 * int->float conversions at run-time. */
11772 #define float64_256 make_float64(0x4070000000000000LL)
11773 #define float64_512 make_float64(0x4080000000000000LL)
11774 #define float16_maxnorm make_float16(0x7bff)
11775 #define float32_maxnorm make_float32(0x7f7fffff)
11776 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
11778 /* Reciprocal functions
11780 * The algorithm that must be used to calculate the estimate
11781 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
11784 /* See RecipEstimate()
11786 * input is a 9 bit fixed point number
11787 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
11788 * result range 256 .. 511 for a number from 1.0 to 511/256.
11791 static int recip_estimate(int input
)
11794 assert(256 <= input
&& input
< 512);
11795 a
= (input
* 2) + 1;
11798 assert(256 <= r
&& r
< 512);
11803 * Common wrapper to call recip_estimate
11805 * The parameters are exponent and 64 bit fraction (without implicit
11806 * bit) where the binary point is nominally at bit 52. Returns a
11807 * float64 which can then be rounded to the appropriate size by the
11811 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
11813 uint32_t scaled
, estimate
;
11814 uint64_t result_frac
;
11817 /* Handle sub-normals */
11819 if (extract64(frac
, 51, 1) == 0) {
11827 /* scaled = UInt('1':fraction<51:44>) */
11828 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
11829 estimate
= recip_estimate(scaled
);
11831 result_exp
= exp_off
- *exp
;
11832 result_frac
= deposit64(0, 44, 8, estimate
);
11833 if (result_exp
== 0) {
11834 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
11835 } else if (result_exp
== -1) {
11836 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
11842 return result_frac
;
11845 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
11847 switch (fpst
->float_rounding_mode
) {
11848 case float_round_nearest_even
: /* Round to Nearest */
11850 case float_round_up
: /* Round to +Inf */
11852 case float_round_down
: /* Round to -Inf */
11854 case float_round_to_zero
: /* Round to Zero */
11858 g_assert_not_reached();
11861 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
11863 float_status
*fpst
= fpstp
;
11864 float16 f16
= float16_squash_input_denormal(input
, fpst
);
11865 uint32_t f16_val
= float16_val(f16
);
11866 uint32_t f16_sign
= float16_is_neg(f16
);
11867 int f16_exp
= extract32(f16_val
, 10, 5);
11868 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
11871 if (float16_is_any_nan(f16
)) {
11873 if (float16_is_signaling_nan(f16
, fpst
)) {
11874 float_raise(float_flag_invalid
, fpst
);
11875 nan
= float16_silence_nan(f16
, fpst
);
11877 if (fpst
->default_nan_mode
) {
11878 nan
= float16_default_nan(fpst
);
11881 } else if (float16_is_infinity(f16
)) {
11882 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
11883 } else if (float16_is_zero(f16
)) {
11884 float_raise(float_flag_divbyzero
, fpst
);
11885 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
11886 } else if (float16_abs(f16
) < (1 << 8)) {
11887 /* Abs(value) < 2.0^-16 */
11888 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
11889 if (round_to_inf(fpst
, f16_sign
)) {
11890 return float16_set_sign(float16_infinity
, f16_sign
);
11892 return float16_set_sign(float16_maxnorm
, f16_sign
);
11894 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
11895 float_raise(float_flag_underflow
, fpst
);
11896 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
11899 f64_frac
= call_recip_estimate(&f16_exp
, 29,
11900 ((uint64_t) f16_frac
) << (52 - 10));
11902 /* result = sign : result_exp<4:0> : fraction<51:42> */
11903 f16_val
= deposit32(0, 15, 1, f16_sign
);
11904 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
11905 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
11906 return make_float16(f16_val
);
11909 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
11911 float_status
*fpst
= fpstp
;
11912 float32 f32
= float32_squash_input_denormal(input
, fpst
);
11913 uint32_t f32_val
= float32_val(f32
);
11914 bool f32_sign
= float32_is_neg(f32
);
11915 int f32_exp
= extract32(f32_val
, 23, 8);
11916 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
11919 if (float32_is_any_nan(f32
)) {
11921 if (float32_is_signaling_nan(f32
, fpst
)) {
11922 float_raise(float_flag_invalid
, fpst
);
11923 nan
= float32_silence_nan(f32
, fpst
);
11925 if (fpst
->default_nan_mode
) {
11926 nan
= float32_default_nan(fpst
);
11929 } else if (float32_is_infinity(f32
)) {
11930 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
11931 } else if (float32_is_zero(f32
)) {
11932 float_raise(float_flag_divbyzero
, fpst
);
11933 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
11934 } else if (float32_abs(f32
) < (1ULL << 21)) {
11935 /* Abs(value) < 2.0^-128 */
11936 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
11937 if (round_to_inf(fpst
, f32_sign
)) {
11938 return float32_set_sign(float32_infinity
, f32_sign
);
11940 return float32_set_sign(float32_maxnorm
, f32_sign
);
11942 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
11943 float_raise(float_flag_underflow
, fpst
);
11944 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
11947 f64_frac
= call_recip_estimate(&f32_exp
, 253,
11948 ((uint64_t) f32_frac
) << (52 - 23));
11950 /* result = sign : result_exp<7:0> : fraction<51:29> */
11951 f32_val
= deposit32(0, 31, 1, f32_sign
);
11952 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
11953 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
11954 return make_float32(f32_val
);
11957 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
11959 float_status
*fpst
= fpstp
;
11960 float64 f64
= float64_squash_input_denormal(input
, fpst
);
11961 uint64_t f64_val
= float64_val(f64
);
11962 bool f64_sign
= float64_is_neg(f64
);
11963 int f64_exp
= extract64(f64_val
, 52, 11);
11964 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
11966 /* Deal with any special cases */
11967 if (float64_is_any_nan(f64
)) {
11969 if (float64_is_signaling_nan(f64
, fpst
)) {
11970 float_raise(float_flag_invalid
, fpst
);
11971 nan
= float64_silence_nan(f64
, fpst
);
11973 if (fpst
->default_nan_mode
) {
11974 nan
= float64_default_nan(fpst
);
11977 } else if (float64_is_infinity(f64
)) {
11978 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
11979 } else if (float64_is_zero(f64
)) {
11980 float_raise(float_flag_divbyzero
, fpst
);
11981 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
11982 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
11983 /* Abs(value) < 2.0^-1024 */
11984 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
11985 if (round_to_inf(fpst
, f64_sign
)) {
11986 return float64_set_sign(float64_infinity
, f64_sign
);
11988 return float64_set_sign(float64_maxnorm
, f64_sign
);
11990 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
11991 float_raise(float_flag_underflow
, fpst
);
11992 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
11995 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
11997 /* result = sign : result_exp<10:0> : fraction<51:0>; */
11998 f64_val
= deposit64(0, 63, 1, f64_sign
);
11999 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
12000 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
12001 return make_float64(f64_val
);
12004 /* The algorithm that must be used to calculate the estimate
12005 * is specified by the ARM ARM.
12008 static int do_recip_sqrt_estimate(int a
)
12012 assert(128 <= a
&& a
< 512);
12020 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
12023 estimate
= (b
+ 1) / 2;
12024 assert(256 <= estimate
&& estimate
< 512);
12030 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
12036 while (extract64(frac
, 51, 1) == 0) {
12040 frac
= extract64(frac
, 0, 51) << 1;
12044 /* scaled = UInt('01':fraction<51:45>) */
12045 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
12047 /* scaled = UInt('1':fraction<51:44>) */
12048 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
12050 estimate
= do_recip_sqrt_estimate(scaled
);
12052 *exp
= (exp_off
- *exp
) / 2;
12053 return extract64(estimate
, 0, 8) << 44;
12056 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
12058 float_status
*s
= fpstp
;
12059 float16 f16
= float16_squash_input_denormal(input
, s
);
12060 uint16_t val
= float16_val(f16
);
12061 bool f16_sign
= float16_is_neg(f16
);
12062 int f16_exp
= extract32(val
, 10, 5);
12063 uint16_t f16_frac
= extract32(val
, 0, 10);
12066 if (float16_is_any_nan(f16
)) {
12068 if (float16_is_signaling_nan(f16
, s
)) {
12069 float_raise(float_flag_invalid
, s
);
12070 nan
= float16_silence_nan(f16
, s
);
12072 if (s
->default_nan_mode
) {
12073 nan
= float16_default_nan(s
);
12076 } else if (float16_is_zero(f16
)) {
12077 float_raise(float_flag_divbyzero
, s
);
12078 return float16_set_sign(float16_infinity
, f16_sign
);
12079 } else if (f16_sign
) {
12080 float_raise(float_flag_invalid
, s
);
12081 return float16_default_nan(s
);
12082 } else if (float16_is_infinity(f16
)) {
12083 return float16_zero
;
12086 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
12087 * preserving the parity of the exponent. */
12089 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
12091 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
12093 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
12094 val
= deposit32(0, 15, 1, f16_sign
);
12095 val
= deposit32(val
, 10, 5, f16_exp
);
12096 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
12097 return make_float16(val
);
12100 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
12102 float_status
*s
= fpstp
;
12103 float32 f32
= float32_squash_input_denormal(input
, s
);
12104 uint32_t val
= float32_val(f32
);
12105 uint32_t f32_sign
= float32_is_neg(f32
);
12106 int f32_exp
= extract32(val
, 23, 8);
12107 uint32_t f32_frac
= extract32(val
, 0, 23);
12110 if (float32_is_any_nan(f32
)) {
12112 if (float32_is_signaling_nan(f32
, s
)) {
12113 float_raise(float_flag_invalid
, s
);
12114 nan
= float32_silence_nan(f32
, s
);
12116 if (s
->default_nan_mode
) {
12117 nan
= float32_default_nan(s
);
12120 } else if (float32_is_zero(f32
)) {
12121 float_raise(float_flag_divbyzero
, s
);
12122 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
12123 } else if (float32_is_neg(f32
)) {
12124 float_raise(float_flag_invalid
, s
);
12125 return float32_default_nan(s
);
12126 } else if (float32_is_infinity(f32
)) {
12127 return float32_zero
;
12130 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
12131 * preserving the parity of the exponent. */
12133 f64_frac
= ((uint64_t) f32_frac
) << 29;
12135 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
12137 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
12138 val
= deposit32(0, 31, 1, f32_sign
);
12139 val
= deposit32(val
, 23, 8, f32_exp
);
12140 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
12141 return make_float32(val
);
12144 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
12146 float_status
*s
= fpstp
;
12147 float64 f64
= float64_squash_input_denormal(input
, s
);
12148 uint64_t val
= float64_val(f64
);
12149 bool f64_sign
= float64_is_neg(f64
);
12150 int f64_exp
= extract64(val
, 52, 11);
12151 uint64_t f64_frac
= extract64(val
, 0, 52);
12153 if (float64_is_any_nan(f64
)) {
12155 if (float64_is_signaling_nan(f64
, s
)) {
12156 float_raise(float_flag_invalid
, s
);
12157 nan
= float64_silence_nan(f64
, s
);
12159 if (s
->default_nan_mode
) {
12160 nan
= float64_default_nan(s
);
12163 } else if (float64_is_zero(f64
)) {
12164 float_raise(float_flag_divbyzero
, s
);
12165 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
12166 } else if (float64_is_neg(f64
)) {
12167 float_raise(float_flag_invalid
, s
);
12168 return float64_default_nan(s
);
12169 } else if (float64_is_infinity(f64
)) {
12170 return float64_zero
;
12173 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
12175 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
12176 val
= deposit64(0, 61, 1, f64_sign
);
12177 val
= deposit64(val
, 52, 11, f64_exp
);
12178 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
12179 return make_float64(val
);
12182 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
12184 /* float_status *s = fpstp; */
12185 int input
, estimate
;
12187 if ((a
& 0x80000000) == 0) {
12191 input
= extract32(a
, 23, 9);
12192 estimate
= recip_estimate(input
);
12194 return deposit32(0, (32 - 9), 9, estimate
);
12197 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
12201 if ((a
& 0xc0000000) == 0) {
12205 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
12207 return deposit32(0, 23, 9, estimate
);
12210 /* VFPv4 fused multiply-accumulate */
12211 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
12213 float_status
*fpst
= fpstp
;
12214 return float32_muladd(a
, b
, c
, 0, fpst
);
12217 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
12219 float_status
*fpst
= fpstp
;
12220 return float64_muladd(a
, b
, c
, 0, fpst
);
12223 /* ARMv8 round to integral */
12224 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
12226 return float32_round_to_int(x
, fp_status
);
12229 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
12231 return float64_round_to_int(x
, fp_status
);
12234 float32
HELPER(rints
)(float32 x
, void *fp_status
)
12236 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
12239 ret
= float32_round_to_int(x
, fp_status
);
12241 /* Suppress any inexact exceptions the conversion produced */
12242 if (!(old_flags
& float_flag_inexact
)) {
12243 new_flags
= get_float_exception_flags(fp_status
);
12244 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
12250 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
12252 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
12255 ret
= float64_round_to_int(x
, fp_status
);
12257 new_flags
= get_float_exception_flags(fp_status
);
12259 /* Suppress any inexact exceptions the conversion produced */
12260 if (!(old_flags
& float_flag_inexact
)) {
12261 new_flags
= get_float_exception_flags(fp_status
);
12262 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
12268 /* Convert ARM rounding mode to softfloat */
12269 int arm_rmode_to_sf(int rmode
)
12272 case FPROUNDING_TIEAWAY
:
12273 rmode
= float_round_ties_away
;
12275 case FPROUNDING_ODD
:
12276 /* FIXME: add support for TIEAWAY and ODD */
12277 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
12279 case FPROUNDING_TIEEVEN
:
12281 rmode
= float_round_nearest_even
;
12283 case FPROUNDING_POSINF
:
12284 rmode
= float_round_up
;
12286 case FPROUNDING_NEGINF
:
12287 rmode
= float_round_down
;
12289 case FPROUNDING_ZERO
:
12290 rmode
= float_round_to_zero
;
12297 * The upper bytes of val (above the number specified by 'bytes') must have
12298 * been zeroed out by the caller.
12300 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12304 stl_le_p(buf
, val
);
12306 /* zlib crc32 converts the accumulator and output to one's complement. */
12307 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12310 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12314 stl_le_p(buf
, val
);
12316 /* Linux crc32c converts the output to one's complement. */
12317 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12320 /* Return the exception level to which FP-disabled exceptions should
12321 * be taken, or 0 if FP is enabled.
12323 static inline int fp_exception_el(CPUARMState
*env
)
12325 #ifndef CONFIG_USER_ONLY
12327 int cur_el
= arm_current_el(env
);
12329 /* CPACR and the CPTR registers don't exist before v6, so FP is
12330 * always accessible
12332 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12336 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12337 * 0, 2 : trap EL0 and EL1/PL1 accesses
12338 * 1 : trap only EL0 accesses
12339 * 3 : trap no accesses
12341 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
12345 if (cur_el
== 0 || cur_el
== 1) {
12346 /* Trap to PL1, which might be EL1 or EL3 */
12347 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
12352 if (cur_el
== 3 && !is_a64(env
)) {
12353 /* Secure PL1 running at EL3 */
12366 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12367 * check because zero bits in the registers mean "don't trap".
12370 /* CPTR_EL2 : present in v7VE or v8 */
12371 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
12372 && !arm_is_secure_below_el3(env
)) {
12373 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12377 /* CPTR_EL3 : present in v8 */
12378 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
12379 /* Trap all FP ops to EL3 */
12386 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
12387 target_ulong
*cs_base
, uint32_t *pflags
)
12389 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
12390 int fp_el
= fp_exception_el(env
);
12394 int sve_el
= sve_exception_el(env
);
12398 flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
12399 /* Get control bits for tagged addresses */
12400 flags
|= (arm_regime_tbi0(env
, mmu_idx
) << ARM_TBFLAG_TBI0_SHIFT
);
12401 flags
|= (arm_regime_tbi1(env
, mmu_idx
) << ARM_TBFLAG_TBI1_SHIFT
);
12402 flags
|= sve_el
<< ARM_TBFLAG_SVEEXC_EL_SHIFT
;
12404 /* If SVE is disabled, but FP is enabled,
12405 then the effective len is 0. */
12406 if (sve_el
!= 0 && fp_el
== 0) {
12409 int current_el
= arm_current_el(env
);
12411 zcr_len
= env
->vfp
.zcr_el
[current_el
<= 1 ? 1 : current_el
];
12413 if (current_el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
12414 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
12416 if (current_el
< 3 && arm_feature(env
, ARM_FEATURE_EL3
)) {
12417 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
12420 flags
|= zcr_len
<< ARM_TBFLAG_ZCR_LEN_SHIFT
;
12422 *pc
= env
->regs
[15];
12423 flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
12424 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
12425 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
12426 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
12427 | (arm_sctlr_b(env
) << ARM_TBFLAG_SCTLR_B_SHIFT
);
12428 if (!(access_secure_reg(env
))) {
12429 flags
|= ARM_TBFLAG_NS_MASK
;
12431 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
12432 || arm_el_is_aa64(env
, 1)) {
12433 flags
|= ARM_TBFLAG_VFPEN_MASK
;
12435 flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
12436 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
12439 flags
|= (arm_to_core_mmu_idx(mmu_idx
) << ARM_TBFLAG_MMUIDX_SHIFT
);
12441 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12442 * states defined in the ARM ARM for software singlestep:
12443 * SS_ACTIVE PSTATE.SS State
12444 * 0 x Inactive (the TB flag for SS is always 0)
12445 * 1 0 Active-pending
12446 * 1 1 Active-not-pending
12448 if (arm_singlestep_active(env
)) {
12449 flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
12451 if (env
->pstate
& PSTATE_SS
) {
12452 flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
12455 if (env
->uncached_cpsr
& PSTATE_SS
) {
12456 flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
12460 if (arm_cpu_data_is_big_endian(env
)) {
12461 flags
|= ARM_TBFLAG_BE_DATA_MASK
;
12463 flags
|= fp_el
<< ARM_TBFLAG_FPEXC_EL_SHIFT
;
12465 if (arm_v7m_is_handler_mode(env
)) {
12466 flags
|= ARM_TBFLAG_HANDLER_MASK
;