monitor: fix object_del for command-line-created objects
[qemu/ar7.git] / hw / intc / arm_gicv3_dist.c
blob3ea3dd0d40cc528385887b9f15feba864c2107d2
1 /*
2 * ARM GICv3 emulation: Distributor
4 * Copyright (c) 2015 Huawei.
5 * Copyright (c) 2016 Linaro Limited.
6 * Written by Shlomo Pongratz, Peter Maydell
8 * This code is licensed under the GPL, version 2 or (at your option)
9 * any later version.
12 #include "qemu/osdep.h"
13 #include "qemu/log.h"
14 #include "trace.h"
15 #include "gicv3_internal.h"
17 /* The GICD_NSACR registers contain a two bit field for each interrupt which
18 * allows the guest to give NonSecure code access to registers controlling
19 * Secure interrupts:
20 * 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI)
21 * 0b01: NS r/w accesses permitted to ISPENDR, SETSPI_NSR, SGIR
22 * 0b10: as 0b01, and also r/w to ICPENDR, r/o to ISACTIVER/ICACTIVER,
23 * and w/o to CLRSPI_NSR
24 * 0b11: as 0b10, and also r/w to IROUTER and ITARGETSR
26 * Given a (multiple-of-32) interrupt number, these mask functions return
27 * a mask word where each bit is 1 if the NSACR settings permit access
28 * to the interrupt. The mask returned can then be ORed with the GICD_GROUP
29 * word for this set of interrupts to give an overall mask.
32 typedef uint32_t maskfn(GICv3State *s, int irq);
34 static uint32_t mask_nsacr_ge1(GICv3State *s, int irq)
36 /* Return a mask where each bit is set if the NSACR field is >= 1 */
37 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1];
39 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16];
40 raw_nsacr = (raw_nsacr >> 1) | raw_nsacr;
41 return half_unshuffle64(raw_nsacr);
44 static uint32_t mask_nsacr_ge2(GICv3State *s, int irq)
46 /* Return a mask where each bit is set if the NSACR field is >= 2 */
47 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1];
49 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16];
50 raw_nsacr = raw_nsacr >> 1;
51 return half_unshuffle64(raw_nsacr);
54 /* We don't need a mask_nsacr_ge3() because IROUTER<n> isn't a bitmap register,
55 * but it would be implemented using:
56 * raw_nsacr = (raw_nsacr >> 1) & raw_nsacr;
59 static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs,
60 maskfn *maskfn, int irq)
62 /* Return a 32-bit mask which should be applied for this set of 32
63 * interrupts; each bit is 1 if access is permitted by the
64 * combination of attrs.secure, GICD_GROUPR and GICD_NSACR.
66 uint32_t mask;
68 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
69 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI
70 * unless the NSACR bits permit access.
72 mask = *gic_bmp_ptr32(s->group, irq);
73 if (maskfn) {
74 mask |= maskfn(s, irq);
76 return mask;
78 return 0xFFFFFFFFU;
81 static int gicd_ns_access(GICv3State *s, int irq)
83 /* Return the 2 bit NS_access<x> field from GICD_NSACR<n> for the
84 * specified interrupt.
86 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
87 return 0;
89 return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2);
92 static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
93 uint32_t *bmp,
94 maskfn *maskfn,
95 int offset, uint32_t val)
97 /* Helper routine to implement writing to a "set-bitmap" register
98 * (GICD_ISENABLER, GICD_ISPENDR, etc).
99 * Semantics implemented here:
100 * RAZ/WI for SGIs, PPIs, unimplemented IRQs
101 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI.
102 * Writing 1 means "set bit in bitmap"; writing 0 is ignored.
103 * offset should be the offset in bytes of the register from the start
104 * of its group.
106 int irq = offset * 8;
108 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
109 return;
111 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
112 *gic_bmp_ptr32(bmp, irq) |= val;
113 gicv3_update(s, irq, 32);
116 static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
117 uint32_t *bmp,
118 maskfn *maskfn,
119 int offset, uint32_t val)
121 /* Helper routine to implement writing to a "clear-bitmap" register
122 * (GICD_ICENABLER, GICD_ICPENDR, etc).
123 * Semantics implemented here:
124 * RAZ/WI for SGIs, PPIs, unimplemented IRQs
125 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI.
126 * Writing 1 means "clear bit in bitmap"; writing 0 is ignored.
127 * offset should be the offset in bytes of the register from the start
128 * of its group.
130 int irq = offset * 8;
132 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
133 return;
135 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
136 *gic_bmp_ptr32(bmp, irq) &= ~val;
137 gicv3_update(s, irq, 32);
140 static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
141 uint32_t *bmp,
142 maskfn *maskfn,
143 int offset)
145 /* Helper routine to implement reading a "set/clear-bitmap" register
146 * (GICD_ICENABLER, GICD_ISENABLER, GICD_ICPENDR, etc).
147 * Semantics implemented here:
148 * RAZ/WI for SGIs, PPIs, unimplemented IRQs
149 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI.
150 * offset should be the offset in bytes of the register from the start
151 * of its group.
153 int irq = offset * 8;
154 uint32_t val;
156 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
157 return 0;
159 val = *gic_bmp_ptr32(bmp, irq);
160 if (bmp == s->pending) {
161 /* The PENDING register is a special case -- for level triggered
162 * interrupts, the PENDING state is the logical OR of the state of
163 * the PENDING latch with the input line level.
165 uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq);
166 uint32_t level = *gic_bmp_ptr32(s->level, irq);
167 val |= (~edge & level);
169 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
170 return val;
173 static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq)
175 /* Read the value of GICD_IPRIORITYR<n> for the specified interrupt,
176 * honouring security state (these are RAZ/WI for Group 0 or Secure
177 * Group 1 interrupts).
179 uint32_t prio;
181 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
182 return 0;
185 prio = s->gicd_ipriority[irq];
187 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
188 if (!gicv3_gicd_group_test(s, irq)) {
189 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
190 return 0;
192 /* NS view of the interrupt priority */
193 prio = (prio << 1) & 0xff;
195 return prio;
198 static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq,
199 uint8_t value)
201 /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt,
202 * honouring security state (these are RAZ/WI for Group 0 or Secure
203 * Group 1 interrupts).
205 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
206 return;
209 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
210 if (!gicv3_gicd_group_test(s, irq)) {
211 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
212 return;
214 /* NS view of the interrupt priority */
215 value = 0x80 | (value >> 1);
217 s->gicd_ipriority[irq] = value;
220 static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq)
222 /* Read the value of GICD_IROUTER<n> for the specified interrupt,
223 * honouring security state.
225 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
226 return 0;
229 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
230 /* RAZ/WI for NS accesses to secure interrupts */
231 if (!gicv3_gicd_group_test(s, irq)) {
232 if (gicd_ns_access(s, irq) != 3) {
233 return 0;
238 return s->gicd_irouter[irq];
241 static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq,
242 uint64_t val)
244 /* Write the value of GICD_IROUTER<n> for the specified interrupt,
245 * honouring security state.
247 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
248 return;
251 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
252 /* RAZ/WI for NS accesses to secure interrupts */
253 if (!gicv3_gicd_group_test(s, irq)) {
254 if (gicd_ns_access(s, irq) != 3) {
255 return;
260 s->gicd_irouter[irq] = val;
261 gicv3_cache_target_cpustate(s, irq);
262 gicv3_update(s, irq, 1);
265 static MemTxResult gicd_readb(GICv3State *s, hwaddr offset,
266 uint64_t *data, MemTxAttrs attrs)
268 /* Most GICv3 distributor registers do not support byte accesses. */
269 switch (offset) {
270 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
271 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
272 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
273 /* This GIC implementation always has affinity routing enabled,
274 * so these registers are all RAZ/WI.
276 return MEMTX_OK;
277 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
278 *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR);
279 return MEMTX_OK;
280 default:
281 return MEMTX_ERROR;
285 static MemTxResult gicd_writeb(GICv3State *s, hwaddr offset,
286 uint64_t value, MemTxAttrs attrs)
288 /* Most GICv3 distributor registers do not support byte accesses. */
289 switch (offset) {
290 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
291 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
292 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
293 /* This GIC implementation always has affinity routing enabled,
294 * so these registers are all RAZ/WI.
296 return MEMTX_OK;
297 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
299 int irq = offset - GICD_IPRIORITYR;
301 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
302 return MEMTX_OK;
304 gicd_write_ipriorityr(s, attrs, irq, value);
305 gicv3_update(s, irq, 1);
306 return MEMTX_OK;
308 default:
309 return MEMTX_ERROR;
313 static MemTxResult gicd_readw(GICv3State *s, hwaddr offset,
314 uint64_t *data, MemTxAttrs attrs)
316 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR
317 * support 16 bit accesses, and those registers are all part of the
318 * optional message-based SPI feature which this GIC does not currently
319 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are
320 * reserved.
322 return MEMTX_ERROR;
325 static MemTxResult gicd_writew(GICv3State *s, hwaddr offset,
326 uint64_t value, MemTxAttrs attrs)
328 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR
329 * support 16 bit accesses, and those registers are all part of the
330 * optional message-based SPI feature which this GIC does not currently
331 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are
332 * reserved.
334 return MEMTX_ERROR;
337 static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
338 uint64_t *data, MemTxAttrs attrs)
340 /* Almost all GICv3 distributor registers are 32-bit.
341 * Note that WO registers must return an UNKNOWN value on reads,
342 * not an abort.
345 switch (offset) {
346 case GICD_CTLR:
347 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
348 /* The NS view of the GICD_CTLR sees only certain bits:
349 * + bit [31] (RWP) is an alias of the Secure bit [31]
350 * + bit [4] (ARE_NS) is an alias of Secure bit [5]
351 * + bit [1] (EnableGrp1A) is an alias of Secure bit [1] if
352 * NS affinity routing is enabled, otherwise RES0
353 * + bit [0] (EnableGrp1) is an alias of Secure bit [1] if
354 * NS affinity routing is not enabled, otherwise RES0
355 * Since for QEMU affinity routing is always enabled
356 * for both S and NS this means that bits [4] and [5] are
357 * both always 1, and we can simply make the NS view
358 * be bits 31, 4 and 1 of the S view.
360 *data = s->gicd_ctlr & (GICD_CTLR_ARE_S |
361 GICD_CTLR_EN_GRP1NS |
362 GICD_CTLR_RWP);
363 } else {
364 *data = s->gicd_ctlr;
366 return MEMTX_OK;
367 case GICD_TYPER:
369 /* For this implementation:
370 * No1N == 1 (1-of-N SPI interrupts not supported)
371 * A3V == 1 (non-zero values of Affinity level 3 supported)
372 * IDbits == 0xf (we support 16-bit interrupt identifiers)
373 * DVIS == 0 (Direct virtual LPI injection not supported)
374 * LPIS == 0 (LPIs not supported)
375 * MBIS == 0 (message-based SPIs not supported)
376 * SecurityExtn == 1 if security extns supported
377 * CPUNumber == 0 since for us ARE is always 1
378 * ITLinesNumber == (num external irqs / 32) - 1
380 int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
382 *data = (1 << 25) | (1 << 24) | (s->security_extn << 10) |
383 (0xf << 19) | itlinesnumber;
384 return MEMTX_OK;
386 case GICD_IIDR:
387 /* We claim to be an ARM r0p0 with a zero ProductID.
388 * This is the same as an r0p0 GIC-500.
390 *data = gicv3_iidr();
391 return MEMTX_OK;
392 case GICD_STATUSR:
393 /* RAZ/WI for us (this is an optional register and our implementation
394 * does not track RO/WO/reserved violations to report them to the guest)
396 *data = 0;
397 return MEMTX_OK;
398 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f:
400 int irq;
402 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
403 *data = 0;
404 return MEMTX_OK;
406 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */
407 irq = (offset - GICD_IGROUPR) * 8;
408 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
409 *data = 0;
410 return MEMTX_OK;
412 *data = *gic_bmp_ptr32(s->group, irq);
413 return MEMTX_OK;
415 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f:
416 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL,
417 offset - GICD_ISENABLER);
418 return MEMTX_OK;
419 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f:
420 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL,
421 offset - GICD_ICENABLER);
422 return MEMTX_OK;
423 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f:
424 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1,
425 offset - GICD_ISPENDR);
426 return MEMTX_OK;
427 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f:
428 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2,
429 offset - GICD_ICPENDR);
430 return MEMTX_OK;
431 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f:
432 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2,
433 offset - GICD_ISACTIVER);
434 return MEMTX_OK;
435 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f:
436 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2,
437 offset - GICD_ICACTIVER);
438 return MEMTX_OK;
439 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
441 int i, irq = offset - GICD_IPRIORITYR;
442 uint32_t value = 0;
444 for (i = irq + 3; i >= irq; i--, value <<= 8) {
445 value |= gicd_read_ipriorityr(s, attrs, i);
447 *data = value;
448 return MEMTX_OK;
450 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
451 /* RAZ/WI since affinity routing is always enabled */
452 *data = 0;
453 return MEMTX_OK;
454 case GICD_ICFGR ... GICD_ICFGR + 0xff:
456 /* Here only the even bits are used; odd bits are RES0 */
457 int irq = (offset - GICD_ICFGR) * 4;
458 uint32_t value = 0;
460 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
461 *data = 0;
462 return MEMTX_OK;
465 /* Since our edge_trigger bitmap is one bit per irq, we only need
466 * half of the 32-bit word, which we can then spread out
467 * into the odd bits.
469 value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f);
470 value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f);
471 value = extract32(value, (irq & 0x1f) ? 16 : 0, 16);
472 value = half_shuffle32(value) << 1;
473 *data = value;
474 return MEMTX_OK;
476 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff:
478 int irq;
480 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
481 /* RAZ/WI if security disabled, or if
482 * security enabled and this is an NS access
484 *data = 0;
485 return MEMTX_OK;
487 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */
488 irq = (offset - GICD_IGRPMODR) * 8;
489 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
490 *data = 0;
491 return MEMTX_OK;
493 *data = *gic_bmp_ptr32(s->grpmod, irq);
494 return MEMTX_OK;
496 case GICD_NSACR ... GICD_NSACR + 0xff:
498 /* Two bits per interrupt */
499 int irq = (offset - GICD_NSACR) * 4;
501 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
502 *data = 0;
503 return MEMTX_OK;
506 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
507 /* RAZ/WI if security disabled, or if
508 * security enabled and this is an NS access
510 *data = 0;
511 return MEMTX_OK;
514 *data = s->gicd_nsacr[irq / 16];
515 return MEMTX_OK;
517 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
518 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
519 /* RAZ/WI since affinity routing is always enabled */
520 *data = 0;
521 return MEMTX_OK;
522 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
524 uint64_t r;
525 int irq = (offset - GICD_IROUTER) / 8;
527 r = gicd_read_irouter(s, attrs, irq);
528 if (offset & 7) {
529 *data = r >> 32;
530 } else {
531 *data = (uint32_t)r;
533 return MEMTX_OK;
535 case GICD_IDREGS ... GICD_IDREGS + 0x1f:
536 /* ID registers */
537 *data = gicv3_idreg(offset - GICD_IDREGS);
538 return MEMTX_OK;
539 case GICD_SGIR:
540 /* WO registers, return unknown value */
541 qemu_log_mask(LOG_GUEST_ERROR,
542 "%s: invalid guest read from WO register at offset "
543 TARGET_FMT_plx "\n", __func__, offset);
544 *data = 0;
545 return MEMTX_OK;
546 default:
547 return MEMTX_ERROR;
551 static MemTxResult gicd_writel(GICv3State *s, hwaddr offset,
552 uint64_t value, MemTxAttrs attrs)
554 /* Almost all GICv3 distributor registers are 32-bit. Note that
555 * RO registers must ignore writes, not abort.
558 switch (offset) {
559 case GICD_CTLR:
561 uint32_t mask;
562 /* GICv3 5.3.20 */
563 if (s->gicd_ctlr & GICD_CTLR_DS) {
564 /* With only one security state, E1NWF is RAZ/WI, DS is RAO/WI,
565 * ARE is RAO/WI (affinity routing always on), and only
566 * bits 0 and 1 (group enables) are writable.
568 mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS;
569 } else {
570 if (attrs.secure) {
571 /* for secure access:
572 * ARE_NS and ARE_S are RAO/WI (affinity routing always on)
573 * E1NWF is RAZ/WI (we don't support enable-1-of-n-wakeup)
575 * We can only modify bits[2:0] (the group enables).
577 mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL;
578 } else {
579 /* For non secure access ARE_NS is RAO/WI and EnableGrp1
580 * is RES0. The only writable bit is [1] (EnableGrp1A), which
581 * is an alias of the Secure bit [1].
583 mask = GICD_CTLR_EN_GRP1NS;
586 s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask);
587 if (value & mask & GICD_CTLR_DS) {
588 /* We just set DS, so the ARE_NS and EnG1S bits are now RES0.
589 * Note that this is a one-way transition because if DS is set
590 * then it's not writeable, so it can only go back to 0 with a
591 * hardware reset.
593 s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS);
595 gicv3_full_update(s);
596 return MEMTX_OK;
598 case GICD_STATUSR:
599 /* RAZ/WI for our implementation */
600 return MEMTX_OK;
601 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f:
603 int irq;
605 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
606 return MEMTX_OK;
608 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */
609 irq = (offset - GICD_IGROUPR) * 8;
610 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
611 return MEMTX_OK;
613 *gic_bmp_ptr32(s->group, irq) = value;
614 gicv3_update(s, irq, 32);
615 return MEMTX_OK;
617 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f:
618 gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL,
619 offset - GICD_ISENABLER, value);
620 return MEMTX_OK;
621 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f:
622 gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL,
623 offset - GICD_ICENABLER, value);
624 return MEMTX_OK;
625 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f:
626 gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1,
627 offset - GICD_ISPENDR, value);
628 return MEMTX_OK;
629 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f:
630 gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2,
631 offset - GICD_ICPENDR, value);
632 return MEMTX_OK;
633 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f:
634 gicd_write_set_bitmap_reg(s, attrs, s->active, NULL,
635 offset - GICD_ISACTIVER, value);
636 return MEMTX_OK;
637 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f:
638 gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL,
639 offset - GICD_ICACTIVER, value);
640 return MEMTX_OK;
641 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
643 int i, irq = offset - GICD_IPRIORITYR;
645 if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) {
646 return MEMTX_OK;
649 for (i = irq; i < irq + 4; i++, value >>= 8) {
650 gicd_write_ipriorityr(s, attrs, i, value);
652 gicv3_update(s, irq, 4);
653 return MEMTX_OK;
655 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
656 /* RAZ/WI since affinity routing is always enabled */
657 return MEMTX_OK;
658 case GICD_ICFGR ... GICD_ICFGR + 0xff:
660 /* Here only the odd bits are used; even bits are RES0 */
661 int irq = (offset - GICD_ICFGR) * 4;
662 uint32_t mask, oldval;
664 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
665 return MEMTX_OK;
668 /* Since our edge_trigger bitmap is one bit per irq, our input
669 * 32-bits will compress down into 16 bits which we need
670 * to write into the bitmap.
672 value = half_unshuffle32(value >> 1);
673 mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f);
674 if (irq & 0x1f) {
675 value <<= 16;
676 mask &= 0xffff0000U;
677 } else {
678 mask &= 0xffff;
680 oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f));
681 value = (oldval & ~mask) | (value & mask);
682 *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value;
683 return MEMTX_OK;
685 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff:
687 int irq;
689 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
690 /* RAZ/WI if security disabled, or if
691 * security enabled and this is an NS access
693 return MEMTX_OK;
695 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */
696 irq = (offset - GICD_IGRPMODR) * 8;
697 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
698 return MEMTX_OK;
700 *gic_bmp_ptr32(s->grpmod, irq) = value;
701 gicv3_update(s, irq, 32);
702 return MEMTX_OK;
704 case GICD_NSACR ... GICD_NSACR + 0xff:
706 /* Two bits per interrupt */
707 int irq = (offset - GICD_NSACR) * 4;
709 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
710 return MEMTX_OK;
713 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
714 /* RAZ/WI if security disabled, or if
715 * security enabled and this is an NS access
717 return MEMTX_OK;
720 s->gicd_nsacr[irq / 16] = value;
721 /* No update required as this only affects access permission checks */
722 return MEMTX_OK;
724 case GICD_SGIR:
725 /* RES0 if affinity routing is enabled */
726 return MEMTX_OK;
727 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
728 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
729 /* RAZ/WI since affinity routing is always enabled */
730 return MEMTX_OK;
731 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
733 uint64_t r;
734 int irq = (offset - GICD_IROUTER) / 8;
736 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
737 return MEMTX_OK;
740 /* Write half of the 64-bit register */
741 r = gicd_read_irouter(s, attrs, irq);
742 r = deposit64(r, (offset & 7) ? 32 : 0, 32, value);
743 gicd_write_irouter(s, attrs, irq, r);
744 return MEMTX_OK;
746 case GICD_IDREGS ... GICD_IDREGS + 0x1f:
747 case GICD_TYPER:
748 case GICD_IIDR:
749 /* RO registers, ignore the write */
750 qemu_log_mask(LOG_GUEST_ERROR,
751 "%s: invalid guest write to RO register at offset "
752 TARGET_FMT_plx "\n", __func__, offset);
753 return MEMTX_OK;
754 default:
755 return MEMTX_ERROR;
759 static MemTxResult gicd_writell(GICv3State *s, hwaddr offset,
760 uint64_t value, MemTxAttrs attrs)
762 /* Our only 64-bit registers are GICD_IROUTER<n> */
763 int irq;
765 switch (offset) {
766 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
767 irq = (offset - GICD_IROUTER) / 8;
768 gicd_write_irouter(s, attrs, irq, value);
769 return MEMTX_OK;
770 default:
771 return MEMTX_ERROR;
775 static MemTxResult gicd_readll(GICv3State *s, hwaddr offset,
776 uint64_t *data, MemTxAttrs attrs)
778 /* Our only 64-bit registers are GICD_IROUTER<n> */
779 int irq;
781 switch (offset) {
782 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
783 irq = (offset - GICD_IROUTER) / 8;
784 *data = gicd_read_irouter(s, attrs, irq);
785 return MEMTX_OK;
786 default:
787 return MEMTX_ERROR;
791 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
792 unsigned size, MemTxAttrs attrs)
794 GICv3State *s = (GICv3State *)opaque;
795 MemTxResult r;
797 switch (size) {
798 case 1:
799 r = gicd_readb(s, offset, data, attrs);
800 break;
801 case 2:
802 r = gicd_readw(s, offset, data, attrs);
803 break;
804 case 4:
805 r = gicd_readl(s, offset, data, attrs);
806 break;
807 case 8:
808 r = gicd_readll(s, offset, data, attrs);
809 break;
810 default:
811 r = MEMTX_ERROR;
812 break;
815 if (r == MEMTX_ERROR) {
816 qemu_log_mask(LOG_GUEST_ERROR,
817 "%s: invalid guest read at offset " TARGET_FMT_plx
818 "size %u\n", __func__, offset, size);
819 trace_gicv3_dist_badread(offset, size, attrs.secure);
820 } else {
821 trace_gicv3_dist_read(offset, *data, size, attrs.secure);
823 return r;
826 MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data,
827 unsigned size, MemTxAttrs attrs)
829 GICv3State *s = (GICv3State *)opaque;
830 MemTxResult r;
832 switch (size) {
833 case 1:
834 r = gicd_writeb(s, offset, data, attrs);
835 break;
836 case 2:
837 r = gicd_writew(s, offset, data, attrs);
838 break;
839 case 4:
840 r = gicd_writel(s, offset, data, attrs);
841 break;
842 case 8:
843 r = gicd_writell(s, offset, data, attrs);
844 break;
845 default:
846 r = MEMTX_ERROR;
847 break;
850 if (r == MEMTX_ERROR) {
851 qemu_log_mask(LOG_GUEST_ERROR,
852 "%s: invalid guest write at offset " TARGET_FMT_plx
853 "size %u\n", __func__, offset, size);
854 trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
855 } else {
856 trace_gicv3_dist_write(offset, data, size, attrs.secure);
858 return r;
861 void gicv3_dist_set_irq(GICv3State *s, int irq, int level)
863 /* Update distributor state for a change in an external SPI input line */
864 if (level == gicv3_gicd_level_test(s, irq)) {
865 return;
868 trace_gicv3_dist_set_irq(irq, level);
870 gicv3_gicd_level_replace(s, irq, level);
872 if (level) {
873 /* 0->1 edges latch the pending bit for edge-triggered interrupts */
874 if (gicv3_gicd_edge_trigger_test(s, irq)) {
875 gicv3_gicd_pending_set(s, irq);
879 gicv3_update(s, irq, 1);