4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
23 #include "qemu-common.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
30 #include "hyperv-proto.h"
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "hw/pci/msix.h"
46 #include "migration/blocker.h"
47 #include "exec/memattrs.h"
53 #define DPRINTF(fmt, ...) \
54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #define DPRINTF(fmt, ...) \
60 #define MSR_KVM_WALL_CLOCK 0x11
61 #define MSR_KVM_SYSTEM_TIME 0x12
63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65 #define MSR_BUF_SIZE 4096
67 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR
),
69 KVM_CAP_INFO(EXT_CPUID
),
70 KVM_CAP_INFO(MP_STATE
),
74 static bool has_msr_star
;
75 static bool has_msr_hsave_pa
;
76 static bool has_msr_tsc_aux
;
77 static bool has_msr_tsc_adjust
;
78 static bool has_msr_tsc_deadline
;
79 static bool has_msr_feature_control
;
80 static bool has_msr_misc_enable
;
81 static bool has_msr_smbase
;
82 static bool has_msr_bndcfgs
;
83 static int lm_capable_kernel
;
84 static bool has_msr_hv_hypercall
;
85 static bool has_msr_hv_crash
;
86 static bool has_msr_hv_reset
;
87 static bool has_msr_hv_vpindex
;
88 static bool hv_vpindex_settable
;
89 static bool has_msr_hv_runtime
;
90 static bool has_msr_hv_synic
;
91 static bool has_msr_hv_stimer
;
92 static bool has_msr_hv_frequencies
;
93 static bool has_msr_hv_reenlightenment
;
94 static bool has_msr_xss
;
95 static bool has_msr_spec_ctrl
;
96 static bool has_msr_virt_ssbd
;
97 static bool has_msr_smi_count
;
99 static uint32_t has_architectural_pmu_version
;
100 static uint32_t num_architectural_pmu_gp_counters
;
101 static uint32_t num_architectural_pmu_fixed_counters
;
103 static int has_xsave
;
105 static int has_pit_state2
;
107 static bool has_msr_mcg_ext_ctl
;
109 static struct kvm_cpuid2
*cpuid_cache
;
111 int kvm_has_pit_state2(void)
113 return has_pit_state2
;
116 bool kvm_has_smm(void)
118 return kvm_check_extension(kvm_state
, KVM_CAP_X86_SMM
);
121 bool kvm_has_adjust_clock_stable(void)
123 int ret
= kvm_check_extension(kvm_state
, KVM_CAP_ADJUST_CLOCK
);
125 return (ret
== KVM_CLOCK_TSC_STABLE
);
128 bool kvm_allows_irq0_override(void)
130 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
133 static bool kvm_x2apic_api_set_flags(uint64_t flags
)
135 KVMState
*s
= KVM_STATE(current_machine
->accelerator
);
137 return !kvm_vm_enable_cap(s
, KVM_CAP_X2APIC_API
, 0, flags
);
140 #define MEMORIZE(fn, _result) \
142 static bool _memorized; \
151 static bool has_x2apic_api
;
153 bool kvm_has_x2apic_api(void)
155 return has_x2apic_api
;
158 bool kvm_enable_x2apic(void)
161 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS
|
162 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK
),
166 bool kvm_hv_vpindex_settable(void)
168 return hv_vpindex_settable
;
171 static int kvm_get_tsc(CPUState
*cs
)
173 X86CPU
*cpu
= X86_CPU(cs
);
174 CPUX86State
*env
= &cpu
->env
;
176 struct kvm_msrs info
;
177 struct kvm_msr_entry entries
[1];
181 if (env
->tsc_valid
) {
185 msr_data
.info
.nmsrs
= 1;
186 msr_data
.entries
[0].index
= MSR_IA32_TSC
;
187 env
->tsc_valid
= !runstate_is_running();
189 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
195 env
->tsc
= msr_data
.entries
[0].data
;
199 static inline void do_kvm_synchronize_tsc(CPUState
*cpu
, run_on_cpu_data arg
)
204 void kvm_synchronize_all_tsc(void)
210 run_on_cpu(cpu
, do_kvm_synchronize_tsc
, RUN_ON_CPU_NULL
);
215 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
217 struct kvm_cpuid2
*cpuid
;
220 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
221 cpuid
= g_malloc0(size
);
223 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
224 if (r
== 0 && cpuid
->nent
>= max
) {
232 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
240 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
243 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
245 struct kvm_cpuid2
*cpuid
;
248 if (cpuid_cache
!= NULL
) {
251 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
258 static const struct kvm_para_features
{
261 } para_features
[] = {
262 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
263 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
264 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
265 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
268 static int get_para_features(KVMState
*s
)
272 for (i
= 0; i
< ARRAY_SIZE(para_features
); i
++) {
273 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
274 features
|= (1 << para_features
[i
].feature
);
281 static bool host_tsx_blacklisted(void)
283 int family
, model
, stepping
;\
284 char vendor
[CPUID_VENDOR_SZ
+ 1];
286 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
288 /* Check if we are running on a Haswell host known to have broken TSX */
289 return !strcmp(vendor
, CPUID_VENDOR_INTEL
) &&
291 ((model
== 63 && stepping
< 4) ||
292 model
== 60 || model
== 69 || model
== 70);
295 /* Returns the value for a specific register on the cpuid entry
297 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
317 /* Find matching entry for function/index on kvm_cpuid2 struct
319 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
324 for (i
= 0; i
< cpuid
->nent
; ++i
) {
325 if (cpuid
->entries
[i
].function
== function
&&
326 cpuid
->entries
[i
].index
== index
) {
327 return &cpuid
->entries
[i
];
334 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
335 uint32_t index
, int reg
)
337 struct kvm_cpuid2
*cpuid
;
339 uint32_t cpuid_1_edx
;
342 cpuid
= get_supported_cpuid(s
);
344 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
347 ret
= cpuid_entry_get_reg(entry
, reg
);
350 /* Fixups for the data returned by KVM, below */
352 if (function
== 1 && reg
== R_EDX
) {
353 /* KVM before 2.6.30 misreports the following features */
354 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
355 } else if (function
== 1 && reg
== R_ECX
) {
356 /* We can set the hypervisor flag, even if KVM does not return it on
357 * GET_SUPPORTED_CPUID
359 ret
|= CPUID_EXT_HYPERVISOR
;
360 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
361 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
362 * and the irqchip is in the kernel.
364 if (kvm_irqchip_in_kernel() &&
365 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
366 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
369 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
370 * without the in-kernel irqchip
372 if (!kvm_irqchip_in_kernel()) {
373 ret
&= ~CPUID_EXT_X2APIC
;
377 int disable_exits
= kvm_check_extension(s
,
378 KVM_CAP_X86_DISABLE_EXITS
);
380 if (disable_exits
& KVM_X86_DISABLE_EXITS_MWAIT
) {
381 ret
|= CPUID_EXT_MONITOR
;
384 } else if (function
== 6 && reg
== R_EAX
) {
385 ret
|= CPUID_6_EAX_ARAT
; /* safe to allow because of emulated APIC */
386 } else if (function
== 7 && index
== 0 && reg
== R_EBX
) {
387 if (host_tsx_blacklisted()) {
388 ret
&= ~(CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_HLE
);
390 } else if (function
== 0x80000001 && reg
== R_ECX
) {
392 * It's safe to enable TOPOEXT even if it's not returned by
393 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
394 * us to keep CPU models including TOPOEXT runnable on older kernels.
396 ret
|= CPUID_EXT3_TOPOEXT
;
397 } else if (function
== 0x80000001 && reg
== R_EDX
) {
398 /* On Intel, kvm returns cpuid according to the Intel spec,
399 * so add missing bits according to the AMD spec:
401 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
402 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
403 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EAX
) {
404 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
405 * be enabled without the in-kernel irqchip
407 if (!kvm_irqchip_in_kernel()) {
408 ret
&= ~(1U << KVM_FEATURE_PV_UNHALT
);
410 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EDX
) {
411 ret
|= 1U << KVM_HINTS_REALTIME
;
415 /* fallback for older kernels */
416 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
417 ret
= get_para_features(s
);
423 typedef struct HWPoisonPage
{
425 QLIST_ENTRY(HWPoisonPage
) list
;
428 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
429 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
431 static void kvm_unpoison_all(void *param
)
433 HWPoisonPage
*page
, *next_page
;
435 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
436 QLIST_REMOVE(page
, list
);
437 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
442 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
446 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
447 if (page
->ram_addr
== ram_addr
) {
451 page
= g_new(HWPoisonPage
, 1);
452 page
->ram_addr
= ram_addr
;
453 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
456 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
461 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
464 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
469 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
471 CPUState
*cs
= CPU(cpu
);
472 CPUX86State
*env
= &cpu
->env
;
473 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
474 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
475 uint64_t mcg_status
= MCG_STATUS_MCIP
;
478 if (code
== BUS_MCEERR_AR
) {
479 status
|= MCI_STATUS_AR
| 0x134;
480 mcg_status
|= MCG_STATUS_EIPV
;
483 mcg_status
|= MCG_STATUS_RIPV
;
486 flags
= cpu_x86_support_mca_broadcast(env
) ? MCE_INJECT_BROADCAST
: 0;
487 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
488 * guest kernel back into env->mcg_ext_ctl.
490 cpu_synchronize_state(cs
);
491 if (env
->mcg_ext_ctl
& MCG_EXT_CTL_LMCE_EN
) {
492 mcg_status
|= MCG_STATUS_LMCE
;
496 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
497 (MCM_ADDR_PHYS
<< 6) | 0xc, flags
);
500 static void hardware_memory_error(void)
502 fprintf(stderr
, "Hardware memory error!\n");
506 void kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
508 X86CPU
*cpu
= X86_CPU(c
);
509 CPUX86State
*env
= &cpu
->env
;
513 /* If we get an action required MCE, it has been injected by KVM
514 * while the VM was running. An action optional MCE instead should
515 * be coming from the main thread, which qemu_init_sigbus identifies
516 * as the "early kill" thread.
518 assert(code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
);
520 if ((env
->mcg_cap
& MCG_SER_P
) && addr
) {
521 ram_addr
= qemu_ram_addr_from_host(addr
);
522 if (ram_addr
!= RAM_ADDR_INVALID
&&
523 kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
524 kvm_hwpoison_page_add(ram_addr
);
525 kvm_mce_inject(cpu
, paddr
, code
);
529 fprintf(stderr
, "Hardware memory error for memory used by "
530 "QEMU itself instead of guest system!\n");
533 if (code
== BUS_MCEERR_AR
) {
534 hardware_memory_error();
537 /* Hope we are lucky for AO MCE */
540 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
542 CPUX86State
*env
= &cpu
->env
;
544 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
545 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
546 struct kvm_x86_mce mce
;
548 env
->exception_injected
= -1;
551 * There must be at least one bank in use if an MCE is pending.
552 * Find it and use its values for the event injection.
554 for (bank
= 0; bank
< bank_num
; bank
++) {
555 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
559 assert(bank
< bank_num
);
562 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
563 mce
.mcg_status
= env
->mcg_status
;
564 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
565 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
567 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
572 static void cpu_update_state(void *opaque
, int running
, RunState state
)
574 CPUX86State
*env
= opaque
;
577 env
->tsc_valid
= false;
581 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
583 X86CPU
*cpu
= X86_CPU(cs
);
587 #ifndef KVM_CPUID_SIGNATURE_NEXT
588 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
591 static bool hyperv_hypercall_available(X86CPU
*cpu
)
593 return cpu
->hyperv_vapic
||
594 (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
);
597 static bool hyperv_enabled(X86CPU
*cpu
)
599 CPUState
*cs
= CPU(cpu
);
600 return kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0 &&
601 (hyperv_hypercall_available(cpu
) ||
603 cpu
->hyperv_relaxed_timing
||
606 cpu
->hyperv_vpindex
||
607 cpu
->hyperv_runtime
||
609 cpu
->hyperv_stimer
||
610 cpu
->hyperv_reenlightenment
||
611 cpu
->hyperv_tlbflush
);
614 static int kvm_arch_set_tsc_khz(CPUState
*cs
)
616 X86CPU
*cpu
= X86_CPU(cs
);
617 CPUX86State
*env
= &cpu
->env
;
624 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
) ?
625 kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
) :
628 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
629 * TSC frequency doesn't match the one we want.
631 int cur_freq
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
632 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
634 if (cur_freq
<= 0 || cur_freq
!= env
->tsc_khz
) {
635 warn_report("TSC frequency mismatch between "
636 "VM (%" PRId64
" kHz) and host (%d kHz), "
637 "and TSC scaling unavailable",
638 env
->tsc_khz
, cur_freq
);
646 static bool tsc_is_stable_and_known(CPUX86State
*env
)
651 return (env
->features
[FEAT_8000_0007_EDX
] & CPUID_APM_INVTSC
)
652 || env
->user_tsc_khz
;
655 static int hyperv_handle_properties(CPUState
*cs
)
657 X86CPU
*cpu
= X86_CPU(cs
);
658 CPUX86State
*env
= &cpu
->env
;
660 if (cpu
->hyperv_relaxed_timing
) {
661 env
->features
[FEAT_HYPERV_EAX
] |= HV_HYPERCALL_AVAILABLE
;
663 if (cpu
->hyperv_vapic
) {
664 env
->features
[FEAT_HYPERV_EAX
] |= HV_HYPERCALL_AVAILABLE
;
665 env
->features
[FEAT_HYPERV_EAX
] |= HV_APIC_ACCESS_AVAILABLE
;
667 if (cpu
->hyperv_time
) {
668 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_TIME
) <= 0) {
669 fprintf(stderr
, "Hyper-V clocksources "
670 "(requested by 'hv-time' cpu flag) "
671 "are not supported by kernel\n");
674 env
->features
[FEAT_HYPERV_EAX
] |= HV_HYPERCALL_AVAILABLE
;
675 env
->features
[FEAT_HYPERV_EAX
] |= HV_TIME_REF_COUNT_AVAILABLE
;
676 env
->features
[FEAT_HYPERV_EAX
] |= HV_REFERENCE_TSC_AVAILABLE
;
678 if (cpu
->hyperv_frequencies
) {
679 if (!has_msr_hv_frequencies
) {
680 fprintf(stderr
, "Hyper-V frequency MSRs "
681 "(requested by 'hv-frequencies' cpu flag) "
682 "are not supported by kernel\n");
685 env
->features
[FEAT_HYPERV_EAX
] |= HV_ACCESS_FREQUENCY_MSRS
;
686 env
->features
[FEAT_HYPERV_EDX
] |= HV_FREQUENCY_MSRS_AVAILABLE
;
688 if (cpu
->hyperv_crash
) {
689 if (!has_msr_hv_crash
) {
690 fprintf(stderr
, "Hyper-V crash MSRs "
691 "(requested by 'hv-crash' cpu flag) "
692 "are not supported by kernel\n");
695 env
->features
[FEAT_HYPERV_EDX
] |= HV_GUEST_CRASH_MSR_AVAILABLE
;
697 if (cpu
->hyperv_reenlightenment
) {
698 if (!has_msr_hv_reenlightenment
) {
700 "Hyper-V Reenlightenment MSRs "
701 "(requested by 'hv-reenlightenment' cpu flag) "
702 "are not supported by kernel\n");
705 env
->features
[FEAT_HYPERV_EAX
] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL
;
707 env
->features
[FEAT_HYPERV_EDX
] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
708 if (cpu
->hyperv_reset
) {
709 if (!has_msr_hv_reset
) {
710 fprintf(stderr
, "Hyper-V reset MSR "
711 "(requested by 'hv-reset' cpu flag) "
712 "is not supported by kernel\n");
715 env
->features
[FEAT_HYPERV_EAX
] |= HV_RESET_AVAILABLE
;
717 if (cpu
->hyperv_vpindex
) {
718 if (!has_msr_hv_vpindex
) {
719 fprintf(stderr
, "Hyper-V VP_INDEX MSR "
720 "(requested by 'hv-vpindex' cpu flag) "
721 "is not supported by kernel\n");
724 env
->features
[FEAT_HYPERV_EAX
] |= HV_VP_INDEX_AVAILABLE
;
726 if (cpu
->hyperv_runtime
) {
727 if (!has_msr_hv_runtime
) {
728 fprintf(stderr
, "Hyper-V VP_RUNTIME MSR "
729 "(requested by 'hv-runtime' cpu flag) "
730 "is not supported by kernel\n");
733 env
->features
[FEAT_HYPERV_EAX
] |= HV_VP_RUNTIME_AVAILABLE
;
735 if (cpu
->hyperv_synic
) {
736 if (!has_msr_hv_synic
||
737 kvm_vcpu_enable_cap(cs
, KVM_CAP_HYPERV_SYNIC
, 0)) {
738 fprintf(stderr
, "Hyper-V SynIC is not supported by kernel\n");
742 env
->features
[FEAT_HYPERV_EAX
] |= HV_SYNIC_AVAILABLE
;
744 if (cpu
->hyperv_stimer
) {
745 if (!has_msr_hv_stimer
) {
746 fprintf(stderr
, "Hyper-V timers aren't supported by kernel\n");
749 env
->features
[FEAT_HYPERV_EAX
] |= HV_SYNTIMERS_AVAILABLE
;
754 static int hyperv_init_vcpu(X86CPU
*cpu
)
756 if (cpu
->hyperv_vpindex
&& !hv_vpindex_settable
) {
758 * the kernel doesn't support setting vp_index; assert that its value
763 struct kvm_msrs info
;
764 struct kvm_msr_entry entries
[1];
767 .entries
[0].index
= HV_X64_MSR_VP_INDEX
,
770 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
776 if (msr_data
.entries
[0].data
!= hyperv_vp_index(cpu
)) {
777 error_report("kernel's vp_index != QEMU's vp_index");
785 static Error
*invtsc_mig_blocker
;
787 #define KVM_MAX_CPUID_ENTRIES 100
789 int kvm_arch_init_vcpu(CPUState
*cs
)
792 struct kvm_cpuid2 cpuid
;
793 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
794 } QEMU_PACKED cpuid_data
;
795 X86CPU
*cpu
= X86_CPU(cs
);
796 CPUX86State
*env
= &cpu
->env
;
797 uint32_t limit
, i
, j
, cpuid_i
;
799 struct kvm_cpuid_entry2
*c
;
800 uint32_t signature
[3];
801 int kvm_base
= KVM_CPUID_SIGNATURE
;
803 Error
*local_err
= NULL
;
805 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
809 r
= kvm_arch_set_tsc_khz(cs
);
814 /* vcpu's TSC frequency is either specified by user, or following
815 * the value used by KVM if the former is not present. In the
816 * latter case, we query it from KVM and record in env->tsc_khz,
817 * so that vcpu's TSC frequency can be migrated later via this field.
820 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
821 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
828 /* Paravirtualization CPUIDs */
829 if (hyperv_enabled(cpu
)) {
830 c
= &cpuid_data
.entries
[cpuid_i
++];
831 c
->function
= HV_CPUID_VENDOR_AND_MAX_FUNCTIONS
;
832 if (!cpu
->hyperv_vendor_id
) {
833 memcpy(signature
, "Microsoft Hv", 12);
835 size_t len
= strlen(cpu
->hyperv_vendor_id
);
838 error_report("hv-vendor-id truncated to 12 characters");
841 memset(signature
, 0, 12);
842 memcpy(signature
, cpu
->hyperv_vendor_id
, len
);
844 c
->eax
= HV_CPUID_MIN
;
845 c
->ebx
= signature
[0];
846 c
->ecx
= signature
[1];
847 c
->edx
= signature
[2];
849 c
= &cpuid_data
.entries
[cpuid_i
++];
850 c
->function
= HV_CPUID_INTERFACE
;
851 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
852 c
->eax
= signature
[0];
857 c
= &cpuid_data
.entries
[cpuid_i
++];
858 c
->function
= HV_CPUID_VERSION
;
862 c
= &cpuid_data
.entries
[cpuid_i
++];
863 c
->function
= HV_CPUID_FEATURES
;
864 r
= hyperv_handle_properties(cs
);
868 c
->eax
= env
->features
[FEAT_HYPERV_EAX
];
869 c
->ebx
= env
->features
[FEAT_HYPERV_EBX
];
870 c
->edx
= env
->features
[FEAT_HYPERV_EDX
];
872 c
= &cpuid_data
.entries
[cpuid_i
++];
873 c
->function
= HV_CPUID_ENLIGHTMENT_INFO
;
874 if (cpu
->hyperv_relaxed_timing
) {
875 c
->eax
|= HV_RELAXED_TIMING_RECOMMENDED
;
877 if (cpu
->hyperv_vapic
) {
878 c
->eax
|= HV_APIC_ACCESS_RECOMMENDED
;
880 if (cpu
->hyperv_tlbflush
) {
881 if (kvm_check_extension(cs
->kvm_state
,
882 KVM_CAP_HYPERV_TLBFLUSH
) <= 0) {
883 fprintf(stderr
, "Hyper-V TLB flush support "
884 "(requested by 'hv-tlbflush' cpu flag) "
885 " is not supported by kernel\n");
888 c
->eax
|= HV_REMOTE_TLB_FLUSH_RECOMMENDED
;
889 c
->eax
|= HV_EX_PROCESSOR_MASKS_RECOMMENDED
;
892 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
894 c
= &cpuid_data
.entries
[cpuid_i
++];
895 c
->function
= HV_CPUID_IMPLEMENT_LIMITS
;
897 c
->eax
= cpu
->hv_max_vps
;
900 kvm_base
= KVM_CPUID_SIGNATURE_NEXT
;
901 has_msr_hv_hypercall
= true;
904 if (cpu
->expose_kvm
) {
905 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
906 c
= &cpuid_data
.entries
[cpuid_i
++];
907 c
->function
= KVM_CPUID_SIGNATURE
| kvm_base
;
908 c
->eax
= KVM_CPUID_FEATURES
| kvm_base
;
909 c
->ebx
= signature
[0];
910 c
->ecx
= signature
[1];
911 c
->edx
= signature
[2];
913 c
= &cpuid_data
.entries
[cpuid_i
++];
914 c
->function
= KVM_CPUID_FEATURES
| kvm_base
;
915 c
->eax
= env
->features
[FEAT_KVM
];
916 c
->edx
= env
->features
[FEAT_KVM_HINTS
];
919 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
921 for (i
= 0; i
<= limit
; i
++) {
922 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
923 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
926 c
= &cpuid_data
.entries
[cpuid_i
++];
927 assert(cpuid_i
< 100);
931 /* Keep reading function 2 till all the input is received */
935 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
936 KVM_CPUID_FLAG_STATE_READ_NEXT
;
937 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
938 times
= c
->eax
& 0xff;
940 for (j
= 1; j
< times
; ++j
) {
941 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
942 fprintf(stderr
, "cpuid_data is full, no space for "
943 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
946 c
= &cpuid_data
.entries
[cpuid_i
++];
948 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
949 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
957 if (i
== 0xd && j
== 64) {
961 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
963 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
965 if (i
== 4 && c
->eax
== 0) {
968 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
971 if (i
== 0xd && c
->eax
== 0) {
974 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
975 fprintf(stderr
, "cpuid_data is full, no space for "
976 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
979 c
= &cpuid_data
.entries
[cpuid_i
++];
987 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
988 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
991 for (j
= 1; j
<= times
; ++j
) {
992 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
993 fprintf(stderr
, "cpuid_data is full, no space for "
994 "cpuid(eax:0x14,ecx:0x%x)\n", j
);
997 c
= &cpuid_data
.entries
[cpuid_i
++];
1000 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1001 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1008 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1013 if (limit
>= 0x0a) {
1016 cpu_x86_cpuid(env
, 0x0a, 0, &eax
, &unused
, &unused
, &edx
);
1018 has_architectural_pmu_version
= eax
& 0xff;
1019 if (has_architectural_pmu_version
> 0) {
1020 num_architectural_pmu_gp_counters
= (eax
& 0xff00) >> 8;
1022 /* Shouldn't be more than 32, since that's the number of bits
1023 * available in EBX to tell us _which_ counters are available.
1026 if (num_architectural_pmu_gp_counters
> MAX_GP_COUNTERS
) {
1027 num_architectural_pmu_gp_counters
= MAX_GP_COUNTERS
;
1030 if (has_architectural_pmu_version
> 1) {
1031 num_architectural_pmu_fixed_counters
= edx
& 0x1f;
1033 if (num_architectural_pmu_fixed_counters
> MAX_FIXED_COUNTERS
) {
1034 num_architectural_pmu_fixed_counters
= MAX_FIXED_COUNTERS
;
1040 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
1042 for (i
= 0x80000000; i
<= limit
; i
++) {
1043 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1044 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
1047 c
= &cpuid_data
.entries
[cpuid_i
++];
1048 assert(cpuid_i
< 100);
1052 /* Query for all AMD cache information leaves */
1053 for (j
= 0; ; j
++) {
1055 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1057 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1062 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1063 fprintf(stderr
, "cpuid_data is full, no space for "
1064 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1067 c
= &cpuid_data
.entries
[cpuid_i
++];
1073 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1078 /* Call Centaur's CPUID instructions they are supported. */
1079 if (env
->cpuid_xlevel2
> 0) {
1080 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
1082 for (i
= 0xC0000000; i
<= limit
; i
++) {
1083 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1084 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
1087 c
= &cpuid_data
.entries
[cpuid_i
++];
1091 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1095 cpuid_data
.cpuid
.nent
= cpuid_i
;
1097 if (((env
->cpuid_version
>> 8)&0xF) >= 6
1098 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
1099 (CPUID_MCE
| CPUID_MCA
)
1100 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
1101 uint64_t mcg_cap
, unsupported_caps
;
1105 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
1107 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
1111 if (banks
< (env
->mcg_cap
& MCG_CAP_BANKS_MASK
)) {
1112 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1113 (int)(env
->mcg_cap
& MCG_CAP_BANKS_MASK
), banks
);
1117 unsupported_caps
= env
->mcg_cap
& ~(mcg_cap
| MCG_CAP_BANKS_MASK
);
1118 if (unsupported_caps
) {
1119 if (unsupported_caps
& MCG_LMCE_P
) {
1120 error_report("kvm: LMCE not supported");
1123 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64
,
1127 env
->mcg_cap
&= mcg_cap
| MCG_CAP_BANKS_MASK
;
1128 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &env
->mcg_cap
);
1130 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
1135 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
1137 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
1139 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
1140 !!(c
->ecx
& CPUID_EXT_SMX
);
1143 if (env
->mcg_cap
& MCG_LMCE_P
) {
1144 has_msr_mcg_ext_ctl
= has_msr_feature_control
= true;
1147 if (!env
->user_tsc_khz
) {
1148 if ((env
->features
[FEAT_8000_0007_EDX
] & CPUID_APM_INVTSC
) &&
1149 invtsc_mig_blocker
== NULL
) {
1151 error_setg(&invtsc_mig_blocker
,
1152 "State blocked by non-migratable CPU device"
1154 r
= migrate_add_blocker(invtsc_mig_blocker
, &local_err
);
1156 error_report_err(local_err
);
1157 error_free(invtsc_mig_blocker
);
1161 vmstate_x86_cpu
.unmigratable
= 1;
1165 if (cpu
->vmware_cpuid_freq
1166 /* Guests depend on 0x40000000 to detect this feature, so only expose
1167 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1169 && kvm_base
== KVM_CPUID_SIGNATURE
1170 /* TSC clock must be stable and known for this feature. */
1171 && tsc_is_stable_and_known(env
)) {
1173 c
= &cpuid_data
.entries
[cpuid_i
++];
1174 c
->function
= KVM_CPUID_SIGNATURE
| 0x10;
1175 c
->eax
= env
->tsc_khz
;
1176 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1177 * APIC_BUS_CYCLE_NS */
1179 c
->ecx
= c
->edx
= 0;
1181 c
= cpuid_find_entry(&cpuid_data
.cpuid
, kvm_base
, 0);
1182 c
->eax
= MAX(c
->eax
, KVM_CPUID_SIGNATURE
| 0x10);
1185 cpuid_data
.cpuid
.nent
= cpuid_i
;
1187 cpuid_data
.cpuid
.padding
= 0;
1188 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
1194 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
1196 cpu
->kvm_msr_buf
= g_malloc0(MSR_BUF_SIZE
);
1198 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_RDTSCP
)) {
1199 has_msr_tsc_aux
= false;
1202 r
= hyperv_init_vcpu(cpu
);
1210 migrate_del_blocker(invtsc_mig_blocker
);
1214 void kvm_arch_reset_vcpu(X86CPU
*cpu
)
1216 CPUX86State
*env
= &cpu
->env
;
1219 if (kvm_irqchip_in_kernel()) {
1220 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
1221 KVM_MP_STATE_UNINITIALIZED
;
1223 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
1226 if (cpu
->hyperv_synic
) {
1228 for (i
= 0; i
< ARRAY_SIZE(env
->msr_hv_synic_sint
); i
++) {
1229 env
->msr_hv_synic_sint
[i
] = HV_SINT_MASKED
;
1234 void kvm_arch_do_init_vcpu(X86CPU
*cpu
)
1236 CPUX86State
*env
= &cpu
->env
;
1238 /* APs get directly into wait-for-SIPI state. */
1239 if (env
->mp_state
== KVM_MP_STATE_UNINITIALIZED
) {
1240 env
->mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1244 static int kvm_get_supported_msrs(KVMState
*s
)
1246 static int kvm_supported_msrs
;
1250 if (kvm_supported_msrs
== 0) {
1251 struct kvm_msr_list msr_list
, *kvm_msr_list
;
1253 kvm_supported_msrs
= -1;
1255 /* Obtain MSR list from KVM. These are the MSRs that we must
1258 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
1259 if (ret
< 0 && ret
!= -E2BIG
) {
1262 /* Old kernel modules had a bug and could write beyond the provided
1263 memory. Allocate at least a safe amount of 1K. */
1264 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
1266 sizeof(msr_list
.indices
[0])));
1268 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
1269 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
1273 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
1274 switch (kvm_msr_list
->indices
[i
]) {
1276 has_msr_star
= true;
1278 case MSR_VM_HSAVE_PA
:
1279 has_msr_hsave_pa
= true;
1282 has_msr_tsc_aux
= true;
1284 case MSR_TSC_ADJUST
:
1285 has_msr_tsc_adjust
= true;
1287 case MSR_IA32_TSCDEADLINE
:
1288 has_msr_tsc_deadline
= true;
1290 case MSR_IA32_SMBASE
:
1291 has_msr_smbase
= true;
1294 has_msr_smi_count
= true;
1296 case MSR_IA32_MISC_ENABLE
:
1297 has_msr_misc_enable
= true;
1299 case MSR_IA32_BNDCFGS
:
1300 has_msr_bndcfgs
= true;
1305 case HV_X64_MSR_CRASH_CTL
:
1306 has_msr_hv_crash
= true;
1308 case HV_X64_MSR_RESET
:
1309 has_msr_hv_reset
= true;
1311 case HV_X64_MSR_VP_INDEX
:
1312 has_msr_hv_vpindex
= true;
1314 case HV_X64_MSR_VP_RUNTIME
:
1315 has_msr_hv_runtime
= true;
1317 case HV_X64_MSR_SCONTROL
:
1318 has_msr_hv_synic
= true;
1320 case HV_X64_MSR_STIMER0_CONFIG
:
1321 has_msr_hv_stimer
= true;
1323 case HV_X64_MSR_TSC_FREQUENCY
:
1324 has_msr_hv_frequencies
= true;
1326 case HV_X64_MSR_REENLIGHTENMENT_CONTROL
:
1327 has_msr_hv_reenlightenment
= true;
1329 case MSR_IA32_SPEC_CTRL
:
1330 has_msr_spec_ctrl
= true;
1333 has_msr_virt_ssbd
= true;
1339 g_free(kvm_msr_list
);
1345 static Notifier smram_machine_done
;
1346 static KVMMemoryListener smram_listener
;
1347 static AddressSpace smram_address_space
;
1348 static MemoryRegion smram_as_root
;
1349 static MemoryRegion smram_as_mem
;
1351 static void register_smram_listener(Notifier
*n
, void *unused
)
1353 MemoryRegion
*smram
=
1354 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
1356 /* Outer container... */
1357 memory_region_init(&smram_as_root
, OBJECT(kvm_state
), "mem-container-smram", ~0ull);
1358 memory_region_set_enabled(&smram_as_root
, true);
1360 /* ... with two regions inside: normal system memory with low
1363 memory_region_init_alias(&smram_as_mem
, OBJECT(kvm_state
), "mem-smram",
1364 get_system_memory(), 0, ~0ull);
1365 memory_region_add_subregion_overlap(&smram_as_root
, 0, &smram_as_mem
, 0);
1366 memory_region_set_enabled(&smram_as_mem
, true);
1369 /* ... SMRAM with higher priority */
1370 memory_region_add_subregion_overlap(&smram_as_root
, 0, smram
, 10);
1371 memory_region_set_enabled(smram
, true);
1374 address_space_init(&smram_address_space
, &smram_as_root
, "KVM-SMRAM");
1375 kvm_memory_listener_register(kvm_state
, &smram_listener
,
1376 &smram_address_space
, 1);
1379 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
1381 uint64_t identity_base
= 0xfffbc000;
1382 uint64_t shadow_mem
;
1384 struct utsname utsname
;
1386 #ifdef KVM_CAP_XSAVE
1387 has_xsave
= kvm_check_extension(s
, KVM_CAP_XSAVE
);
1391 has_xcrs
= kvm_check_extension(s
, KVM_CAP_XCRS
);
1394 #ifdef KVM_CAP_PIT_STATE2
1395 has_pit_state2
= kvm_check_extension(s
, KVM_CAP_PIT_STATE2
);
1398 hv_vpindex_settable
= kvm_check_extension(s
, KVM_CAP_HYPERV_VP_INDEX
);
1400 ret
= kvm_get_supported_msrs(s
);
1406 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
1409 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1410 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1411 * Since these must be part of guest physical memory, we need to allocate
1412 * them, both by setting their start addresses in the kernel and by
1413 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1415 * Older KVM versions may not support setting the identity map base. In
1416 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1419 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
1420 /* Allows up to 16M BIOSes. */
1421 identity_base
= 0xfeffc000;
1423 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
1429 /* Set TSS base one page after EPT identity map. */
1430 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
1435 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1436 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
1438 fprintf(stderr
, "e820_add_entry() table is full\n");
1441 qemu_register_reset(kvm_unpoison_all
, NULL
);
1443 shadow_mem
= machine_kvm_shadow_mem(ms
);
1444 if (shadow_mem
!= -1) {
1446 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
1452 if (kvm_check_extension(s
, KVM_CAP_X86_SMM
) &&
1453 object_dynamic_cast(OBJECT(ms
), TYPE_PC_MACHINE
) &&
1454 pc_machine_is_smm_enabled(PC_MACHINE(ms
))) {
1455 smram_machine_done
.notify
= register_smram_listener
;
1456 qemu_add_machine_init_done_notifier(&smram_machine_done
);
1459 if (enable_cpu_pm
) {
1460 int disable_exits
= kvm_check_extension(s
, KVM_CAP_X86_DISABLE_EXITS
);
1463 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1464 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1465 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1467 if (disable_exits
) {
1468 disable_exits
&= (KVM_X86_DISABLE_EXITS_MWAIT
|
1469 KVM_X86_DISABLE_EXITS_HLT
|
1470 KVM_X86_DISABLE_EXITS_PAUSE
);
1473 ret
= kvm_vm_enable_cap(s
, KVM_CAP_X86_DISABLE_EXITS
, 0,
1476 error_report("kvm: guest stopping CPU not supported: %s",
1484 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
1486 lhs
->selector
= rhs
->selector
;
1487 lhs
->base
= rhs
->base
;
1488 lhs
->limit
= rhs
->limit
;
1500 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
1502 unsigned flags
= rhs
->flags
;
1503 lhs
->selector
= rhs
->selector
;
1504 lhs
->base
= rhs
->base
;
1505 lhs
->limit
= rhs
->limit
;
1506 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
1507 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
1508 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
1509 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
1510 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
1511 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
1512 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
1513 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
1514 lhs
->unusable
= !lhs
->present
;
1518 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
1520 lhs
->selector
= rhs
->selector
;
1521 lhs
->base
= rhs
->base
;
1522 lhs
->limit
= rhs
->limit
;
1523 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
1524 ((rhs
->present
&& !rhs
->unusable
) * DESC_P_MASK
) |
1525 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
1526 (rhs
->db
<< DESC_B_SHIFT
) |
1527 (rhs
->s
* DESC_S_MASK
) |
1528 (rhs
->l
<< DESC_L_SHIFT
) |
1529 (rhs
->g
* DESC_G_MASK
) |
1530 (rhs
->avl
* DESC_AVL_MASK
);
1533 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
1536 *kvm_reg
= *qemu_reg
;
1538 *qemu_reg
= *kvm_reg
;
1542 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
1544 CPUX86State
*env
= &cpu
->env
;
1545 struct kvm_regs regs
;
1549 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
1555 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
1556 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
1557 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
1558 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
1559 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
1560 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
1561 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
1562 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
1563 #ifdef TARGET_X86_64
1564 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
1565 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
1566 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
1567 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
1568 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
1569 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
1570 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
1571 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
1574 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
1575 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
1578 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
1584 static int kvm_put_fpu(X86CPU
*cpu
)
1586 CPUX86State
*env
= &cpu
->env
;
1590 memset(&fpu
, 0, sizeof fpu
);
1591 fpu
.fsw
= env
->fpus
& ~(7 << 11);
1592 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
1593 fpu
.fcw
= env
->fpuc
;
1594 fpu
.last_opcode
= env
->fpop
;
1595 fpu
.last_ip
= env
->fpip
;
1596 fpu
.last_dp
= env
->fpdp
;
1597 for (i
= 0; i
< 8; ++i
) {
1598 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
1600 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
1601 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1602 stq_p(&fpu
.xmm
[i
][0], env
->xmm_regs
[i
].ZMM_Q(0));
1603 stq_p(&fpu
.xmm
[i
][8], env
->xmm_regs
[i
].ZMM_Q(1));
1605 fpu
.mxcsr
= env
->mxcsr
;
1607 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
1610 #define XSAVE_FCW_FSW 0
1611 #define XSAVE_FTW_FOP 1
1612 #define XSAVE_CWD_RIP 2
1613 #define XSAVE_CWD_RDP 4
1614 #define XSAVE_MXCSR 6
1615 #define XSAVE_ST_SPACE 8
1616 #define XSAVE_XMM_SPACE 40
1617 #define XSAVE_XSTATE_BV 128
1618 #define XSAVE_YMMH_SPACE 144
1619 #define XSAVE_BNDREGS 240
1620 #define XSAVE_BNDCSR 256
1621 #define XSAVE_OPMASK 272
1622 #define XSAVE_ZMM_Hi256 288
1623 #define XSAVE_Hi16_ZMM 416
1624 #define XSAVE_PKRU 672
1626 #define XSAVE_BYTE_OFFSET(word_offset) \
1627 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1629 #define ASSERT_OFFSET(word_offset, field) \
1630 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1631 offsetof(X86XSaveArea, field))
1633 ASSERT_OFFSET(XSAVE_FCW_FSW
, legacy
.fcw
);
1634 ASSERT_OFFSET(XSAVE_FTW_FOP
, legacy
.ftw
);
1635 ASSERT_OFFSET(XSAVE_CWD_RIP
, legacy
.fpip
);
1636 ASSERT_OFFSET(XSAVE_CWD_RDP
, legacy
.fpdp
);
1637 ASSERT_OFFSET(XSAVE_MXCSR
, legacy
.mxcsr
);
1638 ASSERT_OFFSET(XSAVE_ST_SPACE
, legacy
.fpregs
);
1639 ASSERT_OFFSET(XSAVE_XMM_SPACE
, legacy
.xmm_regs
);
1640 ASSERT_OFFSET(XSAVE_XSTATE_BV
, header
.xstate_bv
);
1641 ASSERT_OFFSET(XSAVE_YMMH_SPACE
, avx_state
);
1642 ASSERT_OFFSET(XSAVE_BNDREGS
, bndreg_state
);
1643 ASSERT_OFFSET(XSAVE_BNDCSR
, bndcsr_state
);
1644 ASSERT_OFFSET(XSAVE_OPMASK
, opmask_state
);
1645 ASSERT_OFFSET(XSAVE_ZMM_Hi256
, zmm_hi256_state
);
1646 ASSERT_OFFSET(XSAVE_Hi16_ZMM
, hi16_zmm_state
);
1647 ASSERT_OFFSET(XSAVE_PKRU
, pkru_state
);
1649 static int kvm_put_xsave(X86CPU
*cpu
)
1651 CPUX86State
*env
= &cpu
->env
;
1652 X86XSaveArea
*xsave
= env
->kvm_xsave_buf
;
1655 return kvm_put_fpu(cpu
);
1657 x86_cpu_xsave_all_areas(cpu
, xsave
);
1659 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
1662 static int kvm_put_xcrs(X86CPU
*cpu
)
1664 CPUX86State
*env
= &cpu
->env
;
1665 struct kvm_xcrs xcrs
= {};
1673 xcrs
.xcrs
[0].xcr
= 0;
1674 xcrs
.xcrs
[0].value
= env
->xcr0
;
1675 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
1678 static int kvm_put_sregs(X86CPU
*cpu
)
1680 CPUX86State
*env
= &cpu
->env
;
1681 struct kvm_sregs sregs
;
1683 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
1684 if (env
->interrupt_injected
>= 0) {
1685 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
1686 (uint64_t)1 << (env
->interrupt_injected
% 64);
1689 if ((env
->eflags
& VM_MASK
)) {
1690 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1691 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1692 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1693 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1694 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1695 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1697 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1698 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1699 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1700 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1701 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1702 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1705 set_seg(&sregs
.tr
, &env
->tr
);
1706 set_seg(&sregs
.ldt
, &env
->ldt
);
1708 sregs
.idt
.limit
= env
->idt
.limit
;
1709 sregs
.idt
.base
= env
->idt
.base
;
1710 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
1711 sregs
.gdt
.limit
= env
->gdt
.limit
;
1712 sregs
.gdt
.base
= env
->gdt
.base
;
1713 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
1715 sregs
.cr0
= env
->cr
[0];
1716 sregs
.cr2
= env
->cr
[2];
1717 sregs
.cr3
= env
->cr
[3];
1718 sregs
.cr4
= env
->cr
[4];
1720 sregs
.cr8
= cpu_get_apic_tpr(cpu
->apic_state
);
1721 sregs
.apic_base
= cpu_get_apic_base(cpu
->apic_state
);
1723 sregs
.efer
= env
->efer
;
1725 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
1728 static void kvm_msr_buf_reset(X86CPU
*cpu
)
1730 memset(cpu
->kvm_msr_buf
, 0, MSR_BUF_SIZE
);
1733 static void kvm_msr_entry_add(X86CPU
*cpu
, uint32_t index
, uint64_t value
)
1735 struct kvm_msrs
*msrs
= cpu
->kvm_msr_buf
;
1736 void *limit
= ((void *)msrs
) + MSR_BUF_SIZE
;
1737 struct kvm_msr_entry
*entry
= &msrs
->entries
[msrs
->nmsrs
];
1739 assert((void *)(entry
+ 1) <= limit
);
1741 entry
->index
= index
;
1742 entry
->reserved
= 0;
1743 entry
->data
= value
;
1747 static int kvm_put_one_msr(X86CPU
*cpu
, int index
, uint64_t value
)
1749 kvm_msr_buf_reset(cpu
);
1750 kvm_msr_entry_add(cpu
, index
, value
);
1752 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1755 void kvm_put_apicbase(X86CPU
*cpu
, uint64_t value
)
1759 ret
= kvm_put_one_msr(cpu
, MSR_IA32_APICBASE
, value
);
1763 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
1765 CPUX86State
*env
= &cpu
->env
;
1768 if (!has_msr_tsc_deadline
) {
1772 ret
= kvm_put_one_msr(cpu
, MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1782 * Provide a separate write service for the feature control MSR in order to
1783 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1784 * before writing any other state because forcibly leaving nested mode
1785 * invalidates the VCPU state.
1787 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
1791 if (!has_msr_feature_control
) {
1795 ret
= kvm_put_one_msr(cpu
, MSR_IA32_FEATURE_CONTROL
,
1796 cpu
->env
.msr_ia32_feature_control
);
1805 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
1807 CPUX86State
*env
= &cpu
->env
;
1811 kvm_msr_buf_reset(cpu
);
1813 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1814 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1815 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1816 kvm_msr_entry_add(cpu
, MSR_PAT
, env
->pat
);
1818 kvm_msr_entry_add(cpu
, MSR_STAR
, env
->star
);
1820 if (has_msr_hsave_pa
) {
1821 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1823 if (has_msr_tsc_aux
) {
1824 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, env
->tsc_aux
);
1826 if (has_msr_tsc_adjust
) {
1827 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, env
->tsc_adjust
);
1829 if (has_msr_misc_enable
) {
1830 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
,
1831 env
->msr_ia32_misc_enable
);
1833 if (has_msr_smbase
) {
1834 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, env
->smbase
);
1836 if (has_msr_smi_count
) {
1837 kvm_msr_entry_add(cpu
, MSR_SMI_COUNT
, env
->msr_smi_count
);
1839 if (has_msr_bndcfgs
) {
1840 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
1843 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, env
->xss
);
1845 if (has_msr_spec_ctrl
) {
1846 kvm_msr_entry_add(cpu
, MSR_IA32_SPEC_CTRL
, env
->spec_ctrl
);
1848 if (has_msr_virt_ssbd
) {
1849 kvm_msr_entry_add(cpu
, MSR_VIRT_SSBD
, env
->virt_ssbd
);
1852 #ifdef TARGET_X86_64
1853 if (lm_capable_kernel
) {
1854 kvm_msr_entry_add(cpu
, MSR_CSTAR
, env
->cstar
);
1855 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, env
->kernelgsbase
);
1856 kvm_msr_entry_add(cpu
, MSR_FMASK
, env
->fmask
);
1857 kvm_msr_entry_add(cpu
, MSR_LSTAR
, env
->lstar
);
1862 * The following MSRs have side effects on the guest or are too heavy
1863 * for normal writeback. Limit them to reset or full state updates.
1865 if (level
>= KVM_PUT_RESET_STATE
) {
1866 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, env
->tsc
);
1867 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
1868 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1869 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_ASYNC_PF
)) {
1870 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
1872 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_PV_EOI
)) {
1873 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, env
->pv_eoi_en_msr
);
1875 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_STEAL_TIME
)) {
1876 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, env
->steal_time_msr
);
1878 if (has_architectural_pmu_version
> 0) {
1879 if (has_architectural_pmu_version
> 1) {
1880 /* Stop the counter. */
1881 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
1882 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1885 /* Set the counter values. */
1886 for (i
= 0; i
< num_architectural_pmu_fixed_counters
; i
++) {
1887 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
,
1888 env
->msr_fixed_counters
[i
]);
1890 for (i
= 0; i
< num_architectural_pmu_gp_counters
; i
++) {
1891 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
,
1892 env
->msr_gp_counters
[i
]);
1893 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
,
1894 env
->msr_gp_evtsel
[i
]);
1896 if (has_architectural_pmu_version
> 1) {
1897 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
,
1898 env
->msr_global_status
);
1899 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
1900 env
->msr_global_ovf_ctrl
);
1902 /* Now start the PMU. */
1903 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
,
1904 env
->msr_fixed_ctr_ctrl
);
1905 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
,
1906 env
->msr_global_ctrl
);
1910 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1911 * only sync them to KVM on the first cpu
1913 if (current_cpu
== first_cpu
) {
1914 if (has_msr_hv_hypercall
) {
1915 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
,
1916 env
->msr_hv_guest_os_id
);
1917 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
,
1918 env
->msr_hv_hypercall
);
1920 if (cpu
->hyperv_time
) {
1921 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
,
1924 if (cpu
->hyperv_reenlightenment
) {
1925 kvm_msr_entry_add(cpu
, HV_X64_MSR_REENLIGHTENMENT_CONTROL
,
1926 env
->msr_hv_reenlightenment_control
);
1927 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_CONTROL
,
1928 env
->msr_hv_tsc_emulation_control
);
1929 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_STATUS
,
1930 env
->msr_hv_tsc_emulation_status
);
1933 if (cpu
->hyperv_vapic
) {
1934 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
,
1937 if (has_msr_hv_crash
) {
1940 for (j
= 0; j
< HV_CRASH_PARAMS
; j
++)
1941 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
,
1942 env
->msr_hv_crash_params
[j
]);
1944 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_CTL
, HV_CRASH_CTL_NOTIFY
);
1946 if (has_msr_hv_runtime
) {
1947 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, env
->msr_hv_runtime
);
1949 if (cpu
->hyperv_vpindex
&& hv_vpindex_settable
) {
1950 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_INDEX
, hyperv_vp_index(cpu
));
1952 if (cpu
->hyperv_synic
) {
1955 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
, HV_SYNIC_VERSION
);
1957 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
,
1958 env
->msr_hv_synic_control
);
1959 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
,
1960 env
->msr_hv_synic_evt_page
);
1961 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
,
1962 env
->msr_hv_synic_msg_page
);
1964 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_synic_sint
); j
++) {
1965 kvm_msr_entry_add(cpu
, HV_X64_MSR_SINT0
+ j
,
1966 env
->msr_hv_synic_sint
[j
]);
1969 if (has_msr_hv_stimer
) {
1972 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_config
); j
++) {
1973 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_CONFIG
+ j
* 2,
1974 env
->msr_hv_stimer_config
[j
]);
1977 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_count
); j
++) {
1978 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_COUNT
+ j
* 2,
1979 env
->msr_hv_stimer_count
[j
]);
1982 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
1983 uint64_t phys_mask
= MAKE_64BIT_MASK(0, cpu
->phys_bits
);
1985 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, env
->mtrr_deftype
);
1986 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, env
->mtrr_fixed
[0]);
1987 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, env
->mtrr_fixed
[1]);
1988 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, env
->mtrr_fixed
[2]);
1989 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, env
->mtrr_fixed
[3]);
1990 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, env
->mtrr_fixed
[4]);
1991 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, env
->mtrr_fixed
[5]);
1992 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, env
->mtrr_fixed
[6]);
1993 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, env
->mtrr_fixed
[7]);
1994 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, env
->mtrr_fixed
[8]);
1995 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, env
->mtrr_fixed
[9]);
1996 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, env
->mtrr_fixed
[10]);
1997 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
1998 /* The CPU GPs if we write to a bit above the physical limit of
1999 * the host CPU (and KVM emulates that)
2001 uint64_t mask
= env
->mtrr_var
[i
].mask
;
2004 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
),
2005 env
->mtrr_var
[i
].base
);
2006 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), mask
);
2009 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) {
2010 int addr_num
= kvm_arch_get_supported_cpuid(kvm_state
,
2011 0x14, 1, R_EAX
) & 0x7;
2013 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CTL
,
2014 env
->msr_rtit_ctrl
);
2015 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_STATUS
,
2016 env
->msr_rtit_status
);
2017 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_BASE
,
2018 env
->msr_rtit_output_base
);
2019 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_MASK
,
2020 env
->msr_rtit_output_mask
);
2021 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CR3_MATCH
,
2022 env
->msr_rtit_cr3_match
);
2023 for (i
= 0; i
< addr_num
; i
++) {
2024 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_ADDR0_A
+ i
,
2025 env
->msr_rtit_addrs
[i
]);
2029 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2030 * kvm_put_msr_feature_control. */
2035 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, env
->mcg_status
);
2036 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, env
->mcg_ctl
);
2037 if (has_msr_mcg_ext_ctl
) {
2038 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, env
->mcg_ext_ctl
);
2040 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
2041 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
2045 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
2050 if (ret
< cpu
->kvm_msr_buf
->nmsrs
) {
2051 struct kvm_msr_entry
*e
= &cpu
->kvm_msr_buf
->entries
[ret
];
2052 error_report("error: failed to set MSR 0x%" PRIx32
" to 0x%" PRIx64
,
2053 (uint32_t)e
->index
, (uint64_t)e
->data
);
2056 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
2061 static int kvm_get_fpu(X86CPU
*cpu
)
2063 CPUX86State
*env
= &cpu
->env
;
2067 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
2072 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
2073 env
->fpus
= fpu
.fsw
;
2074 env
->fpuc
= fpu
.fcw
;
2075 env
->fpop
= fpu
.last_opcode
;
2076 env
->fpip
= fpu
.last_ip
;
2077 env
->fpdp
= fpu
.last_dp
;
2078 for (i
= 0; i
< 8; ++i
) {
2079 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
2081 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
2082 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
2083 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(&fpu
.xmm
[i
][0]);
2084 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(&fpu
.xmm
[i
][8]);
2086 env
->mxcsr
= fpu
.mxcsr
;
2091 static int kvm_get_xsave(X86CPU
*cpu
)
2093 CPUX86State
*env
= &cpu
->env
;
2094 X86XSaveArea
*xsave
= env
->kvm_xsave_buf
;
2098 return kvm_get_fpu(cpu
);
2101 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
2105 x86_cpu_xrstor_all_areas(cpu
, xsave
);
2110 static int kvm_get_xcrs(X86CPU
*cpu
)
2112 CPUX86State
*env
= &cpu
->env
;
2114 struct kvm_xcrs xcrs
;
2120 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
2125 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
2126 /* Only support xcr0 now */
2127 if (xcrs
.xcrs
[i
].xcr
== 0) {
2128 env
->xcr0
= xcrs
.xcrs
[i
].value
;
2135 static int kvm_get_sregs(X86CPU
*cpu
)
2137 CPUX86State
*env
= &cpu
->env
;
2138 struct kvm_sregs sregs
;
2141 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
2146 /* There can only be one pending IRQ set in the bitmap at a time, so try
2147 to find it and save its number instead (-1 for none). */
2148 env
->interrupt_injected
= -1;
2149 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
2150 if (sregs
.interrupt_bitmap
[i
]) {
2151 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
2152 env
->interrupt_injected
= i
* 64 + bit
;
2157 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
2158 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
2159 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
2160 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
2161 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
2162 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
2164 get_seg(&env
->tr
, &sregs
.tr
);
2165 get_seg(&env
->ldt
, &sregs
.ldt
);
2167 env
->idt
.limit
= sregs
.idt
.limit
;
2168 env
->idt
.base
= sregs
.idt
.base
;
2169 env
->gdt
.limit
= sregs
.gdt
.limit
;
2170 env
->gdt
.base
= sregs
.gdt
.base
;
2172 env
->cr
[0] = sregs
.cr0
;
2173 env
->cr
[2] = sregs
.cr2
;
2174 env
->cr
[3] = sregs
.cr3
;
2175 env
->cr
[4] = sregs
.cr4
;
2177 env
->efer
= sregs
.efer
;
2179 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2180 x86_update_hflags(env
);
2185 static int kvm_get_msrs(X86CPU
*cpu
)
2187 CPUX86State
*env
= &cpu
->env
;
2188 struct kvm_msr_entry
*msrs
= cpu
->kvm_msr_buf
->entries
;
2190 uint64_t mtrr_top_bits
;
2192 kvm_msr_buf_reset(cpu
);
2194 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, 0);
2195 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, 0);
2196 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, 0);
2197 kvm_msr_entry_add(cpu
, MSR_PAT
, 0);
2199 kvm_msr_entry_add(cpu
, MSR_STAR
, 0);
2201 if (has_msr_hsave_pa
) {
2202 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, 0);
2204 if (has_msr_tsc_aux
) {
2205 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, 0);
2207 if (has_msr_tsc_adjust
) {
2208 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, 0);
2210 if (has_msr_tsc_deadline
) {
2211 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, 0);
2213 if (has_msr_misc_enable
) {
2214 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
, 0);
2216 if (has_msr_smbase
) {
2217 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, 0);
2219 if (has_msr_smi_count
) {
2220 kvm_msr_entry_add(cpu
, MSR_SMI_COUNT
, 0);
2222 if (has_msr_feature_control
) {
2223 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
, 0);
2225 if (has_msr_bndcfgs
) {
2226 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, 0);
2229 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, 0);
2231 if (has_msr_spec_ctrl
) {
2232 kvm_msr_entry_add(cpu
, MSR_IA32_SPEC_CTRL
, 0);
2234 if (has_msr_virt_ssbd
) {
2235 kvm_msr_entry_add(cpu
, MSR_VIRT_SSBD
, 0);
2237 if (!env
->tsc_valid
) {
2238 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, 0);
2239 env
->tsc_valid
= !runstate_is_running();
2242 #ifdef TARGET_X86_64
2243 if (lm_capable_kernel
) {
2244 kvm_msr_entry_add(cpu
, MSR_CSTAR
, 0);
2245 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, 0);
2246 kvm_msr_entry_add(cpu
, MSR_FMASK
, 0);
2247 kvm_msr_entry_add(cpu
, MSR_LSTAR
, 0);
2250 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, 0);
2251 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, 0);
2252 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_ASYNC_PF
)) {
2253 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, 0);
2255 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_PV_EOI
)) {
2256 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, 0);
2258 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_STEAL_TIME
)) {
2259 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, 0);
2261 if (has_architectural_pmu_version
> 0) {
2262 if (has_architectural_pmu_version
> 1) {
2263 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
2264 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
2265 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
, 0);
2266 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
, 0);
2268 for (i
= 0; i
< num_architectural_pmu_fixed_counters
; i
++) {
2269 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
, 0);
2271 for (i
= 0; i
< num_architectural_pmu_gp_counters
; i
++) {
2272 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
, 0);
2273 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
, 0);
2278 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, 0);
2279 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, 0);
2280 if (has_msr_mcg_ext_ctl
) {
2281 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, 0);
2283 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
2284 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, 0);
2288 if (has_msr_hv_hypercall
) {
2289 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
, 0);
2290 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
, 0);
2292 if (cpu
->hyperv_vapic
) {
2293 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
2295 if (cpu
->hyperv_time
) {
2296 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, 0);
2298 if (cpu
->hyperv_reenlightenment
) {
2299 kvm_msr_entry_add(cpu
, HV_X64_MSR_REENLIGHTENMENT_CONTROL
, 0);
2300 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_CONTROL
, 0);
2301 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_STATUS
, 0);
2303 if (has_msr_hv_crash
) {
2306 for (j
= 0; j
< HV_CRASH_PARAMS
; j
++) {
2307 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
, 0);
2310 if (has_msr_hv_runtime
) {
2311 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, 0);
2313 if (cpu
->hyperv_synic
) {
2316 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
, 0);
2317 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
, 0);
2318 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
, 0);
2319 for (msr
= HV_X64_MSR_SINT0
; msr
<= HV_X64_MSR_SINT15
; msr
++) {
2320 kvm_msr_entry_add(cpu
, msr
, 0);
2323 if (has_msr_hv_stimer
) {
2326 for (msr
= HV_X64_MSR_STIMER0_CONFIG
; msr
<= HV_X64_MSR_STIMER3_COUNT
;
2328 kvm_msr_entry_add(cpu
, msr
, 0);
2331 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
2332 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, 0);
2333 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, 0);
2334 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, 0);
2335 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, 0);
2336 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, 0);
2337 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, 0);
2338 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, 0);
2339 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, 0);
2340 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, 0);
2341 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, 0);
2342 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, 0);
2343 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, 0);
2344 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
2345 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
), 0);
2346 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), 0);
2350 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) {
2352 kvm_arch_get_supported_cpuid(kvm_state
, 0x14, 1, R_EAX
) & 0x7;
2354 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CTL
, 0);
2355 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_STATUS
, 0);
2356 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_BASE
, 0);
2357 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_MASK
, 0);
2358 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CR3_MATCH
, 0);
2359 for (i
= 0; i
< addr_num
; i
++) {
2360 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_ADDR0_A
+ i
, 0);
2364 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, cpu
->kvm_msr_buf
);
2369 if (ret
< cpu
->kvm_msr_buf
->nmsrs
) {
2370 struct kvm_msr_entry
*e
= &cpu
->kvm_msr_buf
->entries
[ret
];
2371 error_report("error: failed to get MSR 0x%" PRIx32
,
2372 (uint32_t)e
->index
);
2375 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
2377 * MTRR masks: Each mask consists of 5 parts
2378 * a 10..0: must be zero
2380 * c n-1.12: actual mask bits
2381 * d 51..n: reserved must be zero
2382 * e 63.52: reserved must be zero
2384 * 'n' is the number of physical bits supported by the CPU and is
2385 * apparently always <= 52. We know our 'n' but don't know what
2386 * the destinations 'n' is; it might be smaller, in which case
2387 * it masks (c) on loading. It might be larger, in which case
2388 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2389 * we're migrating to.
2392 if (cpu
->fill_mtrr_mask
) {
2393 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS
> 52);
2394 assert(cpu
->phys_bits
<= TARGET_PHYS_ADDR_SPACE_BITS
);
2395 mtrr_top_bits
= MAKE_64BIT_MASK(cpu
->phys_bits
, 52 - cpu
->phys_bits
);
2400 for (i
= 0; i
< ret
; i
++) {
2401 uint32_t index
= msrs
[i
].index
;
2403 case MSR_IA32_SYSENTER_CS
:
2404 env
->sysenter_cs
= msrs
[i
].data
;
2406 case MSR_IA32_SYSENTER_ESP
:
2407 env
->sysenter_esp
= msrs
[i
].data
;
2409 case MSR_IA32_SYSENTER_EIP
:
2410 env
->sysenter_eip
= msrs
[i
].data
;
2413 env
->pat
= msrs
[i
].data
;
2416 env
->star
= msrs
[i
].data
;
2418 #ifdef TARGET_X86_64
2420 env
->cstar
= msrs
[i
].data
;
2422 case MSR_KERNELGSBASE
:
2423 env
->kernelgsbase
= msrs
[i
].data
;
2426 env
->fmask
= msrs
[i
].data
;
2429 env
->lstar
= msrs
[i
].data
;
2433 env
->tsc
= msrs
[i
].data
;
2436 env
->tsc_aux
= msrs
[i
].data
;
2438 case MSR_TSC_ADJUST
:
2439 env
->tsc_adjust
= msrs
[i
].data
;
2441 case MSR_IA32_TSCDEADLINE
:
2442 env
->tsc_deadline
= msrs
[i
].data
;
2444 case MSR_VM_HSAVE_PA
:
2445 env
->vm_hsave
= msrs
[i
].data
;
2447 case MSR_KVM_SYSTEM_TIME
:
2448 env
->system_time_msr
= msrs
[i
].data
;
2450 case MSR_KVM_WALL_CLOCK
:
2451 env
->wall_clock_msr
= msrs
[i
].data
;
2453 case MSR_MCG_STATUS
:
2454 env
->mcg_status
= msrs
[i
].data
;
2457 env
->mcg_ctl
= msrs
[i
].data
;
2459 case MSR_MCG_EXT_CTL
:
2460 env
->mcg_ext_ctl
= msrs
[i
].data
;
2462 case MSR_IA32_MISC_ENABLE
:
2463 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
2465 case MSR_IA32_SMBASE
:
2466 env
->smbase
= msrs
[i
].data
;
2469 env
->msr_smi_count
= msrs
[i
].data
;
2471 case MSR_IA32_FEATURE_CONTROL
:
2472 env
->msr_ia32_feature_control
= msrs
[i
].data
;
2474 case MSR_IA32_BNDCFGS
:
2475 env
->msr_bndcfgs
= msrs
[i
].data
;
2478 env
->xss
= msrs
[i
].data
;
2481 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
2482 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
2483 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
2486 case MSR_KVM_ASYNC_PF_EN
:
2487 env
->async_pf_en_msr
= msrs
[i
].data
;
2489 case MSR_KVM_PV_EOI_EN
:
2490 env
->pv_eoi_en_msr
= msrs
[i
].data
;
2492 case MSR_KVM_STEAL_TIME
:
2493 env
->steal_time_msr
= msrs
[i
].data
;
2495 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
2496 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
2498 case MSR_CORE_PERF_GLOBAL_CTRL
:
2499 env
->msr_global_ctrl
= msrs
[i
].data
;
2501 case MSR_CORE_PERF_GLOBAL_STATUS
:
2502 env
->msr_global_status
= msrs
[i
].data
;
2504 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
2505 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
2507 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
2508 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
2510 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
2511 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
2513 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
2514 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
2516 case HV_X64_MSR_HYPERCALL
:
2517 env
->msr_hv_hypercall
= msrs
[i
].data
;
2519 case HV_X64_MSR_GUEST_OS_ID
:
2520 env
->msr_hv_guest_os_id
= msrs
[i
].data
;
2522 case HV_X64_MSR_APIC_ASSIST_PAGE
:
2523 env
->msr_hv_vapic
= msrs
[i
].data
;
2525 case HV_X64_MSR_REFERENCE_TSC
:
2526 env
->msr_hv_tsc
= msrs
[i
].data
;
2528 case HV_X64_MSR_CRASH_P0
... HV_X64_MSR_CRASH_P4
:
2529 env
->msr_hv_crash_params
[index
- HV_X64_MSR_CRASH_P0
] = msrs
[i
].data
;
2531 case HV_X64_MSR_VP_RUNTIME
:
2532 env
->msr_hv_runtime
= msrs
[i
].data
;
2534 case HV_X64_MSR_SCONTROL
:
2535 env
->msr_hv_synic_control
= msrs
[i
].data
;
2537 case HV_X64_MSR_SIEFP
:
2538 env
->msr_hv_synic_evt_page
= msrs
[i
].data
;
2540 case HV_X64_MSR_SIMP
:
2541 env
->msr_hv_synic_msg_page
= msrs
[i
].data
;
2543 case HV_X64_MSR_SINT0
... HV_X64_MSR_SINT15
:
2544 env
->msr_hv_synic_sint
[index
- HV_X64_MSR_SINT0
] = msrs
[i
].data
;
2546 case HV_X64_MSR_STIMER0_CONFIG
:
2547 case HV_X64_MSR_STIMER1_CONFIG
:
2548 case HV_X64_MSR_STIMER2_CONFIG
:
2549 case HV_X64_MSR_STIMER3_CONFIG
:
2550 env
->msr_hv_stimer_config
[(index
- HV_X64_MSR_STIMER0_CONFIG
)/2] =
2553 case HV_X64_MSR_STIMER0_COUNT
:
2554 case HV_X64_MSR_STIMER1_COUNT
:
2555 case HV_X64_MSR_STIMER2_COUNT
:
2556 case HV_X64_MSR_STIMER3_COUNT
:
2557 env
->msr_hv_stimer_count
[(index
- HV_X64_MSR_STIMER0_COUNT
)/2] =
2560 case HV_X64_MSR_REENLIGHTENMENT_CONTROL
:
2561 env
->msr_hv_reenlightenment_control
= msrs
[i
].data
;
2563 case HV_X64_MSR_TSC_EMULATION_CONTROL
:
2564 env
->msr_hv_tsc_emulation_control
= msrs
[i
].data
;
2566 case HV_X64_MSR_TSC_EMULATION_STATUS
:
2567 env
->msr_hv_tsc_emulation_status
= msrs
[i
].data
;
2569 case MSR_MTRRdefType
:
2570 env
->mtrr_deftype
= msrs
[i
].data
;
2572 case MSR_MTRRfix64K_00000
:
2573 env
->mtrr_fixed
[0] = msrs
[i
].data
;
2575 case MSR_MTRRfix16K_80000
:
2576 env
->mtrr_fixed
[1] = msrs
[i
].data
;
2578 case MSR_MTRRfix16K_A0000
:
2579 env
->mtrr_fixed
[2] = msrs
[i
].data
;
2581 case MSR_MTRRfix4K_C0000
:
2582 env
->mtrr_fixed
[3] = msrs
[i
].data
;
2584 case MSR_MTRRfix4K_C8000
:
2585 env
->mtrr_fixed
[4] = msrs
[i
].data
;
2587 case MSR_MTRRfix4K_D0000
:
2588 env
->mtrr_fixed
[5] = msrs
[i
].data
;
2590 case MSR_MTRRfix4K_D8000
:
2591 env
->mtrr_fixed
[6] = msrs
[i
].data
;
2593 case MSR_MTRRfix4K_E0000
:
2594 env
->mtrr_fixed
[7] = msrs
[i
].data
;
2596 case MSR_MTRRfix4K_E8000
:
2597 env
->mtrr_fixed
[8] = msrs
[i
].data
;
2599 case MSR_MTRRfix4K_F0000
:
2600 env
->mtrr_fixed
[9] = msrs
[i
].data
;
2602 case MSR_MTRRfix4K_F8000
:
2603 env
->mtrr_fixed
[10] = msrs
[i
].data
;
2605 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT
- 1):
2607 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].mask
= msrs
[i
].data
|
2610 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].base
= msrs
[i
].data
;
2613 case MSR_IA32_SPEC_CTRL
:
2614 env
->spec_ctrl
= msrs
[i
].data
;
2617 env
->virt_ssbd
= msrs
[i
].data
;
2619 case MSR_IA32_RTIT_CTL
:
2620 env
->msr_rtit_ctrl
= msrs
[i
].data
;
2622 case MSR_IA32_RTIT_STATUS
:
2623 env
->msr_rtit_status
= msrs
[i
].data
;
2625 case MSR_IA32_RTIT_OUTPUT_BASE
:
2626 env
->msr_rtit_output_base
= msrs
[i
].data
;
2628 case MSR_IA32_RTIT_OUTPUT_MASK
:
2629 env
->msr_rtit_output_mask
= msrs
[i
].data
;
2631 case MSR_IA32_RTIT_CR3_MATCH
:
2632 env
->msr_rtit_cr3_match
= msrs
[i
].data
;
2634 case MSR_IA32_RTIT_ADDR0_A
... MSR_IA32_RTIT_ADDR3_B
:
2635 env
->msr_rtit_addrs
[index
- MSR_IA32_RTIT_ADDR0_A
] = msrs
[i
].data
;
2643 static int kvm_put_mp_state(X86CPU
*cpu
)
2645 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
2647 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
2650 static int kvm_get_mp_state(X86CPU
*cpu
)
2652 CPUState
*cs
= CPU(cpu
);
2653 CPUX86State
*env
= &cpu
->env
;
2654 struct kvm_mp_state mp_state
;
2657 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
2661 env
->mp_state
= mp_state
.mp_state
;
2662 if (kvm_irqchip_in_kernel()) {
2663 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
2668 static int kvm_get_apic(X86CPU
*cpu
)
2670 DeviceState
*apic
= cpu
->apic_state
;
2671 struct kvm_lapic_state kapic
;
2674 if (apic
&& kvm_irqchip_in_kernel()) {
2675 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
2680 kvm_get_apic_state(apic
, &kapic
);
2685 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
2687 CPUState
*cs
= CPU(cpu
);
2688 CPUX86State
*env
= &cpu
->env
;
2689 struct kvm_vcpu_events events
= {};
2691 if (!kvm_has_vcpu_events()) {
2695 events
.exception
.injected
= (env
->exception_injected
>= 0);
2696 events
.exception
.nr
= env
->exception_injected
;
2697 events
.exception
.has_error_code
= env
->has_error_code
;
2698 events
.exception
.error_code
= env
->error_code
;
2699 events
.exception
.pad
= 0;
2701 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
2702 events
.interrupt
.nr
= env
->interrupt_injected
;
2703 events
.interrupt
.soft
= env
->soft_interrupt
;
2705 events
.nmi
.injected
= env
->nmi_injected
;
2706 events
.nmi
.pending
= env
->nmi_pending
;
2707 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
2710 events
.sipi_vector
= env
->sipi_vector
;
2713 if (has_msr_smbase
) {
2714 events
.smi
.smm
= !!(env
->hflags
& HF_SMM_MASK
);
2715 events
.smi
.smm_inside_nmi
= !!(env
->hflags2
& HF2_SMM_INSIDE_NMI_MASK
);
2716 if (kvm_irqchip_in_kernel()) {
2717 /* As soon as these are moved to the kernel, remove them
2718 * from cs->interrupt_request.
2720 events
.smi
.pending
= cs
->interrupt_request
& CPU_INTERRUPT_SMI
;
2721 events
.smi
.latched_init
= cs
->interrupt_request
& CPU_INTERRUPT_INIT
;
2722 cs
->interrupt_request
&= ~(CPU_INTERRUPT_INIT
| CPU_INTERRUPT_SMI
);
2724 /* Keep these in cs->interrupt_request. */
2725 events
.smi
.pending
= 0;
2726 events
.smi
.latched_init
= 0;
2728 /* Stop SMI delivery on old machine types to avoid a reboot
2729 * on an inward migration of an old VM.
2731 if (!cpu
->kvm_no_smi_migration
) {
2732 events
.flags
|= KVM_VCPUEVENT_VALID_SMM
;
2736 if (level
>= KVM_PUT_RESET_STATE
) {
2737 events
.flags
|= KVM_VCPUEVENT_VALID_NMI_PENDING
;
2738 if (env
->mp_state
== KVM_MP_STATE_SIPI_RECEIVED
) {
2739 events
.flags
|= KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
2743 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
2746 static int kvm_get_vcpu_events(X86CPU
*cpu
)
2748 CPUX86State
*env
= &cpu
->env
;
2749 struct kvm_vcpu_events events
;
2752 if (!kvm_has_vcpu_events()) {
2756 memset(&events
, 0, sizeof(events
));
2757 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
2761 env
->exception_injected
=
2762 events
.exception
.injected
? events
.exception
.nr
: -1;
2763 env
->has_error_code
= events
.exception
.has_error_code
;
2764 env
->error_code
= events
.exception
.error_code
;
2766 env
->interrupt_injected
=
2767 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
2768 env
->soft_interrupt
= events
.interrupt
.soft
;
2770 env
->nmi_injected
= events
.nmi
.injected
;
2771 env
->nmi_pending
= events
.nmi
.pending
;
2772 if (events
.nmi
.masked
) {
2773 env
->hflags2
|= HF2_NMI_MASK
;
2775 env
->hflags2
&= ~HF2_NMI_MASK
;
2778 if (events
.flags
& KVM_VCPUEVENT_VALID_SMM
) {
2779 if (events
.smi
.smm
) {
2780 env
->hflags
|= HF_SMM_MASK
;
2782 env
->hflags
&= ~HF_SMM_MASK
;
2784 if (events
.smi
.pending
) {
2785 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
2787 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
2789 if (events
.smi
.smm_inside_nmi
) {
2790 env
->hflags2
|= HF2_SMM_INSIDE_NMI_MASK
;
2792 env
->hflags2
&= ~HF2_SMM_INSIDE_NMI_MASK
;
2794 if (events
.smi
.latched_init
) {
2795 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
2797 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
2801 env
->sipi_vector
= events
.sipi_vector
;
2806 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
2808 CPUState
*cs
= CPU(cpu
);
2809 CPUX86State
*env
= &cpu
->env
;
2811 unsigned long reinject_trap
= 0;
2813 if (!kvm_has_vcpu_events()) {
2814 if (env
->exception_injected
== 1) {
2815 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
2816 } else if (env
->exception_injected
== 3) {
2817 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
2819 env
->exception_injected
= -1;
2823 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2824 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2825 * by updating the debug state once again if single-stepping is on.
2826 * Another reason to call kvm_update_guest_debug here is a pending debug
2827 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2828 * reinject them via SET_GUEST_DEBUG.
2830 if (reinject_trap
||
2831 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
2832 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
2837 static int kvm_put_debugregs(X86CPU
*cpu
)
2839 CPUX86State
*env
= &cpu
->env
;
2840 struct kvm_debugregs dbgregs
;
2843 if (!kvm_has_debugregs()) {
2847 for (i
= 0; i
< 4; i
++) {
2848 dbgregs
.db
[i
] = env
->dr
[i
];
2850 dbgregs
.dr6
= env
->dr
[6];
2851 dbgregs
.dr7
= env
->dr
[7];
2854 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
2857 static int kvm_get_debugregs(X86CPU
*cpu
)
2859 CPUX86State
*env
= &cpu
->env
;
2860 struct kvm_debugregs dbgregs
;
2863 if (!kvm_has_debugregs()) {
2867 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
2871 for (i
= 0; i
< 4; i
++) {
2872 env
->dr
[i
] = dbgregs
.db
[i
];
2874 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
2875 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
2880 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
2882 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2885 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
2887 if (level
>= KVM_PUT_RESET_STATE
) {
2888 ret
= kvm_put_msr_feature_control(x86_cpu
);
2894 if (level
== KVM_PUT_FULL_STATE
) {
2895 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2896 * because TSC frequency mismatch shouldn't abort migration,
2897 * unless the user explicitly asked for a more strict TSC
2898 * setting (e.g. using an explicit "tsc-freq" option).
2900 kvm_arch_set_tsc_khz(cpu
);
2903 ret
= kvm_getput_regs(x86_cpu
, 1);
2907 ret
= kvm_put_xsave(x86_cpu
);
2911 ret
= kvm_put_xcrs(x86_cpu
);
2915 ret
= kvm_put_sregs(x86_cpu
);
2919 /* must be before kvm_put_msrs */
2920 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
2924 ret
= kvm_put_msrs(x86_cpu
, level
);
2928 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
2932 if (level
>= KVM_PUT_RESET_STATE
) {
2933 ret
= kvm_put_mp_state(x86_cpu
);
2939 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
2943 ret
= kvm_put_debugregs(x86_cpu
);
2948 ret
= kvm_guest_debug_workarounds(x86_cpu
);
2955 int kvm_arch_get_registers(CPUState
*cs
)
2957 X86CPU
*cpu
= X86_CPU(cs
);
2960 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
2962 ret
= kvm_get_vcpu_events(cpu
);
2967 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2968 * KVM_GET_REGS and KVM_GET_SREGS.
2970 ret
= kvm_get_mp_state(cpu
);
2974 ret
= kvm_getput_regs(cpu
, 0);
2978 ret
= kvm_get_xsave(cpu
);
2982 ret
= kvm_get_xcrs(cpu
);
2986 ret
= kvm_get_sregs(cpu
);
2990 ret
= kvm_get_msrs(cpu
);
2994 ret
= kvm_get_apic(cpu
);
2998 ret
= kvm_get_debugregs(cpu
);
3004 cpu_sync_bndcs_hflags(&cpu
->env
);
3008 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
3010 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3011 CPUX86State
*env
= &x86_cpu
->env
;
3015 if (cpu
->interrupt_request
& (CPU_INTERRUPT_NMI
| CPU_INTERRUPT_SMI
)) {
3016 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
3017 qemu_mutex_lock_iothread();
3018 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
3019 qemu_mutex_unlock_iothread();
3020 DPRINTF("injected NMI\n");
3021 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
3023 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
3027 if (cpu
->interrupt_request
& CPU_INTERRUPT_SMI
) {
3028 qemu_mutex_lock_iothread();
3029 cpu
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
3030 qemu_mutex_unlock_iothread();
3031 DPRINTF("injected SMI\n");
3032 ret
= kvm_vcpu_ioctl(cpu
, KVM_SMI
);
3034 fprintf(stderr
, "KVM: injection failed, SMI lost (%s)\n",
3040 if (!kvm_pic_in_kernel()) {
3041 qemu_mutex_lock_iothread();
3044 /* Force the VCPU out of its inner loop to process any INIT requests
3045 * or (for userspace APIC, but it is cheap to combine the checks here)
3046 * pending TPR access reports.
3048 if (cpu
->interrupt_request
& (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
3049 if ((cpu
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
3050 !(env
->hflags
& HF_SMM_MASK
)) {
3051 cpu
->exit_request
= 1;
3053 if (cpu
->interrupt_request
& CPU_INTERRUPT_TPR
) {
3054 cpu
->exit_request
= 1;
3058 if (!kvm_pic_in_kernel()) {
3059 /* Try to inject an interrupt if the guest can accept it */
3060 if (run
->ready_for_interrupt_injection
&&
3061 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
3062 (env
->eflags
& IF_MASK
)) {
3065 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
3066 irq
= cpu_get_pic_interrupt(env
);
3068 struct kvm_interrupt intr
;
3071 DPRINTF("injected interrupt %d\n", irq
);
3072 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
3075 "KVM: injection failed, interrupt lost (%s)\n",
3081 /* If we have an interrupt but the guest is not ready to receive an
3082 * interrupt, request an interrupt window exit. This will
3083 * cause a return to userspace as soon as the guest is ready to
3084 * receive interrupts. */
3085 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
3086 run
->request_interrupt_window
= 1;
3088 run
->request_interrupt_window
= 0;
3091 DPRINTF("setting tpr\n");
3092 run
->cr8
= cpu_get_apic_tpr(x86_cpu
->apic_state
);
3094 qemu_mutex_unlock_iothread();
3098 MemTxAttrs
kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
3100 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3101 CPUX86State
*env
= &x86_cpu
->env
;
3103 if (run
->flags
& KVM_RUN_X86_SMM
) {
3104 env
->hflags
|= HF_SMM_MASK
;
3106 env
->hflags
&= ~HF_SMM_MASK
;
3109 env
->eflags
|= IF_MASK
;
3111 env
->eflags
&= ~IF_MASK
;
3114 /* We need to protect the apic state against concurrent accesses from
3115 * different threads in case the userspace irqchip is used. */
3116 if (!kvm_irqchip_in_kernel()) {
3117 qemu_mutex_lock_iothread();
3119 cpu_set_apic_tpr(x86_cpu
->apic_state
, run
->cr8
);
3120 cpu_set_apic_base(x86_cpu
->apic_state
, run
->apic_base
);
3121 if (!kvm_irqchip_in_kernel()) {
3122 qemu_mutex_unlock_iothread();
3124 return cpu_get_mem_attrs(env
);
3127 int kvm_arch_process_async_events(CPUState
*cs
)
3129 X86CPU
*cpu
= X86_CPU(cs
);
3130 CPUX86State
*env
= &cpu
->env
;
3132 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
3133 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3134 assert(env
->mcg_cap
);
3136 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
3138 kvm_cpu_synchronize_state(cs
);
3140 if (env
->exception_injected
== EXCP08_DBLE
) {
3141 /* this means triple fault */
3142 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
3143 cs
->exit_request
= 1;
3146 env
->exception_injected
= EXCP12_MCHK
;
3147 env
->has_error_code
= 0;
3150 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
3151 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
3155 if ((cs
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
3156 !(env
->hflags
& HF_SMM_MASK
)) {
3157 kvm_cpu_synchronize_state(cs
);
3161 if (kvm_irqchip_in_kernel()) {
3165 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
3166 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
3167 apic_poll_irq(cpu
->apic_state
);
3169 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
3170 (env
->eflags
& IF_MASK
)) ||
3171 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
3174 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
3175 kvm_cpu_synchronize_state(cs
);
3178 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
3179 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
3180 kvm_cpu_synchronize_state(cs
);
3181 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
,
3182 env
->tpr_access_type
);
3188 static int kvm_handle_halt(X86CPU
*cpu
)
3190 CPUState
*cs
= CPU(cpu
);
3191 CPUX86State
*env
= &cpu
->env
;
3193 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
3194 (env
->eflags
& IF_MASK
)) &&
3195 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
3203 static int kvm_handle_tpr_access(X86CPU
*cpu
)
3205 CPUState
*cs
= CPU(cpu
);
3206 struct kvm_run
*run
= cs
->kvm_run
;
3208 apic_handle_tpr_access_report(cpu
->apic_state
, run
->tpr_access
.rip
,
3209 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
3214 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
3216 static const uint8_t int3
= 0xcc;
3218 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
3219 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
3225 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
3229 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
3230 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
3242 static int nb_hw_breakpoint
;
3244 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
3248 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
3249 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
3250 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
3257 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
3258 target_ulong len
, int type
)
3261 case GDB_BREAKPOINT_HW
:
3264 case GDB_WATCHPOINT_WRITE
:
3265 case GDB_WATCHPOINT_ACCESS
:
3272 if (addr
& (len
- 1)) {
3284 if (nb_hw_breakpoint
== 4) {
3287 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
3290 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
3291 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
3292 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
3298 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
3299 target_ulong len
, int type
)
3303 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
3308 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
3313 void kvm_arch_remove_all_hw_breakpoints(void)
3315 nb_hw_breakpoint
= 0;
3318 static CPUWatchpoint hw_watchpoint
;
3320 static int kvm_handle_debug(X86CPU
*cpu
,
3321 struct kvm_debug_exit_arch
*arch_info
)
3323 CPUState
*cs
= CPU(cpu
);
3324 CPUX86State
*env
= &cpu
->env
;
3328 if (arch_info
->exception
== 1) {
3329 if (arch_info
->dr6
& (1 << 14)) {
3330 if (cs
->singlestep_enabled
) {
3334 for (n
= 0; n
< 4; n
++) {
3335 if (arch_info
->dr6
& (1 << n
)) {
3336 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
3342 cs
->watchpoint_hit
= &hw_watchpoint
;
3343 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
3344 hw_watchpoint
.flags
= BP_MEM_WRITE
;
3348 cs
->watchpoint_hit
= &hw_watchpoint
;
3349 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
3350 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
3356 } else if (kvm_find_sw_breakpoint(cs
, arch_info
->pc
)) {
3360 cpu_synchronize_state(cs
);
3361 assert(env
->exception_injected
== -1);
3364 env
->exception_injected
= arch_info
->exception
;
3365 env
->has_error_code
= 0;
3371 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
3373 const uint8_t type_code
[] = {
3374 [GDB_BREAKPOINT_HW
] = 0x0,
3375 [GDB_WATCHPOINT_WRITE
] = 0x1,
3376 [GDB_WATCHPOINT_ACCESS
] = 0x3
3378 const uint8_t len_code
[] = {
3379 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3383 if (kvm_sw_breakpoints_active(cpu
)) {
3384 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
3386 if (nb_hw_breakpoint
> 0) {
3387 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
3388 dbg
->arch
.debugreg
[7] = 0x0600;
3389 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
3390 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
3391 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
3392 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
3393 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
3398 static bool host_supports_vmx(void)
3400 uint32_t ecx
, unused
;
3402 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
3403 return ecx
& CPUID_EXT_VMX
;
3406 #define VMX_INVALID_GUEST_STATE 0x80000021
3408 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
3410 X86CPU
*cpu
= X86_CPU(cs
);
3414 switch (run
->exit_reason
) {
3416 DPRINTF("handle_hlt\n");
3417 qemu_mutex_lock_iothread();
3418 ret
= kvm_handle_halt(cpu
);
3419 qemu_mutex_unlock_iothread();
3421 case KVM_EXIT_SET_TPR
:
3424 case KVM_EXIT_TPR_ACCESS
:
3425 qemu_mutex_lock_iothread();
3426 ret
= kvm_handle_tpr_access(cpu
);
3427 qemu_mutex_unlock_iothread();
3429 case KVM_EXIT_FAIL_ENTRY
:
3430 code
= run
->fail_entry
.hardware_entry_failure_reason
;
3431 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
3433 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
3435 "\nIf you're running a guest on an Intel machine without "
3436 "unrestricted mode\n"
3437 "support, the failure can be most likely due to the guest "
3438 "entering an invalid\n"
3439 "state for Intel VT. For example, the guest maybe running "
3440 "in big real mode\n"
3441 "which is not supported on less recent Intel processors."
3446 case KVM_EXIT_EXCEPTION
:
3447 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
3448 run
->ex
.exception
, run
->ex
.error_code
);
3451 case KVM_EXIT_DEBUG
:
3452 DPRINTF("kvm_exit_debug\n");
3453 qemu_mutex_lock_iothread();
3454 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
3455 qemu_mutex_unlock_iothread();
3457 case KVM_EXIT_HYPERV
:
3458 ret
= kvm_hv_handle_exit(cpu
, &run
->hyperv
);
3460 case KVM_EXIT_IOAPIC_EOI
:
3461 ioapic_eoi_broadcast(run
->eoi
.vector
);
3465 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
3473 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
3475 X86CPU
*cpu
= X86_CPU(cs
);
3476 CPUX86State
*env
= &cpu
->env
;
3478 kvm_cpu_synchronize_state(cs
);
3479 return !(env
->cr
[0] & CR0_PE_MASK
) ||
3480 ((env
->segs
[R_CS
].selector
& 3) != 3);
3483 void kvm_arch_init_irq_routing(KVMState
*s
)
3485 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
3486 /* If kernel can't do irq routing, interrupt source
3487 * override 0->2 cannot be set up as required by HPET.
3488 * So we have to disable it.
3492 /* We know at this point that we're using the in-kernel
3493 * irqchip, so we can use irqfds, and on x86 we know
3494 * we can use msi via irqfd and GSI routing.
3496 kvm_msi_via_irqfd_allowed
= true;
3497 kvm_gsi_routing_allowed
= true;
3499 if (kvm_irqchip_is_split()) {
3502 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3503 MSI routes for signaling interrupts to the local apics. */
3504 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
3505 if (kvm_irqchip_add_msi_route(s
, 0, NULL
) < 0) {
3506 error_report("Could not enable split IRQ mode.");
3513 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
3516 if (machine_kernel_irqchip_split(ms
)) {
3517 ret
= kvm_vm_enable_cap(s
, KVM_CAP_SPLIT_IRQCHIP
, 0, 24);
3519 error_report("Could not enable split irqchip mode: %s",
3523 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3524 kvm_split_irqchip
= true;
3532 /* Classic KVM device assignment interface. Will remain x86 only. */
3533 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
3534 uint32_t flags
, uint32_t *dev_id
)
3536 struct kvm_assigned_pci_dev dev_data
= {
3537 .segnr
= dev_addr
->domain
,
3538 .busnr
= dev_addr
->bus
,
3539 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
3544 dev_data
.assigned_dev_id
=
3545 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
3547 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
3552 *dev_id
= dev_data
.assigned_dev_id
;
3557 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
3559 struct kvm_assigned_pci_dev dev_data
= {
3560 .assigned_dev_id
= dev_id
,
3563 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
3566 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
3567 uint32_t irq_type
, uint32_t guest_irq
)
3569 struct kvm_assigned_irq assigned_irq
= {
3570 .assigned_dev_id
= dev_id
,
3571 .guest_irq
= guest_irq
,
3575 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
3576 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
3578 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
3582 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
3585 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
3586 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
3588 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
3591 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
3593 struct kvm_assigned_pci_dev dev_data
= {
3594 .assigned_dev_id
= dev_id
,
3595 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
3598 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
3601 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
3604 struct kvm_assigned_irq assigned_irq
= {
3605 .assigned_dev_id
= dev_id
,
3609 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
3612 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
3614 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
3615 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
3618 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
3620 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
3621 KVM_DEV_IRQ_GUEST_MSI
, virq
);
3624 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
3626 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
3627 KVM_DEV_IRQ_HOST_MSI
);
3630 bool kvm_device_msix_supported(KVMState
*s
)
3632 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3633 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3634 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
3637 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
3638 uint32_t nr_vectors
)
3640 struct kvm_assigned_msix_nr msix_nr
= {
3641 .assigned_dev_id
= dev_id
,
3642 .entry_nr
= nr_vectors
,
3645 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
3648 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
3651 struct kvm_assigned_msix_entry msix_entry
= {
3652 .assigned_dev_id
= dev_id
,
3657 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
3660 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
3662 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
3663 KVM_DEV_IRQ_GUEST_MSIX
, 0);
3666 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
3668 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
3669 KVM_DEV_IRQ_HOST_MSIX
);
3672 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
3673 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
3675 X86IOMMUState
*iommu
= x86_iommu_get_default();
3679 MSIMessage src
, dst
;
3680 X86IOMMUClass
*class = X86_IOMMU_GET_CLASS(iommu
);
3682 src
.address
= route
->u
.msi
.address_hi
;
3683 src
.address
<<= VTD_MSI_ADDR_HI_SHIFT
;
3684 src
.address
|= route
->u
.msi
.address_lo
;
3685 src
.data
= route
->u
.msi
.data
;
3687 ret
= class->int_remap(iommu
, &src
, &dst
, dev
? \
3688 pci_requester_id(dev
) : \
3689 X86_IOMMU_SID_INVALID
);
3691 trace_kvm_x86_fixup_msi_error(route
->gsi
);
3695 route
->u
.msi
.address_hi
= dst
.address
>> VTD_MSI_ADDR_HI_SHIFT
;
3696 route
->u
.msi
.address_lo
= dst
.address
& VTD_MSI_ADDR_LO_MASK
;
3697 route
->u
.msi
.data
= dst
.data
;
3703 typedef struct MSIRouteEntry MSIRouteEntry
;
3705 struct MSIRouteEntry
{
3706 PCIDevice
*dev
; /* Device pointer */
3707 int vector
; /* MSI/MSIX vector index */
3708 int virq
; /* Virtual IRQ index */
3709 QLIST_ENTRY(MSIRouteEntry
) list
;
3712 /* List of used GSI routes */
3713 static QLIST_HEAD(, MSIRouteEntry
) msi_route_list
= \
3714 QLIST_HEAD_INITIALIZER(msi_route_list
);
3716 static void kvm_update_msi_routes_all(void *private, bool global
,
3717 uint32_t index
, uint32_t mask
)
3720 MSIRouteEntry
*entry
;
3724 /* TODO: explicit route update */
3725 QLIST_FOREACH(entry
, &msi_route_list
, list
) {
3728 if (!msix_enabled(dev
) && !msi_enabled(dev
)) {
3731 msg
= pci_get_msi_message(dev
, entry
->vector
);
3732 kvm_irqchip_update_msi_route(kvm_state
, entry
->virq
, msg
, dev
);
3734 kvm_irqchip_commit_routes(kvm_state
);
3735 trace_kvm_x86_update_msi_routes(cnt
);
3738 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
3739 int vector
, PCIDevice
*dev
)
3741 static bool notify_list_inited
= false;
3742 MSIRouteEntry
*entry
;
3745 /* These are (possibly) IOAPIC routes only used for split
3746 * kernel irqchip mode, while what we are housekeeping are
3747 * PCI devices only. */
3751 entry
= g_new0(MSIRouteEntry
, 1);
3753 entry
->vector
= vector
;
3754 entry
->virq
= route
->gsi
;
3755 QLIST_INSERT_HEAD(&msi_route_list
, entry
, list
);
3757 trace_kvm_x86_add_msi_route(route
->gsi
);
3759 if (!notify_list_inited
) {
3760 /* For the first time we do add route, add ourselves into
3761 * IOMMU's IEC notify list if needed. */
3762 X86IOMMUState
*iommu
= x86_iommu_get_default();
3764 x86_iommu_iec_register_notifier(iommu
,
3765 kvm_update_msi_routes_all
,
3768 notify_list_inited
= true;
3773 int kvm_arch_release_virq_post(int virq
)
3775 MSIRouteEntry
*entry
, *next
;
3776 QLIST_FOREACH_SAFE(entry
, &msi_route_list
, list
, next
) {
3777 if (entry
->virq
== virq
) {
3778 trace_kvm_x86_remove_msi_route(virq
);
3779 QLIST_REMOVE(entry
, list
);
3787 int kvm_arch_msi_data_to_gsi(uint32_t data
)