target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "exec/exec-all.h"
  27 #include "qapi/error.h"
  28 #include "qemu/error-report.h"
  29 #include "hw/qdev-properties.h"
  30 #include "migration/vmstate.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 /* RISC-V CPU definitions */
  34
  35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  36
  37 const char * const riscv_int_regnames[] = {
  38   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  39   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  40   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  41   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  42   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  43 };
  44
  45 const char * const riscv_fpr_regnames[] = {
  46   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  47   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  48   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  49   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  50   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  51   "f30/ft10", "f31/ft11"
  52 };
  53
  54 const char * const riscv_excp_names[] = {
  55     "misaligned_fetch",
  56     "fault_fetch",
  57     "illegal_instruction",
  58     "breakpoint",
  59     "misaligned_load",
  60     "fault_load",
  61     "misaligned_store",
  62     "fault_store",
  63     "user_ecall",
  64     "supervisor_ecall",
  65     "hypervisor_ecall",
  66     "machine_ecall",
  67     "exec_page_fault",
  68     "load_page_fault",
  69     "reserved",
  70     "store_page_fault",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "reserved",
  75     "guest_exec_page_fault",
  76     "guest_load_page_fault",
  77     "reserved",
  78     "guest_store_page_fault",
  79 };
  80
  81 const char * const riscv_intr_names[] = {
  82     "u_software",
  83     "s_software",
  84     "vs_software",
  85     "m_software",
  86     "u_timer",
  87     "s_timer",
  88     "vs_timer",
  89     "m_timer",
  90     "u_external",
  91     "vs_external",
  92     "h_external",
  93     "m_external",
  94     "reserved",
  95     "reserved",
  96     "reserved",
  97     "reserved"
  98 };
  99
 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 101 {
 102     if (async) {
 103         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
 104                riscv_intr_names[cause] : "(unknown)";
 105     } else {
 106         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
 107                riscv_excp_names[cause] : "(unknown)";
 108     }
 109 }
 110
 111 static void set_misa(CPURISCVState *env, target_ulong misa)
 112 {
 113     env->misa_mask = env->misa = misa;
 114 }
 115
 116 static void set_priv_version(CPURISCVState *env, int priv_ver)
 117 {
 118     env->priv_ver = priv_ver;
 119 }
 120
 121 static void set_vext_version(CPURISCVState *env, int vext_ver)
 122 {
 123     env->vext_ver = vext_ver;
 124 }
 125
 126 static void set_feature(CPURISCVState *env, int feature)
 127 {
 128     env->features |= (1ULL << feature);
 129 }
 130
 131 static void set_resetvec(CPURISCVState *env, int resetvec)
 132 {
 133 #ifndef CONFIG_USER_ONLY
 134     env->resetvec = resetvec;
 135 #endif
 136 }
 137
 138 static void riscv_any_cpu_init(Object *obj)
 139 {
 140     CPURISCVState *env = &RISCV_CPU(obj)->env;
 141     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 142     set_priv_version(env, PRIV_VERSION_1_11_0);
 143 }
 144
 145 static void riscv_base_cpu_init(Object *obj)
 146 {
 147     CPURISCVState *env = &RISCV_CPU(obj)->env;
 148     /* We set this in the realise function */
 149     set_misa(env, 0);
 150 }
 151
 152 static void rvxx_sifive_u_cpu_init(Object *obj)
 153 {
 154     CPURISCVState *env = &RISCV_CPU(obj)->env;
 155     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 156     set_priv_version(env, PRIV_VERSION_1_10_0);
 157 }
 158
 159 static void rvxx_sifive_e_cpu_init(Object *obj)
 160 {
 161     CPURISCVState *env = &RISCV_CPU(obj)->env;
 162     set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
 163     set_priv_version(env, PRIV_VERSION_1_10_0);
 164     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 165 }
 166
 167 #if defined(TARGET_RISCV32)
 168
 169 static void rv32_ibex_cpu_init(Object *obj)
 170 {
 171     CPURISCVState *env = &RISCV_CPU(obj)->env;
 172     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 173     set_priv_version(env, PRIV_VERSION_1_10_0);
 174     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 175 }
 176
 177 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 178 {
 179     CPURISCVState *env = &RISCV_CPU(obj)->env;
 180     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 181     set_priv_version(env, PRIV_VERSION_1_10_0);
 182     set_resetvec(env, DEFAULT_RSTVEC);
 183     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 184 }
 185
 186 #endif
 187
 188 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 189 {
 190     ObjectClass *oc;
 191     char *typename;
 192     char **cpuname;
 193
 194     cpuname = g_strsplit(cpu_model, ",", 1);
 195     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 196     oc = object_class_by_name(typename);
 197     g_strfreev(cpuname);
 198     g_free(typename);
 199     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 200         object_class_is_abstract(oc)) {
 201         return NULL;
 202     }
 203     return oc;
 204 }
 205
 206 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 207 {
 208     RISCVCPU *cpu = RISCV_CPU(cs);
 209     CPURISCVState *env = &cpu->env;
 210     int i;
 211
 212 #if !defined(CONFIG_USER_ONLY)
 213     if (riscv_has_ext(env, RVH)) {
 214         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 215     }
 216 #endif
 217     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 218 #ifndef CONFIG_USER_ONLY
 219     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 220     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
 221 #ifdef TARGET_RISCV32
 222     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
 223                  (target_ulong)(env->mstatus >> 32));
 224 #endif
 225     if (riscv_has_ext(env, RVH)) {
 226         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 227         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
 228                      (target_ulong)env->vsstatus);
 229     }
 230     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 231     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 232     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 233     if (riscv_has_ext(env, RVH)) {
 234         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 235     }
 236     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 237     if (riscv_has_ext(env, RVH)) {
 238         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 239     }
 240     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 241     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 242     if (riscv_has_ext(env, RVH)) {
 243         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 244     }
 245     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 246     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 247     if (riscv_has_ext(env, RVH)) {
 248         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 249     }
 250     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 251     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 252     if (riscv_has_ext(env, RVH)) {
 253         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 254     }
 255     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
 256     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
 257     if (riscv_has_ext(env, RVH)) {
 258         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 259         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 260     }
 261 #endif
 262
 263     for (i = 0; i < 32; i++) {
 264         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 265                      riscv_int_regnames[i], env->gpr[i]);
 266         if ((i & 3) == 3) {
 267             qemu_fprintf(f, "\n");
 268         }
 269     }
 270     if (flags & CPU_DUMP_FPU) {
 271         for (i = 0; i < 32; i++) {
 272             qemu_fprintf(f, " %s %016" PRIx64,
 273                          riscv_fpr_regnames[i], env->fpr[i]);
 274             if ((i & 3) == 3) {
 275                 qemu_fprintf(f, "\n");
 276             }
 277         }
 278     }
 279 }
 280
 281 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 282 {
 283     RISCVCPU *cpu = RISCV_CPU(cs);
 284     CPURISCVState *env = &cpu->env;
 285     env->pc = value;
 286 }
 287
 288 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
 289 {
 290     RISCVCPU *cpu = RISCV_CPU(cs);
 291     CPURISCVState *env = &cpu->env;
 292     env->pc = tb->pc;
 293 }
 294
 295 static bool riscv_cpu_has_work(CPUState *cs)
 296 {
 297 #ifndef CONFIG_USER_ONLY
 298     RISCVCPU *cpu = RISCV_CPU(cs);
 299     CPURISCVState *env = &cpu->env;
 300     /*
 301      * Definition of the WFI instruction requires it to ignore the privilege
 302      * mode and delegation registers, but respect individual enables
 303      */
 304     return (env->mip & env->mie) != 0;
 305 #else
 306     return true;
 307 #endif
 308 }
 309
 310 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 311                           target_ulong *data)
 312 {
 313     env->pc = data[0];
 314 }
 315
 316 static void riscv_cpu_reset(DeviceState *dev)
 317 {
 318     CPUState *cs = CPU(dev);
 319     RISCVCPU *cpu = RISCV_CPU(cs);
 320     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 321     CPURISCVState *env = &cpu->env;
 322
 323     mcc->parent_reset(dev);
 324 #ifndef CONFIG_USER_ONLY
 325     env->priv = PRV_M;
 326     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 327     env->mcause = 0;
 328     env->pc = env->resetvec;
 329 #endif
 330     cs->exception_index = EXCP_NONE;
 331     env->load_res = -1;
 332     set_default_nan_mode(1, &env->fp_status);
 333 }
 334
 335 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 336 {
 337 #if defined(TARGET_RISCV32)
 338     info->print_insn = print_insn_riscv32;
 339 #elif defined(TARGET_RISCV64)
 340     info->print_insn = print_insn_riscv64;
 341 #endif
 342 }
 343
 344 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 345 {
 346     CPUState *cs = CPU(dev);
 347     RISCVCPU *cpu = RISCV_CPU(dev);
 348     CPURISCVState *env = &cpu->env;
 349     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 350     int priv_version = PRIV_VERSION_1_11_0;
 351     int vext_version = VEXT_VERSION_0_07_1;
 352     target_ulong target_misa = 0;
 353     Error *local_err = NULL;
 354
 355     cpu_exec_realizefn(cs, &local_err);
 356     if (local_err != NULL) {
 357         error_propagate(errp, local_err);
 358         return;
 359     }
 360
 361     if (cpu->cfg.priv_spec) {
 362         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 363             priv_version = PRIV_VERSION_1_11_0;
 364         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 365             priv_version = PRIV_VERSION_1_10_0;
 366         } else {
 367             error_setg(errp,
 368                        "Unsupported privilege spec version '%s'",
 369                        cpu->cfg.priv_spec);
 370             return;
 371         }
 372     }
 373
 374     set_priv_version(env, priv_version);
 375     set_vext_version(env, vext_version);
 376
 377     if (cpu->cfg.mmu) {
 378         set_feature(env, RISCV_FEATURE_MMU);
 379     }
 380
 381     if (cpu->cfg.pmp) {
 382         set_feature(env, RISCV_FEATURE_PMP);
 383     }
 384
 385     set_resetvec(env, cpu->cfg.resetvec);
 386
 387     /* If misa isn't set (rv32 and rv64 machines) set it here */
 388     if (!env->misa) {
 389         /* Do some ISA extension error checking */
 390         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 391             error_setg(errp,
 392                        "I and E extensions are incompatible");
 393                        return;
 394        }
 395
 396         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 397             error_setg(errp,
 398                        "Either I or E extension must be set");
 399                        return;
 400        }
 401
 402        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 403                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 404                                cpu->cfg.ext_d)) {
 405             warn_report("Setting G will also set IMAFD");
 406             cpu->cfg.ext_i = true;
 407             cpu->cfg.ext_m = true;
 408             cpu->cfg.ext_a = true;
 409             cpu->cfg.ext_f = true;
 410             cpu->cfg.ext_d = true;
 411         }
 412
 413         /* Set the ISA extensions, checks should have happened above */
 414         if (cpu->cfg.ext_i) {
 415             target_misa |= RVI;
 416         }
 417         if (cpu->cfg.ext_e) {
 418             target_misa |= RVE;
 419         }
 420         if (cpu->cfg.ext_m) {
 421             target_misa |= RVM;
 422         }
 423         if (cpu->cfg.ext_a) {
 424             target_misa |= RVA;
 425         }
 426         if (cpu->cfg.ext_f) {
 427             target_misa |= RVF;
 428         }
 429         if (cpu->cfg.ext_d) {
 430             target_misa |= RVD;
 431         }
 432         if (cpu->cfg.ext_c) {
 433             target_misa |= RVC;
 434         }
 435         if (cpu->cfg.ext_s) {
 436             target_misa |= RVS;
 437         }
 438         if (cpu->cfg.ext_u) {
 439             target_misa |= RVU;
 440         }
 441         if (cpu->cfg.ext_h) {
 442             target_misa |= RVH;
 443         }
 444         if (cpu->cfg.ext_v) {
 445             target_misa |= RVV;
 446             if (!is_power_of_2(cpu->cfg.vlen)) {
 447                 error_setg(errp,
 448                         "Vector extension VLEN must be power of 2");
 449                 return;
 450             }
 451             if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 452                 error_setg(errp,
 453                         "Vector extension implementation only supports VLEN "
 454                         "in the range [128, %d]", RV_VLEN_MAX);
 455                 return;
 456             }
 457             if (!is_power_of_2(cpu->cfg.elen)) {
 458                 error_setg(errp,
 459                         "Vector extension ELEN must be power of 2");
 460                 return;
 461             }
 462             if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
 463                 error_setg(errp,
 464                         "Vector extension implementation only supports ELEN "
 465                         "in the range [8, 64]");
 466                 return;
 467             }
 468             if (cpu->cfg.vext_spec) {
 469                 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
 470                     vext_version = VEXT_VERSION_0_07_1;
 471                 } else {
 472                     error_setg(errp,
 473                            "Unsupported vector spec version '%s'",
 474                            cpu->cfg.vext_spec);
 475                     return;
 476                 }
 477             } else {
 478                 qemu_log("vector verison is not specified, "
 479                         "use the default value v0.7.1\n");
 480             }
 481             set_vext_version(env, vext_version);
 482         }
 483
 484         set_misa(env, RVXLEN | target_misa);
 485     }
 486
 487     riscv_cpu_register_gdb_regs_for_features(cs);
 488
 489     qemu_init_vcpu(cs);
 490     cpu_reset(cs);
 491
 492     mcc->parent_realize(dev, errp);
 493 }
 494
 495 static void riscv_cpu_init(Object *obj)
 496 {
 497     RISCVCPU *cpu = RISCV_CPU(obj);
 498
 499     cpu_set_cpustate_pointers(cpu);
 500 }
 501
 502 static Property riscv_cpu_properties[] = {
 503     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 504     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 505     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 506     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 507     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 508     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 509     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 510     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 511     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 512     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 513     /* This is experimental so mark with 'x-' */
 514     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 515     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
 516     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 517     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 518     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 519     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 520     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
 521     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 522     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 523     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 524     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 525     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 526     DEFINE_PROP_END_OF_LIST(),
 527 };
 528
 529 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 530 {
 531     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 532     CPUClass *cc = CPU_CLASS(c);
 533     DeviceClass *dc = DEVICE_CLASS(c);
 534
 535     device_class_set_parent_realize(dc, riscv_cpu_realize,
 536                                     &mcc->parent_realize);
 537
 538     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 539
 540     cc->class_by_name = riscv_cpu_class_by_name;
 541     cc->has_work = riscv_cpu_has_work;
 542     cc->do_interrupt = riscv_cpu_do_interrupt;
 543     cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
 544     cc->dump_state = riscv_cpu_dump_state;
 545     cc->set_pc = riscv_cpu_set_pc;
 546     cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
 547     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 548     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 549     cc->gdb_num_core_regs = 33;
 550 #if defined(TARGET_RISCV32)
 551     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 552 #elif defined(TARGET_RISCV64)
 553     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 554 #endif
 555     cc->gdb_stop_before_watchpoint = true;
 556     cc->disas_set_info = riscv_cpu_disas_set_info;
 557 #ifndef CONFIG_USER_ONLY
 558     cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
 559     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
 560     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 561     /* For now, mark unmigratable: */
 562     cc->vmsd = &vmstate_riscv_cpu;
 563 #endif
 564 #ifdef CONFIG_TCG
 565     cc->tcg_initialize = riscv_translate_init;
 566     cc->tlb_fill = riscv_cpu_tlb_fill;
 567 #endif
 568     device_class_set_props(dc, riscv_cpu_properties);
 569 }
 570
 571 char *riscv_isa_string(RISCVCPU *cpu)
 572 {
 573     int i;
 574     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 575     char *isa_str = g_new(char, maxlen);
 576     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 577     for (i = 0; i < sizeof(riscv_exts); i++) {
 578         if (cpu->env.misa & RV(riscv_exts[i])) {
 579             *p++ = qemu_tolower(riscv_exts[i]);
 580         }
 581     }
 582     *p = '\0';
 583     return isa_str;
 584 }
 585
 586 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 587 {
 588     ObjectClass *class_a = (ObjectClass *)a;
 589     ObjectClass *class_b = (ObjectClass *)b;
 590     const char *name_a, *name_b;
 591
 592     name_a = object_class_get_name(class_a);
 593     name_b = object_class_get_name(class_b);
 594     return strcmp(name_a, name_b);
 595 }
 596
 597 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 598 {
 599     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 600     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 601
 602     qemu_printf("%.*s\n", len, typename);
 603 }
 604
 605 void riscv_cpu_list(void)
 606 {
 607     GSList *list;
 608
 609     list = object_class_get_list(TYPE_RISCV_CPU, false);
 610     list = g_slist_sort(list, riscv_cpu_list_compare);
 611     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 612     g_slist_free(list);
 613 }
 614
 615 #define DEFINE_CPU(type_name, initfn)      \
 616     {                                      \
 617         .name = type_name,                 \
 618         .parent = TYPE_RISCV_CPU,          \
 619         .instance_init = initfn            \
 620     }
 621
 622 static const TypeInfo riscv_cpu_type_infos[] = {
 623     {
 624         .name = TYPE_RISCV_CPU,
 625         .parent = TYPE_CPU,
 626         .instance_size = sizeof(RISCVCPU),
 627         .instance_align = __alignof__(RISCVCPU),
 628         .instance_init = riscv_cpu_init,
 629         .abstract = true,
 630         .class_size = sizeof(RISCVCPUClass),
 631         .class_init = riscv_cpu_class_init,
 632     },
 633     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 634 #if defined(TARGET_RISCV32)
 635     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base_cpu_init),
 636     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 637     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rvxx_sifive_e_cpu_init),
 638     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
 639     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rvxx_sifive_u_cpu_init),
 640 #elif defined(TARGET_RISCV64)
 641     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base_cpu_init),
 642     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rvxx_sifive_e_cpu_init),
 643     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rvxx_sifive_u_cpu_init),
 644 #endif
 645 };
 646
 647 DEFINE_TYPES(riscv_cpu_type_infos)