target/arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 #include "exec/translator.h"
   5 #include "internals.h"
   6
   7
   8 /* internal defines */
   9 typedef struct DisasContext {
  10     DisasContextBase base;
  11     const ARMISARegisters *isar;
  12
  13     /* The address of the current instruction being translated. */
  14     target_ulong pc_curr;
  15     target_ulong page_start;
  16     uint32_t insn;
  17     /* Nonzero if this instruction has been conditionally skipped.  */
  18     int condjmp;
  19     /* The label that will be jumped to when the instruction is skipped.  */
  20     TCGLabel *condlabel;
  21     /* Thumb-2 conditional execution bits.  */
  22     int condexec_mask;
  23     int condexec_cond;
  24     int thumb;
  25     int sctlr_b;
  26     MemOp be_data;
  27 #if !defined(CONFIG_USER_ONLY)
  28     int user;
  29 #endif
  30     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  31     uint8_t tbii;      /* TBI1|TBI0 for insns */
  32     uint8_t tbid;      /* TBI1|TBI0 for data */
  33     uint8_t tcma;      /* TCMA1|TCMA0 for MTE */
  34     bool ns;        /* Use non-secure CPREG bank on access */
  35     int fp_excp_el; /* FP exception EL or 0 if enabled */
  36     int sve_excp_el; /* SVE exception EL or 0 if enabled */
  37     int sve_len;     /* SVE vector length in bytes */
  38     /* Flag indicating that exceptions from secure mode are routed to EL3. */
  39     bool secure_routed_to_el3;
  40     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  41     int vec_len;
  42     int vec_stride;
  43     bool v7m_handler_mode;
  44     bool v8m_secure; /* true if v8M and we're in Secure mode */
  45     bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
  46     bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
  47     bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
  48     bool v7m_lspact; /* FPCCR.LSPACT set */
  49     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  50      * so that top level loop can generate correct syndrome information.
  51      */
  52     uint32_t svc_imm;
  53     int aarch64;
  54     int current_el;
  55     /* Debug target exception level for single-step exceptions */
  56     int debug_target_el;
  57     GHashTable *cp_regs;
  58     uint64_t features; /* CPU features bits */
  59     /* Because unallocated encodings generate different exception syndrome
  60      * information from traps due to FP being disabled, we can't do a single
  61      * "is fp access disabled" check at a high level in the decode tree.
  62      * To help in catching bugs where the access check was forgotten in some
  63      * code path, we set this flag when the access check is done, and assert
  64      * that it is set at the point where we actually touch the FP regs.
  65      */
  66     bool fp_access_checked;
  67     bool sve_access_checked;
  68     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  69      * single-step support).
  70      */
  71     bool ss_active;
  72     bool pstate_ss;
  73     /* True if the insn just emitted was a load-exclusive instruction
  74      * (necessary for syndrome information for single step exceptions),
  75      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  76      */
  77     bool is_ldex;
  78     /* True if AccType_UNPRIV should be used for LDTR et al */
  79     bool unpriv;
  80     /* True if v8.3-PAuth is active.  */
  81     bool pauth_active;
  82     /* True if v8.5-MTE access to tags is enabled.  */
  83     bool ata;
  84     /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv.  */
  85     bool mte_active[2];
  86     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
  87     bool bt;
  88     /* True if any CP15 access is trapped by HSTR_EL2 */
  89     bool hstr_active;
  90     /*
  91      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
  92      *  < 0, set by the current instruction.
  93      */
  94     int8_t btype;
  95     /* A copy of cpu->dcz_blocksize. */
  96     uint8_t dcz_blocksize;
  97     /* True if this page is guarded.  */
  98     bool guarded_page;
  99     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
 100     int c15_cpar;
 101     /* TCG op of the current insn_start.  */
 102     TCGOp *insn_start;
 103 #define TMP_A64_MAX 16
 104     int tmp_a64_count;
 105     TCGv_i64 tmp_a64[TMP_A64_MAX];
 106 } DisasContext;
 107
 108 typedef struct DisasCompare {
 109     TCGCond cond;
 110     TCGv_i32 value;
 111     bool value_global;
 112 } DisasCompare;
 113
 114 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
 115 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
 116 extern TCGv_i64 cpu_exclusive_addr;
 117 extern TCGv_i64 cpu_exclusive_val;
 118
 119 static inline int arm_dc_feature(DisasContext *dc, int feature)
 120 {
 121     return (dc->features & (1ULL << feature)) != 0;
 122 }
 123
 124 static inline int get_mem_index(DisasContext *s)
 125 {
 126     return arm_to_core_mmu_idx(s->mmu_idx);
 127 }
 128
 129 /* Function used to determine the target exception EL when otherwise not known
 130  * or default.
 131  */
 132 static inline int default_exception_el(DisasContext *s)
 133 {
 134     /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
 135      * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 136      * exceptions can only be routed to ELs above 1, so we target the higher of
 137      * 1 or the current EL.
 138      */
 139     return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
 140             ? 3 : MAX(1, s->current_el);
 141 }
 142
 143 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 144 {
 145     /* We don't need to save all of the syndrome so we mask and shift
 146      * out unneeded bits to help the sleb128 encoder do a better job.
 147      */
 148     syn &= ARM_INSN_START_WORD2_MASK;
 149     syn >>= ARM_INSN_START_WORD2_SHIFT;
 150
 151     /* We check and clear insn_start_idx to catch multiple updates.  */
 152     assert(s->insn_start != NULL);
 153     tcg_set_insn_start_param(s->insn_start, 2, syn);
 154     s->insn_start = NULL;
 155 }
 156
 157 /* is_jmp field values */
 158 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 159 /* CPU state was modified dynamically; exit to main loop for interrupts. */
 160 #define DISAS_UPDATE_EXIT  DISAS_TARGET_1
 161 /* These instructions trap after executing, so the A32/T32 decoder must
 162  * defer them until after the conditional execution state has been updated.
 163  * WFI also needs special handling when single-stepping.
 164  */
 165 #define DISAS_WFI       DISAS_TARGET_2
 166 #define DISAS_SWI       DISAS_TARGET_3
 167 /* WFE */
 168 #define DISAS_WFE       DISAS_TARGET_4
 169 #define DISAS_HVC       DISAS_TARGET_5
 170 #define DISAS_SMC       DISAS_TARGET_6
 171 #define DISAS_YIELD     DISAS_TARGET_7
 172 /* M profile branch which might be an exception return (and so needs
 173  * custom end-of-TB code)
 174  */
 175 #define DISAS_BX_EXCRET DISAS_TARGET_8
 176 /*
 177  * For instructions which want an immediate exit to the main loop, as opposed
 178  * to attempting to use lookup_and_goto_ptr.  Unlike DISAS_UPDATE_EXIT, this
 179  * doesn't write the PC on exiting the translation loop so you need to ensure
 180  * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
 181  * return from cpu_tb_exec.
 182  */
 183 #define DISAS_EXIT      DISAS_TARGET_9
 184 /* CPU state was modified dynamically; no need to exit, but do not chain. */
 185 #define DISAS_UPDATE_NOCHAIN  DISAS_TARGET_10
 186
 187 #ifdef TARGET_AARCH64
 188 void a64_translate_init(void);
 189 void gen_a64_set_pc_im(uint64_t val);
 190 extern const TranslatorOps aarch64_translator_ops;
 191 #else
 192 static inline void a64_translate_init(void)
 193 {
 194 }
 195
 196 static inline void gen_a64_set_pc_im(uint64_t val)
 197 {
 198 }
 199 #endif
 200
 201 void arm_test_cc(DisasCompare *cmp, int cc);
 202 void arm_free_cc(DisasCompare *cmp);
 203 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 204 void arm_gen_test_cc(int cc, TCGLabel *label);
 205
 206 /* Return state of Alternate Half-precision flag, caller frees result */
 207 static inline TCGv_i32 get_ahp_flag(void)
 208 {
 209     TCGv_i32 ret = tcg_temp_new_i32();
 210
 211     tcg_gen_ld_i32(ret, cpu_env,
 212                    offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
 213     tcg_gen_extract_i32(ret, ret, 26, 1);
 214
 215     return ret;
 216 }
 217
 218 /* Set bits within PSTATE.  */
 219 static inline void set_pstate_bits(uint32_t bits)
 220 {
 221     TCGv_i32 p = tcg_temp_new_i32();
 222
 223     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 224
 225     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 226     tcg_gen_ori_i32(p, p, bits);
 227     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 228     tcg_temp_free_i32(p);
 229 }
 230
 231 /* Clear bits within PSTATE.  */
 232 static inline void clear_pstate_bits(uint32_t bits)
 233 {
 234     TCGv_i32 p = tcg_temp_new_i32();
 235
 236     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 237
 238     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 239     tcg_gen_andi_i32(p, p, ~bits);
 240     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 241     tcg_temp_free_i32(p);
 242 }
 243
 244 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
 245 static inline void gen_ss_advance(DisasContext *s)
 246 {
 247     if (s->ss_active) {
 248         s->pstate_ss = 0;
 249         clear_pstate_bits(PSTATE_SS);
 250     }
 251 }
 252
 253 static inline void gen_exception(int excp, uint32_t syndrome,
 254                                  uint32_t target_el)
 255 {
 256     TCGv_i32 tcg_excp = tcg_const_i32(excp);
 257     TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
 258     TCGv_i32 tcg_el = tcg_const_i32(target_el);
 259
 260     gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
 261                                        tcg_syn, tcg_el);
 262
 263     tcg_temp_free_i32(tcg_el);
 264     tcg_temp_free_i32(tcg_syn);
 265     tcg_temp_free_i32(tcg_excp);
 266 }
 267
 268 /* Generate an architectural singlestep exception */
 269 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
 270 {
 271     bool same_el = (s->debug_target_el == s->current_el);
 272
 273     /*
 274      * If singlestep is targeting a lower EL than the current one,
 275      * then s->ss_active must be false and we can never get here.
 276      */
 277     assert(s->debug_target_el >= s->current_el);
 278
 279     gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
 280 }
 281
 282 /*
 283  * Given a VFP floating point constant encoded into an 8 bit immediate in an
 284  * instruction, expand it to the actual constant value of the specified
 285  * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
 286  */
 287 uint64_t vfp_expand_imm(int size, uint8_t imm8);
 288
 289 /* Vector operations shared between ARM and AArch64.  */
 290 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 291                    uint32_t opr_sz, uint32_t max_sz);
 292 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 293                    uint32_t opr_sz, uint32_t max_sz);
 294 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 295                    uint32_t opr_sz, uint32_t max_sz);
 296 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 297                    uint32_t opr_sz, uint32_t max_sz);
 298 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 299                    uint32_t opr_sz, uint32_t max_sz);
 300
 301 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 302                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 303 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 304                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 305
 306 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 307                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 308 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 309                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 310 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 311                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 312
 313 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 314 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
 315 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
 316 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 317 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 318
 319 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 320                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 321 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 322                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 323 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 324                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 325 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 326                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 327
 328 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 329                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 330 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 331                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 332
 333 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 334                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 335 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 336                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 337 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 338                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 339 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 340                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 341
 342 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 343                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 344 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 345                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 346
 347 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 348                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 349 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 350                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 351
 352 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 353                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 354 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 355                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 356
 357 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 358                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 359 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 360                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 361
 362 /*
 363  * Forward to the isar_feature_* tests given a DisasContext pointer.
 364  */
 365 #define dc_isar_feature(name, ctx) \
 366     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 367
 368 /* Note that the gvec expanders operate on offsets + sizes.  */
 369 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
 370 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
 371                          uint32_t, uint32_t);
 372 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
 373                         uint32_t, uint32_t, uint32_t);
 374 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
 375                         uint32_t, uint32_t, uint32_t);
 376
 377 /* Function prototype for gen_ functions for calling Neon helpers */
 378 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
 379 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
 380 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
 381 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
 382 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
 383 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
 384 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
 385 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
 386 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
 387 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
 388 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
 389 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
 390 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
 391 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
 392 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
 393 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 394 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 395 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 396
 397 /*
 398  * Enum for argument to fpstatus_ptr().
 399  */
 400 typedef enum ARMFPStatusFlavour {
 401     FPST_FPCR,
 402     FPST_FPCR_F16,
 403     FPST_STD,
 404     FPST_STD_F16,
 405 } ARMFPStatusFlavour;
 406
 407 /**
 408  * fpstatus_ptr: return TCGv_ptr to the specified fp_status field
 409  *
 410  * We have multiple softfloat float_status fields in the Arm CPU state struct
 411  * (see the comment in cpu.h for details). Return a TCGv_ptr which has
 412  * been set up to point to the requested field in the CPU state struct.
 413  * The options are:
 414  *
 415  * FPST_FPCR
 416  *   for non-FP16 operations controlled by the FPCR
 417  * FPST_FPCR_F16
 418  *   for operations controlled by the FPCR where FPCR.FZ16 is to be used
 419  * FPST_STD
 420  *   for A32/T32 Neon operations using the "standard FPSCR value"
 421  * FPST_STD_F16
 422  *   as FPST_STD, but where FPCR.FZ16 is to be used
 423  */
 424 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
 425 {
 426     TCGv_ptr statusptr = tcg_temp_new_ptr();
 427     int offset;
 428
 429     switch (flavour) {
 430     case FPST_FPCR:
 431         offset = offsetof(CPUARMState, vfp.fp_status);
 432         break;
 433     case FPST_FPCR_F16:
 434         offset = offsetof(CPUARMState, vfp.fp_status_f16);
 435         break;
 436     case FPST_STD:
 437         offset = offsetof(CPUARMState, vfp.standard_fp_status);
 438         break;
 439     case FPST_STD_F16:
 440         offset = offsetof(CPUARMState, vfp.standard_fp_status_f16);
 441         break;
 442     default:
 443         g_assert_not_reached();
 444     }
 445     tcg_gen_addi_ptr(statusptr, cpu_env, offset);
 446     return statusptr;
 447 }
 448
 449 #endif /* TARGET_ARM_TRANSLATE_H */