hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "mac_dbdma.h"
  29 #include "nvram.h"
  30 #include "pc.h"
  31 #include "sysemu.h"
  32 #include "net.h"
  33 #include "isa.h"
  34 #include "pci.h"
  35 #include "usb-ohci.h"
  36 #include "boards.h"
  37 #include "fw_cfg.h"
  38 #include "escc.h"
  39 #include "ide.h"
  40 #include "loader.h"
  41 #include "elf.h"
  42 #include "kvm.h"
  43
  44 #define MAX_IDE_BUS 2
  45 #define VGA_BIOS_SIZE 65536
  46 #define CFG_ADDR 0xf0000510
  47
  48 /* temporary frame buffer OSI calls for the video.x driver. The right
  49    solution is to modify the driver to use VGA PCI I/Os */
  50 /* XXX: to be removed. This is no way related to emulation */
  51 static int vga_osi_call (CPUState *env)
  52 {
  53     static int vga_vbl_enabled;
  54     int linesize;
  55
  56 #if 0
  57     printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
  58 #endif
  59
  60     /* same handler as PearPC, coming from the original MOL video
  61        driver. */
  62     switch(env->gpr[5]) {
  63     case 4:
  64         break;
  65     case 28: /* set_vmode */
  66         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  67             env->gpr[3] = 1;
  68         else
  69             env->gpr[3] = 0;
  70         break;
  71     case 29: /* get_vmode_info */
  72         if (env->gpr[6] != 0) {
  73             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  74                 env->gpr[3] = 1;
  75                 break;
  76             }
  77         }
  78         env->gpr[3] = 0;
  79         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  80         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  81         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  82         env->gpr[7] = 85 << 16; /* refresh rate */
  83         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  84         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  85         linesize = (linesize + 3) & ~3;
  86         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  87         break;
  88     case 31: /* set_video power */
  89         env->gpr[3] = 0;
  90         break;
  91     case 39: /* video_ctrl */
  92         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  93             vga_vbl_enabled = env->gpr[6];
  94         env->gpr[3] = 0;
  95         break;
  96     case 47:
  97         break;
  98     case 59: /* set_color */
  99         /* R6 = index, R7 = RGB */
 100         env->gpr[3] = 0;
 101         break;
 102     case 64: /* get color */
 103         /* R6 = index */
 104         env->gpr[3] = 0;
 105         break;
 106     case 116: /* set hwcursor */
 107         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 108         break;
 109     default:
 110         fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
 111                 ppc_dump_gpr(env, 5));
 112         break;
 113     }
 114
 115     return 1; /* osi_call handled */
 116 }
 117
 118 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 119 {
 120     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 121     return 0;
 122 }
 123
 124 static void ppc_heathrow_init (ram_addr_t ram_size,
 125                                const char *boot_device,
 126                                const char *kernel_filename,
 127                                const char *kernel_cmdline,
 128                                const char *initrd_filename,
 129                                const char *cpu_model)
 130 {
 131     CPUState *env = NULL, *envs[MAX_CPUS];
 132     char *filename;
 133     qemu_irq *pic, **heathrow_irqs;
 134     int linux_boot, i;
 135     ram_addr_t ram_offset, bios_offset, vga_bios_offset;
 136     uint32_t kernel_base, initrd_base;
 137     int32_t kernel_size, initrd_size;
 138     PCIBus *pci_bus;
 139     MacIONVRAMState *nvr;
 140     int vga_bios_size, bios_size;
 141     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 142     int escc_mem_index, ide_mem_index[2];
 143     uint16_t ppc_boot_device;
 144     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 145     void *fw_cfg;
 146     void *dbdma;
 147     uint8_t *vga_bios_ptr;
 148
 149     linux_boot = (kernel_filename != NULL);
 150
 151     /* init CPUs */
 152     if (cpu_model == NULL)
 153         cpu_model = "G3";
 154     for (i = 0; i < smp_cpus; i++) {
 155         env = cpu_init(cpu_model);
 156         if (!env) {
 157             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 158             exit(1);
 159         }
 160         /* Set time-base frequency to 16.6 Mhz */
 161         cpu_ppc_tb_init(env,  16600000UL);
 162         env->osi_call = vga_osi_call;
 163         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 164         envs[i] = env;
 165     }
 166
 167     /* Make sure all register sets take effect */
 168     cpu_synchronize_state(env);
 169
 170     /* allocate RAM */
 171     if (ram_size > (2047 << 20)) {
 172         fprintf(stderr,
 173                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 174                 ((unsigned int)ram_size / (1 << 20)));
 175         exit(1);
 176     }
 177
 178     ram_offset = qemu_ram_alloc(ram_size);
 179     cpu_register_physical_memory(0, ram_size, ram_offset);
 180
 181     /* allocate and load BIOS */
 182     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 183     if (bios_name == NULL)
 184         bios_name = PROM_FILENAME;
 185     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 186     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 187
 188     /* Load OpenBIOS (ELF) */
 189     if (filename) {
 190         bios_size = load_elf(filename, 0, NULL, NULL, NULL,
 191                                1, ELF_MACHINE, 0);
 192         qemu_free(filename);
 193     } else {
 194         bios_size = -1;
 195     }
 196     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 197         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 198         exit(1);
 199     }
 200
 201     /* allocate and load VGA BIOS */
 202     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 203     vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
 204     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
 205     if (filename) {
 206         vga_bios_size = load_image(filename, vga_bios_ptr + 8);
 207         qemu_free(filename);
 208     } else {
 209         vga_bios_size = -1;
 210     }
 211     if (vga_bios_size < 0) {
 212         /* if no bios is present, we can still work */
 213         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
 214                 VGABIOS_FILENAME);
 215         vga_bios_size = 0;
 216     } else {
 217         /* set a specific header (XXX: find real Apple format for NDRV
 218            drivers) */
 219         vga_bios_ptr[0] = 'N';
 220         vga_bios_ptr[1] = 'D';
 221         vga_bios_ptr[2] = 'R';
 222         vga_bios_ptr[3] = 'V';
 223         cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
 224         vga_bios_size += 8;
 225
 226         /* Round to page boundary */
 227         vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
 228             TARGET_PAGE_MASK;
 229     }
 230
 231     if (linux_boot) {
 232         uint64_t lowaddr = 0;
 233         int bswap_needed;
 234
 235 #ifdef BSWAP_NEEDED
 236         bswap_needed = 1;
 237 #else
 238         bswap_needed = 0;
 239 #endif
 240         kernel_base = KERNEL_LOAD_ADDR;
 241         /* Now we can load the kernel. The first step tries to load the kernel
 242            supposing PhysAddr = 0x00000000. If that was wrong the kernel is
 243            loaded again, the new PhysAddr being computed from lowaddr. */
 244         kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL,
 245                                1, ELF_MACHINE, 0);
 246         if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
 247             kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
 248                                    NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 249         }
 250         if (kernel_size < 0)
 251             kernel_size = load_aout(kernel_filename, kernel_base,
 252                                     ram_size - kernel_base, bswap_needed,
 253                                     TARGET_PAGE_SIZE);
 254         if (kernel_size < 0)
 255             kernel_size = load_image_targphys(kernel_filename,
 256                                               kernel_base,
 257                                               ram_size - kernel_base);
 258         if (kernel_size < 0) {
 259             hw_error("qemu: could not load kernel '%s'\n",
 260                       kernel_filename);
 261             exit(1);
 262         }
 263         /* load initrd */
 264         if (initrd_filename) {
 265             initrd_base = INITRD_LOAD_ADDR;
 266             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 267                                               ram_size - initrd_base);
 268             if (initrd_size < 0) {
 269                 hw_error("qemu: could not load initial ram disk '%s'\n",
 270                          initrd_filename);
 271                 exit(1);
 272             }
 273         } else {
 274             initrd_base = 0;
 275             initrd_size = 0;
 276         }
 277         ppc_boot_device = 'm';
 278     } else {
 279         kernel_base = 0;
 280         kernel_size = 0;
 281         initrd_base = 0;
 282         initrd_size = 0;
 283         ppc_boot_device = '\0';
 284         for (i = 0; boot_device[i] != '\0'; i++) {
 285             /* TOFIX: for now, the second IDE channel is not properly
 286              *        used by OHW. The Mac floppy disk are not emulated.
 287              *        For now, OHW cannot boot from the network.
 288              */
 289 #if 0
 290             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 291                 ppc_boot_device = boot_device[i];
 292                 break;
 293             }
 294 #else
 295             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 296                 ppc_boot_device = boot_device[i];
 297                 break;
 298             }
 299 #endif
 300         }
 301         if (ppc_boot_device == '\0') {
 302             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 303             exit(1);
 304         }
 305     }
 306
 307     isa_mem_base = 0x80000000;
 308
 309     /* Register 2 MB of ISA IO space */
 310     isa_mmio_init(0xfe000000, 0x00200000);
 311
 312     /* XXX: we register only 1 output pin for heathrow PIC */
 313     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 314     heathrow_irqs[0] =
 315         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 316     /* Connect the heathrow PIC outputs to the 6xx bus */
 317     for (i = 0; i < smp_cpus; i++) {
 318         switch (PPC_INPUT(env)) {
 319         case PPC_FLAGS_INPUT_6xx:
 320             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 321             heathrow_irqs[i][0] =
 322                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 323             break;
 324         default:
 325             hw_error("Bus model not supported on OldWorld Mac machine\n");
 326         }
 327     }
 328
 329     /* init basic PC hardware */
 330     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 331         hw_error("Only 6xx bus is supported on heathrow machine\n");
 332     }
 333     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 334     pci_bus = pci_grackle_init(0xfec00000, pic);
 335     pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
 336
 337     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 338                                serial_hds[1], ESCC_CLOCK, 4);
 339
 340     for(i = 0; i < nb_nics; i++)
 341         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 342
 343
 344     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 345         fprintf(stderr, "qemu: too many IDE bus\n");
 346         exit(1);
 347     }
 348
 349     /* First IDE channel is a MAC IDE on the MacIO bus */
 350     hd[0] = drive_get(IF_IDE, 0, 0);
 351     hd[1] = drive_get(IF_IDE, 0, 1);
 352     dbdma = DBDMA_init(&dbdma_mem_index);
 353     ide_mem_index[0] = -1;
 354     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 355
 356     /* Second IDE channel is a CMD646 on the PCI bus */
 357     hd[0] = drive_get(IF_IDE, 1, 0);
 358     hd[1] = drive_get(IF_IDE, 1, 1);
 359     hd[3] = hd[2] = NULL;
 360     pci_cmd646_ide_init(pci_bus, hd, 0);
 361
 362     /* cuda also initialize ADB */
 363     cuda_init(&cuda_mem_index, pic[0x12]);
 364
 365     adb_kbd_init(&adb_bus);
 366     adb_mouse_init(&adb_bus);
 367
 368     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
 369     pmac_format_nvram_partition(nvr, 0x2000);
 370
 371     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
 372                dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
 373                escc_mem_index);
 374
 375     if (usb_enabled) {
 376         usb_ohci_init_pci(pci_bus, -1);
 377     }
 378
 379     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 380         graphic_depth = 15;
 381
 382     /* No PCI init: the BIOS will do it */
 383
 384     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 385     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 386     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 387     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 388     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 389     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 390     if (kernel_cmdline) {
 391         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 392         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 393     } else {
 394         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 395     }
 396     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 397     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 398     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 399
 400     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 401     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 402     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 403
 404     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 405 }
 406
 407 static QEMUMachine heathrow_machine = {
 408     .name = "g3beige",
 409     .desc = "Heathrow based PowerMAC",
 410     .init = ppc_heathrow_init,
 411     .max_cpus = MAX_CPUS,
 412 #ifndef TARGET_PPC64
 413     .is_default = 1,
 414 #endif
 415 };
 416
 417 static void heathrow_machine_init(void)
 418 {
 419     qemu_register_machine(&heathrow_machine);
 420 }
 421
 422 machine_init(heathrow_machine_init);